JP2008148274A - Semiconductor integrated circuit for rf communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage of an interference signal to the frequency band of a transmission signal for communication of DCS1800 and PCS1900 caused by the higher harmonic wave of a system reference clock pulse output signal to be supplied to a baseband LSI from the digital interface of a semiconductor integrated circuit for RF communication. <P>SOLUTION: An output buffer 317 which outputs a system reference clock pulse output signal SysCLk<SB>-</SB>SL to be supplied to the baseband LSI includes buffer circuits OB<SB>-</SB>1, OB<SB>-</SB>2, OB<SB>-</SB>3, ..., OB<SB>-</SB>n and a control register CNT<SB>-</SB>REG. The control register CNT<SB>-</SB>REG stores a control bit signal for setting the driving capability of the output buffer 317. The slew rate of rising Tr and falling Tf of SysCLk<SB>-</SB>SL is set by the control bit signal so that the level of the interference signal in the RF transmission frequency signal of the DCS1800 and the PCS1900 caused by the higher harmonic wave of a fundamental frequency of SysCLk<SB>-</SB>SL achieves the standard of GMSK. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention includes an RF reception signal analog signal processing subunit and an RF transmission signal analog signal processing subunit, and a semiconductor integrated circuit for RF communication that performs bidirectional signal transfer using an LSI that performs baseband digital signal processing and a digital interface. It relates to the circuit. The present invention is particularly useful for reducing leakage of interference signals into the frequency band of a communication transmission signal due to harmonics of a system reference clock supplied from the digital interface of the RF communication semiconductor integrated circuit to the LSI. Regarding technology.

In a general PLL (Phase Locked Loop) circuit with only an integer division ratio, the frequency resolution of the locked loop is the reference frequency f _REF , so the precise frequency resolution requires a small reference frequency f _REF , and therefore a small loop It becomes a frequency band. The narrow loop frequency band is undesirable because it takes a long switching time, and the phase noise of the voltage-controlled oscillator (VCO) of the PLL circuit is not sufficiently suppressed, and is susceptible to noise from outside the PLL circuit.

According to the following Non-Patent Document 1, the fractional synthesizer was developed to have a finer frequency resolution than the reference frequency f _REF , and in the fractional N divider, the division ratio is periodically changed from N to N + 1, As a result, the average frequency division ratio increases by N (N + 1) frequency duty ratios than N. The overflow from the accumulator is used to modulate the instantaneous divide ratio.

  Thus, in the fractional N-PLL circuit, the frequency division ratio N of the frequency divider in the negative feedback loop of the PLL circuit is a rational number including not only an integer but also a fraction (decimal number). Non-Patent Document 2 below describes that a fractional N-PLL circuit having sufficient bandwidth and resolution to select a desired channel and capture modulation is used for a GSM transmission / reception device. Has been. In this fractional N-PLL circuit, since the ΣΔ modulator to which digital data is supplied controls the denominator by the frequency divider, the oscillation frequency of the voltage controlled oscillator is modulated with the desired channel as the center.

  On the other hand, Non-Patent Document 3 below describes a high-speed, low power consumption digital interface between an RF chip and a baseband chip. Non-Patent Document 3 below describes that an A / D converter and a D / A converter are mounted on an RF transmission / reception chip, and an analog portion is replaced with a digital signal processing unit. In Non-Patent Document 3 below, the digital signal generated by the RF transceiver chip must be transferred to the baseband chip without contaminating the RF signal by electromagnetic emission (EMC), and from the baseband chip to the RF chip. It is described that the transferred digital signal is the same.

  Non-Patent Document 4 below describes the specifications of the digital interface between the RF IC and the baseband. According to this specification, the following eight types of signals are defined by the digital interface. The first is a signal of transmission / reception data (RxTxData), and burst symbols are transferred from the baseband to the RF IC during transmission Tx, and multiplexed IQ samples are transferred from the RF IC to the baseband during reception Rx. Is a bidirectional signal. The second is a transmission / reception enable (RxTxEn) signal that is enabled by the baseband during the transmission mode Tx and enabled by the RF IC during the reception mode Rx. The third, fourth, and fifth are the bidirectional control data (CtrlData) signal of the bidirectional three-wire control interface for accessing the register set of the RF IC, the control enable (CtrlEn) signal from the baseband, and the base. And a control clock (CtrlClk) signal from the band. The sixth is a strobe signal from the baseband, which is used to set the exact timing of events inside the RF IC. The seventh is a system clock (SysClk) signal, which is a 26 MHz master clock output from the RF IC when the eighth system clock enable (SysClkEn) signal is asserted by the baseband.

  Non-Patent Document 4 below indicates that most of the above eight types of signals, for example, the system clock, require slew rate control to limit the signal spectrum in order to avoid undesired interference inside the RF IC. It is described. Non-Patent Document 4 below requires EMC control for the first transmission / reception data (RxTxData) signal and the sixth strobe signal, but the third, fourth, and fifth. The control data (CtrlData) signal, the control enable (CtrlEn) signal, the control clock (CtrlClk) signal, and the eighth system clock enable (SysClkEn) signal are described as not requiring EMC control. . Further, the following Non-Patent Document 4 describes that the EMC control means that the regulation for controlling the rise time and fall time of the signal is made in order to limit the amount of signal spectrum.

Brian Miller and Robert J.M. Conley, “A Multiple Modulator Fractional Divider”, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 40. NO. 3. JUNE 1991. PP. 578-583. E. Hegazi et al, “A 17mW Transmitter and Frequency Syntheizer for 900MHz GSM Fully Integrated in 0.35-μm CMOS”, 2002 Symposium On VLSI Circuits. PP. 234-237. K. Chabrak et al, "New Concept of a High-Speed Low-Power Digital Interface for Multi-Standard Mobile Transceiver RFIC's in 0.13μm CMOS", 2005 IEEE International Symposium on Microwave, Antenna, Propergation and EMC Technologies for Wireless Communications Proceedings , PP. 281-284. Andrew Fogg, "DigRF BASEBAND / RF DIGITAL INTERFACE SPECIFICATION", Logical, Electrorical and Timing Characteristics EGPRS Version Digital Interface Working Group Rapporteur Andrew Fogg, TTPCom Version 1.12http: //146.101.169.51/DigRF Standard v112. pdf [October 5, 2006 search]

  Prior to the present invention, the inventors engaged in the development of an RF IC that supports GSM communication.

  The GSM (Global System for Mobile Communication) system is a communication system that performs GMSK (Gaussian minimum shift keying) modulation using only phase modulation as one of TDMA systems. TDMA is an abbreviation for Time-Division Multiple Access. In the TDMA system, each time slot of the plurality of time slots of the mobile phone terminal device can be set to any of an idle state, a reception operation from the base station, and a transmission operation to the base station. A method for improving a communication data transfer rate as compared with the GSM method is also known. As an improvement method, an EDGE (Enhanced Data for GSM Evolution) method that uses amplitude modulation as well as phase modulation has recently been attracting attention. GPRS is an abbreviation for General Packet Radio Service.

FIG. 1 is a diagram showing an overall configuration of a mobile terminal device equipped with a digital interface RF IC and a baseband LSI which have been studied by the present inventors prior to the present invention. FIG. 1 is also a diagram showing the overall configuration of a mobile terminal device according to an embodiment of the present invention. Here, the mobile terminal device is a mobile phone terminal device, but may be a mobile communication device for a notebook personal computer or a PDA (Personal Digital Assist) device. The fractional N-PLL circuit of the RF analog signal processing integrated circuit 300 (RF_IC) 300 includes a reference frequency oscillator VCXO. The reference oscillation frequency f _REF generated from the reference frequency oscillator VCXO is an AFC control D / A conversion to which an automatic frequency control (AFC) digital signal is supplied from the crystal unit Xtal (501) and the baseband LSI (400). The unit 315 (AFCDAC) provides a stable and accurate reference signal. In the RF analog signal processing integrated circuit 300 (RF_IC) 300, the oscillation frequency of the RF voltage-controlled oscillator of the frequency synthesizer of the oscillation frequency and the transceiver of the RF transmission voltage controlled oscillator reference oscillation frequency _{f REF} to the base of the reference frequency oscillator VCXO And are generated. An RF analog signal processing integrated circuit 300 (RF_IC) corresponding to the recent GSM communication system is configured to correspond to four frequency bands of GSM850, GSM900, DCS1800, and PCS1900. Therefore, the oscillation frequency of the RF transmission voltage controlled oscillator and the oscillation frequency of the RF voltage controlled oscillator must correspond to these four multi-frequency bands. The reference oscillation frequency f _REF of the reference frequency oscillator VCXO of the RF analog signal processing integrated circuit 300 (RF_IC) is a relatively low frequency on the order of several tens of MHz, whereas for RF transmission corresponding to a plurality of multi-frequency bands. The oscillation frequency of the voltage controlled oscillator and the oscillation frequency of the RF voltage controlled oscillator are relatively high frequencies on the order of several GHz. Thus, compared with the reference oscillation frequency f _REF of the reference frequency oscillator VCXO, the oscillation frequency from the RF transmission voltage controlled oscillator and the oscillation frequency of the RF voltage controlled oscillator are much higher. In this way, the fractional N-PLL circuit multiplies the reference oscillation frequency f _REF on the order of several tens of MHz by a frequency multiplication ratio by a frequency multiplication ratio that is the reciprocal of the fractional N division ratio, thereby transmitting an RF signal on the order of several GHz. A reference oscillation frequency of the trusted voltage controlled oscillator and an oscillation frequency of the RF voltage controlled oscillator are generated.

On the other hand, the RF analog signal processing integrated circuit 300 (RF_IC) is supplied with an external power supply voltage Vdd_ext having a standard value of 2.8 volts and a fluctuation range of 2.67 volts (minimum value) to 3.0 volts (maximum value). Therefore, it is necessary to prevent the reference oscillation frequency f _REF of the reference frequency oscillator VCXO from fluctuating due to the external power supply voltage fluctuation Vdd_ext. For this reason, the fluctuating external power supply voltage Vdd_ext is supplied to the on-chip voltage regulator. An internal stabilized power supply voltage maintained at a stable value of, for example, approximately 2.45 volts is generated from the on-chip voltage regulator, and the internal stabilized power supply voltage of approximately 2.45 volts is supplied to the reference frequency oscillator VCXO. become. If an internal stabilized power supply voltage maintained at a stable value is supplied to the reference frequency oscillator VCXO, the reference oscillation frequency f _REF of the reference frequency oscillator VCXO does not fluctuate due to the external power supply voltage fluctuation Vdd_ext, but stabilizes on the order of several tens of MHz. A reference oscillation frequency f _REF is obtained. Therefore, the internal stabilized power supply voltage from the on-chip voltage regulator is not supplied to the RF voltage controlled oscillator and the RF transmission voltage controlled oscillator of the fractional N-PLL circuit of the RF analog signal processing integrated circuit 300 (RF_IC). Alternatively, the external power supply voltage Vdd_ext may be supplied. Nevertheless, the oscillation frequency of the RF transmission voltage controlled oscillator and the oscillation frequency of the RF voltage controlled oscillator can be stably maintained by the fractional N-PLL circuit at a frequency multiplication ratio that is the reciprocal of the fractional N division ratio. . Thus, the frequency down-conversion from the RF reception signal to the baseband reception signal in the reception system signal processing subunit of the RF analog signal processing integrated circuit 300 (RF_IC) and the transmission system of the RF analog signal processing integrated circuit 300 (RF_IC) The fractional N-PLL circuit includes an RF voltage controlled oscillator for generating an RF carrier signal used for frequency up-conversion from a baseband transmission signal to an intermediate frequency transmission signal or an RF transmission signal in the signal processing subunit. become. The oscillation frequency of the RF voltage controlled oscillator of the fractional N-PLL circuit is set by the fractional division, so that the oscillation frequency of the RF transmission voltage controlled oscillator is finally set.

  On the other hand, transmission / reception devices such as mobile terminal devices generally include an RF analog signal processing integrated circuit and a baseband LSI. The RF analog signal processing integrated circuit performs modulation / demodulation, frequency up-conversion and frequency down-conversion of the transmission / reception signal, and the baseband LSI transmits the transmission signal to the I digital baseband transmission signal in phase with the fundamental wave and the Q digital baseband transmission of quadrature component The received data is restored from the I digital baseband received signal and the Q digital baseband received signal. Thus, the signal processing of the RF analog signal processing integrated circuit is mainly analog signal processing, and the signal processing of the baseband LSI is mainly digital signal processing. However, an A / D converter that converts an analog signal into a digital signal and a D / A converter that converts a digital signal into an analog signal are necessary between them. Conventionally, these A / D converters and Since the D / A converter is arranged in the baseband LSI, the signal transfer between them is an analog signal.

  On the other hand, baseband LSIs, mainly digital signal processing, have integrated transistors smaller than RF ICs due to advances in process technology, and power supply voltage tends to drop to 1.8 volts or less. . Therefore, it is difficult to arrange an A / D converter and a D / A converter that require an operating voltage higher than 2 volts in a baseband LSI. In such a situation, as described in Non-Patent Document 3 and Non-Patent Document 4, an A / D converter and a D / A converter between them are combined into an RF analog signal processing integrated circuit. Development of a digital interface RF IC and a baseband LSI using a digital signal for signal transfer between the two was carried out.

  In the mobile terminal apparatus shown in FIG. 1, A / D converters 303 and 304 and D / A converters 307, 308, and 315 are arranged inside an RF analog signal processing integrated circuit 300 (RF_IC). That is, the A / D converters 303 and 304 digitally output the analog baseband signals RxABI and RxABQ output from the RF reception signal analog signal processing subunit 301 (RX SPU) in the RF analog signal processing integrated circuit 300 (RF_IC). The baseband signals RxDBI and RxDBQ are converted and supplied to the baseband signal processing LSI 400 (BB_LSI). In addition, the D / A converters 307 and 308 convert the quadrature components TxDBI and TxDBQ of the digital baseband transmission signal output from the baseband signal processing LSI 400 (BB_LSI) into analog baseband transmission signals TxABI and TxABQ, respectively, and RF analog signals. This signal is supplied to the RF transmission signal analog signal processing subunit 302 (TX SPU) inside the processing integrated circuit 300 (RF_IC). The D / A converter 315 for AFC control converts the AFC control digital signal output from the baseband processor core 401 obtained in the digital signal path L3 of the RF digital interface 402 of the baseband signal processing LSI 400 into an AFC control analog signal. To the system reference clock oscillator 314 (VCXO).

  On the other hand, according to the description of Non-Patent Document 4, a device conforming to the specifications of the digital interface must operate correctly with respect to the system clock SysClk having an error of at least 100 ppm (0.01%) at 26 MHz plus or minus. I must.

  In the mobile terminal device shown in FIG. 1, the system reference clock signal SysCLk having a substantially sinusoidal waveform with an oscillation frequency of 26 MHz oscillated by the system reference clock oscillator 314 (VCXO) is waveform-shaped by the transmission / reception control subunit 310. This is supplied to the circuit 3103. The waveform shaping circuit 3103 performs waveform shaping from a sine wave waveform to a pulse waveform, and the digital system reference clock signal SysCLk_SL having a pulse waveform with a frequency of 26 MHz is output from the waveform shaping circuit 3103 via the output buffer 317 to the baseband signal processing LSI 400. To be supplied.

  The baseband signal processing LSI 400 uses the RF analog signal processing integrated circuit 300 and the front end module 200 to establish GSM or EDGE communication. At that time, the GSM timer 403 (GSM Timer) in the baseband signal processing LSI 400 supplies the system reference clock enable signal SysCLkEn to the RF analog signal processing integrated circuit 300. Then, the system reference clock signal SysCLk based on the output of the system reference clock oscillator 314 of the RF analog signal processing integrated circuit 300 is sent to the GSM timer in the baseband signal processing LSI 400 via the waveform shaping circuit 3103 of the transmission / reception control subunit 310. 403 (GSM Timer). This information is also supplied to the baseband signal processing LSI 400 internal baseband processor core 401 (BB_Pr_Core). Then, the CPU in the baseband processor core 401 starts time slot operation setting in the time division multiple access system via the RF digital interface 402 (Dig_RF_INT) and the digital signal paths L1, L2, L3, and L4. A digital signal processor (DSP) inside the baseband processor core 401 executes signal processing on the received baseband signal processed by the RF received signal analog signal processing subunit 301 of the RF analog signal processing integrated circuit 300. By this signal processing, when communication established in advance is a GSM system, phase demodulation is performed by generating a phase modulation component. As a result of the phase demodulation, an audio signal of the conversation of the communication partner is obtained by the D / A converter 502 (DAC) and the speaker 503 (SP) outside the baseband signal processing LSI 400. On the other hand, an analog audio signal uttered by a user using the mobile terminal apparatus of FIG. 1 is converted into a digital audio signal by a microphone 504 (MIC) and an A / D converter 505 (ADC). A digital signal processor (DSP) in the baseband processor core 401 executes signal processing relating to the digital audio signal. By this signal processing, when the communication established in advance is a GSM system, phase demodulation is executed. As a result, a phase modulation component can be included in the transmission baseband signal to be processed by the RF transmission signal analog signal processing subunit 302 of the RF analog signal processing integrated circuit 300. When the communication established in advance is the EDGE system, the transmission / reception information of communication includes not only the phase modulation component but also the amplitude modulation component, so that the data transfer rate of communication can be improved.

  On the other hand, in the GSM (Global System for Mobile Communication) communication system standard, in order to suppress the level of the interference signal included in the transmission signal, the reference frequency of the system reference clock signal between the mobile phone terminal device and the base station is set. The error is required to be reduced to 0.1 ppm or less. Therefore, even in the mobile terminal apparatus shown in FIG. 1, the error of the 26 MHz oscillation frequency oscillated from the system reference clock oscillator 314 (VCXO) must be 0.1 ppm or less.

  On the other hand, as described above, the RF IC corresponding to the recent GSM communication system needs to correspond to four frequency bands of GSM850, GSM900, DCS1800, and PCS1900. Prior to the present invention, the inventors made a prototype of the digital interface RF IC shown in FIG. 1 and evaluated the characteristics. As a result of the characteristic evaluation, it is clear that the level of the interference signal included in the transmission signals of the two frequency bands DCS1800 and PCS1900, which is the higher of the above four frequency bands, does not achieve the suppression level specified by the GSM standard. It became.

  The present inventors have elucidated the mechanism of the occurrence of this defect as a result of difficult failure analysis.

  That is, as the interface with the baseband LSI of the RF IC changed from an analog interface to a digital interface, the waveform of the system reference clock output signal with an oscillation frequency of 26 MHz also changed from a sine waveform to a pulse waveform. The system reference clock pulse output signal SysCLk_SL having a pulse waveform of a fundamental frequency of 26 MHz of the RF IC of the digital interface includes not only a component of the fundamental frequency of 26 MHz but also harmonic signal components of even and odd times of the fundamental frequency of 26 MHz. In particular, the rising and falling portions of the pulse waveform of the system reference clock pulse output signal SysCLk_SL include harmonic signal components of even and odd times of the high frequency. The harmonics of 66, 67, 68, 72, and 73 times the fundamental frequency of the system reference clock signal of 26 MHz become the harmonics of the following five frequencies.

26MHz × 66 = 1716MHz
26MHz × 67 = 1742MHz
26MHz × 68 = 1768MHz
26 MHz x 72 = 1872 MHz
26MHz × 73 = 1898MHz
The first three harmonics become interference signals to the frequency band of 1710 to 1785 MHz of the transmission frequency signal Tx_DCS1800 of DCS1800, and the last two harmonics are interference signals to the frequency band of 1850 to 1910 MHz of the transmission frequency signal Tx_PCS1900 of PCS1900. It becomes.

  According to the GMSK (Gaussian minimum shift keying) standard of GSM communication, the interference signal level in the RF transmission frequency signal is strictly determined. FIG. 7 shows a frequency spectrum of an RF transmission signal of a mobile phone terminal device defined by the GMSK standard, and a thick solid line PSD is a level defined by the GMSK standard. The amount of attenuation in the vicinity of the center frequency (RF transmission frequency) ± 200 KHz is −30 dBm or less, and the amount of attenuation in the vicinity of the center frequency (RF transmission frequency) ± 400 KHz is −60 dBm or less.

  According to studies by the present inventors, two transmission frequency signal bands of DCS1800 and PCS1900 are caused by interference signals due to harmonics of the five frequencies in the vicinity of 60 to 70 times the basic frequency of the system reference clock signal. It was revealed that the GMSK standard could not be achieved.

  Further, the harmonics of 32, 34, and 35 times the fundamental frequency of the system reference clock signal become harmonics of the following three frequencies.

26 MHz x 32 = 832 MHz
26MHz × 34 = 884MHz
26MHz × 35 = 910MHz
The first harmonic is an interference signal for the GSM850 transmission frequency signal Tx_GSM850 to the frequency band of 824 to 849 MHz, and the last two harmonics are interference signals for the GSM900 transmission frequency signal Tx_GSM900 to the frequency band of 880 to 915 MHz. It becomes. However, the harmonic RF frequency near 30 times 26 MHz of the fundamental frequency of the system reference clock signal is as low as about half of the RF frequency of harmonics near 60 to 70 times the fundamental frequency of the system reference clock signal 26 MHz. . As a result, it has been clarified that the GMSK standard can be achieved in two transmission frequency signal bands of GSM850 and GSM900 by the interference signal caused by the harmonics of the three frequencies near 30 times the basic frequency of 26 MHz of the system reference clock signal. It was.

  As described above, the present invention has been made on the basis of the examination made by the present inventors prior to the present invention and the results of difficult elucidation of the mechanism of occurrence of defects.

  Accordingly, an object of the present invention is an LSI (400) that includes an RF reception signal analog signal processing subunit (301) and an RF transmission signal analog signal processing subunit (302), and performs baseband digital signal processing. This is an RF communication semiconductor integrated circuit 300 (RF_IC) that performs bidirectional signal transfer using a digital interface. The RF reception signal analog signal processing subunit (301) performs frequency down conversion of the RF reception signal to an analog baseband reception signal, and the RF transmission signal analog signal processing subunit (302) is an RF of the analog baseband transmission signal. The frequency up-conversion to the transmission signal is performed. In addition, the RF communication semiconductor integrated circuit 300 (RF_IC) generates a system reference clock signal (SysCLk) for generating a high frequency signal used for the frequency down-conversion and the frequency up-conversion. (314, VCXO). The RF communication semiconductor integrated circuit 300 (RF_IC) generates a system reference clock pulse output signal (SysCLk_SL) in response to the system reference clock signal (SysCLk) oscillated by the system reference clock oscillator (314, VCXO). (400) and an output buffer (317) of the digital interface.

  Based on the above elucidation results, the present inventors set the frequency band of the transmission signal by the harmonics of the system reference clock pulse output signal (SysCLk_SL) supplied from the RF integrated circuit 300 (RF_IC) to the LSI (400). In order to reduce the leakage of the interference signal, the basic technical idea of the present invention is reached, in which the slew rate of the pulse output signal (SysCLk_SL) is controlled. At first glance, the basic technical idea of the present invention is similar to the slew rate control technique described in Non-Patent Document 4.

  However, the slew rate control technique described in Non-Patent Document 4 avoids unwanted interference inside the RF IC by mainly controlling the slew rate of the digital signal supplied from the baseband to the RF IC. Is. On the other hand, the basic technical idea of the present invention is that the frequency band of communication transmission signals of DCS1800 and PCS1900 is generated by the harmonics of the system reference clock pulse output signal supplied from the RF IC to the baseband signal processing LSI. The slew rate of the rising and falling edges of the clock pulse output signal (SysCLk_SL) is controlled in order to reduce the leakage of the interference signal. The undesired signal reduced by the present invention is a serious jamming signal called a jamming signal to the frequency band of the communication transmission signals of DCS1800 and PCS1900, and the slew rate control technique described in Non-Patent Document 4 is used. This is not the level of reduction of undesired interference inside the RF IC, which is the purpose of the above.

  Accordingly, an object of the present invention is to transmit DCS 1800 and PCS 1900 for communication by harmonics of a system reference clock pulse output signal supplied to an LSI that performs baseband digital signal processing from a digital interface of an RF communication semiconductor integrated circuit. The object is to reduce the leakage of interfering signals into the signal frequency band.

  Another object of the present invention is to reduce interference with the RF transmission signal due to harmonics of the system reference clock pulse output signal when supplying the system reference clock pulse output signal from the output buffer to the outside of the chip. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one aspect of the present invention, at least an LSI (400) that performs baseband digital signal processing and an RF communication semiconductor integrated circuit (300) that performs bidirectional signal transfer using a digital interface include: Digital interface units (305, 311, 316, 317). The RF communication semiconductor integrated circuit (300) includes an RF reception signal analog signal processing subunit (301) and an RF transmission signal analog signal processing subunit (302).

  The RF reception signal analog signal processing subunit (301) performs frequency down-conversion of the RF reception signal to analog baseband reception signals (RxABI, RxABQ), and the RF transmission signal analog signal processing subunit (302) is an analog base. Frequency up-conversion of band transmission signals (TxABI, TxABQ) to RF transmission signals is performed.

  The RF communication semiconductor integrated circuit (300) includes a system reference clock oscillator (314, oscillating a system reference clock signal (SysCLk) for generating a high-frequency signal used for the frequency down-conversion and the frequency up-conversion. VCXO). The RF communication semiconductor integrated circuit 300 (RF_IC) generates a system reference clock pulse output signal (SysCLk_SL) in response to the system reference clock signal (SysCLk) oscillated by the system reference clock oscillator (314, VCXO). (400) and an output buffer (317) of a digital interface (see FIG. 1).

  The output buffer (317) is supplied with the system reference clock signal (SysCLk) oscillated by the system reference clock oscillator (314, VCXO) and supplies the system reference clock pulse output signal (SysCLk_SL) to the LSI (400). The buffer circuit (OB_1, OB_2, OB_3... OB_n) to be supplied and the control register (CNT_REG) connected to the buffer circuit (OB_1, OB_2, OB_3... OB_n) are included.

  In the control register (CNT_REG) of the output buffer (317), a control bit for setting the driving capability of the system reference clock pulse output signal (SysCLk_SL) supplied from the output buffer (317) to the LSI (400). The signal is stored.

  The control bit signal of the control register (CNT_REG) is control data (Ctrl Data) supplied from the LSI (400) to the digital interface units (305, 311, 316, 317).

  The system reference clock pulse output signal (SysCLk_SL) so that the level of the interference signal in the RF transmission frequency signal of DCS 1800 and PCS 1900 due to the harmonic of the fundamental frequency of the system reference clock pulse output signal (SysCLk_SL) achieves the GMSK standard. The slew rate of rising (Tr) and falling (Tf) of SysCLk_SL is set by the control bit signal of the control register (CNT_REG) (see FIG. 2).

  According to the means of the above one form, the level of the interference signal in the RF transmission frequency signal of the DCS 1800 and the PCS 1900 due to the harmonic of the fundamental frequency of the system reference clock pulse output signal (SysCLk_SL) can achieve the GMSK standard. In addition, a slew rate of rising (Tr) and falling (Tf) of the system reference clock pulse output signal (SysCLk_SL) is set. Therefore, the level of the interference signal in the RF transmission frequency signal of the DCS 1800 and the PCS 1900 due to the harmonic of the fundamental frequency of the system reference clock pulse output signal (SysCLk_SL) can achieve the GMSK standard. As a result, the interference signal to the frequency band of the DCS1800 and PCS1900 communication transmission signals due to the harmonics of the system reference clock pulse output signal supplied to the LSI that performs baseband digital signal processing from the digital interface of the semiconductor integrated circuit for RF communication Can be reduced.

  In the semiconductor integrated circuit for RF communication (300) according to a preferred embodiment of the present invention, the control data (Ctrl Data) as the control bit signal of the control register (CNT_REG) is received during the initialization process by reset (RST). It is supplied from the LSI (400) to the digital interface units (305, 311, 316, 317) (see FIG. 8).

An RF communication semiconductor integrated circuit (300) according to a preferred embodiment of the present invention includes a phase comparator (f) in which the reference frequency signal (f _REF ) formed from the reference frequency oscillator (314) is supplied to one input terminal. PDC), a charge pump circuit (CPC) responsive to the output of the phase comparator (PDC), and a low pass filter (LFC) responsive to the output of the charge pump circuit (CPC). The RF communication semiconductor integrated circuit (300) includes an RF voltage controlled oscillator (RFVCO) responsive to a control output voltage (VCNT) of the low pass filter (LFC), an output terminal of the RF voltage controlled oscillator (RFVCO), and the It further includes a frequency divider (DIV) connected between the other input terminal of the phase comparator (PDC). The PLL circuit including the phase comparator (PDC), the charge pump circuit (CPC), the low pass filter (LFC), the RF voltage controlled oscillator (RFVCO), and the frequency divider (DIV) includes a frequency synthesizer (Frct_Synth). Constitute. The RF communication semiconductor integrated circuit (300) uses an RF oscillation output signal (f _RFVCO ) of the output terminal of the RF voltage controlled oscillator of the PLL circuit to generate an RF transmission frequency for an RF transmission signal of RF communication. An RF transmission voltage controlled oscillator (TXVCO) for generating a signal is provided. The PLL circuit constituting the frequency synthesizer (Frct_Synth) is a fractional PLL circuit whose average frequency division ratio includes an integer and a fraction by changing the frequency division ratio of the frequency divider (DIV) (FIG. 3). reference).

  According to the above-described means, it is possible to obtain a precise frequency resolution when the RF communication semiconductor integrated circuit performs a transmission / reception operation with the base station. Further, it is possible to satisfy strict standards regarding adjacent interference signals of GMSK in the frequency spectrum of the RF transmission signal of the GSM mobile phone terminal equipment (see FIG. 7).

In the semiconductor integrated circuit for RF communication (300) according to a more preferred embodiment of the present invention, the PLL circuit constituting the frequency synthesizer (Frct_Synth) is configured to output the RF oscillation output signal generated from the RF voltage controlled oscillator (RFVCO). comprising _{(f RFVCO)} intermediate frequency divider for generating an intermediate frequency signal _{(f IF DIV)} by the dividing the (IF DIV). The RF communication semiconductor integrated circuit (300) transmits an intermediate frequency from the intermediate frequency signal (f _{IF DIV} ) generated from the intermediate frequency divider ( _{IF DIV} ) and a transmission baseband signal (TxABI, TXABQ). A transmission mixer (TX-MIX_I, TX-MIX_Q) that forms a signal and a transmission system offset PLL circuit (TX_Offset_PLL) are included. The PLL circuit includes an RF divider (RF DIV) that generates a divided RF frequency signal by _{dividing the} RF oscillation output signal (f _RFVCO ) generated from the RF voltage controlled oscillator (RFVCO). . The transmission system offset PLL circuit (TX_Offset_PLL) includes a phase comparison circuit (PC) in which the intermediate frequency transmission signal generated from the transmission mixer (TX-MIX_I, TX-MIX_Q) is supplied to one input terminal; The RF transmission voltage controlled oscillator (TXVCO) responsive to the output of the phase comparison circuit (PC) is included. In the transmission system offset PLL circuit (TX_Offset_PLL), the RF transmission frequency signal (f _TXVCO ) generated from the RF transmission voltage controlled oscillator (TXVCO) is supplied to one input terminal and the RF divider (RF DIV) is supplied. The frequency-divided RF frequency signal generated from (1) is supplied to the other input terminal, and includes a phase control feedback frequency downmixer (DWN_MIX_PM). The output signal of the frequency down mixer (DWN_MIX_PM) for phase control feedback is supplied to the other input terminal of the phase comparison circuit (PC) (see FIG. 3).

In the RF communication semiconductor integrated circuit (300) according to a further preferred embodiment of the present invention, the RF reception signal analog signal processing subunit (RX SPU) includes low noise amplifiers (LNA1 to LNA4) for amplifying the RF reception signal. The RF reception signal analog signal processing subunit (RX SPU) generates reception baseband signals (RxABI, RxABQ) by being supplied with the RF amplification reception output signals generated by the low noise amplifiers (LNA1 to LNA4). Receiving mixers (RX-MIX_I, RX-MIX_Q) are included. The PLL circuit constituting the frequency synthesizer (Frct_Synth), the RF voltage-controlled oscillator wherein the receiving mixer by the RF oscillation output signal dividing (RX of the oscillation frequency generated from _{(RFVCO) (f} RFVCO) -MIX_I, RX-MIX_Q) A first frequency divider (DIV1) that forms an RF carrier signal to be supplied to the first frequency divider (DIV1) and a second frequency divider (DIV4) that divides the output signal of the first frequency divider (DIV1) Including.

  Assume that the RF communication semiconductor integrated circuit (300) receives the RF reception signal in the GSM850 frequency band or GSM900 frequency band. In this case, the frequency division output signal generated from the first frequency divider (DIV1) is transmitted to the reception mixer (RX-MIX_I, RX-MIX_Q) as the RF carrier signal. Thereby, the reception mixer (RX-MIX_I, RX-MIX_Q) generates reception baseband signals (RxABI, RxABQ) obtained by frequency conversion from the RF reception signal in the frequency band of the GSM850 or the frequency band of the GSM900. Is done.

Assume that the RF communication semiconductor integrated circuit (300) receives the RF reception signal in the frequency band of DCS1800 or the frequency band of PCS1900. In this case, the RF oscillation output signal of the oscillation frequency (f _RFVCO ) generated from the RF voltage controlled oscillator (RFVCO) is transmitted to the reception mixer (RX-MIX_I, RX-MIX_Q) as the RF carrier signal. Is done. Accordingly, reception baseband signals (RxABI, RxABQ) obtained by frequency conversion from the RF reception signal in the frequency band of the DCS 1800 or the frequency band of the PCS 1900 are generated.

Assume that the RF communication semiconductor integrated circuit (300) forms the RF transmission frequency signal in the GSM850 frequency band or the GSM900 frequency band. In this case, the intermediate frequency transmission signal is formed from the intermediate frequency signal and the transmission baseband signal (TxABI, TxABQ) by the transmission mixer (TX-MIX_I, TX-MIX_Q), and the RF divider (RF As the DIV), the first frequency divider (DIV1) and the second frequency divider (DIV4) operate. As a result, the frequency-divided output signal of the second frequency divider (DIV4) is supplied to the other input terminal of the phase control feedback frequency downmixer (DWN_MIX_PM) of the transmission system offset PLL circuit (TX_Offset_PLL). It is transmitted as an RF frequency signal. The transmission frequency offset PLL circuit (TX_Offset_PLL) converts the intermediate frequency transmission signal into the RF transmission frequency signal (f _TXVCO ) in the frequency band of the GSM850 or the frequency band of the GSM900.

Assume that the RF communication semiconductor integrated circuit (300) forms the RF transmission frequency signal in the frequency band of DCS1800 or the frequency band of PCS1900. In this case, the intermediate frequency transmission signal is formed from the intermediate frequency signal and the transmission baseband signal (TxABI, TxABQ) by the transmission mixer (TX-MIX_I, TX-MIX_Q), and the RF divider (RF As the DIV), the first frequency divider (DIV1) operates. As a result, the frequency-divided output signal of the first frequency divider (DIV1) is supplied to the other input terminal of the phase control feedback frequency downmixer (DWN_MIX_PM) of the transmission system offset PLL circuit (TX_Offset_PLL). It is transmitted as an RF frequency signal. The transmission frequency offset PLL circuit (TX_Offset_PLL) converts the frequency of the intermediate frequency transmission signal to the RF transmission frequency signal (f _TXVCO ) in the frequency band of the DCS 1800 or the frequency band of the PCS 1900 (see FIG. 4). .

  According to the further preferred mode of the present invention, reception and transmission of four frequency bands of GSM850, GSM900, DCS1800, and PCS1900 are possible.

  A semiconductor integrated circuit for RF communication (300) according to a more specific form of the present invention is configured in a polar loop system to support an EDGE (Enhanced Data for GSM Evolution; Enhanced Data for GPRS) system. The transmission system offset PLL circuit (TX_Offset_PLL) includes a phase loop (PM LP) for phase modulation of the polar loop system and an amplitude loop (AM LP) of the polar loop system. The phase comparison circuit (PC) of the transmission system offset PLL circuit (TX_Offset_PLL), the RF transmission voltage controlled oscillator (TXVCO), and the phase control feedback frequency downmixer (DWN_MIX_PM) are connected to the phase loop (PM LP). Configure (see FIG. 5).

  According to the means of the more specific form of the present invention, it is possible to cope with the EDGE system with a high communication data transfer rate that uses amplitude modulation for both phase modulation.

  A semiconductor integrated circuit for RF communication (300) according to a more specific form of the present invention is configured by a polar modulator system to support the EDGE system. The transmission system offset PLL circuit (TX_Offset_PLL) includes a phase loop (PM LP) for phase modulation of the polar modulator system and an amplitude loop (AM LP) of the polar modulator system. The phase comparison circuit (PC) of the transmission system offset PLL circuit (TX_Offset_PLL), the RF transmission voltage controlled oscillator (TXVCO), and the phase control feedback frequency downmixer (DWN_MIX_PM) are connected to the phase loop (PM LP). Configure (see FIG. 6).

  According to the means of the more specific form of the present invention, it is possible to cope with the EDGE system with a high communication data transfer rate that uses amplitude modulation for both phase modulation.

  In the semiconductor integrated circuit for RF communication (300) according to another embodiment of the present invention, the RF reception signal analog signal processing subunit (RX SPU) includes low noise amplifiers (LNA1 to LNA4) for amplifying the RF reception signal. . The RF reception signal analog signal processing subunit (RX SPU) is supplied with the RF amplified reception output signal generated by the low noise amplifiers (LNA1 to LNA4) and the reception carrier signal generated by the frequency synthesizer (Frct_Synth). Reception mixers (RX-MIX_I, RX-MIX_Q) for generating reception baseband signals (RxABI, RxABQ). The RF transmission signal analog signal processing subunit (TX SPU) includes transmission mixers (TX-MIX_I, TX-MIX_Q) to which transmission baseband signals (TxABI, TxABQ) are supplied, and the RF transmission signal analog signal processing subunit (TX SPU) is supplied with the transmission carrier signal generated by the frequency synthesizer (Frct_Synth). Accordingly, the RF transmission signal analog signal processing subunit (TX SPU) generates RF transmission signals (Tx_GSM850, Tx_GSM900, Tx_DCS1800, Tx_PCS1900) (see FIG. 4).

  In a semiconductor integrated circuit for RF communication (300) according to a more specific form of the present invention, the fractional PLL circuit includes a ΣΔ modulator (ΣΔMod) for calculating the decimal of the average division ratio (see FIG. 3). ).

  In addition, according to the improved embodiment of the present invention, the output buffer (317) includes a plurality of output buffers (OB_1, OB_2, OB_3, OB_4) to which the system reference clock signal (SysCLk) is supplied in parallel to input terminals. including. The plurality of output buffers include a first output buffer (OB_1) and a second output buffer (OB_2). A first drive capability of the system reference clock pulse output signal (SysCLk_SL) of the first output buffer (OB_1) is set to a predetermined magnitude, and a second drive capability of the second output buffer (OB_2) is set to the first output buffer (OB_2). It is set smaller than the first drive capability of the output buffer (see FIG. 9).

  A first response delay time (τd1) responsive to the system reference clock signal (SysCLk) of the first output buffer (OB_1) is set to a predetermined delay time, and the system reference clock of the second output buffer (OB_2) is set. The second response delay time (τd2) responding to the signal (SysCLk) is set to be smaller than the first response delay time (τd1) of the first output buffer (OB_1).

  According to the means of the improved embodiment of the present invention, the system reference clock pulse output signal (SysCLk_SL) output from the output buffer (OB_1, OB_2, OB_3, OB_4) from a low level to a high level or high The harmonic signal level at the start of the level change from the level to the low level can be significantly reduced (see FIGS. 11 and 12).

  According to a further improved aspect of the present invention, the output buffer further includes a first delay circuit (Inv_1). The first delay circuit (Inv_1) supplies the system reference clock signal (SysCLk) to the input of the first output buffer (OB_1) to form the first response delay time (τd1).

  According to a further improved aspect of the present invention, the plurality of buffer circuits further include intermediate output buffers (OB_3, OB_4). The intermediate drive capability of the intermediate buffer circuits (OB_3, OB_4) is set to a size between the first drive capability of the first output buffer and the second drive capability of the second output buffer (FIG. 9). The intermediate response delay time (τd3, τd4) in response to the system reference clock pulse output signal (SysCLk_SL) of the intermediate buffer circuit (OB_3, OB_4) is equal to the first response delay time of the first output buffer (OB_1). The time is set to the time between the second response delay time of the second output buffer (OB_2) (see FIG. 10).

  Furthermore, according to the most improved mode of the present invention, the buffer circuit further includes intermediate delay circuits (Inv_3, Inv_4). The intermediate delay circuit (Inv_3, Inv_4) supplies the system reference clock signal (SysCLk) to the input of the intermediate output buffer (OB_3, OB_4) to form the intermediate response delay time (τd3, τd4).

  In addition, an RF communication semiconductor integrated circuit (300) according to another embodiment of the present invention includes an RF transmission signal processing subunit that performs frequency up-conversion of analog baseband transmission signals (TxABI, TxABQ) to RF transmission signals ( 302). The integrated circuit (300) includes a system reference clock oscillator (314, VCXO) that generates a system reference clock signal (SysCLk) for generating a high-frequency signal used for the frequency up-conversion. The integrated circuit (300) supplies an output buffer for supplying a system reference clock pulse output signal (SysCLk_SL) in response to the system reference clock signal (SysCLk) oscillated by the system reference clock oscillator (314, VCXO). (317).

  The output buffer (317) includes a plurality of output buffers (OB_1, OB_2, OB_3, OB_4) to which the system reference clock signal (SysCLk) is supplied in parallel to an input terminal, and the system reference clock pulse output signal (SysCLk_SL). And a control register (CNT_REG) for storing control bits (CB0, CB1) for setting the driving capability of the control signal. The plurality of output buffers include a first output buffer (OB_1), a second output buffer (OB_2), and intermediate output buffers (OB_3, OB_4).

  The first drive capability of the system reference clock pulse output signal (SysCLk_SL) of the first output buffer (OB_1) is set to a predetermined magnitude. The second drive capability of the system reference clock pulse output signal (SysCLk_SL) of the second output buffer (OB_2) is set to be smaller than the first drive capability of the first output buffer. The intermediate drive capability of the system reference clock pulse output signal (SysCLk_SL) of the intermediate buffer circuit (OB_3, OB_4) is the first drive capability of the first output buffer and the second drive capability of the second output buffer. Is set to a size between.

  The first output buffer (OB_1) is activated regardless of the value of the control bits (CB0, CB1) stored in the control register (CNT_REG) and is responsive to the system reference clock signal (SysCLk). A system reference clock pulse output signal (SysCLk_SL) can be generated. The second output buffer (OB_2) is activated by a predetermined combination (“10”, “01”, “00”) of the values of the control bits (CB0, CB1) stored in the control register (CNT_REG). The system reference clock pulse output signal (SysCLk_SL) can be generated in response to the system reference clock signal (SysCLk). The intermediate buffer circuit (OB_3, OB_4) is activated by a specific combination (“01”, “00”) of the values of the control bits (CB0, CB1) stored in the control register (CNT_REG). The system reference clock pulse output signal (SysCLk_SL) can be generated in response to the system reference clock signal (SysCLk).

  A first response delay time (τd1) responsive to the system reference clock signal (SysCLk) of the first output buffer (OB_1) is set to a predetermined delay time, and the system reference clock of the second output buffer (OB_2) is set. The second response delay time (τd2) responding to the signal (SysCLk) is set to be smaller than the first response delay time (τd1) of the first output buffer (OB_1). The intermediate response delay time (τd3, τd4) in response to the system reference clock signal (SysCLk) of the intermediate buffer circuit (OB_3, OB_4) is the same as the first response delay time of the first output buffer (OB_1) and the first response delay time. It is set to a time between the second response delay time of the 2-output buffer (OB_2) (see FIGS. 9 and 10).

  According to the means of the other embodiment of the present invention, the pulse output signal (SysCLk_SL) output from the output buffer (OB_1, OB_2, OB_3, OB_4) from a low level to a high level or from a high level. The harmonic signal level at the start of the level change to the low level can be significantly reduced, and the interference with the RF transmission signal can be reduced (see FIGS. 11 and 12).

  According to still another preferable aspect of the present invention, the output buffer further includes a first delay circuit (Inv_1) and intermediate delay circuits (Inv_3, Inv_4). The first delay circuit (Inv_1) supplies the system reference clock signal (SysCLk) to the input of the first output buffer (OB_1) to form the first response delay time (τd1). The intermediate delay circuit (Inv_3, Inv_4) supplies the system reference clock signal (SysCLk) to the input of the intermediate output buffer (OB_3, OB_4) to form the intermediate response delay time (τd3, τd4).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, the frequency of DCS1800 and PCS1900 communication transmission signals due to the harmonics of the system reference clock pulse output signal supplied to the LSI that performs baseband digital signal processing from the digital interface of the RF communication semiconductor integrated circuit. Leakage of interference signals into the band can be reduced.

≪Overall configuration of mobile terminal device≫
FIG. 1 is a diagram illustrating an overall configuration of a mobile terminal apparatus according to an embodiment of the present invention. Here, the mobile terminal device is a mobile phone terminal device, but may be a mobile communication device for a notebook personal computer or a PDA (Personal Digital Assist) device. In the mobile terminal apparatus shown in FIG. 1, A / D converters 303 and 304 and D / A converters 307, 308, and 315 are arranged inside an RF analog signal processing integrated circuit 300 (RF_IC). That is, the A / D converters 303 and 304 digitally output the analog baseband signals RxABI and RxABQ output from the RF reception signal analog signal processing subunit 301 (RX SPU) inside the RF analog signal processing integrated circuit 300 (RF_IC). The baseband signals RxDBI and RxDBQ are converted and supplied to the baseband signal processing LSI 400 (BB_LSI). Further, the D / A converters 307 and 308 convert the quadrature components TxDBI and TxDBQ of the digital baseband transmission signal output from the baseband signal processing LSI 400 (BB_LSI) into analog baseband transmission signals TxABI and TxABQ, respectively, and RF analog signals. This signal is supplied to the RF transmission signal analog signal processing subunit 302 (TX SPU) inside the processing integrated circuit 300 (RF_IC). Furthermore, the AFC control D / A converter 315 (AFCDAC) performs AFC control on the AFC control digital signal output from the baseband processor core 401 obtained in the digital signal path L3 of the RF digital interface 402 of the baseband signal processing LSI 400. The analog signal is converted and supplied to the system reference clock oscillator 314 (VCXO).

  The antenna 100 (ANT) receives a reception signal from a base station having a radio frequency (hereinafter referred to as RF) so that the mobile phone terminal device performs a reception operation from the base station and a transmission operation to the base station. On the other hand, it outputs an RF transmission signal to the base station. The antenna 100 is connected to a front end module 200 (FEM). The front end module 200 has an antenna switch 201 (ANT_SW). When the antenna switch 201 is connected to the upper side, an RF reception signal received by the antenna 100 is, for example, a reception filter 202 (SAW) by a surface acoustic wave device (passes a desired frequency signal and attenuates an interference frequency signal). To be supplied. On the other hand, when the antenna switch 201 is connected to the lower side, the antenna switch 201 is connected to the output of the transmission RF power amplifier 203 (RF_PA). Therefore, an RF transmission signal from the antenna 100 to the base station is output by the RF power output of the transmission RF power amplifier 203. The antenna switch 201 of the front-end module 200 is connected to the upper side in the time slot for the reception operation of the TDMA method (time division multiple access), and is connected to the lower side in the time slot for the transmission operation.

  The RF reception signal output from the reception filter 202 of the front-end module 200 is supplied to the RF reception signal analog signal processing subunit 301 (RX SPU) in the RF analog signal processing integrated circuit 300 (RF_IC) which is an RF analog signal processing unit. Is being supplied to the input. On the other hand, the RF input of the transmission RF power amplifier 203 of the front end module 200 is connected to the output of the RF transmission signal analog signal processing subunit 302 (TX SPU) inside the RF analog signal processing integrated circuit 300.

<< Overall configuration of RF analog signal processing integrated circuit >>
Next, the RF analog signal processing integrated circuit 300 that performs bidirectional signal transfer using the baseband digital LSI 400 and the digital interface will be described in detail.

  The RF analog signal processing integrated circuit 300 first includes an RF reception signal analog signal processing subunit 301 and an RF transmission signal analog signal processing subunit 302. The RF reception signal analog signal processing subunit 301 performs frequency down-conversion of the RF reception signal to the analog baseband reception signals RxABI and RxABQ, and the RF transmission signal analog signal processing subunit 302 performs RF of the analog baseband transmission signals TxABI and TxABQ. Perform frequency up-conversion to the transmitted signal. Further, the RF analog signal processing integrated circuit 300 generates a high frequency signal used for frequency down conversion in the RF reception signal analog signal processing subunit 301 and frequency up conversion in the RF transmission signal analog signal processing subunit 302. A reference frequency oscillator 314 for generating a reference frequency signal of Further, the RF analog signal processing integrated circuit 300 converts the AFC control digital input signal supplied from the baseband LSI 400 into an AFC control analog output signal and controls the frequency of the reference frequency signal generated from the reference frequency oscillator 314. A control D / A converter 315 is further included.

  The RF reception signal analog signal processing subunit 301 inside the RF analog signal processing integrated circuit 300 forms quadrature components RxABI and RxABQ of the analog baseband reception signal from the RF reception signal from the reception filter 202. These quadrature components RxABI and RxABQ are supplied to the inputs of the A / D converter 303 (I_ADC) for the analog baseband received signal I and the A / D converter 304 (Q_ADC) for the analog baseband received signal Q. The The analog baseband reception signals I and Q A / D converters 303 and 304 convert the supplied analog baseband reception signals RxABI and RxABQ into digital baseband reception signals RxDBI and RxDBQ. These digital baseband received signals RxDBI and RxDBQ are supplied to two inputs of a multiplexer 305 (MPX). The multiplexer 305 is connected to a baseband signal processing LSI 400 (BB_LSI) which is a baseband digital signal processing unit via a bidirectional digital signal path L5. Since the bidirectional digital signal path L5 is a single (1 bit) signal line, two digital baseband received signals RxDBI and RxDBQ are supplied to the baseband signal processing LSI 400 in a time division manner in the receiving operation.

  In the transmission operation, the multiplexer 305 performs digital baseband modulation on the digital baseband transmission signal TxDB applied from the baseband signal processing LSI 400 via the bidirectional digital signal path L5 which is a single (1 bit) signal line. Output to the device 306 (Dig_MOD). The digital baseband modulator 306 forms quadrature components TxDBI and TxDBQ of the digital baseband transmission signal from the digital baseband transmission signal TxDB supplied from the multiplexer 305. These orthogonal components TxDBI and TxDBQ are respectively supplied to the inputs of the D / A converter 307 (I_DAC) for the digital baseband transmission signal I and the D / A converter 308 (Q_DAC) for the digital baseband transmission signal Q. The Digital baseband transmission signals I and Q D / A converters 307 and 308 convert the supplied digital baseband transmission signals TxDBI and TxDBQ into analog baseband transmission signals TxABI and TxABQ. These signals TxABI and TxABQ are supplied to the input of the RF transmission signal analog signal processing subunit 302 (TX SPU) inside the RF analog signal processing integrated circuit 300. The RF transmission signal analog signal processing subunit 302 forms an RF transmission signal from the analog baseband transmission signals TxABI and TxABQ, and supplies the RF transmission signal to the RF power input of the RF power amplifier 203 for transmission. The transmission RF power amplifier 203 amplifies the RF power input to generate an RF amplified output signal as an RF power output. The amplification gain of the transmission RF power amplifier 203 is set by the automatic power control voltage Vapc of the ramp signal D / A converter 309 (Ramp DAC) in the RF analog signal processing integrated circuit 300. Not only the operating conditions of the ramp signal D / A converter 309 but also the operating conditions of the RF reception signal analog signal processing subunit 301 and the RF transmission signal analog signal processing subunit 302 are similar to those in the RF analog signal processing integrated circuit 300. Controlled by the transmission / reception control subunit 310 (Rx / Tx_CTRL). The transmission / reception control subunit 310 is connected to the baseband signal processing LSI 400 via the first interface 311 (INT_1), the second interface 312 (INT_2), and digital signal paths L1, L2, L3, and L4.

≪Digital interface of RF analog signal processing integrated circuit≫
The digital signal of the digital signal path L1 is control data (Ctrl Data) supplied from the baseband signal processing LSI 400, and this control data includes a command code for setting operation and control information for command execution. Yes. The digital signal of the digital signal path L2 is a control clock (Ctrl CLk) supplied from the baseband signal processing LSI 400, and this control clock is a synchronization control signal for setting operation. The digital signal of the digital signal path L3 is a control enable signal (Ctrl En) supplied from the baseband signal processing LSI 400. This control enable signal (Ctrl En) is used as a baseband signal when the baseband signal processing LSI 400 sets the operating conditions of the internal circuit of the RF analog signal processing integrated circuit 300 and the transmission / reception operation of the front end module 200. The LSI is driven to a level enabling enabling by the processing LSI 400. On the other hand, the digital signal of the digital signal path L4 is a strobe signal (Strb) used in a special operation mode of operation setting with a plurality of time slots as one setting unit. In this special operation mode, before the strobe signal (Strb) is output to the digital signal path L4, an operation setting is reserved with a plurality of time slots as one setting unit. After the reservation of the operation setting in this special operation mode is completed, the strobe signal (Strb) is supplied to the second interface 312 (INT_2) of the RF analog signal processing integrated circuit 300. The instruction code for which the operation setting is reserved and the control information for executing the instruction are supplied from the transmission / reception control subunit 310 to the RF analog signal processing subunits 301 and 302 and the front-end module 200 at any timing of the time slot. This strobe signal (Strb) is determined.

<< System Reference Clock Oscillator for RF Analog Signal Processing Integrated Circuit >>
The RF analog signal processing integrated circuit 300 has a system reference clock oscillator 314 (VCXO). The oscillation frequency of the system reference clock signal SysCLk based on the output of the system reference clock oscillator 314 includes a crystal oscillator 501 (Xtal) outside the integrated circuit 300 and a D / A converter 315 (AFCDAC) for automatic frequency control (AFC). The AFC control analog signal can be stably maintained. The AFC control digital signal supplied to the D / A converter 315 (AFCDAC) for AFC control is sent to the baseband processor core of the baseband signal processing LSI 400 via the digital signal path L1 to the first interface 311 (INT_1). This is low-speed data of several tens to several hundreds KHz, which is a kind of control data (Ctrl Data) supplied from 401. The baseband processor core 401 of the baseband signal processing LSI 400 corrects an error from the target value 26 MHz of the oscillation frequency of the system reference clock signal SysCLk of the system reference clock oscillator 314 (VCXO) by digital signal processing of the digital baseband signal. A digital AFC control digital signal is generated. Since this AFC control digital signal is converted into an AFC control analog signal by the D / A converter 315 (AFCDAC), the capacity of the variable capacitance element of the system reference clock oscillator 314 (VCXO) is controlled by the AFC control analog signal. As a result, the oscillation frequency of the system reference clock signal SysCLk of the system reference clock oscillator 314 (VCXO) matches the target value of 26 MHz.

≪Transmission and reception operation of mobile terminal device≫
Next, the transmission / reception operation of the mobile terminal device will be described. The baseband signal processing LSI 400 establishes GSM or EDGE communication using the RF analog signal processing integrated circuit 300 and the front end module 200. At that time, the GSM timer 403 (GSM Timer) in the baseband signal processing LSI 400 supplies the system reference clock enable signal SysCLkEn to the input buffer 316 of the RF analog signal processing integrated circuit 300. Then, the system reference clock pulse output signal SysCLk_SL in response to the system reference clock signal SysCLk output from the system reference clock oscillator 314 of the RF analog signal processing integrated circuit 300 is converted into the waveform shaping circuit 3103 and the output buffer 317 of the transmission / reception control subunit 310. To the GSM timer 403 (GSM Timer) in the baseband signal processing LSI 400. This information is also supplied to the baseband signal processing LSI 400 internal baseband processor core 401 (BB_Pr_Core). Then, the CPU in the baseband processor core 401 starts time slot operation setting in the time division multiple access system via the RF digital interface 402 (Dig_RF_INT) and the digital signal paths L1, L2, L3, and L4. A digital signal processor (DSP) inside the baseband processor core 401 executes signal processing on the received baseband signal processed by the RF received signal analog signal processing subunit 301 of the RF analog signal processing integrated circuit 300. By this signal processing, when communication established in advance is a GSM system, phase demodulation is performed by generating a phase modulation component. As a result of the phase demodulation, an audio signal of the conversation of the communication partner is obtained by the D / A converter 502 (DAC) and the speaker 503 (SP) outside the baseband signal processing LSI 400. On the other hand, an analog audio signal uttered by a user using the mobile terminal apparatus of FIG. 1 is converted into a digital audio signal by a microphone 504 (MIC) and an A / D converter 505 (ADC). A digital signal processor (DSP) in the baseband processor core 401 executes signal processing relating to the digital audio signal. By this signal processing, phase demodulation is executed when communication established in advance is a GSM system. As a result, a phase modulation component can be included in the transmission baseband signal to be processed by the RF transmission signal analog signal processing subunit 302 of the RF analog signal processing integrated circuit 300. When the communication established in advance is the EDGE system, the transmission / reception information of communication includes not only the phase modulation component but also the amplitude modulation component, so that the data transfer rate of communication can be improved. The baseband signal processing LSI 400 has an SRAM 404 as a built-in memory, and can be used as a work memory for GSM or EDGE communication.

  The baseband signal processing LSI 400 can be connected to an external nonvolatile memory (not shown) and an application processor (not shown). The application processor is connected to a liquid crystal display device (not shown) and a key input device (not shown), and can execute various application programs including general-purpose programs and games. Phase demodulation and transmission base for GSM reception baseband signals by a boot program (startup initialization program), an operating system program (OS), a digital signal processor (DSP) inside the baseband signal processing LSI 400 of a mobile device such as a cellular phone A program for phase modulation relating to a band signal and various application programs are stored in an external nonvolatile memory.

≪Output buffer that outputs system reference clock pulse output signal≫
FIG. 2 is a circuit diagram showing a configuration of an output buffer 317 that outputs and supplies the system reference clock pulse output signal SysCLk_SL from the digital interface of the RF analog signal processing integrated circuit 300 shown in FIG. 1 to the baseband signal processing LSI 400. .

  The output buffer 317 in FIG. 2 is supplied with a system reference clock signal SysCLk oscillated by a system reference clock oscillator 314 (VCXO), and thereby outputs a plurality of buffer circuits OB_1 of a digital interface that outputs a system reference clock pulse output signal SysCLk_SL. OB_2, OB_3... OB_n are included. A control register CNT_REG is connected to the plurality of buffer circuits OB_1, OB_2, OB_3,. Stored. Output enable signals OE_1, OE_2, OE_3,... OE_n are supplied from the control register CNT_REG to the plurality of buffer circuits OB_1, OB_2, OB_3,. The buffer circuit supplied with the high level output enable signal is activated to contribute to the driving of the system reference clock pulse output signal SysCLk_SL, and the buffer circuit supplied with the low level output enable signal is inactivated. For example, by storing a 3-bit control signal in the control register CNT_REG, eight types of drive capability of the system reference clock pulse output signal SysCLk_SL can be set from the maximum drive capability “000” to the minimum drive capability “111”.

  As shown in the lower part of FIG. 2, one period of the 26 MHz system reference clock pulse output signal SysCLk_SL is 38.462 nSec. In the case of the maximum drive capability “000”, the rising time Tr of the system reference clock pulse output signal SysCLk_SL is set to a minimum of 2 nSec and the fall time Tf is set to a minimum 2 nSec with a load capacity of 10 pF. At this time, the interference level due to harmonic signals of even and odd multiples of the fundamental frequency of 26 MHz is maximized. In the case of the minimum driving capability “111”, the rising time Tr of the system reference clock pulse output signal SysCLk_SL is set to a maximum of 18 nSec and the falling time Tf is set to a maximum of 18 nSec with a load capacity of 10 pF. At this time, the interference level due to harmonic signals of even and odd multiples of the fundamental frequency of 26 MHz is minimized. Therefore, the interference signal level to the transmission signal frequency band of DCS1800 and PCS1900 by the harmonics of 66 times, 67 times, 68 times, 72 times and 73 times of the fundamental frequency 26 MHz of the system reference clock signal satisfies the GMSK standard. The driving ability, that is, the rise time Tr and the fall time Tf may be set. This setting range is a range that satisfies the high-level and low-level pulse widths of the system reference clock pulse output signal SysCLk_SL required by the baseband signal processing LSI 400.

  A control signal of a plurality of bits in the control register CNT_REG is supplied from the baseband LSI 400 via the first interface 311 (INT_1) of the digital interface and the digital signal path L1 during the initialization process by power-on or reset described below. Can. A multi-bit control signal set from the baseband LSI 400 to the control register CNT_REG can be stored in an external nonvolatile memory that stores the various application programs described above.

≪Time slot≫
FIG. 8 is a state transition diagram showing a plurality of operations in which the RF analog signal processing integrated circuit 300 shown in FIG. 1 can be set in one time slot of the time division multiple access method.

  First, the operation state of the RF analog signal processing integrated circuit 300 starts from a reset state 3051 (RST) when the mobile terminal device is powered on or reset by hardware or software, as shown in FIG.

  When the initialization process (initialization process) by this power-on or reset is completed, the operation state of the RF analog signal processing integrated circuit 300 automatically transitions to the idle state 3052 (IDL). Further, during this initialization process, the drive capability of the system reference clock pulse output signal SysCLk_SL of the output buffer 317 is set to any of eight types from the maximum drive capability “000” to the minimum drive capability “111”. In the idle state 3052, the bias currents of the plurality of analog circuits in the RF analog signal processing integrated circuit 300 are set to a minute current, and the control clock signals to the plurality of logic circuits are also in a static state. The entire circuit 300 is in a standby state with extremely low power consumption. Further, the RF analog signal processing integrated circuit 300 in the state where the actual reception operation is completed in the reception state 3054 (Rx) or the state where the actual transmission operation is completed in the transmission state 3055 (Tx) receives the word WRD4. Even so, a transition to the idle state 3052 is possible. That is, even when the instruction code of the word WRD4, which is an instruction to transition to the idle state from the baseband signal processing LSI 400, is received, the operation state of the RF analog signal processing integrated circuit 300 transitions to the idle state 3052. Further, the RF analog signal processing integrated circuit 300 in the warm-up state 3053 described below also receives the instruction code of the word WRD4 that is a transition instruction to the idle state from the baseband signal processing LSI 400, so that the RF analog signal processing integrated circuit The operation state of 300 is changed to the idle state 3052. Therefore, one of the operation states that can be set in one time slot by a control command from the baseband signal processing LSI 400 is an idle state 3052.

  When the RF analog signal processing integrated circuit 300 in the idle state 3052 receives the instruction code of the word WRD1 which is a transition instruction to the warm-up state from the baseband signal processing LSI 400, the operation state of the RF analog signal processing integrated circuit 300 is Transition from the idle state 3052 to the warm-up state 3053 (WARM). This warm-up state 3053 is a preparation period for the next reception state 3054 (Rx) or transmission state 3055 (Tx). That is, using this warm-up state 3053, the RF analog signal processing integrated circuit 300 prepares the operation of the PLL frequency synthesizer for the next reception operation or transmission operation. As will be described in detail later, this PLL frequency synthesizer has a PLL (Phase Locked Loop) circuit. This PLL circuit uses the frequency of the reception carrier signal used in the reception mixer and the transmission carrier used in the transmission mixer based on the stably maintained frequency of the system reference clock signal SysCLk from the output of the system reference clock oscillator 314. Determine the frequency of the signal. Since the PLL circuit includes a delay circuit element, a response time that cannot be ignored is required to stabilize the operation condition after the operation condition is set. For this reason, a warm-up state 3053 is provided. Accordingly, another one of operation states that can be set in one time slot by a control command from the baseband signal processing LSI 400 is a warm-up state 3053.

  When the RF analog signal processing integrated circuit 300 receives the instruction code of the word WRD2 from the baseband signal processing LSI 400 after the warm-up state 3053 that is the preparation period of the transmission state or the reception state, the RF analog signal processing integrated circuit 300 The operation state changes from the warm-up state 3053 to the reception state 3054. When the RF analog signal processing integrated circuit 300 receives the instruction code of the word WRD3 from the baseband signal processing LSI 400, the operation state of the RF analog signal processing integrated circuit 300 transits from the warm-up state 3053 to the transmission state 3055.

  The reception state 3054 has two types of states. One is a real reception state. In this state, the RF received signal analog signal processing subunit 301 of the RF analog signal processing integrated circuit 300 forms digital baseband received signals RxDBI and RxDBQ based on the received radio wave from the base station, and the multiplexer 305 and the bidirectional digital The signal is transferred to the baseband signal processing LSI 400 via the signal path L5. The other is a virtual reception state. In this state, any digital baseband received signal RxDBI, RxDBQ is transmitted from the RF received signal analog signal processing subunit 301 of the RF analog signal processing integrated circuit 300 to the baseband signal processing LSI 400 via the multiplexer 305 and the bidirectional digital signal path L5. Will not be transferred to. This virtual reception state is referred to as a monitor state (Mx) in the embodiment of the present invention. In this monitoring state, for example, the RF reception signal analog signal processing subunit 301 of the RF analog signal processing integrated circuit 300 detects the field intensity of the radio wave transmitted from the base station and received by the mobile phone terminal device. A reception operation of a type different from the reception state is executed. Note that transition to the monitor state (Mx), which is one of the reception states 3054, is also possible by receiving the instruction code of the word WRD2.

≪Fractional N-PLL≫
FIG. 3 shows the configuration of the fractional N-PLL fractional synthesizer Frct_Synth arranged inside the RF analog signal processing integrated circuit 300 (RF_IC) of the mobile terminal apparatus shown in FIG. 1 which is one embodiment of the present invention. FIG.

  The RF analog signal processing integrated circuit 300 (RF_IC) including the fractional N-PLL shown in FIG. 3 can correspond to the quad bands of GSM850, GSM900, DCS1800, and PCS1900 as described in detail in FIG. In particular, when the RF analog signal processing integrated circuit 300 (RF_IC) transmits one of 1710 to 1785 MHz of the transmission frequency signal Tx_DCS1800 of DCS1800 and 1850 to 1910 MHz of the transmission frequency signal Tx_PCS1900 of PCS1900, the system is transmitted to the baseband LSI. The output buffer 317 that supplies the reference clock pulse output signal SysCLk_SL operates favorably. That is, the harmonic signal level from the output buffer 317 is set so that the interference signal level due to the harmonics of the five frequencies in the vicinity of 60 to 70 times the fundamental frequency 26 MHz of the system reference clock signal satisfies the GMSK standard. Has been.

Hereinafter, the fractional N-PLL shown in FIG. 3 will be described in detail. As shown in FIG. 3, the fractional synthesizer Frct_Synth is a stable and accurate reference oscillation frequency based on the crystal oscillator Xtal and the AFC control analog output signal (V _TUNE ) of the AFC control D / A converter 315 (AFCDAC). f Includes a reference frequency oscillator (VCXO) 314 set to _REF . The reference oscillation frequency f _REF is set to a frequency of 26 MHz, for example. The reference frequency signal of the reference oscillation frequency f _REF from the reference frequency oscillator (VCXO) 314 is supplied to one input terminal of the phase comparator PDC of the fractional PLL circuit. The output of the phase comparator PDC is supplied to the RF voltage controlled oscillator RFVCO via the charge pump circuit CPC and the low pass filter LFC. The output of the RF voltage controlled oscillator RFVCO is supplied to the input of the frequency divider DIV, and the frequency division output signal of the frequency divider DIV is supplied to the other input terminal of the phase comparator PDC. A control input terminal for controlling the frequency division ratio of the frequency divider DIV is connected to a frequency division ratio setting logic DRSL. The frequency division ratio setting logic DRSL has channel selection information for RF communication from a baseband LSI (not shown). Channel_inf is supplied. The frequency divider DIV is composed of a counter, and is set, for example, as a control input terminal for controlling the frequency division ratio by counting up the change from low level to high level of the output of the RF voltage controlled oscillator RFVCO from zero. The frequency division output signal of the frequency divider DIV is changed from the low level to the high level at the frequency of the value obtained by subtracting 1 from the value. When the frequency-divided output signal of the frequency divider DIV becomes high level, the count value of the counter is set to zero by the change of the output of the next RF voltage controlled oscillator RFVCO from low level to high level, and the frequency of the frequency divider DIV is divided. The frequency division output signal is returned to the low level, and the next frequency division operation is executed. The frequency division ratio setting logic DRSL includes a frequency division ratio calculator DRALU, a ΣΔ modulator ΣΔMod, and an adder ADD. First, the integer unit Int and the fractional unit Fra of the frequency division ratio calculator DRALU calculate integer value information I and fractional value information F based on the input channel selection information Channel_inf. The integer value information I from the integer unit Int of the division ratio calculator DRALU is supplied to one input terminal of the adder ADD, and the fractional value information F from the fraction unit Fra of the division ratio calculator DRALU is supplied to the ΣΔ modulator ΣΔMod. is supplied to the reference frequency signal from the reference frequency oscillator (VCXO) 314 to ΣΔ modulator ΣΔMod is further supplied as _{f REF} is the operating clock signal. On the other hand, the ΣΔ modulator ΣΔMod holds denominator information G for setting a frequency division ratio as internal information. As an example, the denominator information G is set to 1625. The ΣΔ modulator ΣΔMod generates an output signal F / G having fractional value information F / denominator information G, for example, 403/1625 fraction information from fractional value information F and denominator information G, This is supplied to the other input terminal of the adder ADD. The adder ADD sets the output information of the integer value information I (for example, I = 137) and the output signal F / G to I + F / G, for example, 137+ (403/1625) = 137.248 as the average division ratio N. Supply to frequency divider DIV. As a result, the average frequency division ratio of the frequency divider DIV is set to a value including 137.248, an integer and a fraction (decimal number). Thus, the fractional examination constellation Frct_Synth a reference frequency oscillator (VCXO) 314 reference oscillation frequency _{f REF} 26 MHz and the average frequency division ratio N (137.248) and the RF oscillation of the oscillation frequency _{f RFVCO} of 3568.448MHz that multiplication from Generate an output signal. The average frequency division ratio N will be described in detail. The frequency according to the integer value information I (I = 137) from the integer unit Int of the frequency division ratio calculator DRALU and the output signal F / G from the ΣΔ modulator ΣΔMod. In response to the overflow and 1-bit output generated at (403/1625), the frequency division ratio n of the frequency divider DIV is changed from n (= I = 137) to n + 1 (= I + 1 = 138). Therefore, the frequency at which the frequency division ratio of the frequency divider DIV is n (= I = 137) is 1222/1652 = 75.2%, and the frequency division ratio of the frequency divider DIV is n + 1 (= I + 1 = 138). The frequency is 403/1625 = 24.8%. Therefore, the average frequency division ratio N is 137 × 0.752 + 138 × 0.248 = 137.248.

The frequency control of the transmission system signal processing subunit of the communication semiconductor integrated circuit RF analog signal processing integrated circuit 300 (RF_IC) is performed using a fractional synthesizer Frct_Synth including a reference frequency oscillator (VCXO) 314. Further, the closed loop band of the fractional N-PLL circuit constituting the fractional synthesizer Frct_Synth is set to the order of several tens of KHz which is much lower than 100 KHz. A specific example of this closed loop band is 30 KHz. This transmission system signal processing subunit includes a transmission system offset PLL circuit TX_Offset_PLL. By being supplied to the fractional examination constellation Frct_Synth intermediate frequency divider IF DIV which RF oscillation output signal is set to the division ratio 26 which is the output of the RF voltage controlled oscillator RFVCO oscillation frequency _f RFVCO (3568.448MHz) A doubled intermediate frequency signal (137.248 MHz) is formed from the output of the intermediate frequency divider IF DIV. The double intermediate frequency signal (137.248 MHz) is supplied to the input of the 90 ° phase shifter 90degShift to form two intermediate frequency signals (68.624 MHz) having different 90 ° phases. The transmission mixers TX-MIX_I, TX-MIX_Q are supplied with the baseband transmission signals TxABI, TxABQ and two intermediate frequency signals (68.624 MHz) that are 90 ° out of phase, so that the transmission mixers TX-MIX_I, TX- An intermediate frequency transmission signal (68.624 MHz) obtained by vector synthesis is formed at the output of the adder connected to the output of MIX_Q. This intermediate frequency transmission signal (68.624 MHz) is supplied to one input terminal of the phase comparator PC. The output of the phase comparator PC is supplied to the RF transmission voltage controlled oscillator TXVCO via the low pass filter LF1, so that the frequency of the RF transmission voltage controlled oscillator TXVCO is controlled to about 1715.6 MHz. The oscillation output signal of the RF transmission voltage controlled oscillator TXVCO is supplied to one input terminal of the phase control feedback frequency downmixer DWN_MIX_PM via the buffer amplifier BF, and is supplied to the other input terminal of the phase control feedback frequency downmixer DWN_MIX_PM. The RF signal (1784.2224 MHz) for the downmixer is supplied from the RF frequency divider RF DIV set to the frequency division ratio 2. In the phase control feedback frequency downmixer DWN_MIX_PM, the oscillation signal (approximately 1715.6 MHz) from the RF transmission voltage controlled oscillator TXVCO and the downmixer RF signal (1784.224 MHz) from the RF divider RF DIV are mixed. Is called. Therefore, a feedback signal having a difference frequency of 1784.2224 MHz−1715.6 MHz = 68.624 MHz is formed from the output of the phase control feedback frequency down mixer DWN_MIX_PM and supplied to the other input terminal of the phase comparator PC. The The transmission system offset PLL circuit TX_Offset_PLL performs negative feedback control so that the phase and frequency of the two input signals of the phase comparator PC coincide with each other. As a result, an accurate 1715.6 MHz from the RF transmission voltage control oscillator TXVCO is obtained. A signal having an RF transmission frequency f _TXVCO can be obtained. Further, an intermediate frequency transmission signal f _IF (68.624 MHz) obtained by vector synthesis at the output of the adder connected to the outputs of the transmission mixers TX-MIX_I and TX-MIX_Q is input to one input terminal of the phase comparator PC. Have been supplied. Furthermore, to the other input terminal of the phase comparator PC, RF voltage-controlled oscillator RFVCO oscillation frequency _{f RFVCO} the dividing ratio 2 by dividing the dividing RF oscillation frequency _{f RFVCO} / 2 RF transmission voltage controlled oscillator from TXVCO difference frequency signal obtained by subtracting the frequency _{f TXVCO} of the RF transmission frequency signal _{(f RFVCO / 2-f TXVCO} ) is supplied. Since the negative feedback control of the transmission system offset PLL circuit TX_Offset_PLL matches the reference frequency of one input terminal of the phase comparator PC and the negative feedback frequency of the other input terminal of the phase comparator PC, the following relationship is established. .

_{f IF = f RFVCO / 2-} f TXVCO ... (5 type)
When the above equation is modified, the following equation is obtained.

_{f TXVCO = f RFVCO / 2-} f IF ... (6 type)
= (356.448 MHz / 2)-68.624 MHz
= 1784.224 MHz-68.624 MHz
= 1715.6MHz
Therefore, the RF transmission frequency f _TXVCO generated from the RF transmission voltage controlled oscillator TXVCO inside the transmission system offset PLL circuit TX_Offset_PLL is the oscillation frequency f of the RF oscillation output signal generated from the RF voltage controlled oscillator RFVCO inside the fractional synthesizer Frct_Synth. is set correctly in response to an intermediate frequency transmission signal f _IF output of _RFVCO the connected adders to the output of the transmission mixer. The intermediate frequency transmission signal f _IF is also accurately set by the RF transmission frequency f _TXVCO generated from the RF transmission voltage controlled oscillator TXVCO inside the transmission system offset PLL circuit TX_Offset_PLL.

  On the other hand, the RF transmission signal generated from the RF transmission voltage controlled oscillator TXVCO inside the transmission system offset PLL circuit TX_Offset_PLL is transmitted from the antenna to the base station via the RF power amplifier and the antenna switch.

<< More Specific Embodiment of the Present Invention >>
FIG. 4 is a diagram showing a configuration of an RF analog signal processing integrated circuit RF IC according to a more specific embodiment of the present invention. The RF IC shown in FIG. 4 is configured to correspond to four quad bands of GSM850, GSM900, DCS1800, and PCS1900 in both the reception operation from the base station and the transmission operation to the base station. DCS is an abbreviation for Digital Cellular System, and PCS is an abbreviation for Personal Communication System. In FIG. 4, Frct_Synth is an RF carrier synchronization subunit configured by the fractional PLL circuit or the fractional synthesizer described with reference to FIG.

  The RF IC corresponding to the quad band is composed of the fractional synthesizer Frct_Synth described in FIG. 3, the RF reception signal analog signal processing subunit RX SPU, and the RF transmission signal analog signal processing subunit TX SPU. Has been. The RF reception signal received by the antenna ANT of the cellular phone terminal device is supplied to the RF reception signal analog signal processing unit RX SPU via the antenna switch ANTSW and the surface acoustic wave filter SAW. The RF reception signal analog signal processing subunit RX SPU demodulates the input RF reception signal to generate reception baseband signals RxABI and RxABQ, and supplies the reception baseband signals RxABI and RxABQ to the baseband LSI (BB_LSI). To do. Transmission baseband signals TxABI and TxABQ are supplied from the baseband LSI (BB_LSI) to the RF transmission signal analog signal processing subunit TX SPU. The RF transmission signal analog signal processing subunit TX SPU modulates the input transmission baseband signal to form an RF transmission signal, and the RF power amplifiers RF_PA1, RD_PA2 and the antenna switch ANTSW Supply to antenna ANT.

  First, the reception operation of the RF reception signal analog signal processing subunit RX SPU will be described. An RF reception signal received by an antenna of a mobile phone terminal device is supplied to four low noise amplifiers via an antenna switch ANTSW and a surface acoustic wave filter SAW. The frequency band of the RF reception signal Rx_GSM850 in the GSM850 band is 869 MHz to 894 MHz, and is amplified by the first low noise amplifier LNA1. The frequency band of the RF reception signal Rx_GSM900 in the GSM900 band is 925 MHz to 960 MHz, and is amplified by the second low noise amplifier LNA2. The frequency band of the RF reception signal Rx_DCS1800 in the band of DCS1800 is 1805 MHz to 1880 MHz, and is amplified by the third low noise amplifier LNA3. The frequency band of the RF reception signal Rx_PCS1900 in the band of PCS1900 is 1930 MHz to 1990 MHz, and is amplified by the fourth low noise amplifier LNA4. The RF amplified reception output signals of the four low noise amplifiers LNA1 to LNA4 are supplied to one input terminal of two mixing circuits RX-MIX_I and RX-MIX_Q constituting the reception mixer. Two RF carrier signals having a 90 ° phase formed by a 90 ° phase shifter 90 deg Shift (1/2) are supplied to the other input terminals of the two mixing circuits RX-MIX_I and RX-MIX_Q. In the reception mode of GSM850 or GSM900, the output of the RF voltage controlled oscillator RFVCO is supplied to the 90 ° phase shifter 90degShift (1/2) via the 1/2 frequency divider DIV1 with a frequency division ratio of 2. In the reception mode of DCS 1800 or PCS 1900, the output of the RF voltage controlled oscillator RFVCO is directly supplied to the 90 ° phase shifter 90 deg Shift (1/2). A reception baseband signal RxABI and a reception baseband signal RxABQ are generated from the output of the mixing circuit RX-MIX_I and the output of the mixing circuit RX-MIX_Q, respectively. The received baseband signals RxABI, RxABQ are converted into baseband LSIs via variable gain amplifiers PGI1, PGA1, PGAI3, PGAQ1, PGAQ2, PGAQ3, filter circuits FCI1, FCI2, FCI3, FCQ1, FCQ2, FCQ3, buffer amplifiers BAI, BAQ. BB_LSI).

To accommodate operation of receiving 869MHz~894MHz band frequency band of the RF reception signal Rx_GSM850 of GSM850, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3476MHz～3576MHz. The oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is divided by a quarter by a frequency divider DIV1 (1/2) set to a frequency division ratio of 2 and a 90 ° phase shifter 90 degShift (1/2). The RF frequency-divided frequency signal divided by 869 MHz to 894 MHz is supplied to two mixing circuits RX-MIX_I and RX-MIX_Q constituting the receiving mixer. Accordingly, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_GSM850 of the GSM850 band. To accommodate operation of receiving 925MHz~960MHz band frequency band of the RF reception signal Rx_GSM900 of GSM900, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3700MHz～3840MHz. The oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is divided by a quarter by a frequency divider DIV1 (1/2) set to a frequency division ratio of 2 and a 90 ° phase shifter 90 degShift (1/2). The RF frequency-divided frequency signal frequency-divided by ¼ to 925 MHz to 960 MHz is supplied to two mixing circuits RX-MIX_I and RX-MIX_Q constituting the receiving mixer. Therefore, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_GSM900 of the GSM900 band. Frequency band of the RF reception signal Rx_DCS1800 of DCS1800 is to correspond to the reception operation of 1805MHz～1880MHz, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO is set to 3610MHz～3760MHz. The oscillation frequency _{f RFVCO} of the RF voltage-controlled oscillator RFVCO is 1/2 frequency division by 90 ° phase shifter 90degShift (1/2), RF division frequency signal received mixer is 1/2 frequency-divided into 1805MHz~1880MHz Are supplied to two mixing circuits RX-MIX_I and RX-MIX_Q. Accordingly, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_DCS1800 of the band of DCS1800. Frequency band of the RF reception signal Rx_PCS1900 of PCS1900 is to correspond to the reception operation of 1930MHz～1990MHz, the oscillation frequency _{f RFVCO} of the RF voltage-controlled oscillator RFVCO is set to 3860MHz～3980MHz. The oscillation frequency _{f RFVCO} of the RF voltage-controlled oscillator RFVCO is 1/2 frequency division by 90 ° phase shifter 90degShift (1/2), RF division frequency signal received mixer is 1/2 frequency-divided into 1930MHz~1990MHz Are supplied to two mixing circuits RX-MIX_I and RX-MIX_Q. Accordingly, analog baseband reception signals RxABI and RXABQ are formed from the outputs of the two mixing circuits RX-MIX_I and RX-MIX_Q by receiving the RF reception signal Rx_PCS1900 in the band of PCS1900.

Next, the transmission operation of the RF transmission signal analog signal processing subunit TX SPU will be described. By supplying the RF oscillation output signal of the output of the RF voltage controlled oscillator RFVCO of the fractional synthesizer Frct_Synth to the intermediate frequency divider DIV2 (1 / N _IF ) set to a predetermined division ratio, the intermediate frequency division is performed. A double intermediate frequency signal is formed from the output of the device DIV2 (1 / N _IF ). The double intermediate frequency signal is supplied to the input of the 90 ° phase shifter 90degShift, thereby forming two intermediate frequency signals of 68.624 MHz having different 90 ° phases. The transmission mixers TX-MIX_I and TX-MIX_Q are supplied with the baseband transmission signals TxABI and TxABQ from the baseband LSI (BB_LSI) and two intermediate frequency signals of 68.624 MHz that are 90 ° out of phase. A vector synthesized 68.624 MHz intermediate frequency transmission signal is formed at the output of the adder connected to the outputs of the mixers TX-MIX_I and TX-MIX_Q. The intermediate frequency transmission signal of 68.624 MHz is supplied to one input terminal of the phase comparator PC. The output of the phase comparator PC is supplied to the RF transmission voltage controlled oscillator TXVCO via the low pass filter LPF1, so that the oscillation frequency of the RF transmission voltage controlled oscillator TXVCO is controlled to about 3431.2 MHz. The frequency transmission band of the RF transmission signal Tx_GSM850 in the GSM850 band is 824 MHz to 849 MHz, and the two frequency dividers DIV5 (1 / 2) is supplied to the input of the first RF power amplifier RF_PA1 via the frequency divider DIV3 (1/2). The frequency band of the RF transmission signal Tx_GSM900 in the band of GSM900 is 880 MHz to 915 MHz, and the two frequency dividers DIV5 (1/1) in which the oscillation output signal 3520 MHz to 3660 MHz of the RF transmission voltage controlled oscillator TXVCO is set to the division ratio 2 2) is supplied to the input of the first RF power amplifier RF_PA1 via the frequency divider DIV3 (1/2). The frequency band of the RF transmission signal Tx_DCS1800 in the band of DCS 1800 is 1710 MHz to 1785 MHz, and one frequency divider DIV5 (1/2) in which the oscillation output signal 3420 MHz to 3570 MHz of the RF transmission voltage controlled oscillator TXVCO is set to the division ratio 2 2) to the input of the second RF power amplifier RF_PA2. The frequency band of the RF transmission signal Tx_PCS1900 in the band of PCS1900 is 1850 MHz to 1910 MHz, and one frequency divider DIV5 (1/1) in which the oscillation output signal 3700 MHz to 3820 MHz of the RF transmission voltage-controlled oscillator TXVCO is set to the division ratio 2 2) to the input of the second RF power amplifier RF_PA2.

It is necessary to correspond to the transmission operation of 824 MHz to 848 MHz in the frequency band of the RF transmission signal Tx_GSM850 in the GSM850 band and 880 MHz to 915 MHz in the frequency band of the RF transmission signal Tx_GSM900 in the GSM900 band. Therefore, the oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is transmitted to the transmission system offset PLL circuit TX_Offset_PLL via the two frequency dividers DIV1 (1/2) and DIV4 (1/2) set to the frequency division ratio 2. It is supplied to one input terminal of the phase control feedback frequency down mixer DWN_MIX_PM. Further, an intermediate frequency divider DIV2 connected to a 90 ° phase shifter 90degShift (1/2) connected to two mixing circuits TX-MIX_I and TX-MIX_Q that constitute a transmission mixer of the transmission system offset PLL circuit TX_Offset_PLL ( The frequency division ratio N _IF of 1 / N _IF is set to 26. Accordingly, two frequency dividers DIV5 (1/2) and frequency divider DIV3 (1/2) in which the oscillation output signal of the oscillation frequency f _TXVCO of the RF transmission voltage controlled oscillator TXVCO is set to the frequency division ratio 2 are And supplied to one input terminal of the frequency downmixer DWN_MIX_PM for phase control feedback. At the other input terminal of the frequency down mixer DWN_MIX_PM for phase control feedback, the 1/4 frequency division signal of the oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is divided into two frequency dividers DIV1 (1/2), DIV4 (1 / 2). In the phase control feedback frequency down mixer DWN_MIX_PM, mixing of the 1/4 frequency-divided signal of the oscillation output signal of the oscillation frequency _{f TXVCO} 1/4 divided signal and the RF transmission voltage-controlled oscillator TXVCO of the oscillation frequency _{f RFVCO} row Is called. Therefore, a feedback signal having a frequency difference of (1/4) × f _RFVCO− (1/4) f _TXVCO is formed from the output of the phase control feedback frequency downmixer DWN_MIX_PM, and the phase of the transmission system offset PLL circuit TX_Offset_PLL It is supplied to the other input terminal of the comparator PC. Further, one input terminal of the phase comparator PC is supplied with an intermediate frequency transmission signal f _IF that is vector-synthesized at the output of the adder connected to the outputs of the transmission mixers TX-MIX_I and TX-MIX_Q. . This intermediate frequency transmission signal f _IF is divided into f _RFVCO / 52 by a 1/2 frequency division function with 26 which is a frequency division ratio N _IF of the intermediate frequency divider DIV2 (1 / N _IF ) and a 90 ° phase shifter 90 degShift. It becomes. Since the negative feedback control of the transmission system offset PLL circuit TX_Offset_PLL matches the reference frequency of one input terminal of the phase comparator PC and the negative feedback frequency of the other input terminal of the phase comparator PC, the following relationship is established. .

_{f RFVCO / 52 = (1/4)} × f RFVCO - (1/4) × f TXVCO
_{(1/4) × f TXVCO = (} 1/4) × f RFVCO -f RFVCO / 52
= ((13-1) / 52) * f _RFVCO
= (12/52) × _{f RFVCO
∴f RFVCO = 4.33333 × (1/4)} × f TXVCO
Therefore, it is necessary to cope with the transmission operation of 824 MHz to 848 MHz in the frequency band of the RF transmission signal Tx_GSM850 in the GSM850 band and 880 MHz to 915 MHz in the frequency band of the RF transmission signal Tx_GSM900 in the GSM900 band. Therefore, by setting the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO to 4.33333 times the 1/4 frequency signal of the oscillation frequency _{f TXVCO} of the RF transmission voltage-controlled oscillator _{TXVCO ((1/4) × f TXVCO} ) It ’s fine. Therefore, in response to 824MHz~849MHz the frequency band of the RF transmit signal Tx_GSM850 band GSM850, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3570.6639MHz～3678.9971MHz. In response to 880MHz~915MHz bands the frequency band of the RF transmit signal Tx_GSM900 of GSM900, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3813.3304MHz～3974.997MHz.

It is necessary to cope with the transmission operation of the frequency band 1710 MHz to 1785 MHz of the RF transmission signal Tx_DCS1800 in the band of DCS1800 and the frequency band 1850 MHz to 1910 MHz of the RF transmission signal Tx_PCS1900 in the band of PCS1900. Therefore, the oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is supplied to the frequency down mixer for phase control feedback of the transmission system offset PLL circuit TX_Offset_PLL via one frequency divider DIV1 (1/2) set to the frequency division ratio 2. It is supplied to one input terminal of DWN_MIX_PM. Further, an intermediate frequency divider DIV2 connected to a 90 ° phase shifter 90degShift (1/2) connected to two mixing circuits TX-MIX_I and TX-MIX_Q that constitute a transmission mixer of the transmission system offset PLL circuit TX_Offset_PLL ( The frequency division ratio N _IF of 1 / N _IF is set to 26. Therefore, the frequency control mixer DWN_MIX_PM for phase control feedback passes through one frequency divider DIV5 (1/2) in which the oscillation output signal of the oscillation frequency f _TXVCO of the RF transmission voltage controlled oscillator TXVCO is set to the frequency division ratio 2. Is supplied to one input terminal. A frequency- _divided signal of the oscillation frequency f _RFVCO of the RF voltage controlled oscillator RFVCO is supplied to the other input terminal of the frequency down mixer DWN_MIX_PM for phase control feedback via one frequency divider DIV1 (1/2). Has been. Mixing is carried out in 1/2 divided signal of the oscillation output signal of the oscillation frequency _{f TXVCO} of 1/2 frequency division signal and the RF transmission voltage-controlled oscillator TXVCO of the phase control feedback frequency down mixer DWN_MIX_PM the oscillation frequency _{f RFVCO} . Therefore, a feedback signal having a frequency difference of (1/2) × f _RFVCO− (1/2) × f _TXVCO is formed from the output of the phase control feedback frequency down mixer DWN_MIX_PM, and the transmission system offset PLL circuit TX_Offset_PLL It is supplied to the other input terminal of the phase comparator PC. Further, the one input terminal of the phase comparator PC, transmission mixers TX-MIX_I, TX-MIX_Q intermediate frequency transmit signal _{f IF} which is vector synthesized with the output of the connected adder outputs are supplied. This intermediate frequency transmission signal f _IF is divided into f _RFVCO / 52 by a 1/2 frequency division function with 26 which is a frequency division ratio N _IF of the intermediate frequency divider DIV2 (1 / N _IF ) and a 90 ° phase shifter 90 degShift. It becomes. Since the negative feedback control of the transmission system offset PLL circuit TX_Offset_PLL matches the reference frequency of one input terminal of the phase comparator PC and the negative feedback frequency of the other input terminal of the phase comparator PC, the following relationship is established. .

_{f RFVCO / 52 = (1/2)} × f RFVCO - (1/2) × f TXVCO
_{(1/2) × f TXVCO = (} 1/2) × f RFVCO -f RFVCO / 52
= ((26-1) / 52) × f RFVCO = (25/52) × f RFVCO
_{∴f RFVCO = 2.08 × (1/2)} × f TXVCO
Therefore, it is necessary to cope with the transmission operation of the frequency band 1710 MHz to 1785 MHz of the RF transmission signal Tx_DCS1800 in the band of DCS1800 and the frequency band 1850 MHz to 1910 MHz of the RF transmission signal Tx_PCS1900 in the band of PCS1900. Therefore, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO, set to 2.08 times the 1/2 frequency division signal of the oscillation frequency _{f TXVCO} of the RF transmission voltage-controlled oscillator _{TXVCO ((1/2) × f TXVCO} ) Just do it. Therefore, in response to 1710MHz~1785MHz the frequency band of the RF transmit signal Tx_DCS1800 band DCS1800, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3556.8MHz～3712.8MHz. In response to 1850MHz~1910MHz bands the frequency band of the RF transmit signal Tx_PCS1900 of PCS1900, the oscillation frequency _{f RFVCO} of RF voltage-controlled oscillator RFVCO may be set to 3848MHz～3972.8MHz.

  FIG. 5 is a diagram showing a configuration of an RF analog signal processing integrated circuit RF IC according to a more specific embodiment of the present invention.

  This RF IC employs a polar-loop transmission method for supporting the EDGE method in which communication between a base station and a communication terminal device uses amplitude modulation for both phase modulation.

  One semiconductor chip of the RF IC includes three subunits Frct_Synth, RX SPU, and TX SPU. In addition to the RF IC, FIG. 5 also shows an antenna ANT for transmission / reception of a mobile phone terminal device and a front-end module FEM. The front end module FEM includes an antenna switch ANT_SW, a transmission RF power amplifier RF_PA, and a power coupler CPL for detecting transmission power from the transmission RF power amplifier RF_PA.

In FIG. 5, Frct_Synth is an RF carrier synchronization subunit configured by the fractional PLL circuit or the fractional synthesizer described with reference to FIG. In the RF carrier synchronization subunit Frct_Synth, the fractional frequency synthesizer to which the system reference clock signal from the system reference clock oscillator VCXO in which the oscillation frequency frequency f _REF is stably maintained by the crystal resonator Xtal outside the integrated circuit RF IC is applied. The RF oscillation frequency f RFVCO of the RF oscillator _RFVCO is also maintained stably. The RF output of the RF oscillator RFVCO is supplied to the divider DIV1 (DIV4) (1/2 or 1/4), so that the RF from the output of the divider DIV1 (DIV4) (1/2 or 1/4) is RF. A signal ΦRF is obtained. The RF signal ΦRF is supplied to the RF reception signal analog signal processing subunit RX SPU and the RF transmission signal analog signal processing subunit TX SPU in the communication RF analog signal processing integrated circuit RF IC. That is, the RF transmission signal analog signal processing subunit 302TX SPU is configured in a polar loop system to support the EDGE system.

  In the time slot set to the reception state, the antenna switch ANT_SW of the front end module FEM is connected to the upper side. Therefore, the RF reception signal received by the antenna ANT is supplied to the input of the low noise amplifier LNA of the RF reception signal analog signal processing subunit RX SPU via the reception filter SAW configured by, for example, a surface acoustic wave device. The RF amplified output signal of the low noise amplifier LNA is supplied to one input of two mixing circuits RX-MIX_I and RX-MIX_Q constituting the receiving mixer. The other input of the two mixing circuits RX-MIX_I and RX-MIX_Q has a 90 ° phase shifter 90degShift (1/1 based on the RF signal ΦRF from the frequency divider DIV1 (DIV4) (1/2 or 1/4). Two RF carrier signals having a 90 ° phase formed in 2) are supplied. As a result, in the mixer circuits RX-MIX_I and RX-MIX_Q of the reception mixer, direct down frequency conversion from the RF reception signal frequency to the baseband signal frequency is performed, and reception analog baseband signals RxABI and RxABQ are obtained from the output. The received analog baseband signals RxABI and RxABQ are amplified by variable gain amplifiers PGA1, PGA1, PGA3, PGAQ1, PGAQ2, and PGAQ3 whose gains are adjusted according to the reception time slot setting, and then A / D conversion in the chip of the RF IC Is converted into a digital signal. This digital received signal is supplied to a baseband signal processing LSI (not shown).

In the time slot set to the transmission state, a digital transmission baseband signal is supplied to the RF IC from a baseband signal processing LSI (not shown). As a result, the analog baseband transmission signals TxABI and TxABQ are converted from the output of the D / A converter (not shown) inside the RF IC into two mixing circuits TX-MIX_I of the transmission mixer of the RF transmission signal analog signal processing subunit TX SPU. , TX-MIX_Q. By RF oscillation frequency _{f RFVCO} RF oscillator RFVCO it is divided by an intermediate frequency divider DIV2 (1 _{/ N IF),} an intermediate frequency _{f IF} of the signal ΦIF is obtained. Two IF transmission carrier signals having a 90 ° phase formed by a 90 ° phase shifter 90degShift based on the IF signal ΦIF are supplied to the other inputs of the two mixing circuits TX-MIX_I and TX-MIX_Q. As a result, in the mixer circuits TX-MIX_I and TX-MIX_Q of the transmission mixer, frequency up-conversion from the frequency of the analog baseband transmission signal to the IF transmission signal is executed, and one IF transmission modulation vector-synthesized from the adder A signal is obtained. The IF transmission modulation signal from the adder is supplied to one input of the phase comparator PC constituting the PM loop circuit PM LP for transmitting the phase modulation component of the RF transmission signal analog signal processing subunit TX SPU. In the PM loop circuit PM LP, the output of the phase comparator PC is transmitted to the control input of the transmission oscillator TXVCO via the charge pump CP and the low pass filter LF1.

  The operating voltage from the voltage regulator Vreg is supplied to the buffer amplifier BF whose input is connected to the output of the transmission oscillator TXVCO. The output of the transmission voltage controlled oscillator TXVCO is supplied to the input of the PM loop frequency downmixer DWN_MIX_PM to which the RF signal ΦRF is supplied from the frequency divider DIV1 (DIV4) (1/2 or 1/4), so that DWN_MIX_PM The first IF transmission feedback signal is obtained from the output of. For the phase modulation information when the transmission time slot is GSM, the first IF transmission feedback signal is supplied to the other input of the phase comparator PC constituting the PM loop circuit PM LP via the switch SW_1. As a result, the transmission signal that is the output of the transmission RF power amplifier RF_PA includes accurate phase modulation information of the GSM system. Further, transmission power information (amplification gain of the RF power amplifier RF_PA for transmission) when the transmission time slot is the GSM system is specified by the lamp output voltage Vramp of the ramp signal D / A converter Ramp DAC in the RF IC. This lamp output voltage Vramp is supplied to the 10 MHz filter (10 MHz Filter) via the switch SW2. The lamp output voltage Vramp from this filter and the transmission power detection signal Vdet from the power coupler CPL for detecting the transmission power of the transmission RF power amplifier RF_PA and the power detection circuit PDET are supplied to the error amplifier Err_Amp. By the power supply voltage control or bias voltage control by the automatic power control voltage Vapc from the output of the error amplifier Err_Amp, the amplification gain of the transmission RF power amplifier RF_PA is set in proportion to the distance between the base station and the portable communication terminal device. The digital ramp input signal supplied from the baseband signal processing unit such as the baseband LSI to the ramp signal D / A converter Ramp DAC is a transmission power level indicating signal indicating the level of transmission power. The transmission power level is controlled to be high in proportion to the distance from the communication terminal device. An analog ramp output voltage Vramp is generated from the output of the ramp signal D / A converter Ramp DAC.

  On the other hand, when the transmission time slot is the EDGE system, the IF transmission modulation signal from the adder includes not only phase modulation information but also amplitude modulation information. Therefore, the IF transmission modulation signal from the adder is not only supplied to one input of the phase comparator PC constituting the PM loop circuit PM LP but also one input of the amplitude comparator AC constituting the AM loop circuit AM LP. To be supplied. At this time, the output of the transmission oscillator TXVCO is not supplied to the other input of the phase comparator PC via the PM loop frequency downmixer DWN_MIX_PM. Rather, the information related to the transmission power of the RF power amplifier RF_PA for transmission (RF transmission power level RFPLV) is transmitted through the power coupler CPL, the variable gain circuit MVGA, and the frequency down mixer DWN_MIX_AM for the AM loop to the other of the phase comparator PC. Will be supplied to the input. Further, the information (RF transmission power level RFPLV) related to the transmission power of the transmission RF power amplifier RF_PA is also supplied to the other input of the amplitude comparator AC that constitutes the AM loop circuit AM LP, the power coupler CPL, and the variable gain circuit MVGA. , And AM loop frequency down mixer DWN_MIX_AM. In the AM loop circuit AM LP, the output of the amplitude comparator AC is supplied to the 10 MHz filter (10 MHz Filter) via the low pass filter LF2, the variable gain circuit IVGA, the voltage / current converter V / I, the charge pump CP, and the switch WS2. . As a result, the transmission power signal output from the transmission RF power amplifier RF_PA that amplifies the RF oscillation output signal of the transmission oscillator TXVCO is first included in the PM loop circuit PM LP including accurate EDGE phase modulation information. Further, the AM loop circuit AM LP causes the transmission power signal output from the transmission RF power amplifier RF_PA to include accurate amplitude modulation information of the EDGE system.

  As the power coupler CPL that detects the transmission power of the transmission RF power amplifier RF_PA, a coupler that detects the transmission power of the RF power amplifier RF_PA electromagnetically or capacitively can be used. As this power coupler CPL, a current sense type coupler can also be employed. In this current sense type coupler, a small detection DC / AC operation current proportional to the DC / AC operation current of the final stage power amplification element of the RF power amplifier RF_PA is caused to flow to the detection amplification element.

  In the RF IC of FIG. 5, the control circuit CNTL is such that the gains of the two variable gain circuits MVGA and IVGA of the AM loop circuit AM LP responding to the ramp voltage Vramp of the ramp signal D / A converter Ramp DAC are reversed. Generates two 8-bit control signals in response to the 10-bit digital ramp signal. That is, when the gain of the variable gain circuit MVGA decreases in response to the ramp voltage Vramp, the sum of the gains of the two variable gain circuits MVGA and IVGA becomes substantially constant by increasing the gain of the variable gain circuit IVGA. As a result, the phase margin of the open loop frequency characteristic of the AM loop circuit AM LP is significantly reduced in response to the ramp voltage Vramp.

  FIG. 6 shows an RF IC that is different from the RF IC that employs the polar-loop transmission method shown in FIG. 5 because the communication with the base station corresponds to the EDGE method that uses amplitude modulation for both phase modulation. That is, the RF IC shown in FIG. 6 adopts a polar modulator system transmission method in order to correspond to the EDGE method in which communication with the base station uses amplitude modulation for both phase modulation and RF transmission signal analog signal. The processing subunit TX SPU is configured in a polar modulator system for supporting the EDGE system.

  That is, the amplitude modulation loop control circuit AM_LP for controlling the amplitude of the RF transmission output signal from the transmission RF power amplifier RF_PA based on the transmission intermediate frequency signal formed by the transmission modulation circuits TX_MIX_I and TX_MIX_Q is as follows: It is configured.

  In this AM loop circuit AM LP, the output of the amplitude comparator AC is the low-pass filter LF2, the variable gain circuit IVGA, the voltage / current converter V / I, the output of the buffer amplifier BF via the charge pump CP, and the transmission voltage controlled oscillator. The signal is supplied to an amplitude modulation variable gain amplifier VGA inserted between the TXVCO input and the TXVCO input. One input terminal of the amplitude comparator AC of the AM loop circuit AM LP is supplied with the transmission intermediate frequency signal formed by the transmission modulation circuit (TX_MIX_I, TX_MIX_Q). At the other input terminal of the amplitude comparator AC, information (RF transmission power level RFPLV) related to the transmission power of the transmission RF power amplifier RF_PA is the power coupler CPL, variable gain circuit MVGA, AM loop frequency down mixer DWN_MIX_AM Is supplied through. As a result, it is inserted between the output of the buffer amplifier BF and the input of the transmission voltage controlled oscillator TXVCO so that the IF signal amplitude of the other input terminal matches the IF signal amplitude of one input terminal of the amplitude comparator AC. The gain of the amplitude modulation variable gain amplifier VGA is controlled by the output of the amplitude comparator AC via the low-pass filter LF2, the variable gain circuit IVGA, the voltage / current converter V / I, and the charge pump CP. As a result, the transmission power of the transmission RF power amplifier RF_PA includes accurate amplitude modulation information of the EDGE method.

  In both the GSM system and the EDGE system, the ramp output voltage Vramp of the ramp signal D / A converter Ramp DAC, the power coupler CPL that detects the transmission power of the transmission RF power amplifier 203, and the power detection circuit PDET The transmission power detection signal Vdet from is supplied to the error amplifier Err_Amp. By the power supply voltage control or bias voltage control using the automatic power control voltage Vapc from the output of the error amplifier Err_Amp, the amplification gain of the RF power amplifier RF_PA for transmission is set in proportion to the distance between the base station and the portable communication terminal device. Control is performed.

≪Improved output buffer≫
FIG. 9 is a circuit diagram showing a configuration of an output buffer 317 further improved from the output buffer 317 of FIG. The output buffer 317 shown in FIG. 9 also outputs and supplies the system reference clock pulse output signal SysCLk_SL to the baseband signal processing LSI 400 from the digital interface of the RF analog signal processing integrated circuit 300 shown in FIG.

  Similarly to FIG. 2, the 2-bit control signals CB0 and CB1 from the control register CNT_REG for setting the drive capability are supplied to the control gates G2, G3, and G4 of the output buffer 317 shown in FIG. The other control gate G1 is supplied with the enable control signal EN and the system reference clock signal SysCLk oscillated by the system reference clock oscillator 314 (VCXO) of FIG. The clock output of the control gate G1 is supplied to the input terminal of the delay circuit DL_Ckt via the buffer. The delay circuit DL_Ckt includes a plurality of delay circuits Inv_1, Inv_3, and Inv_4, and supplies delayed clock output signals from the plurality of delay circuits to a plurality of input terminals of the output buffer OB. The output buffer 317 (OB) includes a plurality of output buffers OB_1, OB_2, OB_3, and OB_4 to which the system reference clock signal SysCLk is supplied in parallel to the input terminals via the delay circuit DL_Ckt. That is, the output buffer 317 (OB) includes a first output buffer OB_1, a second output buffer OB_2, an intermediate third output buffer OB_3, and a fourth output buffer OB_4. The first drive capability of the system reference clock pulse output signal SysCLk_SL of the first output buffer OB_1 is set to a maximum magnitude, and the second drive capability of the second output buffer OB_2 is greater than the first drive capability of the first output buffer OB_1. It is set to a small minimum driving capacity. The fourth drive capability of the system reference clock pulse output signal SysCLk_SL of the fourth output buffer OB_4 is set to a value next to the first drive capability, and the third drive capability of the third output buffer OB_3 is the second output buffer OB_2. 2 It is set to the next smallest value after the driving ability.

  The system reference clock signal is input to the input terminal of the second output buffer OB_2 having the minimum driving capability inside the output buffer 317 (OB) with the second response delay time τd2 set to the shortest delay time from the delay circuit DL_Ckt. SysCLk is supplied. A third response delay set to the third longest delay time by the delay circuit Inv_3 of the delay circuit DL_Ckt is input to the input terminal of the third output buffer OB_3 having the second smallest driving capability inside the output buffer 317 (OB). The system reference clock signal SysCLk is supplied at time τd3. The third response delay set to the second longest delay time by the delay circuit Inv_4 of the delay circuit DL_Ckt is input to the input terminal of the fourth output buffer OB_4 having the second largest driving capability inside the output buffer 317 (OB). The system reference clock signal SysCLk is supplied at time τd4. The input terminal of the first output buffer OB_1 having the maximum driving capability inside the output buffer 317 (OB) has a first response delay time τd1 set to the longest delay time by the delay circuit Inv_1 of the delay circuit DL_Ckt. A reference clock signal SysCLk is supplied.

  As shown in the table below the circuit diagram of FIG. 9, when the control bits CB0 and CB1 stored in the control register CNT_REG are any one of “10”, “01”, and “00”, the control gate G2 The second output buffer OB_2 is activated by the high-level second output enable signal OE_2. The activated second output buffer OB_2 outputs and supplies the system reference clock pulse output signal SysCLk_SL to the output pad O_Pad in response to the system reference clock signal SysCLk. When the control bits CB0 and CB1 stored in the control register CNT_REG are either "01" or "00", the third output buffer OB_3 is activated by the high-level third output enable signal OE_3 from the control gate G3. Is done. The activated third output buffer OB_3 outputs and supplies the system reference clock pulse output signal SysCLk_SL to the output pad O_Pad in response to the system reference clock signal SysCLk. When the control bits CB0 and CB1 stored in the control register CNT_REG are “00”, the fourth output buffer OB_4 is activated by the high-level fourth output enable signal OE_4 from the control gate G4. The activated fourth output buffer OB_4 outputs and supplies the system reference clock pulse output signal SysCLk_SL to the output pad O_Pad in response to the system reference clock signal SysCLk. The first output buffer OB_1 is activated by the first output enable signal OE_1 having the high level of the power supply voltage Vdd regardless of the control bit stored in the control register CNT_REG. The activated first output buffer OB_1 outputs and supplies the system reference clock pulse output signal SysCLk_SL to the output pad O_Pad in response to the system reference clock signal SysCLk.

  Note that the drive capability of the first output buffer OB_1, the second output buffer OB_2, the third output buffer OB_3, and the fourth output buffer OB_4 of the output buffer 317 (OB) depends on the pull-up P-channel MOSFET of each output buffer. The size and the size of the pull-down N-channel MOSFET can be set.

  Therefore, the upper column, middle column, and lower column of the table below the circuit diagram of FIG. 9 respectively indicate the minimum, intermediate, and maximum states of the output buffer 317 (OB) as a whole. .

  FIG. 10 is a waveform diagram showing how the output buffer 317 shown in FIG. 9 outputs the voltage waveform of the system reference clock pulse output signal SysCLk_SL to the output pad O_Pad in response to the change in the waveform of the system reference clock signal SysCLk. The vertical axis in FIG. 10 indicates the voltage of the system reference clock pulse output signal SysCLk_SL, and the horizontal axis in FIG. The time T on the horizontal axis in FIG. 10 is zero when the system reference clock signal SysCLk as an input changes from low level to high level.

  When the control bits CB0 and CB1 stored in the control register CNT_REG are any one of “10”, “01”, and “00”, the second output enable signal OE_2 having a high level from the control gate G2 Assume that the output buffer OB_2 is activated. A system reference clock pulse is generated from the second response delay time τd2 set to the shortest delay time by the second output buffer OB_2 having the minimum driving capability inside the output buffer 317 (OB) as shown by the line OB_2 in FIG. The voltage of the output signal SysCLk_SL starts to rise at the smallest change rate. When the control bits CB0 and CB1 stored in the control register CNT_REG are either “01” or “00”, the third output buffer OB_3 is set by the high-level third output enable signal OE_3 from the control gate G3. Assume that it is activated. From the third response delay time τd3 set to the second shortest delay time by the third output buffer OB_3 having the second smallest driving capability inside the output buffer 317 (OB), as shown by the line OB_3 in FIG. The voltage of the system reference clock pulse output signal SysCLk_SL starts increasing at the second smallest change rate. Assume that the control bits CB0 and CB1 stored in the control register CNT_REG are “00” and the fourth output buffer OB_4 is activated by the high-level fourth output enable signal OE_4 from the control gate G4. To do. As shown by the line OB_4 in FIG. 10 from the fourth response delay time τd4 set to the second longest delay time by the fourth output buffer OB_4 having the second largest driving capability inside the output buffer 317 (OB). The voltage of the system reference clock pulse output signal SysCLk_SL starts increasing at the second largest change rate. As shown in the line OB_1 in FIG. 10 from the first response delay time τd1 set to the longest delay time by the first output buffer OB_1 having the maximum drive capability inside the output buffer 317 (OB) and always activated. At the same time, the voltage of the system reference clock pulse output signal SysCLk_SL starts to rise at the first largest change rate.

  When only the first output buffer OB_1 having the maximum drive capability is activated by the combination of the values of the control bits CB0 and CB1 stored in the control register CNT_REG, the overall drive capability of the output buffer 317 (OB) is The harmonic level included in the output voltage of the system reference clock pulse output signal SysCLk_SL is relatively low.

  Depending on the combination of the values of control bits CB0 and CB1 stored in the control register CNT_REG, the second output buffer OB_2 having the smallest driving capability, the third output buffer OB_3 having the second smallest driving capability, and the second largest driving capability When the fourth output buffer OB_4 having the same is activated one after another, the overall drive capability of the output buffer 317 (OB) increases, and the harmonic level included in the output voltage of the system reference clock pulse output signal SysCLk_SL Will also increase. However, in this case, since the operation start timing of the four output buffers OB_2, OB_3, OB_4, and OB_1 differs depending on the four response delay times τd2, τd3, τd4, and τd1, the increase in the harmonic level is reduced. can do.

  FIG. 11 shows a voltage waveform of the system reference clock pulse output signal SysCLk_SL obtained at the output pad O_Pad when all of the plurality of delay circuits Inv_1, Inv_3, and Inv_4 of the delay circuit DL_Ckt of the output buffer 317 shown in FIG. 9 are omitted. It is a waveform diagram. In this case, when all the four output buffers OB_2, OB_3, OB_4, and OB_1 are activated, the four output buffers OB_2, OB_3, OB_4, and OB_1 are output from the output pad O_Pad at the same operation start timing. Initiate a change in voltage rise and fall. The voltage change at the change point indicated by the circle from the low level to the high level and the change point indicated by the circle from the high level to the low level of the output voltage of the output pad O_Pad in FIG. It will increase.

  FIG. 12 shows a voltage waveform of the system reference clock pulse output signal SysCLk_SL obtained at the output pad O_Pad when all of the plurality of delay circuits Inv_1, Inv_3, Inv_4 of the delay circuit DL_Ckt of the output buffer 317 shown in FIG. 9 are connected. It is a waveform diagram. In this case, since four different response delay times τd2, τd3, τd4, and τd1 are formed, when all of the four output buffers OB_2, OB_3, OB_4, and OB_1 are activated, the four output buffers OB_2, OB_3, OB_4, and OB_1 start changing the rise and fall of the output voltage of the output pad O_Pad at four different response delay times τd2, τd3, τd4, and τd1, respectively. The voltage change at the change point indicated by the circle from the low level to the high level and the change point indicated by the circle from the high level to the low level of the output voltage of the output pad O_Pad in FIG. Is alleviated.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  In the above embodiment, the baseband signal processing LSI 400 and the application processor are configured by different semiconductor chips. However, in another embodiment, the application processor is integrated in the semiconductor chip of the baseband signal processing LSI 400. One chip can be used.

FIG. 1 is a diagram showing the overall configuration of a mobile terminal device equipped with a digital interface RF IC and a baseband LSI, which have been studied by the present inventors prior to the present invention, and is one embodiment of the present invention. It is a figure which shows the whole structure of the mobile terminal device by a form. FIG. 2 is a circuit diagram showing a configuration of an output buffer that outputs and supplies a system reference clock pulse output signal from the digital interface of the RF analog signal processing integrated circuit shown in FIG. 1 to the baseband signal processing LSI. FIG. 3 is a diagram showing a configuration of a fractional N-PLL fractional synthesizer arranged inside the RF analog signal processing integrated circuit of the mobile terminal apparatus shown in FIG. 1 which is one embodiment of the present invention. FIG. 4 is a diagram showing a configuration of an RF analog signal processing integrated circuit according to a more specific embodiment of the present invention. FIG. 5 is a diagram showing a configuration of an RF analog signal processing integrated circuit according to a more specific embodiment of the present invention. FIG. 6 is a diagram showing a configuration of an RF analog signal processing integrated circuit according to a more specific embodiment of the present invention. FIG. 7 is a diagram showing a frequency spectrum of an RF transmission signal of a mobile phone terminal device defined by the GMSK standard. FIG. 8 is a state transition diagram showing a plurality of operations in which the RF analog signal processing integrated circuit shown in FIG. 1 can be set in one time slot of the time division multiple access method. FIG. 9 is a circuit diagram showing a configuration of an output buffer further improved than the output buffer of FIG. FIG. 10 is a waveform diagram showing how the output buffer shown in FIG. 9 outputs the voltage waveform of the system reference clock pulse output signal to the output pad in response to the change in the waveform of the system reference clock signal. FIG. 11 is a waveform diagram showing the voltage waveform of the system reference clock pulse output signal obtained at the output pad when all of the plurality of delay circuits of the delay circuit of the output buffer shown in FIG. 9 are omitted. FIG. 12 is a waveform diagram showing the voltage waveform of the system reference clock pulse output signal obtained at the output pad when all of the plurality of delay circuits of the delay circuit of the output buffer shown in FIG. 9 are connected.

Explanation of symbols

100 Antenna 200 Front End Module 300 RF Analog Signal Processing Integrated Circuit 310 Transmission / Reception Control Subunit 301 RF Reception Signal Analog Signal Processing Subunit 302 RF Transmission Signal Analog Signal Processing Subunit 314 Reference Frequency Oscillator (VCXO)
315 A / D converter D / A converter 317 Output buffer 400 Baseband signal processing LSI 400
SysCLk System reference clock signal SysCLk_SL System reference clock pulse output signals OB_1, OB_2, OB_3... OB_n Buffer circuit CNT_REG Control register Tr Rising time Tf Falling time

Claims (15)

An LSI for performing baseband digital signal processing and a digital interface unit for bidirectional signal transfer;
RF received signal analog signal processing subunit;
RF transmission signal analog signal processing subunit,
The RF reception signal analog signal processing subunit performs frequency down-conversion of the RF reception signal to an analog baseband reception signal, and the RF transmission signal analog signal processing subunit increases the frequency of the analog baseband transmission signal to the RF transmission signal. A semiconductor integrated circuit for RF communication that performs conversion,
The RF communication semiconductor integrated circuit includes a system reference clock oscillator that oscillates a system reference clock signal for generating a high-frequency signal used for the frequency down-conversion and the frequency up-conversion, and the system reference clock oscillator oscillates. An output buffer of a digital interface that supplies a system reference clock pulse output signal responsive to the system reference clock signal to the LSI,
The output buffer includes a buffer circuit that is supplied with the system reference clock signal oscillated by the system reference clock oscillator and supplies the system reference clock pulse output signal to the LSI, and a control register connected to the buffer circuit. Including
The control register of the output buffer stores a control bit signal that sets the drive capability of the system reference clock pulse output signal supplied from the output buffer to the LSI,
The control bit signal of the control register is control data supplied from the LSI to the digital interface unit,
The rise and fall of the system reference clock pulse output signal so that the interference signal level in the RF transmission frequency signal of the DCS 1800 and PCS 1900 due to the harmonic of the fundamental frequency of the system reference clock pulse output signal achieves the GMSK standard. A semiconductor integrated circuit for RF communication in which a falling slew rate is set by the control bit signal of the control register.   2. The semiconductor integrated circuit for RF communication according to claim 1, wherein the control data as the control bit signal of the control register is supplied from the LSI to the digital interface unit during initialization processing by reset. A phase comparator in which the reference frequency signal formed from the reference frequency oscillator is supplied to one input terminal, a charge pump circuit responsive to the output of the phase comparator, and a low pass responsive to the output of the charge pump circuit A filter, an RF voltage controlled oscillator responsive to the control output voltage of the low pass filter, and a frequency divider connected between the output terminal of the RF voltage controlled oscillator and the other input terminal of the phase comparator. By using the PLL circuit constituting the frequency synthesizer and the RF oscillation output signal of the output terminal of the RF voltage controlled oscillator of the PLL circuit, an RF transmission frequency signal for an RF transmission signal for RF communication is generated. A voltage-controlled oscillator for transmission,
2. The semiconductor device for RF communication according to claim 1, wherein the PLL circuit constituting the frequency synthesizer is a fractional PLL circuit in which an average frequency division ratio includes an integer and a fraction by changing a frequency division ratio of the frequency divider. Integrated circuit. The PLL circuit constituting the frequency synthesizer includes an intermediate frequency divider that generates an intermediate frequency signal by dividing the RF oscillation output signal generated from the RF voltage controlled oscillator,
The RF communication semiconductor integrated circuit includes a transmission mixer that forms an intermediate frequency transmission signal from the intermediate frequency signal generated from the intermediate frequency divider and a transmission baseband signal, a transmission system offset PLL circuit, and the RF An RF divider that generates a divided RF frequency signal by dividing the RF oscillation output signal generated from the voltage controlled oscillator;
The transmission system offset PLL circuit includes a phase comparison circuit to which the intermediate frequency transmission signal generated from the transmission mixer is supplied to one input terminal, and the RF transmission voltage controlled oscillator that responds to an output of the phase comparison circuit The RF transmission frequency signal generated from the RF transmission voltage controlled oscillator is supplied to one input terminal, and the divided RF frequency signal generated from the RF divider is supplied to the other input terminal. 4. The semiconductor integrated circuit for RF communication according to claim 3, further comprising: a frequency down mixer for phase control feedback, wherein an output signal of the frequency down mixer for phase control feedback is supplied to the other input terminal of the phase comparison circuit. The RF reception signal analog signal processing subunit includes a low noise amplifier that amplifies the RF reception signal, and a reception mixer that generates a reception baseband signal by being supplied with the RF amplification reception output signal generated by the low noise amplifier. Including
The PLL circuit constituting the frequency synthesizer divides the RF oscillation output signal of the oscillation frequency generated from the RF voltage controlled oscillator to form an RF carrier signal to be supplied to the reception mixer. A frequency divider, and a second frequency divider that divides the output signal of the first frequency divider,
When the RF communication semiconductor integrated circuit receives the RF reception signal in the GSM850 frequency band or GSM900 frequency band, the divided output signal generated from the first frequency divider is the RF carrier signal. By being transmitted to the reception mixer, a reception baseband signal that is frequency-converted from the RF reception signal in the frequency band of the GSM850 or the frequency band of the GSM900 is generated from the reception mixer,
When the RF communication semiconductor integrated circuit receives the RF reception signal in the frequency band of DCS1800 or the frequency band of PCS1900, the RF oscillation output signal of the oscillation frequency generated from the RF voltage controlled oscillator is the RF By being transmitted to the reception mixer as a carrier signal, a reception baseband signal that is frequency-converted from the RF reception signal in the frequency band of the DCS 1800 or the frequency band of the PCS 1900 is generated,
When the RF communication semiconductor integrated circuit forms the RF transmission frequency signal in the GSM850 frequency band or the GSM900 frequency band, the intermediate frequency transmission signal is generated from the intermediate frequency signal and the transmission baseband signal by the transmission mixer. And the first frequency divider and the second frequency divider operate as the RF frequency divider so that the frequency-divided output signal of the second frequency divider is the value of the transmission system offset PLL circuit. The frequency-divided RF frequency signal is transmitted to the other input terminal of the phase control feedback frequency downmixer, and the intermediate frequency transmission signal is transmitted to the frequency band of the GSM850 or the frequency of the GSM900 by the transmission system offset PLL circuit. Frequency converted to the RF transmission frequency signal of the band,
When the RF communication semiconductor integrated circuit forms the RF transmission frequency signal in the DCS1800 frequency band or the PCS1900 frequency band, the intermediate frequency transmission signal is generated from the intermediate frequency signal and the transmission baseband signal by the transmission mixer. And the first frequency divider operates as the RF frequency divider so that the frequency division output signal of the first frequency divider is the frequency of the phase control feedback frequency downmixer of the transmission system offset PLL circuit. The frequency-divided RF frequency signal is transmitted to the other input terminal, and the intermediate frequency transmission signal is transmitted to the RF transmission frequency signal in the frequency band of the DCS 1800 or the frequency band of the PCS 1900 in the transmission system offset PLL circuit. 5. The semiconductor integrated circuit for RF communication according to claim 4, wherein the frequency is converted. The semiconductor integrated circuit for RF communication is configured by a polar loop system to support the EDGE system,
The transmission system offset PLL circuit includes a phase loop for phase modulation of the polar loop system and an amplitude loop of the polar loop system,
6. The RF according to claim 4, wherein the phase comparison circuit of the transmission system offset PLL circuit, the RF transmission voltage-controlled oscillator, and the phase-controlled feedback frequency downmixer constitute the phase loop. Semiconductor integrated circuit for communication. The RF communication semiconductor integrated circuit is configured by a polar modulator system to support the EDGE system,
The transmission system offset PLL circuit includes a phase loop for the phase modulation of the polar modulator system and an amplitude loop of the polar modulator system,
6. The RF according to claim 4, wherein the phase comparison circuit of the transmission system offset PLL circuit, the RF transmission voltage-controlled oscillator, and the phase-controlled feedback frequency downmixer constitute the phase loop. Semiconductor integrated circuit for communication. The RF reception signal analog signal processing subunit is supplied with a low noise amplifier that amplifies the RF reception signal, an RF amplification reception output signal generated by the low noise amplifier, and a reception carrier signal generated by the frequency synthesizer. And a receiving mixer for generating a received baseband signal,
The RF transmission signal analog signal processing subunit includes a transmission mixer to which a transmission baseband signal is supplied, and a transmission carrier signal generated by the frequency synthesizer is supplied to the RF transmission signal analog signal processing subunit. 6. The semiconductor integrated circuit for RF communication according to claim 4, wherein the RF transmission signal analog signal processing subunit generates an RF transmission signal.   9. The semiconductor integrated circuit for RF communication according to claim 4, wherein the fractional PLL circuit includes a [Sigma] [Delta] modulator for calculating the decimal of the average frequency dividing ratio. The output buffer includes a plurality of output buffers to which the system reference clock signal is supplied in parallel to input terminals;
The plurality of output buffers include a first output buffer and a second output buffer;
The first drive capability of the system reference clock pulse output signal of the first output buffer is set to a predetermined magnitude, and the second drive capability of the second output buffer is greater than the first drive capability of the first output buffer. Is set too small,
A first response delay time responsive to the system reference clock signal of the first output buffer is set to a predetermined delay time, and a second response delay time responsive to the system reference clock signal of the second output buffer is the first response delay time. 2. The semiconductor integrated circuit for RF communication according to claim 1, wherein the semiconductor integrated circuit is set smaller than the first response delay time of one output buffer.   11. The output buffer further includes a first delay circuit, and the first delay circuit supplies the system reference clock signal to an input of the first output buffer to form the first response delay time. Semiconductor integrated circuit for RF communication.   The plurality of buffer circuits further include an intermediate output buffer, and the intermediate drive capability of the intermediate buffer circuit is between the first drive capability of the first output buffer and the second drive capability of the second output buffer. The intermediate response delay time set to a magnitude and responsive to the system reference clock pulse output signal of the intermediate buffer circuit is the first response delay time of the first output buffer and the second response buffer of the second output buffer. 12. The semiconductor integrated circuit for RF communication according to claim 11, wherein the time is set to a time between the delay times.   The RF buffer according to claim 12, wherein the buffer circuit further includes an intermediate delay circuit, and the intermediate delay circuit supplies the system reference clock signal to an input of the intermediate output buffer to form the intermediate response delay time. Semiconductor integrated circuit. An RF transmission signal processing subunit that performs frequency up-conversion of an analog baseband transmission signal to an RF transmission signal;
A system reference clock oscillator for oscillating a system reference clock signal for generating a high-frequency signal used for the frequency up-conversion;
An output buffer for supplying a system reference clock pulse output signal responsive to the system reference clock signal oscillated by the system reference clock oscillator to the outside of the chip;
The output buffer includes a plurality of output buffers to which the system reference clock signal is supplied in parallel to an input terminal, and a control register for storing a control bit for setting a driving capability of the system reference clock pulse output signal,
The plurality of output buffers include a first output buffer, a second output buffer, and an intermediate output buffer;
The first drive capability of the system reference clock pulse output signal of the first output buffer is set to a predetermined magnitude, and the second drive capability of the system reference clock pulse output signal of the second output buffer is set to the first output. The intermediate driving capability of the system reference clock pulse output signal of the intermediate buffer circuit is set smaller than the first driving capability of the buffer, and the first driving capability of the first output buffer and the second driving buffer of the second output buffer Is set to a size between two drive capacities,
The first output buffer may be activated regardless of the value of the control bit stored in the control register to generate the system reference clock pulse output signal in response to the system reference clock signal; The second output buffer is activated by a predetermined combination of values of the control bits stored in the control register, and can generate the system reference clock pulse output signal in response to the system reference clock signal. And the intermediate buffer circuit is activated by a specific combination of values of the control bits stored in the control register to generate the system reference clock pulse output signal in response to the system reference clock signal And
A first response delay time responsive to the system reference clock signal of the first output buffer is set to a predetermined delay time, and a second response delay time responsive to the system reference clock signal of the second output buffer is the first response delay time. An intermediate response delay time that is set smaller than the first response delay time of one output buffer and responds to the system reference clock signal of the intermediate buffer circuit is equal to the first response delay time of the first output buffer and the second response delay time. A semiconductor integrated circuit for RF communication set to a time between the second response delay time of the output buffer. The output buffer further includes a first delay circuit and an intermediate delay circuit;
The first delay circuit supplies the system reference clock signal to an input of the first output buffer to form the first response delay time,
15. The semiconductor integrated circuit for RF communication according to claim 14, wherein the intermediate delay circuit supplies the system reference clock signal to an input of the intermediate output buffer to form the intermediate response delay time.

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