JP2008140842A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of manufacturing an excellent semiconductor device having an SOI structure by surely preventing a peeling resulting from an opening formed when forming a buried insulating layer by a thermal oxidation to a cavity section and by forming a superior SOI structure. <P>SOLUTION: The buried insulating layer 14 is formed, an amorphous semiconductor is deposited on the active surface side of a semiconductor substrate 1 and an amorphous semiconductor film is formed on the surface of a support 12 and the side face sections of the buried insulating layer 14 while the inside of the buried insulating layer 14 is filled with the amorphous semiconductor. Both the amorphous semiconductor film and the amorphous semiconductor are crystallized, a polycrystalline semiconductor film and a polycrystalline semiconductor 16a are formed and the polycrystalline semiconductor film is oxidized thermally to form a thermal oxidation film 17. The support 12 and the thermal oxidation film 17 on the surface of the support are removed, and a second semiconductor layer 6 is exposed, thus obtaining the SOI structure. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention particularly relates to a method for manufacturing a semiconductor device using a technique for forming an SOI (Silicon On Insulator) structure.

Field effect transistors formed on an SOI structure are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, a fully depleted SOI transistor has been actively researched because it can operate at low power consumption and high speed and can be driven at a low voltage.
Conventionally, as a method for manufacturing a semiconductor device having an SOI structure on a bulk wafer, for example, as described in Non-Patent Document 1, an SOI layer is formed on a silicon substrate by using a SBSI (Separation by Bonding Si Islands) method. There is known a method of partially forming the gate electrode and forming an SOI transistor in the SOI layer.

  A method for forming an SOI structure using the above-described SBSI method will be described. First, a silicon germanium (SiGe) layer and a silicon (Si) layer are sequentially epitaxially grown on a silicon substrate, and then a support hole for supporting the silicon layer is formed. Next, after an oxide film or the like is formed thereon, patterning is performed so as to obtain the element formation region and the shape of the support. Thereafter, the silicon germanium layer under the support is selectively etched with hydrofluoric acid, whereby the silicon layer is supported by the support and a cavity is formed under the silicon layer. Then, a BOX (Buried Oxide) layer is formed between the silicon substrate and the silicon layer by growing an oxide film from the silicon substrate side and the silicon layer side using the thermal oxidation method in the cavity. . Further, after planarizing the silicon substrate, etching is performed using an etchant such as hydrofluoric acid to expose the silicon layer on the surface, thereby forming an SOI structure on the silicon substrate.

T.A. Sakai et al. , Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  However, even if the cavity is thermally oxidized and an oxide film is grown from each of the silicon substrate side and the silicon layer side, it is difficult to completely fill the cavity portion. A slight gap will remain between the sides. For example, when the silicon layer is exposed to the surface by performing a planarization process by a CMP method and further etching with an etchant such as hydrofluoric acid, a part of the etchant penetrates into the gap and widens the gap. End up. Then, various loads are applied in the subsequent steps, and stress is generated. For this reason, separation may occur in the gap, and the silicon layer side may be peeled off.

  The present invention has been made in view of the above circumstances, and its object is to perform thermal oxidation on the cavity and reliably prevent peeling due to the gap generated when the buried insulating layer is formed, An object of the present invention is to provide a method capable of manufacturing an excellent semiconductor device having an SOI structure by forming a good SOI structure.

The method of manufacturing a semiconductor device of the present invention includes a step of forming a first semiconductor layer having a higher etching selectivity than the semiconductor substrate so as to cover a portion where the semiconductor region on the active surface side of the semiconductor substrate is exposed,
Forming a second semiconductor layer covering the first semiconductor layer and having a lower etching selectivity than the first semiconductor layer;
An opening for removing the second semiconductor layer and the first semiconductor layer in a region adjacent to an element region formed using a part of the second semiconductor layer and located so as to sandwich the element region. Forming a support hole exposing the substrate semiconductor layer;
Forming a support on the active surface side of the semiconductor substrate so as to cover the element region and fill at least part of the support hole;
Etching the second semiconductor layer and the first semiconductor layer using the support as a mask to form an end exposed surface that at least partially exposes an end of the first semiconductor layer;
Removing the first semiconductor layer by wet etching after the end exposed surface is formed;
Filling the cavity obtained by the wet etching with an oxide film using thermal oxidation to form a buried insulating layer;
After forming the buried insulating layer, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate, and an amorphous semiconductor film is formed at least on the surface of the support and on the side surface of the buried insulating layer. Filling the buried insulating layer with the amorphous semiconductor;
Crystallizing both the amorphous semiconductor film and the amorphous semiconductor to form a polycrystalline semiconductor film and a polycrystalline semiconductor;
Thermally oxidizing the polycrystalline semiconductor film to form a thermal oxide film;
Removing the support and the thermal oxide film on the surface of the support from at least the element region to expose the second semiconductor layer;
Forming a semiconductor device in the second semiconductor layer;
It is characterized by including.

According to this method for manufacturing a semiconductor device, after forming a buried insulating layer, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate. For example, this amorphous semiconductor is deposited by chemical vapor deposition ( By performing the CVD method, not only the amorphous semiconductor film is formed on the surface of the support and the side surface of the buried insulating layer, but also the gap formed in the buried insulating layer is filled with the amorphous semiconductor. be able to. Therefore, the amorphous semiconductor film and the amorphous semiconductor are crystallized together to form a polycrystalline semiconductor film and a polycrystalline semiconductor, and the polycrystalline semiconductor film is thermally oxidized to form a thermal oxide film, and then the support and When the thermal oxide film on the surface of the support is removed from the element region portion and the second semiconductor layer is exposed, the polycrystalline semiconductor can be formed, for example, even if wet etching is performed using a hydrofluoric acid solution. Since it is not etched with a hydrofluoric acid-based solution in the case of crystalline silicon, the gap in the buried insulating layer is held in a state filled with a polycrystalline semiconductor.
Therefore, even if various loads are applied in the subsequent process and stress is generated, the gap is filled with the polycrystalline semiconductor, so that it is reliably prevented that peeling occurs here, and this is good. It becomes possible to form a simple SOI structure.

According to another method of manufacturing a semiconductor device of the present invention, the first semiconductor layer having a higher etching selectivity than the semiconductor substrate is formed so as to cover the exposed portion of the semiconductor region on the active surface side of the semiconductor substrate. And a process of
Forming a second semiconductor layer covering the first semiconductor layer and having a lower etching selectivity than the first semiconductor layer;
An opening for removing the second semiconductor layer and the first semiconductor layer in a region adjacent to an element region formed using a part of the second semiconductor layer and located so as to sandwich the element region. Forming a support hole exposing the substrate semiconductor layer;
Forming a support on the active surface side of the semiconductor substrate so as to cover the element region and fill at least part of the support hole;
Etching the second semiconductor layer and the first semiconductor layer using the support as a mask to form an end exposed surface that at least partially exposes an end of the first semiconductor layer;
Removing the first semiconductor layer by wet etching after the end exposed surface is formed;
Filling the cavity obtained by the wet etching with an oxide film using thermal oxidation to form a buried insulating layer;
After forming the buried insulating layer, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate, and an amorphous semiconductor film is formed at least on the surface of the support and on the side surface of the buried insulating layer. Filling the buried insulating layer with the amorphous semiconductor;
Crystallizing both the amorphous semiconductor film and the amorphous semiconductor to form a polycrystalline semiconductor film and a polycrystalline semiconductor;
Selectively removing the polycrystalline semiconductor film by dry etching;
Removing the support from at least the element region to expose the second semiconductor layer;
Forming a semiconductor device in the second semiconductor layer;
It is characterized by including.

According to this method for manufacturing a semiconductor device, after forming a buried insulating layer, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate. For example, this amorphous semiconductor is deposited by chemical vapor deposition ( By performing the CVD method, not only the amorphous semiconductor film is formed on the surface of the support and the side surface of the buried insulating layer, but also the gap formed in the buried insulating layer is filled with the amorphous semiconductor. be able to. Accordingly, the amorphous semiconductor film and the amorphous semiconductor are crystallized together to form a polycrystalline semiconductor film and a polycrystalline semiconductor, and after the polycrystalline semiconductor film is selectively removed by dry etching, the support is removed from the element region. Even when wet etching is performed using a hydrofluoric acid solution when the second semiconductor layer is exposed by removing from the top, etching with a hydrofluoric acid solution is performed when the polycrystalline semiconductor is, for example, polycrystalline silicon. Therefore, the gap in the buried insulating layer is held in a state filled with the polycrystalline semiconductor.
Therefore, even if various loads are applied in the subsequent process and stress is generated, the gap is filled with the polycrystalline semiconductor, so that it is reliably prevented that peeling occurs here, and this is good. It becomes possible to form a simple SOI structure.

In the method of manufacturing the semiconductor device, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate, and an amorphous semiconductor film is formed on the surface of the support and the side surface of the buried insulating layer. At the same time, the amorphous semiconductor is preferably deposited by chemical vapor deposition in the step of filling the buried insulating layer with the amorphous semiconductor.
By depositing the amorphous semiconductor by chemical vapor deposition in this way, the amorphous semiconductor can be satisfactorily deposited even in a small gap, and thus the gap formed in the buried insulating layer is not non-exposed. It can be satisfactorily embedded with a crystalline semiconductor.

According to another method of manufacturing a semiconductor device of the present invention, the first semiconductor layer having a higher etching selectivity than the semiconductor substrate is formed so as to cover the exposed portion of the semiconductor region on the active surface side of the semiconductor substrate. And a process of
Forming a second semiconductor layer covering the first semiconductor layer and having a lower etching selectivity than the first semiconductor layer;
An opening for removing the second semiconductor layer and the first semiconductor layer in a region adjacent to an element region formed using a part of the second semiconductor layer and located so as to sandwich the element region. Forming a support hole exposing the substrate semiconductor layer;
Forming a support on the active surface side of the semiconductor substrate so as to cover the element region and fill at least part of the support hole;
Etching the second semiconductor layer and the first semiconductor layer using the support as a mask to form an end exposed surface that at least partially exposes an end of the first semiconductor layer;
Removing the first semiconductor layer by wet etching after the end exposed surface is formed;
Filling the cavity obtained by the wet etching with an oxide film using thermal oxidation to form a buried insulating layer;
After forming the buried insulating layer, depositing an amorphous semiconductor on the active surface side of the semiconductor substrate, and forming an amorphous semiconductor film at least on the surface of the support and the side surface of the buried insulating layer When,
Thermally oxidizing the amorphous semiconductor film to form a thermal oxide film;
Removing the support and the thermal oxide film on the surface of the support from at least the element region to expose the second semiconductor layer;
Forming a semiconductor device in the second semiconductor layer;
It is characterized by including.

According to this semiconductor device manufacturing method, after forming the buried insulating layer, the amorphous semiconductor is deposited on the active surface side of the semiconductor substrate. For example, this amorphous semiconductor is deposited by sputtering. The amorphous semiconductor film can be formed on the surface of the support or on the side surface of the buried insulating layer without filling the gap formed in the buried insulating layer with the amorphous semiconductor. Therefore, after that, the amorphous semiconductor film is thermally oxidized to form a thermal oxide film, and the support and the thermal oxide film on the surface of the support are removed from the element region portion to expose the second semiconductor layer. Even if wet etching is performed using a hydrofluoric acid-based solution, a thermal oxide film made of an amorphous semiconductor film formed on the side surface portion of the buried insulating layer is in the gap in the buried insulating layer. Since the penetration of the solution is prevented, the gap in the buried insulating layer is held as it is without being etched with the hydrofluoric acid solution.
Therefore, even if various loads are applied in the subsequent steps and stress is generated, the gap is reinforced by the thermal oxide film made of the amorphous semiconductor film, so that peeling is surely caused here. This makes it possible to form a good SOI structure.
In addition, the obtained semiconductor device is advantageous in terms of electrical characteristics compared to, for example, a case where it is filled with amorphous silicon because the relative permittivity of the gap (air gap) is small.

In the method of manufacturing the semiconductor device, in the step of depositing an amorphous semiconductor on the active surface side of the semiconductor substrate and forming an amorphous semiconductor film on the support surface, the amorphous semiconductor is deposited. Is preferably performed by sputtering or CVD.
If the amorphous semiconductor is deposited by the sputtering method or the CVD method in this way, the amorphous semiconductor is not deposited in a slight gap, so the amorphous semiconductor is buried in the gap formed in the buried insulating layer. However, as described above, it is not etched with a hydrofluoric acid solution, so that peeling is reliably prevented. Moreover, the obtained semiconductor device is advantageous in terms of electrical characteristics because the relative permittivity of the gap (air gap) is small as described above.

In the semiconductor device manufacturing method, it is preferable that the substrate semiconductor layer and the second semiconductor layer are made of single crystal silicon, and the first semiconductor layer is made of single crystal silicon germanium.
In this way, a good SOI structure can be formed by the SBSI method.

In the method for manufacturing a semiconductor device, the amorphous semiconductor is preferably amorphous silicon.
This facilitates the film formation and facilitates the thermal oxidation and etching of the obtained thermal oxide film.

The method for manufacturing a semiconductor device preferably includes a step of forming a buffer layer made of single crystal silicon on the semiconductor substrate before the step of forming the first semiconductor layer.
In this case, by forming the buffer layer before forming the first semiconductor layer, it is possible to suppress the fine defects in the semiconductor substrate from adversely affecting the first semiconductor layer and the second semiconductor layer. can do. Therefore, an SOI structure with further improved quality and yield can be obtained.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings.
1 to 13 are schematic views showing the first embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps, and each figure (a) in FIGS. 1 to 12 is a schematic plan view and each figure (b). These are AA arrow sectional drawing or BB arrow sectional drawing of each figure (a). In these schematic diagrams, for convenience of illustration, the scales of members or parts may be represented differently from actual ones.

  First, as shown in FIGS. 1A and 1B, a semiconductor substrate 1 made of single crystal silicon is prepared. Subsequently, an element isolation layer 2 and a rectangular shape in plan view are formed on the active surface of the semiconductor substrate 1 by a known method. A shaped SOI formation region 3 is formed. The element isolation region 2 is a LOCOS (Local Oxidation of Silicon) oxide film for electrically insulating the SOI formation region 3 and the bulk formation region (not shown). In the SOI formation region 3, a surface 1 a that is a surface of single crystal silicon constituting the semiconductor substrate 1 is exposed. Hereinafter, description of the bulk formation region is omitted. 1A and 1B show only one SOI formation region 3 in a simplified manner, but in reality, a large number of SOI formation regions 3 are formed, and all the SOI formation regions 3 will be described later. The process shall be performed simultaneously.

Next, as shown in FIGS. 2A and 2B, on the surface 1a exposed in the SOI formation region 3, silicon (Si) is epitaxially grown so as to cover it, and the buffer layer 4 made of single crystal Si is formed. Is formed to a thickness of about 20 nm. For this epitaxial growth, a vapor phase method using diborane (Si ₂ H ₆ ) as a source gas is preferably employed. Here, the buffer layer 4 is for improving the crystallinity of the single crystal SiGe layer 5 formed thereon and the single crystal Si layer 6 formed thereon as will be described later. .

Subsequently, silicon germanium (SiGe) is epitaxially grown on the buffer layer 4 so as to cover it, and a single crystal SiGe layer (first semiconductor layer) 5 is formed to a thickness of about 30 nm. For this epitaxial growth, a vapor phase method using diborane (Si ₂ H ₆ ) and germane (GeH ₄ ) as source gases is preferably employed. This single crystal SiGe layer 5 is etched against the surface 1a made of single crystal silicon and further to the buffer layer 4 made of the same single crystal silicon when using hydrofluoric acid as an etchant as will be described later. The selection ratio is large.

Subsequently, silicon (Si) is epitaxially grown on the single crystal SiGe layer 5 so as to cover it, and a single crystal Si layer (second semiconductor layer) 6 is formed to a thickness of about 100 nm. For this epitaxial growth, as in the case of the buffer layer, a vapor phase method using diborane (Si ₂ H ₆ ) as a source gas is preferably employed. Since the single crystal Si layer 6 is made of single crystal silicon as described above, the etching selectivity with respect to the single crystal SiGe layer 5 is small when using hydrofluoric acid as an etchant. It has become.

  The buffer layer 4, the single crystal SiGe layer 5, and the single crystal Si layer 6 are epitaxially grown in the SOI formation region 3 as described above. A crystal buffer layer 4a, a polycrystalline SiGe layer 5a, and a polycrystalline Si layer 6a are formed.

  Next, as shown in FIGS. 3A and 3B, the active region side of the semiconductor substrate 1, that is, the surface on the side where the SOI formation region 3 is formed, is in a region at a position where an element region portion to be described later is sandwiched. The single crystal Si layer 6, the single crystal SiGe, the buffer layer 5, and a part of the surface 1a are removed and opened to form the first support hole 8 and the second support hole 9. Specifically, first, a resist pattern (not shown) that opens regions corresponding to the region 8a in which the first support hole 8 is formed and the region 9a in which the second support hole 9 is formed is formed by photolithography. It is formed using a lithography technique. Next, using this resist pattern as a mask, the single crystal Si layer 6, the single crystal SiGe, the buffer layer 5 and a part of the surface 1a located in the regions 8a and 9a are sequentially removed by dry etching. To do.

  As described above, an element region formed by using a part of the single crystal Si layer 6 is formed between the first support hole 8 and the second support hole 9. That is, a region sandwiched between the first support hole 8 and the second support hole 9 becomes an element region portion 10 as will be described later.

Next, as shown in FIGS. 4A and 4B, a support precursor layer 11 for forming a support to be described later is formed on the entire active surface side of the semiconductor substrate 1. In the present embodiment, silicon oxide (SiO ₂ ) is filled in the first support hole 8 and the second support hole 9 and covered with the single crystal Si layer 6 by CVD (Chemical Vapor Deposition). For example, the support precursor layer 11 is formed with a thickness of about 400 nm. The film forming condition of the support precursor layer 11 is performed at a temperature at which germanium (Ge) contained in the single crystal SiGe layer 5 does not diffuse into the single crystal Si layer 6.

  Next, the support precursor layer 11 is patterned to cover the element region 10 as shown in FIGS. 5A and 5B, and to form the first support hole 8 and the second support hole 9. The support 12 is formed in a state where a part of the support is embedded. That is, a support pattern 12 is obtained by forming a resist pattern (not shown) by photolithography and patterning it by dry etching using the resist pattern as a mask.

  After the support 12 is formed using a resist pattern (not shown) as a mask in this way, the single crystal Si layer 6 and the polycrystal exposed on the active surface side are subsequently exposed as shown in FIG. 6B. The Si layer 6a is removed by dry etching, and the single crystal Si layer 6 is left only directly under the support 12.

  Further, using the resist pattern and the support 12 as a mask, the exposed single crystal SiGe layer 5 and polycrystalline SiGe layer 5a, buffer layer 4 and polycrystalline buffer layer 4a, and part of the surface 1a are sequentially dried. Remove by etching. 6A, both side surfaces of the support 12, that is, the side surface 12a along the line connecting the first support hole 8 and the second support hole 9 are exposed. At the same time, both the single crystal Si layer 6, single crystal SiGe layer 5, and buffer layer 4 remaining immediately below the support 12 are exposed at both side surfaces (end surfaces) positioned immediately below the side surface 12a, and end portions according to the present invention. Exposed surface. Thereafter, the resist pattern on the support 12 is removed. Note that the support 12 supports the single crystal Si layer 6 by patterning the single crystal Si layer 6, the single crystal SiGe layer 5, and the buffer layer 4 in this manner.

  Next, as shown in FIGS. 7A and 7B, the single crystal SiGe layer 5 located below the support 12 is selectively removed by wet etching using hydrofluoric acid. Specifically, the semiconductor substrate 1 is immersed in, for example, hydrofluoric acid from the back surface side (the surface side opposite to the active surface), whereby an etching solution such as hydrofluoric acid is applied to the single crystal SiGe layer 5 below the support 12. Contact. Then, the single crystal Si layer 6 has a lower etching selection ratio than the single crystal SiGe layer 5, and therefore the etching rate is slow, so the single crystal Si layer 6 remains without being etched, and the single crystal SiGe layer 5 is selected. Etched away. Similarly, the buffer layer 4 and the semiconductor substrate 1 (surface 1a) made of single crystal silicon remain without being etched. Therefore, after the single crystal SiGe layer 5 is selectively etched, the cavity 13 is formed between the buffer layer 4 and the single crystal Si layer 6.

Next, by performing thermal oxidation treatment, a buried insulating layer 14 (BOX layer: Buried Oxide layer) is formed in the cavity 13 as shown in FIGS. That is, when the thermal oxidation treatment is performed in this way, the buffer layer 4 (and also the semiconductor substrate 1) and the single crystal Si layer 6 sandwiching the cavity 13 above and below react with oxygen on the cavity 13 side, respectively. As a result, it is oxidized to grow into silicon oxide (SiO ₂ ) and thicken. As a result, the entire inside of the cavity 13 is almost filled with silicon oxide (buried insulating layer 14).

  Here, since the support 12 is provided on the upper part of the single crystal Si layer 6, it is possible to prevent the upper surface side of the single crystal Si layer 6 from being oxidized. Reduction is suppressed. Further, since the buffer layer 4 is as thin as about 20 nm, after the entire buffer layer 4 is oxidized, the surface of the semiconductor substrate 1 (surface 1a) is oxidized to become a part of the buried insulating layer. . When the buffer layer 4 is not formed, the surface of the semiconductor substrate 1 (surface 1a) is oxidized from the beginning, and the buried insulating layer 14 is formed together with silicon oxide generated from the single crystal Si layer 6.

However, even if the cavity portion 13 is thermally oxidized in this way, it is difficult to completely fill the cavity portion 13 as described above, and at present, the semiconductor substrate 1 side and the single crystal Si layer 6 side are not filled. A little gap 7 remains between them.
Therefore, in this embodiment, after the buried insulating layer 14 is formed, amorphous Si as an amorphous semiconductor is deposited to a thickness of about 20 nm on the entire active surface side of the semiconductor substrate 1 by the CVD method. . For example, using a vertical furnace type CVD apparatus, amorphous Si is deposited by introducing SiH ₄ as a source gas under a temperature condition of 550 ° C.

  As a result, as shown in FIGS. 9A and 9B, an amorphous Si film (non-crystalline) is formed on the active surface side of the semiconductor substrate 1 including the surface of the support 12 and the side surface portion of the buried insulating layer 14. Quality semiconductor film) 15 is formed. At the same time, the amorphous Si layer 16 is formed by filling the gap 7 in the buried insulating layer 14 with the amorphous Si (amorphous semiconductor). In the CVD method, since the source gas easily enters the gap 7, the amorphous Si layer 16 can be formed in the gap 7. Here, when amorphous Si is deposited and the amorphous Si film 15 and the amorphous Si layer 16 are formed in this way, the support 12 and the buried insulating layer 14 which are the underlying layers are formed, and further, in the film 15 and in the layers. 16 will leave a boundary.

  Next, the amorphous Si film 15 and the amorphous Si layer 16 are crystallized together by holding them at a temperature of 700 ° C. for about 1 hour in a nitrogen atmosphere. As shown in FIGS. A crystalline Si film 15a and a polycrystalline Si layer 16a are formed. When polycrystallization is performed in this manner, the obtained polycrystalline Si film 15a and polycrystalline Si layer 16a have no boundary. Therefore, the gap 7 is well filled with the polycrystalline Si layer 16a due to the absence of the boundary.

  Next, a thermal oxidation process is performed to thermally oxidize the polycrystalline Si film 15a, thereby forming a thermal oxide film 17 as shown in FIGS. 11 (a) and 11 (b). In this thermal oxidation treatment, the polycrystalline Si film 15a exposed on the surface is thermally oxidized. Therefore, the polycrystalline Si film 15a formed on the opening of the gap 7 is thermally oxidized, so that the gap 7 is filled. The formed polycrystalline Si layer 16a is not oxidized and is maintained in the polycrystalline Si state as it is. That is, as described above, the opening of the gap 7 is blocked by the polycrystalline Si film 15a (thermal oxide film 17), and the boundary in the gap 7 is eliminated, so that oxygen is supplied into the gap 7. Therefore, the polycrystalline Si layer 16a is not oxidized.

Next, as shown in FIGS. 12A and 12B, the entire surface of the semiconductor substrate 1 is planarized. Specifically, first, in order to electrically insulate the SOI structure, silicon oxide (SiO ₂ ) is formed to a thickness of about 1 μm by the CVD method or the like on the entire active surface side of the semiconductor substrate 1 and planarized. An insulating film (not shown) is formed. Subsequently, the active surface side of the semiconductor substrate 1 is planarized by a CMP (Chemical Mechanical Polishing) method, thereby removing the planarization insulating film and the support 12. At the time of removal, the thermal oxide film 17 covering this is also removed, and the support 12 is thus removed.

  In the removal of the support 12 by such a CMP method, the time until the single crystal Si layer 6 is exposed by experiments or the like is obtained in advance, and the CMP processing time is made to correspond to the obtained time. Perform process control. That is, the CMP process is terminated immediately before the single crystal Si layer 6 is exposed.

  Thereafter, wet etching with a hydrofluoric acid solution is performed to remove unnecessary silicon oxide from the element region 10 and the like, thereby exposing the single crystal Si layer 6. By doing so, it is possible to prevent the disadvantage that defects are caused in the single crystal Si layer 6 by the CMP process. In addition, since hydrofluoric acid does not etch polycrystalline silicon, even if a hydrofluoric acid-based solution penetrates into the gap 7, the polycrystalline Si layer 16a is not etched. It is kept in a well-filled state by 16a.

  Next, as shown in the enlarged view of the main part in FIG. 13, a semiconductor device 25 is formed using the single crystal Si layer 6. Specifically, first, the surface of the single crystal Si layer 6 is subjected to thermal oxidation to form the gate insulating film 26. Then, a polycrystalline silicon layer is formed on the gate insulating film 26 by, eg, CVD. Thereafter, the polycrystalline silicon layer is patterned using a photolithography technique and an etching technique, thereby forming a gate electrode 27 on the gate insulating film 26.

  Next, using the gate electrode 27 as a mask, impurities such as As (arsenic), P (phosphorus), and B (boron) are implanted into the single crystal Si layer 6, and both sides of the gate electrode 27 of the single crystal Si layer 6 are implanted. Then, LDD layers 28 and 28 are formed as low concentration impurity introduction layers, respectively. Then, an insulating layer (not shown) is formed on the single crystal Si layer 6 on which the LDD layers 28 and 28 are formed by CVD or the like, and the insulating layer is formed using dry etching such as RIE (Reactive Ion Etching). Etchback is performed to form sidewalls 29 and 29 on the sidewalls of the gate electrode 27, respectively.

  Next, impurities such as As, P, and B are implanted into the single crystal Si layer 6 using the gate electrode 27 and the sidewalls 29 and 29 as a mask. As a result, source / drain regions 30 and 30 made of high-concentration impurity introduced layers are formed on the side of the side walls 29 and 29 in the single-crystal Si layer 6 to obtain a transistor (semiconductor device 25). In addition, by forming a bulk element in a bulk formation region (not shown), a semiconductor device in which an SOI element and a bulk element are mixedly mounted can be formed on the semiconductor substrate 1.

According to this manufacturing method, after forming the buried insulating layer 14, amorphous Si is deposited on the active surface side of the semiconductor substrate 1, so that the amorphous Si film is formed on the surface of the support 12 and the side surface portion of the buried insulating layer 14. 15, the gap 7 formed in the buried insulating layer 14 can be filled with the amorphous Si layer 16. Accordingly, the amorphous Si film 15 and the amorphous Si layer 16 are crystallized together to form a polycrystalline Si film 15a and a polycrystalline Si layer 16a, and the polycrystalline Si film 15a is thermally oxidized to form a thermal oxide film 17, and thereafter When the support 12 and the thermal oxide film 17 on the surface of the support 12 are removed from the element region portion 10 to expose the single crystal Si layer 6, even if wet etching is performed using a hydrofluoric acid-based solution, Since the polycrystalline Si layer 16a is not etched with a hydrofluoric acid-based solution, the gap 7 in the buried insulating layer 14 can be held in a state filled with the polycrystalline Si layer 16a. That is, the upper and lower buried insulating layers 14 and 14 forming the gap 7 can be firmly fixed via the polycrystalline Si layer 16a.
Therefore, even if various loads are applied in the subsequent process and stress is generated, the gap 7 is satisfactorily filled with the polycrystalline Si layer 16a, so that the occurrence of peeling is surely prevented. As a result, a good SOI structure can be formed.

Next, a second embodiment of the semiconductor device manufacturing method according to the present invention will be described.
The second embodiment is mainly different from the first embodiment in that after the amorphous Si film 15 and the amorphous Si layer 16 are polycrystallized, dry etching is performed instead of thermal oxidation. In the point.

  That is, this embodiment is the same as the first embodiment until the polycrystalline Si film 15a and the polycrystalline Si layer 16a are formed as shown in FIGS. 10 (a) and 10 (b). Then, after polycrystallizing in this way, isotropic dry etching is performed to selectively remove the polycrystal Si film 15a as shown in FIG. In this isotropic dry etching, in order to remove the polycrystalline Si layer 16a formed on the side surface of the support 12 with certainty, the direction of the semiconductor substrate 1 is changed and the dry etching is also performed from an oblique direction. Also good. The term “selectively” here means that the polycrystalline Si layer 16a in the gap 7 formed in the buried insulating layer 14 is not removed because it cannot be etched because the support 12 serves as a mask. This means that only the polycrystalline Si film 15a is removed.

After the polycrystalline Si film 15a is selectively removed in this way, the semiconductor device is formed by using the exposed single crystal Si layer 6 after planarizing the entire surface of the semiconductor substrate 1 in the same manner as in the first embodiment. 25 is formed. At that time, even if wet etching with a hydrofluoric acid-based solution is performed after the CMP process, the polycrystalline Si layer 16a in the gap 7 is not etched as described above. Therefore, the gap 7 is satisfactorily filled with the polycrystalline Si layer 16a. It is kept in the state that was done. That is, the upper and lower buried insulating layers 14 and 14 forming the gap 7 can be firmly fixed via the polycrystalline Si layer 16a.
Therefore, even in the manufacturing method of the present embodiment, the gap 7 is satisfactorily filled with the polycrystalline Si layer 16a even if various loads are applied and stress is generated in the process after the semiconductor substrate 1 is planarized. Therefore, it is possible to surely prevent the occurrence of peeling here, thereby forming a good SOI structure.

Next, a third embodiment of the semiconductor device manufacturing method according to the present invention will be described.
The third embodiment is mainly different from the first embodiment in that after the buried insulating layer 14 is formed in the cavity 13, the amorphous Si is deposited not by the CVD method but by the sputtering method. After the film 15 is formed, the film 15 is directly subjected to a thermal oxidation process without being subjected to a polycrystallization process.

  That is, in the present embodiment, the semiconductor including the surface of the support 12 and the side surface of the embedded insulating layer 14 after forming the embedded insulating layer 14 as shown in FIGS. Amorphous Si is deposited on the active surface side of the substrate 1. At this time, in this embodiment, the sputtering method is used instead of the CVD method, and the thickness of the film to be formed is about 100 nm, which is thicker than the above embodiment. When the amorphous Si is deposited by the sputtering method in this way, the source gas does not enter the gap 7 as in the case of the CVD method, and the fine particles that have jumped out of the target fall on the active surface side of the semiconductor substrate 1. Therefore, the gap 7 is not filled with amorphous Si, and therefore the gap 7 formed in the buried insulating layer 14 is maintained as a gap. That is, as shown in FIG. 15, the amorphous Si film 15 is formed on the active surface side of the semiconductor substrate 1 so as to cover the support 12, but the gap 7 is held without being filled.

Next, thermal oxidation is performed to thermally oxidize the amorphous Si film 15 to form a thermal oxide film 18 as shown in FIG. The thermal oxide film 18 formed in this way becomes a film denser than, for example, silicon oxide (SiO ₂ ) deposited and formed by the CVD method, and compared with the case where it is deposited and formed by the CVD method. Since it is formed thick, it has a relatively large resistance to hydrofluoric acid. Further, the amorphous Si film 15 which is thickened by the thermal oxidation treatment itself and is formed to about 100 nm as described above becomes the thermal oxide film 18 of about 200 nm, for example.

  After the thermal oxide film 18 is formed in this way, the entire surface of the semiconductor substrate 1 is planarized and the semiconductor device 25 is formed using the exposed single crystal Si layer 6 in the same manner as in the first embodiment. . At this time, even if wet etching with a hydrofluoric acid solution is performed after the CMP process, the thermal oxide film 18 formed of the amorphous Si film 15 formed on the side surface of the buried insulating layer 14 is not in contact with hydrofluoric acid as described above. Therefore, the hydrofluoric acid solution is prevented from penetrating into the gap 7 in the buried insulating layer 14. Therefore, the gap 7 in the buried insulating layer 14 is maintained as a gap without being etched with the hydrofluoric acid solution.

Therefore, even in the manufacturing method of the present embodiment, even if various loads are applied in the subsequent steps and stress is generated, the gap 7 is reinforced by the thermal oxide film 18, so that the peeling is caused here. Occurrence can be prevented with certainty, and thereby a good SOI structure can be formed.
In addition, the obtained semiconductor device 25 is advantageous in terms of electrical characteristics compared to, for example, a case where it is filled with amorphous silicon because the relative permittivity of the gap (air gap) is small. In other words, the relative permittivity of the void is 1.0, which is sufficiently lower than the relative permittivity of SiO ₂ and 3.9 of polycrystalline Si and 11.9 of polycrystalline Si. In the semiconductor device 25, the capacity of the buried insulating film 14 is reduced, which is advantageous in terms of electrical characteristics.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, although the buffer layer 4 is formed in the embodiment, the single crystal SiGe layer 5 may be formed directly on the surface 1a exposed in the SOI formation region 3 without forming the buffer layer 4. Good.

(A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. (A) (b) is a schematic sectional side view explaining the process of the manufacturing method of this invention. It is a principal part expansion model side sectional view explaining the process of the manufacturing method of this invention. It is a schematic sectional side view explaining the process of the manufacturing method of another embodiment of this invention. It is a schematic sectional side view explaining the process of the manufacturing method of another embodiment of this invention. It is a schematic sectional side view explaining the process of the manufacturing method of another embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... Surface, 2 ... Silicon oxide film (oxide film), 3 ... SOI formation area, 4 ... Buffer layer, 5 ... Single-crystal SiGe layer (1st semiconductor layer), 6 ... Single-crystal Si layer ( (Second semiconductor layer), 7 ... gap, 8 ... first support hole, 9 ... second support hole, 10 ... element region, 12 ... support, 13 ... cavity, 14 ... buried insulating layer, 15 ... Amorphous Si film (amorphous semiconductor film), 15a ... polycrystalline Si film (polycrystalline semiconductor film), 16 ... amorphous Si layer (amorphous semiconductor), 16a ... polycrystalline Si layer (polycrystalline semiconductor), 17, 18 ... thermal oxide film, 25 ... semiconductor device

Claims (8)

Forming a first semiconductor layer having a higher etching selectivity than the semiconductor substrate so as to cover a portion where the semiconductor region on the active surface side of the semiconductor substrate is exposed;
Forming a second semiconductor layer covering the first semiconductor layer and having a lower etching selectivity than the first semiconductor layer;
An opening for removing the second semiconductor layer and the first semiconductor layer in a region adjacent to an element region formed using a part of the second semiconductor layer and located so as to sandwich the element region. Forming a support hole exposing the substrate semiconductor layer;
Forming a support on the active surface side of the semiconductor substrate so as to cover the element region and fill at least part of the support hole;
Etching the second semiconductor layer and the first semiconductor layer using the support as a mask to form an end exposed surface that at least partially exposes an end of the first semiconductor layer;
Removing the first semiconductor layer by wet etching after the end exposed surface is formed;
Filling the cavity obtained by the wet etching with an oxide film using thermal oxidation to form a buried insulating layer;
After forming the buried insulating layer, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate, and an amorphous semiconductor film is formed at least on the surface of the support and on the side surface of the buried insulating layer. Filling the buried insulating layer with the amorphous semiconductor;
Crystallizing both the amorphous semiconductor film and the amorphous semiconductor to form a polycrystalline semiconductor film and a polycrystalline semiconductor;
Thermally oxidizing the polycrystalline semiconductor film to form a thermal oxide film;
Removing the support and the thermal oxide film on the surface of the support from at least the element region to expose the second semiconductor layer;
Forming a semiconductor device in the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising: Forming a first semiconductor layer having a higher etching selectivity than the semiconductor substrate so as to cover a portion where the semiconductor region on the active surface side of the semiconductor substrate is exposed;
Forming a second semiconductor layer covering the first semiconductor layer and having a lower etching selectivity than the first semiconductor layer;
An opening for removing the second semiconductor layer and the first semiconductor layer in a region adjacent to an element region formed using a part of the second semiconductor layer and located so as to sandwich the element region. Forming a support hole exposing the substrate semiconductor layer;
Forming a support on the active surface side of the semiconductor substrate so as to cover the element region and fill at least part of the support hole;
Etching the second semiconductor layer and the first semiconductor layer using the support as a mask to form an end exposed surface that at least partially exposes an end of the first semiconductor layer;
Removing the first semiconductor layer by wet etching after the end exposed surface is formed;
Filling the cavity obtained by the wet etching with an oxide film using thermal oxidation to form a buried insulating layer;
After forming the buried insulating layer, an amorphous semiconductor is deposited on the active surface side of the semiconductor substrate, and an amorphous semiconductor film is formed at least on the surface of the support and on the side surface of the buried insulating layer. Filling the buried insulating layer with the amorphous semiconductor;
Crystallizing both the amorphous semiconductor film and the amorphous semiconductor to form a polycrystalline semiconductor film and a polycrystalline semiconductor;
Selectively removing the polycrystalline semiconductor film by dry etching;
Removing the support from at least the element region to expose the second semiconductor layer;
Forming a semiconductor device in the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   An amorphous semiconductor is deposited on the active surface side of the semiconductor substrate, an amorphous semiconductor film is formed on the surface of the support and the side surface of the buried insulating layer, and the amorphous semiconductor is formed in the buried insulating layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the amorphous semiconductor is deposited by chemical vapor deposition in the step of filling the porous semiconductor. Forming a first semiconductor layer having a higher etching selectivity than the semiconductor substrate so as to cover a portion where the semiconductor region on the active surface side of the semiconductor substrate is exposed;
Forming a second semiconductor layer covering the first semiconductor layer and having a lower etching selectivity than the first semiconductor layer;
An opening for removing the second semiconductor layer and the first semiconductor layer in a region adjacent to an element region formed using a part of the second semiconductor layer and located so as to sandwich the element region. Forming a support hole exposing the substrate semiconductor layer;
Forming a support on the active surface side of the semiconductor substrate so as to cover the element region and fill at least part of the support hole;
Etching the second semiconductor layer and the first semiconductor layer using the support as a mask to form an end exposed surface that at least partially exposes an end of the first semiconductor layer;
Removing the first semiconductor layer by wet etching after the end exposed surface is formed;
Filling the cavity obtained by the wet etching with an oxide film using thermal oxidation to form a buried insulating layer;
After forming the buried insulating layer, depositing an amorphous semiconductor on the active surface side of the semiconductor substrate, and forming an amorphous semiconductor film at least on the surface of the support and the side surface of the buried insulating layer When,
Thermally oxidizing the amorphous semiconductor film to form a thermal oxide film;
Removing the support and the thermal oxide film on the surface of the support from at least the element region to expose the second semiconductor layer;
Forming a semiconductor device in the second semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   In the step of depositing an amorphous semiconductor on the active surface side of the semiconductor substrate and forming an amorphous semiconductor film at least on the surface of the support and the side surface of the buried insulating layer, the amorphous semiconductor is deposited. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the step is performed by a sputtering method or a CVD method.   6. The semiconductor device according to claim 1, wherein the substrate semiconductor layer and the second semiconductor layer are made of single crystal silicon, and the first semiconductor layer is made of single crystal silicon germanium. Production method.   The method of manufacturing a semiconductor device according to claim 1, wherein the amorphous semiconductor is amorphous silicon.   8. The method according to claim 1, further comprising a step of forming a buffer layer made of single crystal silicon on the semiconductor substrate before the step of forming the first semiconductor layer. The manufacturing method of the semiconductor device of description.

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