JP2008139049A - Apparatus for measuring jitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for measuring jitters capable of carrying out timing measurement and jitter measurement at a reduced electric power consumption by a relatively small circuit scale. <P>SOLUTION: This apparatus for measuring jitters is provided with a voltage comparing part for comparing a voltage output from an object to be tested with a plurality of preset voltages to output respective comparison results; a latch part for latching the respective comparison results output from the voltage comparing part at strobe signal input timings to output respective latch results; an integrating part for integrating the respective latch results output from the latch part to find the frequency distribution; and a control part for finding jitter values, based on the frequency distribution obtained by outputting the third strobe signal obtained, based on the first and second strobe signals that differ respectively in the timings. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a jitter measuring apparatus that measures jitter of a signal under measurement, and more particularly to a jitter measuring apparatus that performs timing measurement and jitter measurement with a small circuit scale and low power consumption.

  Prior art documents related to a conventional jitter measuring apparatus for measuring jitter of a signal under measurement include the following.

JP 2004-125552 A

  Conventionally, when jitter occurs in a clock, an output signal, or the like when data is transferred between semiconductor devices, the semiconductor device cannot transfer data with high accuracy. For this reason, it is desired to accurately measure jitter such as clocks and output signals. Under such circumstances, there is a jitter measuring device for measuring the jitter of a signal under measurement.

  FIG. 8 is a block diagram showing an example of a conventional jitter measuring apparatus. In FIG. 8, reference numeral 1 denotes a jitter measurement unit, and 2 denotes a control unit constituted by an ASIC (Application Specific Integrated Circuit) or the like. Reference numeral 3 denotes a jitter measuring apparatus including a jitter measuring unit 1 and a control unit 2.

  The clock signal is input from the clock output end of the control unit 2 to the input end of the test target indicated by “DUT100” in FIG. 8, and the signal under test is measured from the output end of the test target indicated by “DUT100” in FIG. The signal is input to the measurement signal input terminal of the unit 1.

  A strobe signal is input from the strobe output terminal of the control unit 2 to the strobe input terminal of the jitter measuring unit 1. Further, the measurement result is output from the output end of the jitter measuring unit 1 and input to the measurement result input end of the control unit 2.

  FIG. 9 is a configuration diagram showing a specific configuration diagram of an example of a conventional jitter measuring apparatus. In FIG. 9, 4 is a comparator and 5 is a flip-flop. In FIG. 9, 1, 2 and 3 are given the same reference numerals as in FIG.

  The signal under measurement is input to the inverting input terminal of the comparator 4 from the output end of the test target indicated by “DP100” in FIG. Further, the output voltage of the variable voltage source indicated by “VS100” in FIG. 9 is connected to the non-inverting input terminal of the comparator 4.

  The output terminal of the comparator 4 is connected to the data input terminal (D terminal) of the flip-flop 5. The data output terminal (Q terminal) of the flip-flop 5 is connected to the input terminal of the control unit 2, and the clock terminal of the flip-flop 5 is connected to the output terminal of the control unit 2.

  Here, the operation of the conventional example shown in FIGS. 8 and 9 will be described. First, a comparison voltage (threshold value) is set in the comparator 4. For example, the control unit 2 controls the variable voltage source indicated by “VS100” in FIG. 9 and sets the voltage input to the non-inverting input terminal of the comparator 4.

  The control unit 2 outputs a clock signal to the test target indicated by “DUT100” in FIG. A signal under test is output from the test target indicated by “DUT 100” in FIG. 8 and input to the inverting input terminal of the comparator 4.

  The comparator 4 compares the voltage output from the test object indicated by “DUT100” in FIG. 8 with the voltage of the variable voltage source indicated by “VS100” in FIG.

  When the voltage output from the DUT 100 shown in FIG. 8 is larger than the voltage of the variable voltage source shown in “VS100” in FIG. 9, a low-level output signal is output from the comparator 4, and the flip-flop Is input to the data input terminal of the group 5.

  When the voltage output from the device under test indicated by “DUT100” in FIG. 8 is smaller than the voltage of the variable voltage source indicated by “VS100” in FIG. 9, a high level output signal is output from the comparator 4, and the flip-flop Is input to the data input terminal of the group 5.

  The control unit 2 outputs a strobe signal that gives the timing to compare the signal under measurement output from the test target indicated by “DUT100” in FIG.

  The flip-flop 5 latches and outputs the output value of the comparator 4 at the timing when the strobe signal is input. For example, the flip-flop 5 outputs a high level output signal to the control unit 2 when the output signal from the comparator 4 is high level at the timing when the strobe signal is input, and outputs a low level output signal when the output signal is low level. Is output to the control unit 2.

  By repeating these procedures, the control unit 2 can measure the jitter of the signal under measurement from the output value of the flip-flop 5 output at each strobe timing.

  Further, as a conventional example of a jitter measuring apparatus for measuring jitter of a signal under measurement, there is a jitter measuring apparatus disclosed in Patent Document 1.

  A conventional jitter measurement apparatus disclosed in Patent Document 1 includes a multi-strobe generation unit that outputs a multi-strobe signal composed of a plurality of strobe signals a plurality of times, and a comparison result output from a comparator at the timing when each strobe signal is input. And a plurality of flip-flops that output the latch result.

  Further, the jitter measuring apparatus disclosed in Patent Document 1 detects a timing at which the latch result changes based on the latch result output from the flip-flop, and outputs a change point detection result, and a change point detection unit And a histogram generator that generates the frequency distribution by accumulating the number of times the change in the latch result is detected at each timing based on the change point detection result output from the Can be detected.

  However, in the conventional example shown in FIG. 8, since one comparator, flip-flop, and control unit must repeatedly perform the above-described operation, it takes a long time to measure jitter. was there.

Further, the conventional example shown in Patent Document 1 requires a plurality of complicated variable delay circuits in order to generate a plurality of strobe signals, resulting in a problem that the circuit scale and power consumption increase.
Therefore, the problem to be solved by the present invention is to realize a jitter measuring apparatus capable of measuring timing and measuring jitter with a relatively small circuit scale and low power consumption.

In order to achieve the above-described problems, the invention described in claim 1 is included in the present invention.
In a jitter measurement device that measures jitter,
A voltage comparison unit that compares the voltage output from the test object with a plurality of preset voltages and outputs the comparison results, and a strobe signal that inputs the comparison results output from the voltage comparison unit A first latch and a second latch that output the respective latch results by latching at different timings; and an accumulation unit that accumulates the respective latch results output from the latch units to obtain a frequency distribution; And a control unit for obtaining a jitter value from the frequency distribution obtained by outputting the third strobe signal based on the strobe signal of the timing, thereby performing timing measurement and jitter measurement with a relatively small circuit scale and low power consumption. It becomes possible.

The invention according to claim 2
In the jitter measuring apparatus according to claim 1,
In the voltage comparison unit, a voltage output from the test object is input to an inverting input terminal, a voltage output from one of a plurality of variable voltage sources is input to a non-inverting input terminal, and the comparison is performed from an output terminal. By comprising a plurality of comparators that output the results, timing measurement and jitter measurement can be performed with a relatively small circuit scale and low power consumption.

The invention described in claim 3
In the jitter measuring apparatus according to claim 1,
The latch unit has a plurality of flip-flops that output one of the comparison results output from the voltage comparison unit to the data input terminal, the strobe signal to the clock terminal, and output the latch result from the data output terminal. Thus, timing measurement and jitter measurement can be performed with a relatively small circuit scale and low power consumption.

The invention according to claim 4
In the jitter measuring apparatus according to claim 1,
The integration unit is composed of a plurality of counters that input one of the latch results output from the latch unit to the input terminal and output the integration result from the output terminal, thereby enabling a relatively small circuit scale and low power consumption. Thus, timing measurement and jitter measurement can be performed.

The invention according to claim 5
In the jitter measuring apparatus according to claim 1,
The control unit outputs the first strobe signal a plurality of times to obtain a first frequency distribution, calculates a first voltage with an occurrence frequency of 50% in the first frequency distribution by interpolation, The second strobe signal is output a plurality of times to obtain a second frequency distribution, a second voltage with an occurrence frequency of 50% in the second frequency distribution is calculated by interpolation, and the first and second A relational expression indicating the relationship between the timing of the strobe signal and the first and second voltages is obtained, the timing of the strobe signal is obtained from a preset voltage based on the relational expression, and the third timing is determined based on this timing. A strobe signal is output a plurality of times, a third frequency distribution is obtained to calculate a voltage width, and this voltage width is converted into a time width to calculate jitter, thereby allowing a relatively small circuit scale and low power consumption. It is possible to make the ring measured and jitter measurements.

The invention described in claim 6
In the jitter measuring apparatus according to claim 5,
The control unit sets the voltage range in which the frequency of occurrence of the third frequency distribution is more than 0% and less than 100% as the voltage width, thereby enabling timing measurement and jitter with a relatively small circuit scale and low power consumption. Measurement can be performed.

The present invention has the following effects.
According to the inventions of claims 1, 2, 3, 4, 5 and claim 6,
Timing at which the voltage comparison unit compares the voltage output from the device under test with a plurality of preset voltages and outputs the result, and the comparison result obtained by the voltage comparison unit is input to the latch unit when the strobe signal is input. The result is latched and output, and the accumulating unit accumulates the latch results obtained by the latch unit to obtain the frequency distribution, and the control unit is obtained based on the first and second strobe signals having different timings, respectively. By obtaining the jitter value from the frequency distribution obtained by outputting the third strobe signal, it is possible to perform timing measurement and jitter measurement with a relatively small circuit scale and low power consumption.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a jitter measuring apparatus according to the present invention.

  In FIG. 1, reference numeral 6 denotes a jitter measuring unit, and 7 denotes a control unit constituted by an ASIC (Application Specific Integrated Circuit) or the like. Reference numeral 8 denotes a jitter measuring apparatus including a jitter measuring unit 6 and a control unit 7.

  The clock signal is input from the clock output terminal of the control unit 7 to the input terminal of the device under test indicated by “DUT110” in FIG. 1, and the signal under measurement is measured from the output terminal of the device under test indicated by “DUT110” in FIG. The signal is input to the measurement signal input terminal of the unit 6.

  A strobe signal is output from the strobe output terminal of the control unit 7 and input to the strobe input terminal of the jitter measurement unit 6. The measurement result is output from the output terminal of the jitter measurement unit 6 and input to the measurement result input terminal of the control unit 7. Is done.

  FIG. 2 is a specific configuration diagram of an embodiment of the jitter measuring apparatus according to the present invention. In FIG. 2, 9, 10, 11, 12, 13 and 14 are comparators, 15, 16, 17, 18, 19 and 20 are D-type flip-flops, and 21 is delay elements 22, 23, 24, 25, 26 and 27. And 28 are counters. In FIG. 2, 7 and 8 are assigned the same reference numerals as in FIG.

  Further, 50 is a voltage comparison unit 50 composed of comparators 9, 10, 11, 12, 13 and 14 and 50 is a latch unit 51 composed of flip-flops 15, 16, 17, 18, 19 and 20. , 24, 25, 26, 27, and 28.

  A signal under measurement is input to the inverting input terminals of the comparators 9, 10, 11, 12, 13, and 14 from the output end of the test target indicated by “DP110” in FIG.

  In FIG. 2, the output voltages of the variable voltage sources indicated by “VS111”, “VS112”, “VS113”, “VS114”, “VS115” and “VS116” are non-inverted by the comparators 9, 10, 11, 12, 13 and 14. Connected to each input terminal.

  Also, output signals are input from the output terminals of the comparators 9, 10, 11, 12, 13, and 14 to the data input terminals (D terminals) of the flip-flops 15, 16, 17, 18, 19, and 20.

  Strobe signals are respectively input to the clock terminals of the flip-flops 15, 16, 17, 18, 19 and 20, the input terminal of the delay element 21, and the input terminal of the counter 28. A reset signal is input from the output terminal of the delay element 21 to the reset signal input terminals (R terminals) of the flip-flops 15, 16, 17, 18, 19 and 20.

  Output signals are input from the data output terminals (Q terminals) of the flip-flops 15, 16, 17, 18, 19 and 20 to the input terminals of the counters 22, 23, 24, 25, 26 and 27.

  A reset signal is input to the reset signal input terminals of the counters 22, 23, 24, 25, 26, 27, and 28.

  The output terminals of the counters 22, 23, 24, 25, 26, 27 and 28 are indicated by “IP110”, “IP111”, “IP112”, “IP113”, “IP114”, “IP115” and “IP116” in FIG. Each is connected to an input terminal of the control unit 7.

  Here, the operation of the embodiment of the jitter measuring apparatus according to the present invention shown in FIGS. 1 and 2 will be briefly described.

  A predetermined comparison voltage (threshold value) is set by the control unit 7 in each of the comparators 9, 10, 11, 12, 13 and 14. At this time, a reference voltage is determined in advance when calculating the jitter value, and each comparison voltage is set based on the voltage.

  For example, the control unit 7 controls the variable voltage sources indicated by “VS111”, “VS112”, “VS113”, “VS114”, “VS115”, and “VS116” in FIG. 2 in advance using “VT4” as a reference voltage. The voltages input to the non-inverting input terminals of the comparators 9, 10, 11, 12, 13 and 14 are set to “VT1”, “VT2”, “VT3”, “VT4”, “VT5” and “VT” 6, respectively. To do.

  Further, the control unit 7 outputs a clock signal to the test object indicated by “DUT 110” in FIG. 1 a plurality of times. A signal under measurement is output from the object under test indicated by “DUT 110” in FIG. 1 and is input to the inverting input terminals of the comparators 9, 10, 11, 12, 13, and 14, respectively.

  Each time the comparator 9, 10, 11, 12, 13 and 14 receives a signal under measurement from the DUT 110 shown in FIG. 1, the voltage output from the DUT 110 shown in FIG. 1. 2 are compared with the voltage levels of the variable voltage sources indicated by “VS111”, “VS112”, “VS113”, “VS114”, “VS115”, and “VS116” in FIG.

  2 is output from the DUT 110 shown in FIG. 1 rather than the voltage of the variable voltage source shown in “VS111”, “VS112”, “VS113”, “VS114”, “VS115” and “VS116” in FIG. When the voltage is larger, low level output signals are output from the output terminals of the comparators 9, 10, 11, 12, 13 and 14, respectively, and the data input terminals of the flip-flops 15, 16, 17, 18, 19 and 20 are output. Is input.

  Further, the output from the test object shown in “DUT110” in FIG. 1 is higher than the voltage of the variable voltage source shown in “VS111”, “VS112”, “VS113”, “VS114”, “VS115” and “VS116” in FIG. When the applied voltage is smaller, high level output signals are output from the output terminals of the comparators 9, 10, 11, 12, 13 and 14, respectively, and the data of the flip-flops 15, 16, 17, 18, 19 and 20 are output. Input to the input terminal.

  Furthermore, the operation of the embodiment of the jitter measuring apparatus according to the present invention shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3, 4, 5, 6 and 7. FIG.

  FIG. 3 is a flowchart for explaining the operation of the embodiment of the jitter measuring apparatus according to the present invention. 4, 5, 6 and 7 are explanatory diagrams for explaining the operation of an embodiment of the jitter measuring apparatus according to the present invention. 4A and 4B are frequency distributions of output results of the latch unit 51 when the output timing of the strobe signal is “t = a” and “t = b”, respectively.

  In "S101" in FIG. 3, the control unit 7 outputs a strobe signal at the first timing. For example, the control unit 7 outputs a strobe signal a plurality of times at a timing of “t = a (t is time)” in synchronization with a plurality of signals to be measured output from the test target indicated by “DUT110” in FIG. . The strobe signal is input to the clock terminals of the flip-flops 15, 16, 17, 18, 19 and 20, one end of the delay element 21, and the input terminal of the counter 28.

  In the flip-flops 15, 16, 17, 18, 19, and 20, the latch results obtained by latching the output values of the comparators 9, 10, 11, 12, 13, and 14 at the time when the strobe signal is input are displayed as counters 22, 23, 24, 25, 26 and 27, respectively.

  For example, the flip-flop 15 outputs a high-level output signal to the counter 22 when the output signal from the comparator 9 is high when the strobe signal is input.

  The delay element 21 outputs a reset signal to the flip-flops 15, 16, 17, 18, 19 and 20 after being delayed for a predetermined time after the strobe signal is input.

  The flip-flops 15, 16, 17, 18, 19, and 20 receive the reset signal from the delay element 21 and reset the latched values.

  In the counters 22, 23, 24, 25, 26, and 27, when the output signals from the flip-flops 15, 16, 17, 18, 19, and 20 are high level, the counter value is incremented and the output signal is low level. In the case of, the counter value is not incremented. That is, the counters 22, 23, 24, 25, 26, and 27 accumulate the number of occurrences of high level output signals.

  Each time the strobe signal is input, the counter 28 increments the counter value and accumulates the number of strobes.

  The control unit 7 determines whether or not the necessary number of strobes set in advance has been exceeded, and outputs the reset signal to the counters 22, 23, 24, 25, 26, 27 and 28 when the necessary number of times is reached. 22, 23, 24, 25, 26, 27 and 28 reset the counter value.

  Next, in “S102” in FIG. 3, the control unit 7 calculates a voltage with an occurrence frequency of 50% in the frequency distribution obtained from the integration unit 52.

  For example, the control unit 7 obtains the frequency distribution of the output result of the latch unit 51 as shown in FIG. 4A from the counter values accumulated by the counters 22, 23, 24, 25, 26, 27, and 28. The controller 7 obtains a voltage “VTa” at which the occurrence frequency is 50% in the obtained frequency distribution by interpolation.

  Next, in “S103” in FIG. 3, the control unit 7 outputs the strobe signal at the second timing. For example, the control unit 7 outputs the strobe signal a plurality of times at the timing of “t = b”, and inputs it to the clock terminals of the flip-flops 15, 16, 17, 18, 19 and 20, the delay element 21, and one end of the counter 28. The

  Further, the operations in the voltage comparison unit 50, the latch unit 51, and the integration unit 52 in the step “S103” in FIG. 3 are the same as those in the step “S101” in FIG.

  Next, in “S104” in FIG. 3, the control unit 7 calculates a voltage with an occurrence frequency of 50% in the frequency distribution obtained from the integration unit 52.

  For example, the control unit 7 obtains the frequency distribution of the output result of the latch unit 51 as shown in FIG. 4B from the counter values accumulated by the counters 22, 23, 24, 25, 26, 27, and 28. The controller 7 obtains a voltage “VTb” at which the occurrence frequency is 50% in this frequency distribution by interpolation.

  Next, in “S105” in FIG. 3, the control unit 7 obtains the strobe timing (c) at the voltage “VT4” serving as a predetermined reference.

For example, the control unit 7 determines the strobe signal from the timings “t = a” and “t = b” at which the strobe signal is output and the voltages “VTa” and “VTb” at which the frequency distribution frequency at each timing is 50%. The relational expression showing the relation between the output timing and the voltage at which the frequency of occurrence of the frequency distribution is 50% is given by the following expression (1).
SR = (VTb−VTa) / (ba) (1)

Then, by using the relational expression obtained as shown in FIG. 5, the strobe timing (c) at the predetermined reference voltage “VT4” is obtained from the following expression (2) or expression (3).
c = (VT4-VTa) / SR + a (2)
c = (VT4-VTb) / SR + b (3)

  Next, in “S106” in FIG. 3, the control unit 7 outputs a strobe signal at a timing “t = c”. For example, the control unit 7 outputs the strobe signal a plurality of times at the timing of “t = c”, and inputs it to the clock terminals of the flip-flops 15, 16, 17, 18, 19, and 20, the delay element 21, and one end of the counter 28. The

  Further, the operations of the voltage comparison unit 50, the latch unit 51, and the integration unit 52 in the step “S106” in FIG. 3 are the same as those in the step “S101” in FIG.

  Next, in “S107” in FIG. 3, the control unit 7 calculates jitter based on the frequency distribution obtained from the integration unit 52.

  For example, the control unit 7 obtains the frequency distribution of the output result of the latch unit 51 as shown in FIG. 6 from the counter values accumulated by the counters 22, 23, 24, 25, 26, 27, and 28. Further, a voltage range in which the occurrence frequency exceeds 0% and is less than 100% (0% <frequency <100%) is calculated as a voltage width (ΔVj).

  Incidentally, the voltages whose occurrence frequencies are 0% and 100% are excluded from the voltage width (ΔVj) on the assumption that they are not in the jitter range because the output value of the voltage comparison unit 50 is unchanged. And

Further, as shown in FIG. 7, the control unit 7 obtains the jitter value (Tj) by the following equation (4) using the obtained voltage width (ΔVj) and the relational equation obtained in the step “S105” in FIG. .
Tj = ΔVj / SR (4)

  As a result, the voltage comparison unit compares the voltage output from the test object with a plurality of preset voltages and outputs the result, and the latch unit obtains the voltage comparison unit at the timing when the strobe signal is input. The comparison result is latched and the result is output. The accumulating unit accumulates the latch result obtained by the latch unit to obtain the frequency distribution, and the control unit obtains the first and second strobe signals having different timings. By obtaining the jitter value from the frequency distribution obtained by outputting the third strobe signal, timing measurement and jitter measurement can be performed with a relatively small circuit scale and low power consumption.

  In the embodiment shown in FIG. 1 and the like, it is exemplified that the voltage comparison unit 50 includes the comparators 9, 10, 11, 12, 13, and 14. However, the voltage comparison unit 50 is not limited to this, and the voltage comparison unit 50 is not limited thereto. The comparison unit may be composed of one or more comparators.

  In the embodiment shown in FIG. 1 and the like, the latch unit 51 is exemplified as being composed of flip-flops 15, 16, 17, 18, 19, and 20. The latch unit may be composed of one or more flip-flops as long as it detects the value of the output signal of the comparator constituting the voltage comparison unit at the timing when the signal is input.

  In the embodiment shown in FIG. 1 and the like, the control unit 7 uses the frequency distribution of the output result of the latch unit 51 in each comparison voltage obtained from the integrating unit 52 to generate a voltage width in which the occurrence frequency exceeds 0% and is less than 100%. However, the present invention is not particularly limited to this, and the control unit may divide the voltage into a positive voltage width ΔVjp and a negative voltage width ΔVjn with a voltage having a frequency of 50% as a boundary. .

  In the embodiment shown in FIG. 1 and the like, the comparators 9, 10, 11, 12, 13, and 14 have an inverting input terminal at the output end of the object to be tested indicated by “DP110” in FIG. 2, and a non-inverting input terminal. 2 are illustrated as being connected to variable voltage sources indicated by “VS111”, “VS112”, “VS113”, “VS114”, “VS115”, and “VS116”, respectively. Alternatively, the polarity of the comparator may be positive or negative as long as the control unit can integrate the generation frequency of the output signal from the latch unit.

  In the embodiment shown in FIG. 1 and the like, it is exemplified that the control unit 7 is configured by an ASIC or the like, but is not particularly limited thereto, and the control unit 7 is a hardware configured by a logic circuit or the like. It may be realized by hardware.

  In the embodiment shown in FIG. 1 and the like, it is exemplified that the delay element 21 is delayed for a certain time after the strobe signal is input, and the reset signal is output to the latch unit 51. However, the delay element 21 is not particularly limited to this. Alternatively, the control unit 7 may output a reset signal to the latch unit 51 after a strobe signal is output after a predetermined time delay.

  Further, in the embodiment shown in FIG. 1 and the like, the voltage comparison unit 50 is exemplified as being configured by the comparators 9, 10, 11, 12, 13, and 14. The comparator is composed of a differential comparator, and compares the voltage output from the device under test with a preset comparison voltage and outputs a high level signal if the voltage difference is a positive value. If it is a negative value, a low level signal may be output. Further, the comparison voltage set in the differential comparator may be set by a variable offset voltage.

  Further, in the embodiment shown in FIG. 1 and the like, it is exemplified that the output end of the object to be tested shown in “DP110” in FIG. 2 is connected to the comparator, but the present invention is not limited to this. A buffer circuit may be provided between the output terminal to be tested shown in the middle “DP110” and the comparator.

It is a block diagram which shows one Example of the jitter measuring apparatus which concerns on this invention. It is a concrete block diagram of one Example of the jitter measuring apparatus which concerns on this invention. It is a flowchart explaining operation | movement of one Example of the jitter measuring apparatus based on this invention. It is explanatory drawing explaining operation | movement of one Example of the jitter measuring apparatus based on this invention. It is explanatory drawing explaining operation | movement of one Example of the jitter measuring apparatus based on this invention. It is explanatory drawing explaining operation | movement of one Example of the jitter measuring apparatus based on this invention. It is explanatory drawing explaining operation | movement of one Example of the jitter measuring apparatus based on this invention. It is a block diagram which shows an example of the conventional jitter measuring apparatus. It is a specific block diagram of an example of the conventional jitter measuring apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 6 Jitter measuring part 2, 7 Control part 3, 8 Jitter measuring apparatus 4, 9, 10, 11, 12, 13, 14 Comparator 5, 15, 16, 17, 18, 19, 20 Flip-flop 21 Delay element 22 , 23, 24, 25, 26, 27, 28 Counter 50 Voltage comparison unit 51 Latch unit 52 Integration unit

Claims (6)

In a jitter measurement device that measures jitter,
A voltage comparison unit that compares the voltage output from the test object with a plurality of preset voltages and outputs each comparison result; and
A latch unit that latches each comparison result output from the voltage comparison unit at a timing when a strobe signal is input and outputs each latch result;
An integration unit for integrating each latch result output from the latch unit to obtain a frequency distribution;
And a control unit for obtaining a jitter value from the frequency distribution obtained by outputting a third strobe signal based on the first and second strobe signals having different timings. The voltage comparison unit is
A voltage output from the test object is input to an inverting input terminal, a voltage output from one of a plurality of variable voltage sources is input to a non-inverting input terminal, and a plurality of outputs of the comparison result are output from the output terminal. The jitter measuring apparatus according to claim 1, comprising a comparator. The latch portion is
One of the comparison results output from the voltage comparison unit is input to a data input terminal, the strobe signal is input to a clock terminal, and a plurality of flip-flops output the latch result from the data output terminal. The jitter measuring apparatus according to claim 1. The integrating unit is
2. The jitter measuring apparatus according to claim 1, wherein one of the latch results output from the latch unit is input to an input terminal and includes a plurality of counters that output an integration result from the output terminal. The control unit is
Outputting the first strobe signal a plurality of times to obtain a first frequency distribution;
A first voltage at which the frequency of occurrence in the first frequency distribution is 50% is calculated by interpolation;
Outputting the second strobe signal a plurality of times to obtain a second frequency distribution;
A second voltage with an occurrence frequency of 50% in the second frequency distribution is calculated by interpolation,
Obtaining a relational expression indicating the relationship between the timings of the first and second strobe signals and the first and second voltages,
Obtain the timing of the strobe signal from the preset voltage based on this relational expression,
Based on this timing, the third strobe signal is output a plurality of times to obtain a third frequency distribution to calculate a voltage width,
2. The jitter measuring apparatus according to claim 1, wherein the jitter is calculated by converting the voltage width into a time width. The control unit is
6. The jitter measuring apparatus according to claim 5, wherein a voltage range in which the occurrence frequency of the third frequency distribution is greater than 0% and less than 100% is defined as the voltage width.

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