JP2008134149A - Delay time evaluation method, circuit, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve independency, namely, incoherency, between a delay measuring object circuit and a delay time evaluation circuit, concerning the delay time evaluation circuit and a semiconductor device. <P>SOLUTION: The delay time evaluation circuit for evaluating a propagation delay time of a signal in a measuring circuit constituted of a plurality stages of gate circuits, and switching the number of connection stages, is equipped with: a phase difference detection circuit for detecting a phase difference between an input signal and a signal acquired by allowing the input signal to pass the circuit to be measured wherein the number of connection stages is switched to an optional number of stages; a conversion circuit part for generating a pulse train corresponding to the phase difference and outputting it to the outside; and a coupling part for coupling the circuit to be measured with the phase difference detection circuit by capacity coupling or noncontact coupling. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a delay time evaluation method and circuit, and a semiconductor device, and more particularly to a delay time suitable for evaluating propagation delay time of a gate circuit of about one to several stages in an AC manner, that is, while operating the circuit. The present invention relates to an evaluation method, a circuit, and a semiconductor device.

  In recent years, with the increase in the operation speed of semiconductor integrated circuits, it is required to accurately evaluate the delay time when a signal propagates in a circuit formed in a semiconductor device (or semiconductor chip). In particular, recently, it has been desired that the delay time and variations of gate circuits of about one to several stages can be accurately evaluated by actual measurement.

  FIG. 1 is a diagram showing an example of a conventional delay time evaluation circuit using a ring oscillator. In the delay time evaluation circuit shown in the figure, an evaluation target circuit 110 including a plurality of stages of gate circuits is provided with a ring oscillator 120 provided on a signal path, and an output oscillation signal of the ring oscillator 120 is divided by N (that is, 1 Frequency divider 130). In such a configuration, the frequency of the signal obtained by dividing the output oscillation signal of the ring oscillator 120 by N can be measured with a tester or the like, and the delay time of the circuit under evaluation 110 can be obtained based on the measured value. However, in such a method, an accurate delay time cannot be measured unless the number of gate stages of the circuit under evaluation 110 is at least about 10, and the delay time of the gate circuit for one stage can only be obtained as an average value. It was. In FIG. 1, T indicates one cycle of the output oscillation signal of the ring oscillator 120.

  In response to such a problem, the gate circuit to be evaluated is incorporated into a DLL (Delay Locked Loop), and the control voltage of the variable delay circuit in the DLL is converted into the delay time of the gate circuit, thereby providing a gate circuit for one stage. There has been proposed a delay time evaluation circuit capable of measuring the delay time. FIG. 2 is a diagram illustrating an example of a delay time evaluation circuit capable of measuring the delay time of the gate circuit for one stage as described above.

  The delay time evaluation circuit shown in FIG. 2 includes a DLL 200 for outputting the delay clock signal DCLK and a DLL 300 for outputting a voltage converted value of the delay time of the circuit under evaluation 340. The DLL 200 includes a variable delay circuit 210 that delays the reference clock signal REFCLK, and the variable delay circuit 210 includes a plurality of stages of delay elements whose delay amount is controlled by a control voltage Vd1. The delay amount of the variable delay circuit 210 is controlled so that the phase of the output clock signal OUT1 matches the reference clock signal REFCLK. The delay clock signal DCLK can be output to the switch 220 from a plurality of delay stages of the variable delay circuit 210. By switching the switch 220, the reference clock signal REFCLK is delayed according to the number of stages of the delay stages. Delayed clock signal DCLK is output.

  The DLL 300 includes a phase comparison circuit 310, a voltage regulator 320, a variable delay circuit 330, and a circuit under evaluation 340. The phase comparison circuit 310 compares the phases of the output clock signal OUT2 of the DLL 300 and the reference clock signal REFCLK, and the voltage regulator 320 outputs a control voltage Vd2 to be supplied to the variable delay circuit 330 according to the comparison result. The variable delay circuit 330 delays the delayed clock signal DCLK from the switch 220 according to the control voltage Vd2. The evaluated circuit 340 includes a plurality of stages of gate circuits capable of changing the number of connection stages, operates in accordance with an output clock signal of the variable delay circuit 330, and outputs an output clock signal OUT2.

  In the DLL 300, the control voltage Vd2 of the variable delay circuit 330 is adjusted so that the phase of the output clock signal OUT2 matches the reference clock signal REFCLK. Further, when the switch position of the switch 220 is fixed, the total signal delay time by the variable delay circuit 330 and the evaluated circuit 340 is always constant, so that it is variable when the number of stages of the gate circuit of the evaluated circuit 340 is changed. The change amount of the control voltage Vd2 of the delay circuit 330 can be converted into the change amount of the delay time in the circuit to be evaluated 340, and the delay amount of the gate circuit for one stage to several stages can be measured with high accuracy. Such a delay time evaluation circuit is proposed in Patent Document 1, for example.

  As a conventional technique related to the above, a circuit path to be measured including a circuit to be measured and a dummy circuit path having a configuration in which the circuit to be measured is bypassed from this path are provided, and based on a phase difference between output signals of both circuit paths. For example, Patent Document 2 proposes a delay time measuring device that controls the variable delay circuit to align the phase of the input signal to each circuit path and obtains the delay time of the circuit under test from the difference in delay time in each circuit path. ing.

  When the delay time evaluation circuit shown in FIG. 2 is provided in a semiconductor integrated circuit including the circuit to be evaluated 340, since the mounting area of the loop filter provided in the voltage regulator 320 of the DLL 300 is large, the area of the entire circuit increases. There was a problem. In particular, in the delay time evaluation circuit of this configuration, a plurality of DLLs 300 can be provided by sharing the DLL 200 that generates the delay clock DCLK, and the delay times of a large number of gate circuits can be measured. Since the number of loop filters is provided, the circuit area increases accordingly.

  In addition, in order to perform high-accuracy measurement with the above-described delay time evaluation circuit, for example, a voltage calibration circuit that prevents the control voltage Vd2 from changing according to the circuit arrangement of the DLL 300 or the like, and a signal reading error at the pad are used. A circuit or the like to be reduced is actually required, which causes a further increase in circuit area.

Further, in the delay time evaluation circuit described above, it is necessary to measure the control voltage Vd2 using an oscilloscope or the like. Further, when the control voltage Vd2 is converted into a delay time, an error in the delay time caused by the switching position of the switch 220 needs to be estimated in advance based on the measured value of the delay clock signal DCLK. The calibration voltage of the calibration circuit must also be calculated in advance. Therefore, the measurement time may be prolonged due to these causes.
JP 2005-227129 A Japanese Patent Laid-Open No. 2001-263497

  The conventional delay time evaluation circuit is designed with an emphasis on accurately evaluating the delay time of a gate circuit composed of a small number of stages in a short time without increasing the circuit area. It has not been considered to improve the versatility of the evaluation circuit and improve the independence of the delay measurement target circuit and the delay time evaluation circuit, that is, non-interference.

  Therefore, an object of the present invention is to provide a delay time evaluation method and circuit, and a semiconductor device, which can improve the independence of the delay measurement target circuit and the delay time evaluation circuit, that is, the incoherence.

  The above-described problem is a delay time evaluation circuit that evaluates the propagation delay time of a signal in a circuit under test, which is composed of a plurality of stages of gate circuits and the number of connection stages is switchable. A phase difference detection circuit that detects a phase difference of a signal passing through the circuit under measurement whose connection stage number is switched to an arbitrary number of stages, and a conversion circuit unit that generates a pulse train according to the phase difference and outputs the pulse train to the outside The delay time evaluation circuit includes a coupling means for coupling the circuit under measurement and the phase difference detection circuit by capacitive coupling or non-contact coupling.

  The above object can also be achieved by a semiconductor device comprising the delay time evaluation circuit as described above.

  The above-described problem is a delay time evaluation method for evaluating the propagation delay time of a signal in a circuit under test, which is composed of a plurality of stages of gate circuits and the number of connection stages can be switched. A phase difference detection step for detecting a phase difference of a signal passing through the circuit under measurement whose connection stage number is switched to an arbitrary number of stages, a conversion step for generating a pulse train corresponding to the phase difference and outputting the pulse train to the outside, This can also be achieved by a delay time evaluation method including a coupling step of coupling the circuit under measurement and the phase difference detection circuit by capacitive coupling or non-contact coupling.

  ADVANTAGE OF THE INVENTION According to this invention, the delay time evaluation method and circuit which can improve the independence of a delay measuring object circuit and a delay time evaluation circuit, ie, incoherence, and a semiconductor device are realizable.

  Hereinafter, embodiments of the delay time evaluation method and circuit and the semiconductor device according to the present invention will be described with reference to FIG.

  FIG. 3 is a diagram showing a comparative example of a delay time evaluation circuit capable of measuring the delay time of the gate circuit for one stage. The delay time evaluation circuit shown in FIG. 3 includes a reference clock generation circuit 400, a DLL circuit 500, and a frequency counter 600.

  The reference clock generation circuit 400 includes a digital / analog converter (DAC) 410 and a ring oscillator 420. Digital data from an external tester 701 is input to the DAC 410. The ring oscillator 420 generates a reference clock signal REFCLK based on the signal bias from the DAC and supplies the reference clock signal REFCLK to the frequency counter 600 and the DLL circuit 500. Digital data from the frequency counter 600 is output to the tester 701.

  The DLL circuit 500 includes a phase comparison circuit 510, a counter 520, variable delay circuits 530, 540, and 550, an evaluated circuit group 560 and a code reader 570. The reference clock signal REFCLK is supplied to the phase comparison circuit 510 and the variable delay circuit 530.

  The variable delay circuits 530, 540, 550 and a plurality of delay stages whose delay times are variable according to the corresponding control signals Df, Dm, Dc are cascaded to delay the reference clock signal REFCLK. The evaluated circuit group 560 includes a plurality of evaluated circuits that can switch the number of connection stages. The phase comparison circuit 510 compares the phase of the reference clock signal REFCLK with the phase of the output clock signal CLKOUT in which the reference clock signal REFCLK has propagated through the variable delay circuits 530, 540, 550 and the circuit group 560 to be evaluated, and compares the comparison result. Output to the counter 520. The count value of the counter 520 is increased or decreased according to the comparison result of the phase comparison circuit 510 and is output as the control signals Df, Dm, Dc. Thereby, the delay time of the variable delay circuit is controlled so that the phase of the output clock signal CLKOUT matches the phase of the reference clock signal REFCLK. The count value of the counter 520 is output to the tester 701 via the code reader 570.

  The sum of the propagation delay times of the signals by the variable delay circuits 530, 540, 550 and the evaluated circuit group 560 is equal to the cycle of the reference clock signal REFCLK. Since the delay times of the variable delay circuits 530, 540, and 550 are controlled based on the count value from the counter 520, the delay time in the circuit under test 560 can be expressed as a function of the count value. On the other hand, when the number of connection stages of the circuits to be evaluated in the circuit group to be evaluated 560 is fixed, the relationship between the delay time in the circuit group to be evaluated 560 and the count value of the counter 520 is changed by changing the cycle of the reference clock signal REFCLK. Can be requested. Accordingly, by changing the number of connection stages of the circuits to be evaluated in the circuit group to be evaluated 560, the count value of the counter 520 is read by the tester 701 through the code reader 570 each time, so that the circuits to be evaluated for any number of connection stages can be obtained. The delay time can be evaluated. Further, by controlling the delay times of the variable delay circuits 530, 540, and 550 with the digital control signals Df, Dm, and Dc from the counter 520, a loop filter that is necessary in the case of analog control becomes unnecessary, and delay time evaluation is performed. The circuit area of the circuit can be greatly reduced. Furthermore, since it is not necessary to detect an error in voltage value or delay using an oscilloscope or the like, the user operation is simplified and the time required for evaluation is shortened.

    However, in order to design a circuit with reduced time resolution that determines the voltage waveform fluctuation of the reference clock signal REFCLK generated by the reference clock generation circuit 400, complicated control is required, and the versatility of the delay time evaluation circuit is reduced. End up.

  Therefore, the first implementation of a delay time evaluation circuit and a semiconductor device capable of accurately evaluating the delay time of a gate circuit composed of a small number of stages in a short time without increasing the versatility and increasing the circuit area. An example is described below.

  FIG. 4 is a diagram showing a first embodiment of a delay time evaluation circuit according to the present invention. This embodiment of the delay time evaluation circuit adopts the first embodiment of the delay time evaluation method and is provided in the first embodiment of the semiconductor device. The delay time evaluation circuit 10 shown in FIG. 4 is provided in a semiconductor device (or semiconductor chip). The delay time evaluation circuit 10 includes a circuit under test 21, a phase difference detection circuit 22, a phase difference / current conversion circuit 23, a capacitor 24, an analog / digital converter (ADC) 25, and a pulse train generation circuit connected as shown in FIG. 26. A clock signal REFCK from an external tester (not shown) is input to the circuit under measurement 21 and the phase difference detection circuit 22. The output signal DELCK of the circuit under test 21 is also input to the phase difference detection circuit 22.

  The circuit under test 21 is composed of a plurality of stages of gate circuits connected in series like the circuit under test 110 shown in FIG. 1, for example, and the number of connection stages can be switched by a known method.

  The delay time evaluation circuit 10 only exchanges digital data with an external tester. For this reason, the measurement time can be shortened, and at the same time, adaptability to various measurement environments is increased, so that versatility is improved. Further, in FIG. 3, the essential high-precision reference clock generation circuit 400 can be omitted, so that the versatility of the delay time evaluation circuit 10 is improved from the viewpoint of increasing the degree of design freedom.

  The clock signal REFCK in FIG. 4 is required to have a stable pulse rising shape, but the tester that generates the clock signal REFCK may have the same performance as a general-purpose logic tester. That's fine. Depending on the performance of the tester used, a simple circuit that makes the rising waveform of the pulse of the clock signal REFCK constant may be provided at the output stage of the tester or the input stage of the delay time evaluation circuit 10.

  FIG. 5 is a timing chart showing signal waveforms in each part of the delay time evaluation circuit 10 shown in FIG. The clock signal REFCK output from the tester and the signal DELCK obtained by delaying the clock signal REFCK through the circuit under test 21 are input to the phase difference detection circuit 22. For convenience of explanation, it is assumed that the number of stages of the circuit under measurement 21 is n (n is an integer), and the delay in the circuit under measurement 21 is T2 (n). The phase difference detection circuit 22 outputs a pulse PULSE corresponding to the delay T2 (n) of the circuit under measurement 21. The pulse PULSE is converted into a current corresponding to the delay T2 (n) by the phase difference / current conversion circuit 23, and the current is charged in the capacitor 24. As a result, the voltage at the node N1 connecting the phase difference / current conversion circuit 23, the capacitor 24, and the ADC 25 becomes v. The voltage v is converted into digital data by the ADC 25, and the digital data (that is, digital code) is converted into a pulse train OUT having a number of pulses corresponding to the value of the digital data by the pulse train generation circuit 26 and output to the tester. The pulse train OUT is read by a tester. Here, the voltage resolution of the ADC 25 is set according to the target time resolution, and the number of pulses of the pulse train OUT output from the pulse train generation circuit 26 changes according to the delay time T2 (n). The phase difference / current conversion circuit 23, the capacitor 24, the ADC 25, and the pulse train generation circuit 26 constitute a conversion circuit unit that generates and outputs a pulse train OUT corresponding to the phase difference between the clock signal REFCK and the signal DELCK.

  Next, when the number of stages of the circuit under test 21 is switched from n stages to n1 stages (n1 is an integer) and the same measurement is performed, the voltage v changes to the voltage v1. The switching of the number of stages of the circuit under test 21 can be performed by a known method. The number of pulses in the pulse train OUT changes according to the voltage difference (v1−v) between the voltage v and the voltage v1, and the changed amount corresponds to the delay time of | n−n1 | Therefore, the tester can measure the delay time of each stage of the circuit under test 21 based on the pulse train OUT output from the pulse train generation circuit 26.

  Since the capacitor 24 is ideally composed of an element having a capacitance having no voltage dependency, it is necessary to evaluate a deviation from an ideal characteristic of an actually used element. For example, if a plurality of offset delay amounts can be added to the delay time T2 (n), the phase difference / current conversion circuit 23 is compared to the circuit under measurement 21 in which each stage is composed of the same element with n stages. Outputs a plurality of voltages v for each offset delay amount. Next, when the number of stages of the circuit under test 21 is changed, the number of pulses of the pulse train OUT output via the ADC 25 and the pulse train generation circuit 26 is changed with respect to each offset delay amount, including the offset delay amount of zero. It may be confirmed that there is no change, or correction such as treating the change in the number of pulses as a measurement error may be performed on the tester side.

  FIG. 6 is a diagram illustrating the relationship between the voltage v (arbitrary unit) and the delay time T2 (n) (arbitrary unit) on the input side of the node N1, that is, the ADC 25. In FIG. 6, I indicates a linear characteristic when the relationship between the voltage v and the delay time T2 (n) is linear, and II indicates a nonlinear characteristic when the relationship between the voltage v and the delay time T2 (n) is nonlinear. Show.

  FIG. 7 is a diagram showing the relationship between the digital code value (arbitrary unit) on the output side of the ADC 25 and the stage number n (arbitrary unit). When the offset delay amount with respect to the delay time T2 (n) is Δ1, the relationship between the value of the digital code output from the ADC 25 and the number n of stages of the circuit under test 21 is as indicated by IV-1 in FIG. Here, for the same number of stages n, the difference between the values of the output digital data of the ADC 25 when the offset delay amount indicated by III is zero and when the offset delay amount indicated by IV-1 is Δ1 is assumed to be δ1. In FIG. 7, IV-2 shows the relationship between the value of the output digital data of the ADC 25 and the number of stages n of the circuit under test 21 when the offset delay amount with respect to the delay time T2 (n) is Δ2.

  If the relationship between the input voltage v of the ADC 25 and the delay time T2 (n) is linear as indicated by I in FIG. 6, the difference δ1 shown in FIG. 7 does not change even if the number of stages n changes. On the other hand, if the relationship between the input voltage v of the ADC 25 and the delay time T2 (n) is non-linear as indicated by II in FIG. 6, the difference δ1 shown in FIG. 7 shows non-linear changes as the number of stages n changes. Therefore, the measurement by the tester is basically performed after confirming the range of the number of stages n such that δ1 does not change with respect to the switching of the number of stages n. If n exists in a range where δ1 changes with respect to the switching of the number of stages n, the tester may handle the change as a measurement error.

  If the function of the pulse train generation circuit 26 is provided on the tester side, the pulse train generation circuit 26 in the delay time evaluation circuit may be omitted, and the output digital code of the ADC 25 may be output to the tester.

  In the above embodiment, the delay time of an arbitrary number of stages in the circuit under test 21, that is, the gate delay time is measured by a tester using one pulse of the pulse train OUT output from the pulse train generation circuit 26 as a unit of time. However, when the delay time measured in this way is not sufficient, and when it is desired to know the time value of one pulse in the pulse train OUT, for example, as in the second embodiment described below, for example, a circuit under test In FIG. 21, ring oscillation can be performed as shown in FIG. 1 for some values of n when the number of stages n is somewhat large, and the oscillation frequency for each stage may be measured.

  FIG. 8 is a diagram showing a second embodiment of the delay time evaluation circuit according to the present invention. This embodiment of the delay time evaluation circuit adopts the second embodiment of the delay time evaluation method and is provided in the second embodiment of the semiconductor device. In FIG. 8, the same parts as those in FIG.

  In FIG. 8, the circuit under measurement 21 can constitute a ring oscillator unit 37 together with the frequency divider 36. The path for inputting the clock signal REFCK from the tester to the circuit under test 21 and the path for inputting the output signal DELCK from the circuit under test 21 to the phase difference detection circuit 22 can be cut as indicated by S in FIG. . The path division can be realized by a switch circuit, for example. When the path is disconnected by a switch circuit or the like, the input of the first stage gate circuit and the output of the arbitrary stage gate circuit in the circuit under test 21 are connected like the connection of the ring oscillator 120 shown in FIG. A ring oscillator is configured by connecting using another switch circuit or the like. The output of the ring oscillator is output to the tester via the frequency divider 36.

  Therefore, if the circuit under measurement 21 of the ring oscillator unit 37 is ring-oscillated with respect to several values of n when the number of stages n in the circuit under test 21 is somewhat large, the tester uses the output of the frequency divider 36 to determine the number of stages. The oscillation frequency for can be measured. The time per pulse of the pulse train OUT can be calculated by the tester from the difference in the oscillation frequency with respect to the number of stages thus measured. As a result, the delay time of an arbitrary number of stages of the circuit under test 21 can be measured by the tester in units of time values for one pulse of the pulse train OUT.

  According to each of the above embodiments, the delay time of the circuit under evaluation for any number of connection stages can be accurately evaluated by reading the output of the ADC through the tester while changing the number of connection stages of the circuit under evaluation. In particular, the delay time of the circuit to be evaluated can be evaluated in units of one stage, not the average value of each stage. In addition, since it is not necessary to detect an error in voltage value or delay using an oscilloscope or the like, the user's operation is simplified and a general-purpose tester can be used. In addition to this, since the connection between the delay time evaluation circuit and the tester can be realized only by the digital interface, the time required for the evaluation is shortened. Furthermore, since a highly accurate reference clock generation circuit is not required, the versatility of the delay time evaluation circuit is improved from the viewpoint of increasing the degree of design freedom of the delay time evaluation circuit.

  FIG. 9 is a diagram showing a third embodiment of the delay time evaluation circuit according to the present invention. This embodiment of the delay time evaluation circuit employs a third embodiment of the delay time evaluation method and is provided in the third embodiment of the semiconductor device. 9, parts that are the same as those in FIGS. 4 and 8 are given the same reference numerals, and descriptions thereof are omitted.

  The circuit under test 21 includes an inverter array unit 51 and a selection unit 52. The inverter array 51 includes inverters 61 connected as shown in FIG. The selection unit 52 includes a capacitor 73, a resistor 74, and a switch 75 connected as shown in FIG. By opening and closing the switch 75, it is possible to select the number of inverters 61 and the number of inverters 61 that should constitute the inverter array section 51. The clock signal REFCK is input as a reference signal to the input terminal of the inverter string unit 51 formed of the serial connection of the selected inverter 61, and the output signal DELCK output from the output terminal of the inverter string unit 51 is input to the delay time evaluation circuit 10B. Entered. In the arrangement shown in FIG. 9, the wiring distance from the output of each inverter 61 to the delay time evaluation circuit 10 </ b> B is substantially the same, and the propagation delay due to the wiring is substantially constant regardless of the selected inverter 61.

  The delay time evaluation circuit 10 </ b> B further includes a capacitor 81, a resistor 82, and an amplifier 83 connected as shown in FIG. 9, and an output signal of the amplifier 83 is input to the phase difference detection circuit 22. As a result, the clock signal REFCK from the circuit under test 21 is amplified by the amplifier 83 via the capacitive coupling means composed of the capacitor 81 and the resistor 82 and then input to the phase difference detection circuit 22. 21 and the independence of the delay time evaluation circuit 10B, that is, non-interference can be improved. As a result, not only the circuit under test 21 having the configuration shown in FIG. 9 but also various delay data of non-measurement circuits having various configurations can be measured and evaluated by the delay time evaluation circuit 10B.

  The configuration of the capacitive coupling means is not limited to the configuration shown in FIG.

  FIG. 10 is a diagram showing a fourth embodiment of the delay time evaluation circuit according to the present invention. This embodiment of the delay time evaluation circuit employs a fourth embodiment of the delay time evaluation method and is provided in the fourth embodiment of the semiconductor device. 10, parts that are the same as those in FIGS. 4, 8, and 9 are given the same reference numerals, and descriptions thereof are omitted.

  The delay time evaluation circuit 10C further includes a transmitter unit (Tx) 91, a receiver unit (Rx) 93, and a pair of coils 92 provided between the transmitter unit 91 and the receiver unit 93 connected as shown in FIG. The output signal of the receiver 93 is input to the phase difference detection circuit 22. As a result, the clock signal REFCK from the circuit under test 21 is input to the phase difference detection circuit 22 via the non-contact coupling means including the transmitter unit 91, the coil 92, and the receiver unit 93. Independence of the delay time evaluation circuit 10C, that is, non-interference can be improved. As a result, not only the circuit under test 21 having the configuration shown in FIG. 10 but also various delay data of non-measurement circuits having various configurations can be measured and evaluated by the delay time evaluation circuit 10C.

  The configuration of the non-contact coupling means is not limited to the configuration shown in FIG.

In addition, this invention also includes the invention attached to the following.
(Supplementary Note 1) A delay time evaluation circuit that evaluates a propagation delay time of a signal in a circuit under test, which is composed of a plurality of stages of gate circuits and the number of connection stages is switchable,
A phase difference detection circuit for detecting a phase difference between the input signal and the signal passing through the circuit under measurement in which the number of connection stages of the input signal is switched to an arbitrary number of stages;
A conversion circuit unit that generates a pulse train according to the phase difference and outputs the pulse train to the outside;
A delay time evaluation circuit comprising: coupling means for coupling the circuit under measurement and the phase difference detection circuit by capacitive coupling or non-contact coupling.
(Appendix 2) The conversion circuit section
A phase difference / current conversion circuit for converting the phase difference into a current;
A capacitor charged by the current;
An analog / digital converter for converting the voltage of the capacitor into a digital code;
The delay time evaluation circuit according to appendix 1, further comprising: a pulse train generation circuit that converts the digital code into the pulse train having the number of pulses corresponding to the value of the digital code.
(Supplementary Note 3) The number of pulses in the pulse train corresponds to the delay time of the input signal in the circuit under test.
The voltage of the capacitor changes from the voltage v to the voltage v1 when the number of stages of the circuit under test is switched from n to n1 (n and n1 are integers).
The value of the digital code output from the analog / digital converter changes according to the voltage difference (v1-v), and the changed amount corresponds to the delay time of | n−n1 | stage of the circuit under test. The delay time evaluation circuit according to appendix 2, wherein
(Supplementary Note 4) A frequency divider is further provided that divides the output of the circuit under test and outputs it to the outside.
The path for inputting the input signal to the circuit under test and the path for inputting the input signal through the circuit under test to the phase difference detection circuit can be disconnected, and the first stage in the circuit under test can be disconnected. 4. The delay time evaluation circuit according to any one of appendices 1 to 3, wherein a ring oscillator is configured by connecting an input of a gate circuit and an output of a gate circuit at an arbitrary stage.
(Additional remark 5) The semiconductor device provided with the delay time evaluation circuit of any one of Additional remarks 1-4.
(Supplementary Note 6) A delay time evaluation method for evaluating a propagation delay time of a signal in a circuit under test, which is composed of a plurality of stages of gate circuits and the number of connection stages is switchable,
A phase difference detection step of detecting a phase difference between the input signal and the signal passing through the circuit under measurement in which the number of connection stages of the input signal is switched to an arbitrary number of stages;
A conversion step of generating a pulse train corresponding to the phase difference and outputting the pulse train to the outside;
A delay time evaluation method comprising a coupling step of coupling the circuit under measurement and the phase difference detection circuit by capacitive coupling or non-contact coupling.
(Supplementary note 7) The conversion step is:
Converting the phase difference into current,
Charging the capacitor with the current;
Analog / digital conversion of the voltage of the capacitor to digital code,
The delay time evaluation method according to appendix 6, wherein the digital code is converted into the pulse train having the number of pulses corresponding to the value of the digital code.
(Supplementary Note 8) The number of pulses in the pulse train corresponds to the delay time of the input signal in the circuit under test.
The voltage of the capacitor changes from voltage v to voltage v1 when the number of stages of the circuit under test is switched from n to n1.
The value of the digital code output from the analog / digital converter changes according to the voltage difference (v1-v), and the changed amount corresponds to the delay time of | n−n1 | stage of the circuit under test. The delay time evaluation method according to appendix 7, wherein
(Supplementary Note 9) The path for inputting the input signal to the circuit to be measured and the path for inputting the input signal that has passed through the circuit to be measured to the phase difference detection circuit are disconnected. Configuring the ring oscillator by connecting the input of the gate circuit of the stage and the output of the gate circuit of any stage; and
The delay time evaluation method according to any one of appendices 6 to 8, further comprising a step of dividing the output of the circuit under measurement and outputting the output to the outside.
(Supplementary Note 10) The range of the stage number n was confirmed such that the difference δ1 in the digital code value when the offset delay amount is zero and the offset delay amount is Δ1 does not change with respect to the switching of the stage number n for the same stage number n. The delay time evaluation method according to any one of appendices 6 to 9, further comprising a step of measuring the pulse train with a tester.
(Supplementary note 11) The delay according to Supplementary note 10, wherein the tester includes a step of handling the change as a measurement error if n exists in a range in which the difference δ1 changes when the number of stages n is switched. Time evaluation method.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is a figure which shows an example of the conventional delay time evaluation circuit using a ring oscillator. It is a figure which shows an example of the delay time evaluation circuit which can measure the delay time of the gate circuit for one stage. It is a figure which shows the comparative example of the delay time evaluation circuit which can measure the delay time of the gate circuit for one stage. It is a figure which shows 1st Example of the delay time evaluation circuit which becomes this invention. FIG. 5 is a timing chart showing signal waveforms in various parts of the delay time evaluation circuit shown in FIG. 4. FIG. It is a figure which shows the relationship between the voltage v on the input side of ADC, and delay time T2 (n). It is a figure which shows the relationship between the value of the digital code in the output side of ADC, and the stage number n of a to-be-measured circuit. It is a figure which shows 2nd Example of the delay time evaluation circuit which becomes this invention. It is a figure which shows 3rd Example of the delay time evaluation circuit which becomes this invention. It is a figure which shows the 4th Example of the delay time evaluation circuit which becomes this invention.

Explanation of symbols

10, 10A, 10B, 10C Delay time evaluation circuit 21 Circuit under test 22 Phase difference detection circuit 23 Phase difference / current conversion circuit 24 Capacitor 25 ADC
26 Pulse train generation circuit 36 Frequency divider 37 Ring oscillator 81 Capacitor 82 Resistor 83 Amplifier 91 Transmitter unit 92 Coil 93 Receiver unit

Claims (6)

A delay time evaluation circuit that evaluates the propagation delay time of a signal in a circuit under test, which is composed of a plurality of stages of gate circuits and the number of connection stages is switchable,
A phase difference detection circuit for detecting a phase difference between the input signal and the signal passing through the circuit under measurement in which the number of connection stages of the input signal is switched to an arbitrary number of stages;
A conversion circuit unit that generates a pulse train according to the phase difference and outputs the pulse train to the outside;
A delay time evaluation circuit comprising: coupling means for coupling the circuit under measurement and the phase difference detection circuit by capacitive coupling or non-contact coupling. The conversion circuit section
A phase difference / current conversion circuit for converting the phase difference into a current;
A capacitor charged by the current;
An analog / digital converter for converting the voltage of the capacitor into a digital code;
2. The delay time evaluation circuit according to claim 1, further comprising a pulse train generation circuit that converts the digital code into the pulse train having the number of pulses corresponding to the value of the digital code. The number of pulses in the pulse train corresponds to the delay time of the input signal in the circuit under test,
The voltage of the capacitor changes from the voltage v to the voltage v1 when the number of stages of the circuit under test is switched from n to n1 (n and n1 are integers).
The value of the digital code output from the analog / digital converter changes according to the voltage difference (v1-v), and the changed amount corresponds to the delay time of | n−n1 | stage of the circuit under test. The delay time evaluation circuit according to claim 2, wherein:   A semiconductor device comprising the delay time evaluation circuit according to claim 1. A delay time evaluation method for evaluating a propagation delay time of a signal in a circuit under test, which is composed of a plurality of stages of gate circuits and the number of connection stages is switchable,
A phase difference detection step of detecting a phase difference between the input signal and the signal passing through the circuit under measurement in which the number of connection stages of the input signal is switched to an arbitrary number of stages;
A conversion step of generating a pulse train corresponding to the phase difference and outputting the pulse train to the outside;
A delay time evaluation method comprising a coupling step of coupling the circuit under measurement and the phase difference detection circuit by capacitive coupling or non-contact coupling. The conversion step includes:
Converting the phase difference into current,
Charging the capacitor with the current;
Analog / digital conversion of the voltage of the capacitor to digital code,
6. The delay time evaluation method according to claim 5, wherein the digital code is converted into the pulse train having the number of pulses corresponding to the value of the digital code.

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