JP2008130980A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory device forming a large-capacity capacitor, by forming an upper part electrode over the entire surface of a dielectric layer in a groove, without reducing the grain size of an HSG-Si layer nor closing the opening part of the groove that forms a cylinder-type capacitor with HSG-Si. <P>SOLUTION: The manufacturing method of a semiconductor device, equipped with a capacitor formed with a cylinder structure, includes, at least a process in which an oxide film is deposited; a process for forming a cylinder for constituting a capacitor inside of it on the oxide film; a process for forming an amorphous silicon film along the inside surface of the cylinder, for forming a mask layer that suppresses growth of HSG on the amorphous silicon film in the inner peripheral region near a cylinder opening part; a process in which the amorphous silicon is subjected to HSG process and then converted into polycrystalline silicon at the same time; a process for removing the mask layer, a process for forming an insulating film on the polycrystalline silicon; and a process for forming a conductive layer on the insulating film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a capacitor having hemispherical silicon grains (hereinafter referred to as HSG-Si).

As miniaturization of semiconductor elements progresses, memory cells used in DRAMs (Dynamic Random Access Memory) are also reduced in size, and it becomes difficult to secure sufficient capacitor capacity in a storage capacity unit for storing data. Yes.
However, in order to ensure the stable operation and reliability of the DRAM, a capacitor capacity of a certain level or more is required.
As one of the measures for securing a predetermined capacitor capacity, it is conceivable to secure the surface area of the region where the capacitor is formed.
That is, as a capacitor structure, efforts are being made to increase capacitance by a three-dimensional structure, such as a stack type capacitor formed above a semiconductor substrate, a trench type capacitor formed on the inner peripheral surface of a groove deeply engraved in the semiconductor substrate. .

Furthermore, as a method of securing the capacitor capacity by increasing the surface area of the capacitor forming region, a structure in which a large number of HSG-Si is formed on the silicon film surface of the lower electrode in the capacitor is actively used. (For example, refer to Patent Document 1).
On the other hand, in recent years, in order to increase the surface area of the capacitor as much as possible, the groove forming the cylinder type capacitor has been formed deeper.
A conventional method for manufacturing a semiconductor memory device including the cylinder capacitor and HSG-Si will be described below with reference to FIGS.

As shown in FIG. 13, an element isolation region 102 is formed on a semiconductor substrate 101, and a well formation and channel doping process (not shown) is performed. Further, a gate electrode 103 made of a silicon film and a metal film such as W is formed, and an n-type diffusion layer is formed between the gate electrode 103 as a source and a drain (this n-type diffusion layer is not shown). Thereby, a memory cell selecting MOS transistor in the memory element is formed.
Next, a first interlayer insulating film 104 made of a laminated film of a BPSG (Boron Phospho Silicate Glass) film and an NSG (Non-doped Silicate Glass) film is formed on the entire surface of the semiconductor substrate 101 on which the MOS transistor is formed. Do the membrane.

A contact plug hole 105 reaching the n-type diffusion layer as the source and drain on the semiconductor substrate 101 is formed in the first interlayer insulating film 104 formed by anisotropic etching.
Then, a polycrystalline silicon film doped with phosphorus of a predetermined concentration as an impurity is deposited on the entire surface, that is, the polycrystalline silicon film is filled in the contact plug hole 105 and deposited on the interlayer insulating film 104.
The deposited polysilicon film is removed from the first interlayer insulating film 104 by dry etching technique etch back and chemical mechanical polishing (CMP) technique. Then, the contact plug 106 is formed.

Next, as shown in FIG. 14, a second interlayer insulating film 107 made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 101 after the formation of the contact plug 106 by a chemical vapor deposition method (hereinafter referred to as a CVD method) or the like. To form.
Further, using a lithography technique and a dry etching technique, a gate contact hole (not shown) connected to the gate to form a potential is formed for the memory cell transistor and the peripheral circuit transistor that controls the memory cell transistor. . In the memory cell array, the bit contact plug hole 108 reaching the cell contact plug 106 through the second interlayer insulating film 107, and in the peripheral circuit transistor, the first interlayer insulating film 104 and the second interlayer insulating film are used. A bit contact plug hole (not shown) that penetrates the insulating film 107 and exposes the diffusion layer (including the source and drain electrodes) is formed.
A bit contact plug 109 is formed by embedding a conductive material in the bit contact plug hole 108.

Then, a conductive material is deposited on the entire surface, and patterning is performed by etching to form a bit line 110 that is electrically connected to the bit contact plug 109.
Further, a third interlayer insulating film 111 is formed on the entire surface by depositing an oxide film by plasma CVD.
The third interlayer insulating film 111 is flattened by a CMP technique, an opening pattern made of a resist is formed by photolithography, and anisotropic etching is performed using the opening pattern as a mask, and the contact plug 106 and the capacitor deep hole cylinder are formed. A capacitor contact plug hole 112 is formed to connect 117.
Then, the capacitor contact plug 113 made of a polycrystalline silicon film having a predetermined impurity concentration is formed by the same process as that for forming the contact plug 106.

Next, as shown in FIG. 15, an etching stopper nitride film 114 is formed on the entire surface by a CVD method as an etching stopper when the cylinder in which the capacitor is formed is etched.
Then, a silicon oxide film 115 serving as a core of a cylinder for forming a capacitor is formed on the entire surface of the etching stopper nitride film 114 by a CVD method to form a fourth interlayer insulating film 116.

A resist is applied on the fourth interlayer insulating film 116, a resist pattern for forming the cylinder is formed by photolithography, and anisotropic etching is performed using the resist pattern as a mask.
By this etching process, a capacitor cylinder 117 that penetrates the fourth interlayer insulating film 116 and reaches the capacitor contact plug 113 is formed.
When performing the anisotropic etching, the oxide film etch of the silicon oxide film 115 is performed up to the etching stopper nitride film 114, the etching conditions are switched, the etching stopper film 114 is removed, and the capacitor contact plug 113 is exposed.

Next, a natural oxide film (atmosphere in the clean room) formed on the capacitor contact plug 113 in order to suppress an increase in resistance at the interface between the capacitor contact plug 113 and the polycrystalline silicon film 118 to be formed later. A wet etch is performed to remove (formed by reaction with oxygen).
Next, as shown in FIG. 16, an amorphous silicon film to be a part of the lower electrode 120 is formed on the entire surface by CVD.
Next, for the purpose of controlling the size of HSG, phosphorus (P) is implanted into the amorphous silicon film by ion implantation technique, and then the positive resist ( (Not shown) is applied and the entire surface of the positive resist is exposed.

After the exposure, a resist development process is performed to remove the resist on the fourth interlayer insulating film 116. At this time, since the resist filled in the capacitor cylinder 117 is not exposed, it remains without being removed.
Next, the resist remaining in the cylinder 117 is used as a mask for protecting the amorphous silicon film that becomes a part of the lower electrode 120, and the amorphous silicon film on the fourth interlayer insulating film 116 is anisotropically etched. Etch back and remove.

Next, the resist remaining in the capacitor cylinder 117 is removed by oxygen plasma. As a result, the amorphous silicon film remains only on the inner surface of the cylinder 117.
Next, as shown in FIG. 16, in order to increase the surface area of the lower electrode of the capacitor and increase the capacity, HSG-Si 119 is grown on the amorphous silicon film.
As a result of this treatment, the amorphous silicon film is converted into the polycrystalline silicon film 118, and at the same time, the lower electrode 120 having HSG-Si 119 on the surface is formed.

Next, heat treatment is performed in an atmosphere of phosphine (PH ₃ ) in order to suppress depletion of the capacitor surface, which causes a decrease in capacitor capacity, and P is introduced into HSG.
Further, before the capacitor insulating film is formed on the polycrystalline silicon film 118 and the HSG-Si 119, RTP (Rapid Thermal Process) treatment is performed in a nitrogen atmosphere, and the surface is nitrided to form a silicon nitride film. To do. An oxidation stopper for protecting the silicon nitride film from an oxygen atmosphere so that the polycrystalline silicon film 118 and the HSG-Si 119 are not oxidized when a tantalum oxide film that becomes a capacitor insulating film (not shown) is subjected to an oxidation heat treatment. And

After the silicon nitride film is formed as described above, a tantalum oxide film is deposited by the CVD method and annealed in an oxygen atmosphere. This compensates for oxygen deficiency in the tantalum oxide film used as the capacitive insulating film and improves the film quality.
Next, as shown in FIG. 17, a titanium nitride layer 121 and a tungsten layer 122 are sequentially formed, and an upper electrode 123 is formed.

As described above, in order to obtain the capacitor surface area as much as possible, some stacked capacitor DRAMs have a cylinder type MIS structure capacitor in the capacitor cylinder 117 having a depth of 3 μm.
However, when processing a deep cylinder with a fine hole size by anisotropic dry etching, the shape of the cylinder becomes a bowing shape in which the diameter of the top opening is smaller than the center in the depth direction. End up.
In this bowed cylinder, when the HSG-Si is formed, the narrow opening is originally narrowed or blocked, and the capacity insulating film and the upper electrode to be formed thereafter cannot be uniformly formed on the entire surface of the cylinder. End up.

As a result, there arises a problem that it is difficult to form a capacitor having a desired characteristic, and a memory element corresponding to a capacitor having an insufficient capacity becomes a defective bit, and the yield of the DRAM is lowered.
As a measure for avoiding the above-mentioned problem, when forming the lower electrode in the groove, a method of over-etching the polysilicon serving as the lower electrode so that the lower electrode is not formed near the opening of the groove, In order to control the grain size of Si before growing HSG-Si, phosphorus (P) as an impurity concentration is implanted at a high concentration to reduce the grain size in the opening, thereby opening the groove opening. There is a way to widen the frontage.
JP 2003-209188 A

However, in the manufacturing method described above, if the etch back is performed excessively when forming the lower electrode, the lower electrode is etched significantly, resulting in a reduction in the area of the capacitance forming region. Thus, there is a problem that a sufficient capacity cannot be obtained.
Further, in the above manufacturing method, when phosphorus (P) as an impurity concentration is implanted at a high concentration in order to control the grain size of Si when forming the lower electrode, the entire HSG-Si is formed. Since the grain size of the layer becomes small, there is a problem that as a result, the area of the capacity forming region cannot be made sufficiently large and a necessary capacity cannot be obtained.

  The present invention has been made in view of such circumstances, and the upper electrode is formed on the entire surface of the capacitor insulating film inside the cylinder without reducing the grain size of the HSG-Si layer and without closing the opening of the cylinder. And a method of manufacturing a semiconductor memory device capable of forming a capacitor having a larger capacity than that of a conventional one using a cylinder of the same size by improving the yield and aiming for a larger grain size. For the purpose.

  The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a capacitor formed in a cylinder structure, and includes a step of depositing an oxide film, and a cylinder constituting the capacitor inside the oxide film. Forming an amorphous silicon film along the inner surface of the cylinder, and forming a mask layer for suppressing HSG growth on the amorphous silicon film in the inner peripheral region near the cylinder opening. A step of performing an HSG process on the amorphous silicon and simultaneously converting to polycrystalline silicon, a step of removing the mask layer, a step of forming an insulating film on the polycrystalline silicon, and a conductive layer. And at least a step of forming the insulating film on the insulating film.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the mask layer includes an intermediate position between an opening of the cylinder and a position where the inner diameter of the cylinder is bowed most widely in the cylinder in which the amorphous silicon film is formed. A step of forming an SOG film with a thickness filled up to a thickness, a step of forming the mask layer on the entire surface, and leaving only the mask layer on the amorphous silicon on the cylinder side surface in the vicinity of the opening, It has at least a step of removing the mask layer and a step of removing SOG in the trench.

  In the method of manufacturing a semiconductor device according to the present invention, the mask layer is a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film.

  As described above, according to the present invention, in order to increase the capacitance of the cylinder-type capacitor, the surface of the lower electrode is converted into a hemispherical silicon grain (HSG-Si) to increase the area. If the cylinder forming the cell capacitor is deep and bowed, the frontage is narrow and narrows or closes above the cylinder, so that the upper electrode does not enter the bottom of the cylinder and the desired capacitor capacity is obtained. Therefore, in order to prevent the memory element corresponding to the cylinder from becoming a defective bit, by suppressing the HSG formation near the opening of the cylinder, the formation failure of the upper electrode is prevented and the defective bit due to the low capacity is prevented. It is characterized by that.

As described above, according to the method for manufacturing a semiconductor device of the present invention, the region near the opening of the cylinder is masked with the mask layer made of a material that suppresses the formation of HSG, and then the amorphous silicon serving as the lower electrode is subjected to the HSG treatment. Therefore, as in the prior art, the opening is not blocked by the grain of polycrystalline silicon that has been made into HSG, and the formation failure of the upper electrode formed on the capacitor insulating film can be prevented.

Further, according to the method of manufacturing a semiconductor device of the present invention, as described above, the opening of the cylinder is not blocked, so that the grains in the region where the HSG process is performed inside the unmasked cylinder can be performed. As compared with the above, it is possible to grow larger, and in the same size cylinder, it is possible to further increase the capacitor capacity.
Thus, according to the method for manufacturing a semiconductor device of the present invention, the capacitor can be reduced in size when the capacitance is the same as in the conventional case, so that the size can be further reduced.

The semiconductor memory device according to the first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing a cross-sectional structure of the embodiment.
In this figure, a semiconductor substrate 1 is formed of a semiconductor, for example, silicon into which impurities of a predetermined concentration are introduced, for example, p-type (boron or the like) impurities are introduced.
The element isolation region 2 is formed on the surface of the semiconductor substrate 1 at a portion other than the transistor formation region by STI (Shallow Trench Isolation), and insulates and isolates the transistor (memory cell selection transistor).

In the transistor formation region shown in the figure, a gate insulating film (not shown) is formed as a silicon oxide film on the surface of the semiconductor substrate 1 by, for example, thermal oxidation.
On this gate insulating film, the gate electrode 3 is formed of, for example, a multilayer film of a polycrystalline silicon film and a metal film, and the polycrystalline silicon film is formed by introducing impurities during film formation by the CVD method. A doped polycrystalline silicon film can be used. The metal film in the gate electrode 3 can use a refractory metal such as tungsten (W) or tungsten silicide (WSi).
An insulating film 30 is formed of a silicon nitride film (SiN) or the like on the gate electrode 3, and a sidewall 31 of an insulating film such as a silicon nitride film is formed on the side wall of the gate electrode 3.

A source diffusion layer (not shown) is formed on the surface of the semiconductor substrate 1 at one end of the gate electrode 3, and a drain diffusion layer (not shown) is formed at the other end of the gate electrode 3.
In each contact hole formed in a self-aligned manner by the insulating film 30 and the sidewall 31, a cell contact plug 6 connected to the source and drain diffusion layers is formed of a polycrystalline silicon film having a predetermined impurity concentration. ing.
A first interlayer insulating film 4 is formed in a groove formed between the cell contact plugs 6. That is, each cell contact plug 6 is electrically insulated from other adjacent cell contact plugs 6 by the first interlayer insulating film 4.
A second interlayer insulating film 7 and a third interlayer insulating film 11 are formed on the entire surface of the cell contact plug 6 and the first interlayer insulating film 4.

A bit contact hole 8 is formed through the second interlayer insulating film 7 so that the upper surface of the contact plug 6 connected to the drain diffusion layer is exposed.
In the bit contact hole 8, a bit contact plug 9 made of each metal film of Ti / TiN / W is formed.
A bit line 10 made of a metal film of a WN film and a W film is formed on the surface of the bit contact plug 9. That is, the bit line 10 is connected to the diffusion layer of the drain of the MOS transistor via the cell contact plug 6 and the bit contact plug 9.
A capacitor contact plug hole 12 is formed through the second interlayer insulating film 7 and the third interlayer insulating film 11 so that the upper surface of the contact plug 6 connected to the diffusion layer of the source of the MOS transistor is exposed. ing.
In the capacitor contact plug hole 12, a capacitor contact plug 13 made of polycrystalline silicon into which P is introduced as an impurity is formed.

A fourth interlayer insulating film 16 comprising a silicon oxide film 15 and a stopper silicon nitride film 14 is formed on the entire surface, and a capacitor cylinder 17 is formed so that the surface of the capacitor contact plug 13 is exposed. Yes.
A lower electrode 23 having HSG-Si 22 formed on the surface is formed on the bottom and side walls of the capacitor cylinder 17. A capacitive insulating film (not shown) is formed on the lower electrode 23, and an upper electrode 26 is formed so as to fill the cylinder. The upper electrode 26 is composed of a TiN film 24 and a W film 25.
Here, HSG-Si 22 is not formed on the surface of the lower electrode 23 in the vicinity of the opening of the cylinder 17. As a result, the vicinity of the opening of the capacitor cylinder 17 is not blocked by HSG-Si as in the prior art, and the upper electrode 26 is uniformly formed on the entire surface of the capacitor, thereby preventing the occurrence of defective bits.

Next, a method of manufacturing the DRAM shown in FIG. 1 will be described with reference to a series of process cross-sectional views shown in FIGS.
As shown in FIG. 2, a transistor having an element isolation region 2, a gate electrode 3, a source diffusion layer, and a drain diffusion layer (not shown) is formed on a semiconductor substrate 1.
Next, a BPSG film having a thickness of about 600 nm to 700 nm is formed on the entire surface by CVD, and after reflowing at 800 ° C., the surface is planarized by CMP.

Next, an NSG film is formed with a thickness of about 200 nm on the entire surface of the wafer by plasma CVD, and a first interlayer insulating film 4 composed of the BPSG film and the NSG film is formed.
Next, a photoresist is applied, and a photoresist pattern of the cell contact hole is formed by photolithography using a mask for forming the cell contact hole. Next, anisotropic etching is performed using this photoresist pattern as a mask, and cell contact holes 5 reaching the semiconductor substrate 1 through the first interlayer insulating film 4 are formed. Thereafter, the photoresist pattern is removed.

Next, a first silicon film made of polycrystalline silicon doped with phosphorus as an impurity is deposited on the entire surface by a CVD method. At this time, the cell contact hole 5 is formed with a thickness that completely fills the first silicon film.
Next, after etch back by a plasma dry etching method using a chlorine-based gas, only the first silicon film on the first interlayer insulating film 4 is removed by CMP treatment, and the cell contact plug 6 is formed. .
Here, the impurity concentration of the first silicon film is 1.0 × 10 ^{20 to} 4.5 × 10 ²⁰ atoms / cm ³ .

Next, as shown in FIG. 3, a second interlayer insulating film 7 made of a silicon oxide film having a thickness of about 200 nm is formed on the entire surface by plasma CVD.
Next, a photoresist is applied (not shown), and photolithography is performed using a photomask for forming a bit contact hole to form a resist pattern for the bit contact hole. With this resist pattern as a mask, a bit that penetrates the first interlayer insulating film 7 by anisotropic etching and exposes the upper surface of the cell contact plug connected to one diffusion layer (drain diffusion layer) of the MOS transistor Contact hole 8 is formed. At this time, contact holes necessary for peripheral MOS transistors (not shown) other than the memory region are also formed.

Next, the photoresist pattern is removed, and a Ti film having a thickness of 10 nm and a TiN film having a thickness of 15 nm are sequentially formed on the entire surface by CVD (not shown). Thereafter, a W film having a thickness of 200 nm is formed on the entire surface so as to fill the bit contact hole 8.
Next, the Ti film, the TiN film, and the W film formed on the surface of the interlayer insulating film 7 are removed by CMP, and the bit contact plug 9 is formed.
Further, a WN (tungsten nitride) film and a W film are sequentially formed at a thickness of about 10 nm / 40 nm by sputtering.
Next, the WN film and the W film are anisotropically etched by photolithography and dry etching to form the bit line 10.

After removing the photoresist pattern used for the bit line formation, a silicon nitride film (not shown) having a thickness of 5 nm and serving as an oxidation protection film for the bit line 10 is formed by a CVD method.
Next, a third interlayer insulating film 11 made of a silicon oxide film having a thickness of 500 nm is formed on the entire surface by plasma CVD. Thereafter, the surface is flattened by CMP.
Next, the capacitor contact hole 12 is formed by photolithography and dry etching so that the surface of the cell contact plug 6 connected to the source diffusion layer is exposed.

Next, the photoresist pattern used for forming the capacitor contact hole is removed, and a second silicon film (not shown) to which phosphorus is added is formed on the entire surface so as to fill the capacitor contact hole by the CVD method. To do.
Thereafter, the second silicon film formed on the third interlayer insulating film 11 is removed by the etch back method and the CMP method, and the capacitor contact plug 13 is formed.
The impurity concentration of the second silicon film can be the same as that of the first silicon film.

Next, as shown in FIG. 4, a stopper silicon nitride film 14 having a thickness of 50 nm is formed on the entire surface by plasma CVD, and then a silicon oxide film 15 having a thickness of 3000 nm is formed. The sequentially formed stopper silicon nitride film 14 and silicon oxide film 15 constitute a fourth interlayer insulating film 16.
Next, a cylinder 17 is formed by photolithography and dry etching so as to penetrate the fourth interlayer insulating film 16 and expose the surface of the capacitor contact plug 13. In forming the cylinder 17, a hard mask such as a silicon film or an amorphous carbon film can be used in addition to the photoresist mask.

Next, the photoresist pattern used for forming the cylinder 17 is removed. Here, the size of the cylinder 17 in the process of the present embodiment is such that the long side is about 240 nm and the short side is about 200 nm when the minimum separation width from other adjacent cylinders 17 is about 75 nm in plan view. It becomes oval.
In such a fine hole size, when a deep hole of 3000 nm is processed by a dry etching method, as shown in FIG. 4, the cross-sectional shape of the cylinder 17 is a bowing in which the diameter of the opening and the bottom is narrow and the center is wide. Easy to form.

Next, as shown in FIG. 5, an amorphous silicon film is formed on the entire surface after wet pretreatment with a hydrofluoric acid-containing solution to suppress an increase in resistance at the interface with the capacitor contact plug 13. The amorphous silicon film is formed on the entire surface as follows. First, a first silicon film having a thickness of 18 nm is formed, and then a second silicon film having a thickness of 20 nm is continuously formed. The first silicon film is formed at 500 ° C. using monosilane (SiH ₄ ) and phosphine (PH ₃ ) as source gases. The phosphorus content is about 4.4 × 10 ²⁰ atoms / cm ³ . The second silicon film is formed using only monosilane as a source gas so as not to contain phosphorus. The first silicon film and the second silicon film constitute a third silicon film 18.
Thereafter, phosphorus of an implantation amount of about 1.0 × 10 ¹⁴ atoms / cm ^{2 is} implanted by ion implantation so that HSG-Si formed on the side surface near the bottom of the cylinder 17 does not grow too much. Implanted into the silicon film of the layer.

Next, as shown in FIG. 6, an SOG (Spin-On-Glass) film 19 is formed on the entire surface by spin coating, and then etched back with a hydrofluoric acid-containing solution to form on the side surface near the opening of the cylinder 17. The surface of the third silicon film 18 is exposed. The SOG film 19 is formed so that the surface of the SOG film 19 is positioned between the most bowing position and the opening.
Next, heat treatment is performed at about 400 ° C. to cure the SOG film 19. At this time, the temperature of 550 to 600 ° C. at which HSG growth occurs in the second silicon film is not exceeded. If the HSG growth temperature is exceeded, the second-layer silicon film (amorphous silicon film) is turned into polycrystalline silicon halfway, and only the grain size HSG-Si22 that is insufficient in the subsequent HSG process is used. It will not grow.

Next, as shown in FIG. 7, a cover film 20 made of a silicon nitride film is formed on the entire surface by plasma CVD. The cover film may be any material having selectivity with respect to the third silicon film 18 at the time of removal, and a silicon oxynitride film, an aluminum oxide film, or the like can be used.
Next, as shown in FIG. 8, the cover film 20 is etched back by anisotropic etching to leave the sidewalls 21 of the cover film 20 only on the side walls near the opening of the cylinder 17. At this stage, the third silicon film 18 exposed on the surface of the fourth interlayer insulating film 16 may be removed by etching back.

Next, as shown in FIG. 9, the SOG film 19 is selectively removed using a hydrofluoric acid-containing solution. A dilute hydrofluoric acid solution of about HF: H ₂ O = 1: 500 can be used for the wet etching.
Thereby, the cover film 21 for inhibiting HSG-Si growth can be left only on the surface of the third silicon film 18 on the side wall in the vicinity of the opening of the cylinder 17.

Next, as shown in FIG. 10, HSG-Si 22 is grown on the exposed surface of the third silicon film 18.
In the process of forming the HSG-Si 22, for the grain nucleation, in the high vacuum of 10 ⁻¹ Pa, for example, SiH ₄ or Si ₂ H ₆ gas is used for about 16 minutes for the third silicon film 18. Irradiate (supply) the surface. Further, in order to make the nuclei grained, a heat treatment is performed in a vacuum of about 10 ⁻⁵ Pa for about 16 minutes in a range of 550 to 600 ° C. As a result, HSG-Si 22 made of grains having a radius of about 40 to 70 nm is formed on the surface of the third silicon film 18.
Next, the cover film 21 used for inhibiting HSG growth is removed with a hot phosphoric acid solution at 160 ° C.

Next, the inside of the cylinder 17 is filled with photoresist (not shown), and this is used as a protective film, and the HSG-Si 22 and the polycrystalline silicon film 18 formed on the surface of the fourth interlayer insulating film 16 are chlorinated. Etch back and remove. Thereafter, the photoresist filled in the cylinder 17 is removed by oxygen plasma.
By the above-described processing, as shown in FIG. 11, the lower electrode 23 having HSG-Si 22 in which HSG-Si 22 is not formed only in the vicinity of the opening of the cylinder 17 can be formed on the inner surface of the cylinder 17.

Next, in order to increase the impurity concentration on the surface of the lower electrode 23, heat treatment is performed in a phosphine atmosphere to diffuse phosphorus in a vapor phase.
Further, a silicon nitride film having a thickness of about 1 nm is formed on the surface of the lower electrode 23 by heat treatment in an ammonia (NH ₃ ) atmosphere. Thereafter, a tantalum oxide film having a thickness of 8 nm is formed by a CVD method using pentaethoxytantalum as a raw material and oxygen as an oxidizing agent. Further, in order to improve the insulating property of the tantalum oxide film, heat treatment is performed in an oxidizing atmosphere at 750 ° C. to form a capacitive insulating film (not shown). Note that the capacitor insulating film is not limited to a tantalum oxide film, and a metal oxide such as an aluminum oxide film, a hafnium oxide film, or a zirconium oxide film can be used as a single layer or a stacked layer.
Thereafter, as shown in FIG. 12, a TiN film 24 to be an upper electrode and a W film 25 to be a capacitor plate are sequentially formed, and an upper electrode 26 composed of the TiN film 24 and the W layer 25 is formed.
By the above-described process, a semiconductor device having a cylinder type capacitor composed of the lower electrode 23 having HSG-Si is completed.

  According to the above-described capacitor manufacturing method, since HSG-Si does not grow in the opening of the cylinder, it is possible to form a capacitor having good characteristics by avoiding the problem of the cylinder being blocked, and having high reliability. A semiconductor device can be provided.

It is a conceptual diagram which shows the cross section of the structural example of the semiconductor device of one Embodiment of this invention. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in this embodiment. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in the prior art example. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in the prior art example. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in the prior art example. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in the prior art example. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in the prior art example. It is a conceptual diagram which shows the cross-sectional structure in each process explaining the manufacturing method of the cylinder type capacitor used for DRAM in the prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Element isolation region 3 ... Gate electrode 4 ... 1st interlayer insulation film 5 ... Cell contact hole 6 ... Cell contact plug 7 ... 2nd interlayer insulation film 8 ... Bit contact hole 9 ... Bit contact plug 10 ... bit line 11 ... third interlayer insulating film 12 ... capacity contact hole 13 ... capacitor contact plug 14 ... stopper silicon nitride film 15 ... silicon oxide film 16 ... fourth interlayer insulating film 17 ... capacitor cylinder 18 ... third Silicon film 19 ... SOG film 20 ... cover film 22 ... HSG-Si
23 ... Lower electrode 24 ... Ti film 25 ... W film 26 ... Upper electrode 30 ... Insulating film 31 ... Side wall

Claims (3)

A method of manufacturing a semiconductor device including a capacitor formed in a cylinder structure,
Depositing an oxide film;
Forming a cylinder constituting the capacitor in the oxide film inside;
Forming an amorphous silicon film along the inner surface of the cylinder;
Forming a mask layer for suppressing HSG growth on the amorphous silicon film in the inner peripheral region in the vicinity of the cylinder opening;
Performing the HSG treatment on the amorphous silicon and simultaneously converting it to polycrystalline silicon;
Removing the mask layer;
Forming an insulating film on the polycrystalline silicon;
And a step of forming a conductive layer on the insulating film. Forming the mask layer comprises:
A SOG (Spin-On-Glass) film is formed in the cylinder where the amorphous silicon film is formed to a thickness that fills up to an intermediate position between the opening of the cylinder and the position where the inner diameter of the cylinder is the widest bow. Process,
Forming the mask layer on the entire surface;
Leaving only the mask layer on the amorphous silicon film on the cylinder side surface in the vicinity of the opening, and removing the mask layer on the other region;
The method for manufacturing a semiconductor device according to claim 1, further comprising: a step of removing the SOG film in the trench.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer is a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film.

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