JP2008129671A - Pseudo dual port memory circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pseudo dual port memory circuit with a simple configurations using a plurality of single port RAMs of 1W2R or 1W1R. <P>SOLUTION: In this pseudo dual port memory circuit, two single port RAMs are provided with the same address space, and one single port RAM is provided with a write port synchronizing with the first clock, and the other is provided with a write port synchronizing with the second clock whose frequency is different from that of the first clock. This pseudo dual port memory circuit is provided with a flag processing part including the flag of each address of the signal port RAM, and the flag processing part is provided with a means for setting a flag corresponding to the write time of data in one of the signal ports RAM, and for setting the flag corresponding to the write time of data in the other single port. Read access to one of the single port RAM is respectively supplied to the read ports of its own single port RAM and the other single port RAM. This pseudo dual port memory circuit is provided with a means for selecting one read data corresponding to the state of the flag from the read data from the two single port RAMs. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pseudo dual port memory circuit using a single port RAM or a single port RAM in an ASIC.

  The dual port memory of 2W2R (2 write ports and 2 read ports) has a wide application range in circuit design. However, the dual port memory capable of high capacity and high speed operation is expensive, which is disadvantageous in terms of cost. In order to cope with this, a technique using a single port memory has been proposed.

  As described above, the 2W2R dual-port memory is expensive and has a problem that it costs more when the capacity is increased, and it is necessary to control simultaneous read and write to a plurality of ports. For this reason, read latency (read delay) and write latency (write delay) fluctuate, and bus cycle wait control such as busy and ready, which are bus control signals, is necessary. In addition, when wait control is not performed, if data is written from a plurality of ports at the same time, write data becomes indefinite, and processing such as priority control cannot be performed.

  Since there is a problem with the dual port memory as described above, in recent years, a method and a circuit for realizing a pseudo dual port memory by combining a plurality of single port memories have been proposed. As a result, read latency, write latency, and wait processing can be reduced as much as possible. FIG. 19 shows a configuration of one such example (see Patent Document 1) as a configuration of a conventional example.

  In FIG. 19, 80 and 81 are single port RAMs having the same configuration and the same address space with one port input / output, 82 is a 2-port processing unit, 83 is a control unit, 830 is a flag register, 830L, 830R Is a flag storage unit for the single port RAM 80 and a flag storage unit for the single port RAM 81, 84 is connected to the port PL1, the port PL2, and / or the port PR2, or both the port PR1, the port PL2, and the port PR2 The space switch 85 for switching whether to connect to the first port unit 85L and the second port unit 85R, the first port unit 85L inputs the read control signal RL and the write control signal WL from the outside, The wait signal WTL is output to the outside, and the second port unit 85R receives the read control signal RR and write control signal. Enter the WR externally outputs a wait signal WTR outside, BL and BR are input and output buses. 86 and 88 are first memory access buses, 87 and 89 are second memory access buses, R1 and R2 are read control signals for single port RAMs 80 and 81, and W1 and W2 are write control signals for single port RAMs 80 and 81. It is.

When writing data from the first port unit 85L, the first write control signal WL is enabled, and when the write address and write data to the single port RAM 80 and RAM 81 are input from the bus input / output unit BL, the control unit 83 controls the space switch 84 to switch the signal path of the write address and write data, thereby writing the write data to all the RAMs that are not in the single port RAM1, RAM2 in the write address. . At this time, a flag indicating that writing has been performed is set for each address in the flag storage units 830L and 830R corresponding to the RAM type of the flag register 830. Control unit 83 refers to flag register 830 at the time of reading, and reads stored data at the read address from single port RAM 1 or RAM 2 in which the data is written with respect to the read address without being in the access state. Writing and reading are performed with equivalent contents from the first port unit 85L or the second port unit 85R. If writing to the same address occurs simultaneously from two ports, wait signals WTL and WTR are generated and a wait state is entered.
JP-A-6-60007

  In the technique of the conventional example shown in FIG. 19, data writing is executed for all ports that are not in an access state, and at that time, it is necessary to provide a plurality of flags corresponding to each port. In addition, there is a problem in that it has a complicated configuration in which a space switch for switching connection paths of access signals and data signals between the first port, the second port, and the two single-port memories and a control unit thereof are provided. . Furthermore, when writing from two ports to the same address in two single-port memories, there is a problem that a wait state occurs.

  An object of the present invention is to realize a dual port memory circuit having a simple configuration using a plurality of single port RAMs of 1W2R and 1W1R.

  FIG. 1 shows a first principle configuration of the present invention. In the figure, 1-1 and 1-2 are each a 1W2R (1 write port 2 read port) first single port RAM 1 (hereinafter referred to as single port RAM 1) and a second single port RAM 2 (hereinafter referred to as single port RAM 2). Both single port RAMs have the same address space, writing to the single port RAM 1 is executed by the first clock CK1, writing to the single port RAM 2 is executed by the second clock CK2, and reading is performed by any single The port RAM is also executed by either the first clock CK1 or the second clock CK2. The read ports from the single-port RAM 1 are A and B. A is a port for outputting data read by a read request synchronized with the first clock CK1, and B is read by a read request synchronized with the second clock CK2. This is the port that outputs the data. Similarly, the single-port RAM 2 has read ports A and B, A is a port for outputting data read by a read request synchronized with the second clock CK2, and B is a read request synchronized with the first clock CK1. This is the port to which the read data is output.

  2-1 and 2-2 are the first bus address decoder, the second bus address decoder, 3 is provided corresponding to each address of the single port RAM 1 and the single port RAM 2, and which RAM has written last. Flag processing units for setting and holding a flag to be displayed and outputting a flag held corresponding to the address at the time of reading, 4-1 and 4-2 select read data according to the flag corresponding to the read address A read data selection unit and a second read data selection unit. A1 and A2 are write / read control signals, addresses, and in the case of write, the first input port and the second clock (CK2) to which the first clock access synchronized with the first clock (CK1) including the write data is input The second input port to which the second clock access synchronized with the first input, R1, R2 outputs the first read port that outputs the read data synchronized with the first clock and the read data synchronized with the second clock. Second read port.

  When writing, when a write control signal, address, and write data are input from the first input port A1 or the second input port A2, the first bus address decoder 2-1 or the second bus address decoder 2 -2, the address is decoded, and a write request including a write control signal, address and data is supplied to the corresponding single port RAM 1 or single port RAM 2. Further, writing to the single port RAM 1 is executed in synchronization with the first clock (CK1), and writing to the single port RAM 2 is executed in synchronization with the second clock (CK2). The RAM 2 is not executed at the same time, and there is no need to perform write contention control. At the time of writing, the flag (1 bit) corresponding to each address in the flag processing unit 3 is set or reset. That is, when data is written to the single port RAM 1, the flag corresponding to the write address of the single port RAM 1 in the flag processing unit 3 is reset, and when data is written to the single port RAM 2, the flag processing unit 3 A flag corresponding to the corresponding address is set. Thus, on which side the last (recent) data has been written for each address of the single port RAM 1 or 2 is determined by the flag state of the corresponding address of the flag processing unit 3.

  When reading, when a read signal (address and read request) is input from either the first input port A1 or the second input port A2, the corresponding first bus address decoder 2-1 or second bus address is input. An address is decoded by the decoder 2-2 and a read request signal is generated. A read request signal (including an address) is supplied to both the single port RAM1 and the single port RAM2, and reading is performed by the single port RAM1 and RAM2. Each single port RAM1 reads from the port A by reading in synchronization with the first clock CK1. One read data is output, and the other read data is output from the port B by reading in synchronization with the second clock CK2. Similarly, in the single port RAM 2, one read data is output from the port A by reading synchronized with the second clock CK 2, and the other read data is output from the port B by reading synchronized with the first clock CK 1. As the read data from both the single port RAMs, the data read by the same clock are input to the first read data selection unit 4-1 and the second read data selection unit 4-2.

  On the other hand, in the case of reading, the read address is also input to the first read data selection unit 4-1 and the second read data selection unit 4-2, and the flag corresponding to each address output from the flag processing unit 3 A flag corresponding to the read address is selected from among the signals, and the selected flag signal (set or reset) is input to the first read data selection unit 4-1 and the second read data selection unit 4-2. In each selection unit 4-1 or 4-2, when the flag is reset from the read data from the two single-port RAMs 1 and 2, the read data from the single-port RAM 1 is selected, and when the flag is set, the single By selecting read data from the port RAM 2, the latest write data is output.

  If write access occurs simultaneously at the same address, the flag processing unit 3 determines that one access (for example, write access to the single port RAM 1) should be input preferentially. The stored data can be read stably.

  FIG. 2 shows a second principle configuration of the present invention. In this second principle configuration, two single-port RAMs are also used. However, the first principle configuration differs from the first principle configuration in that it is 1W1R (with one write port and one read port). Do not use the flag processing unit.

  In FIG. 2, 5 is a multiplexing unit, 5a is a frequency dividing counter that divides the multiplexing clock (divided by 3 in the example of FIG. 2), and 5b to 5d correspond to the count number of the frequency dividing counter 5a in this example. Three selection units, 5e is an OR gate, 6-1 and 6-2 are both 1W1R (1 write port 1 read port) first single port RAM 3 (hereinafter referred to as single port RAM 3) and second This is a single port RAM 4 (referred to as a single port RAM 4). A10 and A11 are the first clock (CK1) write port, the second clock (CK2) write port, RQ1 and RQ2 are read request (including read address) ports for the single port RAM3 and single port RAM4, and R1 and R2 are This is an output port for read data of the single port RAM3 and RAM4.

  Write access (write request and write data) is individually input to the multiplexing unit 5 from the first clock write port A10 and the second clock write port A11. Write access to the first clock write port A10 is input to the selectors 5b and 5c, and write access to the second clock write port A11 is input to the selector 5d. The selectors 5b and 5c are alternately driven at a frequency obtained by dividing the first clock signal (having a frequency twice that of the second clock) by two, and the selector 5d is driven at the frequency of the second clock. The multiplexing clock (CK3) has a frequency higher than the value obtained by adding the first clock CK1 and the second clock CK2, and in this description, when the frequency is the sum of the first clock CK1 and the second clock CK2, the frequency dividing counter 5a When the multiple clock (CK3) is divided by 3, the outputs of the count values (0, 1, 2) generated by the frequency division of the frequency division counter 5a are supplied to the three selection units 5b to 5d one by one.

  As a result, the selectors 5b to 5d are driven by the three values of the frequency divider counter 5a, the selectors 5b and 5c are driven in two cycles of the first clock, and the two frequency divided outputs of the frequency divider counter 5a are output. The selection units 5b and 5c are sequentially driven at the timing of occurrence, and the write access of the first clock write port A10 is supplied to the single port RAM 3 and the single port RAM 4. At this time, the number of times of writing from the first clock (CK1) write port A10 (even number, odd number) is recognized, and if it is even number, a write instruction is given to the selector 5b, and if it is odd, the selector 5c. Write instruction to. The selectors 5b and 5c receive this write instruction and use the count value of the frequency dividing counter 5a to generate a write request to the OR gate 5e when the selector 5b has a count value of 0 and the selector 5c has a count value of 1. . When there is no write instruction in the selection units 5b and 5c, 0 is sent to the OR gate of 5e. The write request from the second clock (CK2) write port A11 is notified to the selection unit 5d, and the selection unit 5d generates a write request to the OR gate 5e when the count value of the frequency division counter 5a is 2. . If there is no write request in the selector 5c, 0 is sent to the OR gate 5e. Thereby, when the count values of the frequency dividing counter 5a are 0, 1, and 2, the write requests of the selection units 5b, 5c, and 5d are multiplexed by the OR gate 5e, and the write processing is performed in the RAM3 and RAM4.

  According to the second principle configuration, in the multiplexing unit 5, the write access to the two write ports is divided into two by the high-speed multiplexing clock (CK3) so that the time does not overlap, and the write operation is performed. Surely executed.

  In the read operation in the configuration of FIG. 2, when the first clock read access and the second clock read access are independently generated (even if the address and time are the same) for the single port RAM 3 and the single port RAM 4, respectively. Reading is performed in each single port RAM, and read data is output from the read ports R1 and R2.

  According to the present invention, write data can be guaranteed by mounting two single-port RAMs and writing data to physically separate memories, and data can be simultaneously read from the two memories at the time of reading. Can also eliminate the need for contention control.

  According to the first principle configuration of the present invention, when writing data to two 1W2R single port RAMs, a flag indicating which memory access is new is set, and when reading, data is simultaneously read from both memories. By selecting read data with reference to the read and flag bits, new data can always be read, no conflict control is required, and read latency (read delay) can be minimized.

  Furthermore, by connecting the clock used for writing and reading as it is to the memory, it becomes a simple configuration without requiring a clock transfer circuit, and the circuit scale can be reduced and the power consumption can be reduced.

  According to the second principle configuration of the present invention, write contention control is required by dividing the write timing by the multiplexing unit for write access from two ports for two 1W1R single port RAMs. Instead, reading can be performed independently for the two single-port RAMs.

  FIG. 3 shows the configuration of the first embodiment. The first embodiment corresponds to the first principle configuration of the present invention shown in FIG. In the figure, 1-1, 1-2, 2-1 (66M bus address decoder), 2-2 (33M bus address decoder), 3, 4-1 and 4-2 are the same as those in FIG. The first single port RAM 1 and the second single port RAM 2 have a capacity of 4K bits (4096 bits). Further, the first clock CK1 used for the write operation of the single port RAM1 is 66 MHz (hereinafter referred to as 66M), and the second clock CK2 used for the write operation of the single port RAM2 is 33 MHz (hereinafter referred to as 33M). The two single port RAMs 1 and 2 each have two read ports operating at 66M and 33M, and read data based on the respective clocks is output. A1 and A2 are a control signal for writing and reading, an address, and in the case of writing, a first input port to which a 66M clock access synchronized with a 66M clock including write data is input and a 33M clock synchronized with a 33M clock A second input port to which access is input, and R1 and R2 are output ports for generating read data synchronized with 66M and 33M, respectively.

  FIG. 4 shows a configuration example of the flag processing unit of the first embodiment. In the flag processing unit (3 in FIG. 4), a total of 4096 latch circuits 30-0 to 30-4095 (for each address 0 to 4095 corresponding to the capacity (4096 bytes) of the single port RAMs 1 and 2 shown in FIG. Or a flip-flop circuit), which is set by the input of a write request (33 MHz write Request) synchronized with 33M (second clock CK1) and is synchronized with 66M (first clock CK1) (66MHz Write Request) ) To reset. From each latch, “1” (when the latest data is written to the single port RAM 1 at 66M) or “0” (the latest data is written to the single port RAM 2 at 33 M of the second clock CK1 as flag 0 to flag 4095. Occurs).

  FIG. 5 shows a configuration example of the first read data selection unit (4-1 in FIG. 3), 40-1 being a selection unit, and 41-1 being an address selection unit. A flag (latch output) corresponding to all addresses is input from the flag processing unit (3 in FIG. 3) to the address selection unit 41-1, and a flag corresponding to the address is selected by the input of the write address. It inputs into the selection part 40-1. If this flag is “0”, the read data of the A port of the single port RAM 1 is selected. If the flag is “1”, the read data of the B port of the single port RAM 2 is selected.

  FIG. 6 shows a configuration example of the second read data selection unit (4-2 in FIG. 3), 40-2 is a selection unit, and 41-2 is an address selection unit. As in FIG. 5, the address selection unit 41-2 receives flags corresponding to all addresses from the flag processing unit, selects flags corresponding to the write address, and inputs the flags to the selection unit 40-2. . If this flag is “0”, the read data of the B port of the single port RAM 1 is selected, and if the flag is “1”, the read data of the A port of the single port RAM 2 is selected.

  FIG. 7 is a diagram for explaining the operation in the case of simultaneous write access in the first embodiment. In FIG. 7, reference numerals 1-1, 1-2, 2-1, 2-2, 3 and 4-1, 4-2 are the same as those shown in FIG. FIG. 8 is a time chart of signal generation of FIG. 7, wherein a to d of the port 1 (66M) are signals relating to the first single port RAM1, and e to i of the port 2 (33M) are the second single port. This is a signal related to the RAM 2.

  In FIG. 7, the 66M bus address decoder (first bus address decoder) 2-1 and the 33M bus address decoder (second bus address decoder) 2-2 are synchronized with the 66M clock (a in FIG. 8). FIG. 8 shows a time chart when a write access signal is input to the second input port A2 to which the 33M clock access synchronized with the clock of the input ports A1 and 33M (e in FIG. 8) is input. 7 generates a signal indicated by a thick line. In the example of FIG. 8, the write address (b in FIG. 8) of the input port A1 is “a1”, the write data (c in FIG. 8) is “b1”, and the content of the access request (request) is written ( ("Write" in d of FIG. 8). On the other hand, the write address (f in FIG. 8) of the input port A2 is “a1”, the write data (g in FIG. 8) is “c1”, and the content of the access request is written (“write” in h in FIG. 8). It is. In the example of FIG. 8, since writing (data “c1”) to the input port A2 occurred earlier in time, the flag corresponding to the address “a1” of the flag processing unit 3 is set and “1” is output ( I) in FIG. Thereafter, writing to the input port A1 (data “b1”) occurs for the same address “a1”, and at the same time, the flag corresponding to the address “a1” is reset and outputs “0” (FIG. 8). i).

  FIG. 9 is an explanatory diagram of read access to the 66M input port in the first embodiment. In FIG. 9, 1-1, 1-2, 2-1, 2-2, 3 and 4-1, 4-2. These symbols are the same as the same symbols shown in FIGS. FIG. 10 is a time chart of signal generation in FIG. 9, wherein a to g of the port 1 (66M) are signals relating to the first single port RAM1, and h to l of the port (33M) are the second single port RAM2. It is a signal regarding.

  In the time chart shown in FIG. 10, a write access occurs at the input port A1 at time t1 of the first clock 66M (a in FIG. 10), and the data b1 is written to the address a1. The flag is reset to “0” (see b, c, d, and l in FIG. 10). On the other hand, in the single port RAM2, the data c1 is written to the address a1 at the timing T1 of the second clock 33M (h in FIG. 10) (time after the t1), and the flag of the address a1 is set to “1”. The

  Thereafter, when a read access to the address a1 (b, c in FIG. 10) occurs at the input port A1 at the timing of the time t6 of the first clock 66M, as shown in FIG. The read data b1 is output from the single port RAM1 (e in FIG. 10), and the read data c1 is output from the single port RAM2 (same as f). At this time, since the flag processing unit 3 outputs “1” as the flag of the address a1 (l in FIG. 10), the first read data selection unit 4-1 selects the data c1 read from the single-port RAM 2. And the latest (recent) write data is obtained.

  FIG. 11 is an explanatory diagram of read access to the 33M input port in the first embodiment. In FIG. 11, 1-1, 1-2, 2-1, 2-2, 3 and 4-1, 4-2. Are the same as those shown in FIG. FIG. 12 is a time chart of signal generation in FIG. 11, wherein a to d of the port 1 (66M) are signals relating to the first single port RAM1, and e to l of the port 2 (33M) are the second single port. This is a signal related to the RAM 2.

  In the time chart shown in FIG. 12, a write access to the input port A2 occurs at time T1 of the second clock 33M (e in FIG. 12), and the data c1 is written to the address a1. The flag is set to “1” (f, g, h, l in FIG. 12). On the other hand, in the single port RAM1, the data b1 is written to the address a1 at the timing t1 of the first clock 66M (a in FIG. 12) (the time after T1), and the flag of the address a1 is reset to “0”. (B, c, d, l in FIG. 12).

  Thereafter, when a read access to the address a1 (f, g in FIG. 12) occurs at the input port A2 at the timing of the time T3 of the second clock 33M, as shown in FIG. The read data c1 is output from the single port RAM 2 (j in FIG. 12), and the read data b1 is output from the single port RAM 1 (same as i). At this time, since the flag processing unit 3 outputs “0” as the flag of the address a1 (l in FIG. 12), the second read data selection unit 4-2 reads the data b1 read from the single port RAM1 (latest Write data) is selected and output.

  FIG. 13 is an explanatory diagram in the case of simultaneous read access in the first embodiment. In FIG. 13, the symbols 1-1, 1-2, 2-1, 2-2, 3 and 4-1, 4-2 are the above The same reference numerals as those shown in FIG. FIG. 14 is a time chart of signal generation of FIG. 13, wherein a to g of the port 1 (66M) are signals relating to the first single port RAM1, and h to o of the port 2 (33M) are the second single port. This is a signal related to the RAM 2.

  In the time chart shown in FIG. 14, the write access to the input port A2 occurs first at time T1 of the second clock 33M (h in FIG. 14), and the data c1 is written to the address a1, and this address The flag of a1 is set to “1” (i, j, k, o in FIG. 14). On the other hand, in the single port RAM1, the data b1 is written to the address a1 at the timing t1 of the first clock 66M (a in FIG. 14) (the time after T1), and the flag of the address a1 is reset to “0”. (B, c, d, o in FIG. 14).

  Thereafter, read access to the address a1 (b, c and i, j in FIG. 14) is made to the input port A1 and the input port A2, respectively, at the timing t3 of the first clock 66M and the time T3 of the second clock 33M. When generated, read data is output from the two terminals A and B from the single port RAM 1 and the single port RAM 2, respectively, as shown in FIG. Data b1 (e in FIG. 14) is output from the read terminal A of the single port RAM1 in synchronization with 66M, and data c1 (same as f) is output from the terminal B of the single port RAM2 in synchronization with 66M. The two read data are input to the first read data selection unit 4-1. Further, data c1 (m in FIG. 14) is output from the read terminal A of the single port RAM2 in synchronization with 33M, and data b1 (the same l) is output from the terminal B of the single port RAM1 in synchronization with 33M. Thus, the two read data are input to the second read data selection unit 4-2. The read data selection units 4-1 and 4-2 select and output the data b1 from the flag processing unit 3 based on the flag ("0") of the address a1 (g and n in FIG. 14). . As described above, the latest write data is also read by simultaneous reading from the two read ports to the same address.

  FIG. 15 shows the configuration of the second embodiment. The second embodiment corresponds to the second principle configuration of the present invention shown in FIG. In the figure, 5 is a multiplexing unit, 50a to 50c are counters, and 50a is a clock of 33M when a write request synchronized with 33M to the second input port is generated. Port 2 1/2 counter (CTR), 50b halves the 66M clock when a write request synchronized with 66M to the first input port is generated A 1/2 counter for port 1 (CTR) for frequency division, 50c is a 1/3 counter for CUX (CTR) for dividing MUX clock (528M) for multiplexing in the multiplexing unit 5 by 3, and 51 The port 2 write address / data shift register holding the write address for port 2 and write data, 52a is a 0 detector for detecting that the value of the 1/2 counter for port 1 is 0, 52b is 1/2 for port 1 A 1-detection unit 53a for detecting that the value of the counter 50b is 1, and a 0-plane register for port 1 (Reg that holds the write address and write data of port 1 synchronized with 66M by the output of the 0-detection unit 52a) ), 53b holds the port 1 write address and write data by the output of the 1 detector 52b, and the port 1 single register (Reg), 54a rises and falls the port 2 1/2 counter 50a. Port 2/1/2 counter (CTR) edge detection unit 54b, 54c for detecting a port 1/1/2 counter (CTR) rising detection unit for detecting the rising of port 1/2 counter 50, port 1 -1/2 counter falling detection unit, 55a, 55b, 55c are 2 detection units for detecting 2, 0, 1 state of MUX 1/3 counter (CTR) 50c, 0 detection , It is the first detection unit.

  56a receives the output of the port 2 1/2 counter (CTR) 50a for the port 2 (33M) write request signal (Write Request) and is set by the output of the port 2 1/2 counter edge detector 54a. 2 The write request signal FF (flip-flop) 56b reset by the output of the detection unit 55a is the output of the port 1 1/2 counter (CTR) 50b for the port 1 (66M) write request signal (Write Request). In response to this, the 0-plane write request signal FF (flip-flop) 56c is set at the output of the port 1/1/2 counter rising edge detection unit 54b and reset at the timing of the 0 detection unit 55b. (CTR) A one-side write request signal FF (flip-flop) that is set at the output of the falling detection unit 54c and reset at the timing of the one detection unit 55c.57a to 57e are OR circuits, 58a to 58f are AND circuits, and 59 is an FF (flip-flop) for taking a beard (extra waveform) generated in the preceding combinational circuit (AND circuit and OR circuit). Reference numerals 6-1 and 6-2 denote a first single-port RAM 1 (indicated as RAM 1 in the figure) and a second single-port RAM 2 (indicated as RAM 2 in the figure) of 1W1R (one write port and one read port).

  A20 on the input side of the multiplexer 5 is an input terminal for the write address (ADD) and write data (WDT) of port 2 (33M), and A10 is a write address (ADD) of port 1 (66M). Input terminal for write data (WDT), A21 is an input terminal for write request of port 2 (33M), A11 is an input terminal for write request of port 1 (66M), and A30 is MUX Clock. A13 of the single port RAM1 is a read request terminal (Add, read request), R1 is a read data (read dt) terminal, A23 of the single port RAM2 is a read request terminal (Add, read request), and R2 is a read data. (Read dt) terminal.

  FIG. 16 is a time chart of 33M write access in the second embodiment, in which writing to port 2 (33M) in FIG. 15 is performed, with respect to the 33M clock for port 2 (a in FIG. 16). , The write address / write data from terminal A20 is “r1” (r1 includes address and write data) at t1 of the clock cycle, and “r2” (r2 is r1 and r1 at the next cycle t2). (Including different addresses and write data) are generated (b in FIG. 16), stored in the port 2 write address / write data shift register 51, and shifted in order (output e). At this time, the port 2 write request (Write Request) is output from the input terminal A21 (c in FIG. 16). At this time, the port 2 1/2 CTR 50a divides the 33M clock to divide the 0 and 1 planes. When the states are alternately generated (d in FIG. 16) and input to the port 2 1/2 counter edge detection unit FF (flip-flop) 54a, an edge detection output is output as shown in g in FIG. From the output of g and the signal of g, the MUX clock (f in FIG. 16) is divided by 3 by the MUX 1/3 counter 50c (i in FIG. 16), and the 2 detector 55a The output of the write request signal FF 56a reset by the detection output of “2” is input to the OR circuit 57a. The output of the OR circuit 57a is ANDed with the output of the 1 detector 55d of the MUX 1/3 counter 50c by the AND circuit 58a and set in the FF 59, and the port 2 write address / write data shift register 51 The output is set in the FF 59 through the AND circuit 58d and the OR circuit 57d, and the write address / write data (j in FIG. 16) and the write enable signal (k in FIG. 16) of the single port RAMs 1 and 2 are supplied to the single port RAM1. Are supplied to the single port RAM 2 for writing.

  FIG. 17 is a time chart of 66M write access in the second embodiment, and shows a case of writing to port 1 (66M) in FIG. In synchronization with the 66M clock for port 1 (a in FIG. 17), write addresses / write data s1 to s4 (including write address and write data, respectively) from input terminal A10 to clock cycles t1 to t4 ) As shown in FIG. At this time, a port 1 write request is generated from the terminal A11 of FIG. 15, and the 66M clock is divided by 2 by the port 1 1/2 counter 50b (d in FIG. 17). With respect to the 0 and 1 count values of the 1/2 counter for port 1 50b, the 0-plane register 53a for port 1 and the 1-plane register 53b for port 1 are detected by the detection outputs of the 0 detector 52a and 1 detector 52b. The write address and the write data from the terminal A10 are alternately held as shown by e and f in FIG. That is, each write address / write data of s1 and s3 is generated from the 0-plane register by a length of 66 M, and each write address / write data of s2 and s4 is generated from the 1-plane register, and s1 and s3 Are generated by shifting the phase by one clock.

  The rising edge of the output of the port 1/2 counter 50b (d in FIG. 17) is detected by the port 1/1/2 counter rising detector 54b as shown in h of FIG. The 2-counter falling detection unit 54c detects the signal as indicated by i in FIG. 17 and inputs it as a set signal for the 0-plane write request signal FF56b and the 1-plane write request signal FF56c, respectively. These write request signals FF56b and FF56c are input when the MUX clock (g in FIG. 17) receives a MUX clock (g in FIG. 17) and the state of the MUX 1/3 counter 50c (l in FIG. 17) is 0 or 1. Outputs are generated from the 0 detection unit 55b and the 1 detection unit 55c, the 0 side write request signal FF56b and the 1 side write request signal FF56c are reset, and signals j and k in FIG. 17 are generated. The output of the logical sum (OR) of the signals h and j in FIG. 17 is supplied to the AND circuit 58b and ANDed with the two detection outputs by the two detection unit 55e that receives the output of the MUX 1/3 counter 50c. Are output to the OR circuit 57e, set in the FF 59, and supplied to the single port RAM 1 and the single port RAM 2 for writing (s1 and s3 in m in FIG. 17). Similarly, the ORed output of the i and k signals in FIG. 17 is supplied to the AND circuit 58c and ANDed with the 0 detection output by the 0 detection unit 55f that receives the output of the MUX 1/3 counter 50c. It is output to the OR circuit 57e, set in the FF 59, supplied to the single port RAM 1 and the single port RAM 2 and written (s2 and s4 in m in FIG. 17).

  FIG. 18 is a time chart of the simultaneous write access in the second embodiment, where the write to the port 1 (66M) and the write to the port 2 (33M) in FIG. 15 occur simultaneously.

  In synchronization with the 33M clock for port 2 (a in FIG. 18), the write address / write data is generated as indicated by r1 and r2 from the terminal A20 in FIG. b). At this time, a port 2 write request is generated from the terminal A21 in FIG. 15 (c in FIG. 18). On the other hand, at the same time, in synchronization with the 66M clock for port 1 (e in FIG. 18), the write address / write data is indicated as s1 to s4 from the terminal A10 in FIG. (Portion f) and a port 1 write request is generated from the input terminal A11 of FIG. 15 (portion g). In this case, as described in FIGS. 16 and 17, the address and data of the port 2 write request are set in the port 2 write address / write data shift register 51 and sequentially shifted. The port 1 write request address and data are alternately set in the port 1 0 register 53a and port 1 register 53b and sequentially shifted, and each port write request (c, g in FIG. 18). Edge detection, write data selection (j in FIG. 18) and write operation (k in FIG. 18) by frequency division output (count values of 0, 1, and 2) by the MUX 1/3 counter 50c. , Write contention does not occur. As for the read access, there is no problem because the read request to the single port RAM 2 (d in FIG. 18) and the read request to the single port RAM 1 (h in FIG. 18) are performed at different ports. The data is read as indicated by 1 and m of (1 and s4 from the single port RAM1 and r2 from the single port RAM2). However, it is assumed that write access and read access of the same address are not performed simultaneously.

It is a figure which shows the 1st principle structure of this invention. It is a figure which shows the 2nd principle structure of this invention. 1 is a diagram illustrating a configuration of Example 1. FIG. It is a figure which shows the structural example of the flag process part of Example 1. FIG. It is a figure which shows the structural example of a 1st read data selection part. It is a figure which shows the structural example of the 2nd read data selection part. It is explanatory drawing of the simultaneous write access in Example 1. FIG. It is a figure which shows the time chart of the signal generation of FIG. It is explanatory drawing of the read access to the input port of 66M in Example 1. FIG. It is a figure which shows the time chart of the signal generation of FIG. It is explanatory drawing of the read access to the input port of 33M in Example 1. FIG. It is a figure which shows the time chart of the signal generation of FIG. FIG. 6 is an explanatory diagram for simultaneous read access in the first embodiment. It is a figure which shows the time chart of the signal generation of FIG. 6 is a diagram illustrating a configuration of Example 2. FIG. FIG. 10 is a time chart of 33M write access in the second embodiment. It is a figure which shows the time chart of 66M write access in Example 2. FIG. FIG. 10 is a diagram showing a time chart of simultaneous write access in the second embodiment. It is a figure which shows the structure of a prior art example.

Explanation of symbols

1-1 1W2R first single-port RAM
1-2 1W2R second single-port RAM
2-1 First Bus Address Decoder 2-2 Second Bus Address Decoder 3 Flag Processing Unit 4-1 First Read Data Selection Unit 4-2 Second Read Data Selection Unit A1 First synchronized with the first clock Input port A2 Second input port synchronized with the second clock R1 First read port synchronized with the first clock R2 Second read port synchronized with the second clock

Claims (5)

A pseudo dual port memory circuit using two single port RAMs,
The two single port RAMs have the same address space, one single port RAM has a write port for writing in synchronization with a first clock, and the other single port RAM is different from the first clock. A write port for writing in synchronization with the second clock of the frequency;
A flag processing unit having one common flag for each address of the two single-port RAMs;
The flag processing unit sets a flag corresponding to writing to one of the single port RAMs, resets a flag corresponding to writing to the other of the single port RAMs,
Read access to one of the single-port RAMs is supplied to the read port of its own single-port RAM and the other single-port RAM, and from the read data from the two single-port RAMs, the state of the flag corresponding to the read address A pseudo dual-port memory circuit comprising means for selecting one corresponding to the above. In claim 1,
A read request to the one single-port RAM is supplied to a first read port synchronized with the first clock, and to a second read port synchronized with the first clock of the other single-port RAM. Supplied,
A read request to the other single-port RAM is supplied to a first read port synchronized with the second clock, and also to a second read port synchronized with a second clock of the one single-port RAM. Supplied,
The data read by the first read port of the one single-port RAM and the data read from the second read port of the other single-port RAM are input to a first read data selection unit,
The data read by the first read port of the other single port RAM and the data read from the second read port of the one single port RAM are input to a second read data selection unit,
The pseudo dual-port memory circuit, wherein each of the first and second read data selection units selects one data in accordance with the state of the flag. In either claim 1 or 2,
The pseudo dual port memory circuit, wherein the frequency of the first clock is different from the frequency of the second clock. A pseudo dual port memory circuit using two single port RAMs,
The two single-port RAMs have the same address space, and each has one write port that operates in synchronization with a first clock or a second clock having a frequency different from that of the first clock. The port RAM has a read port synchronized with the first clock, and the other single-port RAM has a read port synchronized with the second clock,
The write access synchronized with the first clock and the write access synchronized with the second clock are input to the preceding stage of the write port of the two single-port RAMs, and the first clock and the second clock It has a multiplexing unit that receives a clock for multiplexing higher than the frequency,
The multiplexing unit includes a counter that divides the clock for multiplexing, a write access synchronized with the first clock and a write access synchronized with the second clock by a divided output of the counter. A pseudo dual-port memory circuit, wherein a write access divided into outputs is input to a write port of each single-port RAM. In claim 4,
The frequency of the first clock is an integer multiple of the frequency of the second clock, and the frequency of the multiplexing clock of the multiplexing unit is an integer multiple of the frequency of the second clock higher than the frequency of the first clock. A pseudo dual port memory circuit characterized by:

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