JP2008124713A - Analog signal processing circuit and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog signal processing circuit which prevents transitional deterioration in a level of an output signal of a CDS circuit even in the case of a rapid change of an output signal of a CCD, and an imaging apparatus with the analog signal processing circuit. <P>SOLUTION: A CCD output signal having a feed through period and a signal period, which is outputted from the CCD, is inputted to an input terminal 1 of an analog signal processing circuit 210 through an external input coupling capacitor. The analog signal processing circuit 210 includes an input impedance 2 constituting an integrating circuit together with the external input coupling capacitor, a reference voltage source 3 connected to the input impedance, a DC feedback circuit 5 for keeping a voltage level of the input terminal at a reference voltage VREF during the feed through period, and a CDS circuit 4 which generates an output signal on the basis of the difference between a voltage level during the feed through period of the CCD output signal and that during the signal period of the CCD output signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog signal processing circuit that processes a signal output from a CCD (Charge Coupled Device) used in a digital still camera or the like, and an imaging apparatus using such an analog signal processing circuit.

  Imaging devices such as a digital still camera, a video camera, a mobile phone, and a surveillance camera have a CCD and an analog signal processing circuit that processes a CCD output signal output from the CCD. An analog signal processing circuit described in Patent Document 1 is shown in FIG. As shown in FIG. 5, the analog signal processing circuit 510 inputs a CCD output signal to the input terminal 1 via an external input coupling capacitor Cin.

  One end of the input impedance 2 is connected between the input terminal 1 and a CDS (Correlated Double Sampling) circuit 4, and the reference voltage source 3 is connected between the other end of the input impedance 2 and the ground potential. The potential of the input terminal 1 is determined by the RC integration operation of the input coupling capacitor Cin and the input impedance 2.

  The CDS circuit 4 operates based on a pulse signal P generated by a pulse signal generator (not shown) formed on the same IC chip as the analog signal processing circuit 510, and receives a signal from a signal input to the input terminal 1. Only the components are extracted to generate the output signal c.

  FIG. 6 shows operation waveforms of the conventional analog signal processing circuit shown in FIG. The CCD output signal usually includes, for each pixel, a reset pulse period for indicating the separation of one pixel, a feedthrough period for indicating a reference voltage level, and a signal period for indicating a signal component. However, in order to make the explanation of the operation easy to understand, the CCD output signal shown in FIG. 6A has a waveform in which the signal of the reset pulse period is omitted.

  When there is no signal component in the signal period of the CCD output signal shown in FIG. 6A, the potential at the integration center of the RC integration operation of the input coupling capacitor Cin and the input impedance 2 becomes the reference voltage VREF. That is, as shown in FIG. 6C, the potential of the input terminal 1 becomes the reference voltage VREF. The potential of the input terminal 1 during the field-through period when there is a signal component of the signal period varies depending on the voltage level of the signal component of the CCD output signal due to the RC integration operation, and as shown in FIG. 6C, the reference voltage VREF. Higher voltage.

The CDS circuit 4 samples the voltage level serving as a reference for the CCD output signal at the rising timing of the pulse signal P shown in FIG. 6B, and the voltage of the signal component of the CCD output signal at the falling timing of the pulse signal P. The level is sampled, and the signal component is extracted from the CCD output signal based on the difference between the reference voltage level of the CCD output signal and the voltage level of the signal component. As shown in FIG. 6 (e), the CDS circuit 4 outputs the output signal c including the signal component extracted at the falling timing of the pulse signal P, and the output signal c is predetermined at the rising timing of the pulse signal P. Return to the voltage level. Normally, the CDS circuit 4 extracts and amplifies signal components using a differential amplifier or the like. At this time, as shown in FIG. 6E, the polarity is inverted and the output signal c is output.
JP-A-3-226184

  When the CCD output signal changes abruptly, for example, as shown in FIG. 6A, when the signal component in the signal period changes from the absence of the signal component to the presence of the signal component, the input coupling capacitor Cin and the input impedance 2 By the RC integration operation, the voltage level in the field through period of the input terminal 1 gradually becomes higher than the reference voltage VREF. While the voltage level of the field through period is fluctuating, the voltage level of the feed through period sampled by the CDS circuit 4 and the voltage level of the signal period continue to change. At this time, as shown in FIG. 6 (d), the waveform obtained by subtracting the original signal component from the voltage waveform at the input terminal 1, that is, the voltage level serving as a reference for the CCD output signal gradually increases. For this reason, the reference voltage level differs between the rising timing and falling timing of the pulse signal P. Since the difference in the reference voltage level affects the extraction of the signal component, the output signal c of the CDS circuit 4 generated by the difference between the voltage level in the feedthrough period and the voltage level in the signal period is shown in FIG. As shown in the range Y of (e), the value does not correspond to the level of the original signal component. As described above, in the conventional analog signal processing circuit, when the output signal of the CCD changes suddenly, the level of the output signal c of the CDS circuit deteriorates transiently until the voltage level in the feedthrough period becomes constant. There was a problem of doing.

  The present invention solves the above-described conventional problems, and is an analog signal that prevents the level of the output signal of the CDS circuit from transiently deteriorating even when the output signal of the CCD suddenly changes. It is an object of the present invention to realize an imaging device having a processing circuit and an analog signal processing circuit.

  An analog signal processing circuit of the present invention includes an input terminal for inputting a CCD output signal having a feedthrough period and a signal period output from a CCD through an external input coupling capacitor, and a feedthrough period for a CCD output signal. , And a CDS circuit that generates an output signal based on the difference between the voltage level in the signal period of the CCD output signal, an input impedance that performs an integration operation with the input coupling capacitor, and a reference connected to the input impedance A voltage source, and a DC feedback circuit that maintains the voltage level of the input terminal in the field-through period at the voltage of the reference voltage source.

  The DC feedback circuit includes a first switch having one end connected between the input terminal and the CDS circuit, a second end of the first switch and a non-inverting input terminal, and an inverting input terminal and an output terminal. A buffer circuit connected to each other, a first capacitor connected between the connection point of the first switch and the buffer circuit and the ground potential, and a second switch having one end connected to the output terminal of the buffer circuit And the other end of the second switch is connected to the inverting input terminal, the non-inverting input terminal is connected between the input impedance and the reference voltage source, and the output terminal is connected between the input terminal and the CDS circuit. A comparator and a second capacitor having one end connected to a connection point between the second switch and the comparator and the other end connected to the ground potential may be included.

  An imaging apparatus of the present invention includes a CCD that generates a CCD output signal, a pulse signal generator that generates a pulse signal, an analog signal processing circuit that operates based on the pulse signal and processes the CCD output signal, and analog signal processing And a DSP for processing a signal output from the circuit.

  The CCD and the analog signal processing circuit may be formed by the same IC chip. The pulse signal generator and the analog signal processing circuit may be formed by the same IC chip. The DSP and the analog signal processing circuit may be formed by the same IC chip.

  According to the analog signal processing circuit of the present invention, even when the output signal of the CCD suddenly changes, the reference voltage level in the signal period is set to the field by making the voltage of the input terminal in the field through period constant. Since it becomes the same value as the reference voltage level in the through period, it is possible to prevent the level of the output signal of the CDS circuit from being deteriorated transiently.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Configuration of imaging device]
FIG. 1 shows an imaging apparatus according to an embodiment of the present invention. The imaging apparatus of the present invention processes a CCD 100 that generates a CCD output signal, an input coupling capacitor Cin connected to the CCD 100, and a CCD output signal input via the input coupling capacitor Cin to convert it into a digital signal. Analog front end 200.

  The analog front end 200 processes the CCD output signal input via the input coupling capacitor Cin and outputs an analog signal, and the analog signal output from the analog signal processing circuit 210 is converted into a digital signal. And an A / D converter 220 for converting into

  The image pickup apparatus of the present invention receives an output signal from the analog front end 200, generates a YUV signal, etc., a DSP (Digital Signal Processor) 300, and generates various pulse signals, and the CCD 100 and the analog signal processing circuit 210. And a pulse signal generator 400 for outputting to the DSP 300. In the present embodiment, the pulse signal generator 400 generates pulse signals A, B, and P for controlling the operation timing of the analog signal processing circuit 210 and outputs them to the analog signal processing circuit 210. The analog front end 200 and the pulse signal generator 400 are formed by the same IC chip.

[Internal configuration of analog signal processing circuit]
FIG. 2 shows the internal configuration of the analog signal processing circuit 210. The analog signal processing circuit 210 is connected to the input terminal 1 to which the CCD output signal is input via the external input coupling capacitor Cin shown in FIG. 1 and the pulse signal P generated by the pulse signal generator 400 shown in FIG. And a CDS circuit 4 that generates an output signal c by extracting and amplifying only a desired signal component from the signal input to the input terminal 1.

  The CCD output signal includes, for each pixel, a reset pulse period indicating the separation of one pixel, a field through period for indicating a reference voltage level, and a signal period for indicating a voltage level of a signal component. In the CCD output signal in the field-through period and the signal period, amplifier noise generated when the photocharge detected in the light receiving unit in the CCD 100 is amplified and reset noise generated when the charge detection differential amplifier in the CCD 100 is reset. Etc. are included.

  The CDS circuit 4 uses a differential amplifier or the like to subtract the voltage level in the field through period from the voltage level in the signal period, thereby removing noise contained in the CCD output signal and extracting and amplifying only the signal component. Output. The CDS circuit 4 outputs the output signal c with the polarity reversed.

  One end of the input impedance 2 is connected between the input terminal 1 and the CDS circuit 4, and one end of the reference voltage source 3 that outputs the reference voltage VREF is connected to the other end of the input impedance 2. The other end of the reference voltage source 3 is connected to the ground potential. The input impedance 2 forms an RC integration circuit together with the input coupling capacitor Cin shown in FIG.

  The analog signal processing circuit 210 further includes a DC feedback circuit 5. The DC feedback circuit 5 makes the voltage of the input terminal 1 constant during the field through period of the CCD output signal.

[Internal configuration of DC feedback circuit]
In the DC feedback circuit 5, one end of the switch 6 is connected between the input terminal 1 and the CDS circuit 4, and the other end is connected to the non-inverting input terminal of the buffer circuit 8. The switch 6 switches on / off based on the pulse signal A generated by the pulse signal generator 400. In the present embodiment, the switch 6 is turned on while the pulse signal A is High, and the switch 6 is turned off while the pulse signal A is Low.

  The inverting input terminal of the buffer circuit 8 is connected to the output terminal. The capacitor C1 has one end connected between the switch 6 and the non-inverting input terminal of the buffer circuit 8, and the other end connected to the ground potential.

  The switch 7 is connected between the output terminal of the buffer circuit 8 and the inverting input terminal of the comparator 9. The switch 7 switches on / off based on the pulse signal B generated by the pulse signal generator 400. In the present embodiment, the switch 7 is turned on when the pulse signal B is High, and the switch 7 is turned off when the pulse signal B is Low. The capacitor C2 has one end connected between the switch 7 and the inverting input terminal of the comparator 9, and the other end connected to the ground potential.

  The non-inverting input terminal of the comparator 9 is connected between the reference voltage source 3 and the input impedance 2, and the output terminal of the comparator 9 is connected between the input terminal 1 and the CDS circuit 4.

  In the DC feedback circuit 5, a connection point between the output terminal of the buffer circuit 8 and the switch 7 is a connection point a, and a connection point between the inverting input terminal of the switch circuit 7 and the comparator 9 and the capacitor C2 is a connection point b.

[Operation of analog signal processing circuit]
3A shows the waveform of the CCD output signal, FIG. 3B shows the waveform of the pulse signal A, FIG. 3C shows the waveform of the voltage at the connection point a of the DC feedback circuit 5, and FIG. 3D shows the pulse. The waveform of the signal B and the waveform of the voltage at the connection point b of the DC feedback circuit 5 are shown in FIG. As shown in FIG. 3A, the voltage value in the field through period is equal to the reference voltage VREF.

  When the switch 6 is turned on while the pulse signal A is High, the voltage at the connection point a becomes a value obtained by monitoring the CCD output signal input to the input terminal 1, and the CCD output signal is reset as shown in FIG. The waveform includes a part of the pulse period and a part of the field-through period. When the pulse signal A becomes Low and the switch 6 is turned off, the voltage value at the time when the switch 6 is turned off is held, so that the voltage at the connection point a remains the reference voltage VREF.

  When the switch 7 is turned on while the pulse signal B is High, the voltage at the connection point b becomes equal to the voltage at the connection point a. While the switch 7 is on, the voltage at the connection point a holds the reference voltage VREF as shown in FIG. 3C, so that the voltage at the connection point b becomes the reference voltage VREF. When the pulse signal A becomes Low and the switch 7 is turned off, the voltage value at the time when the switch 7 is turned off is held, so that the voltage at the connection point b remains at the reference voltage VREF. Thus, as shown in FIG. 3E, the voltage at the connection point b always becomes the reference voltage VREF including when the switch 7 is on and when it is off.

  4A shows the waveform of the CCD output signal, FIG. 4B shows the waveform of the pulse signal P, FIG. 4C shows the voltage waveform of the input terminal 1 of the analog signal processing circuit 210, and FIG. 4D shows the reference. The waveform obtained by subtracting the original signal component from the waveform of the input terminal 1 shown in FIG. 4 and the waveform of the output signal c of the CDS circuit 4 are shown in FIG. In the waveform of the CCD output signal in FIG. 4A, the signal in the reset pulse period is omitted for the sake of simplicity.

  The CDS circuit 4 shown in FIG. 2 samples the voltage level serving as a reference for the CCD output signal at the rise timing of the pulse signal P shown in FIG. 4B, and the CCD output signal is sampled at the fall timing of the pulse signal P. The voltage level of the signal component is sampled, and the signal component is extracted from the CCD output signal based on the difference between the reference voltage level of the CCD output signal and the voltage level of the signal component. The CDS circuit 4 outputs the output signal c including the signal component extracted at the falling timing of the pulse signal P, and returns the output signal c to a predetermined voltage level at the rising timing of the pulse signal P. While there is no signal component in the signal period of the CCD output signal, there is no difference between the reference voltage level of the CCD output signal and the voltage level of the signal component, so the CDS output signal c has a constant value.

  When a CCD output signal including a signal component starts to be input, the voltage of the input terminal 1 during the field-through period will fluctuate due to the RC integration operation of the input coupling capacitor Cin shown in FIG. 1 and the input impedance 2 shown in FIG. However, the voltage of the input terminal 1 is maintained at the reference voltage VREF by the comparator 9 and the input impedance 2. Therefore, the voltage of the input terminal 1 in the field through period is always kept at the reference voltage VREF regardless of the voltage level of the signal period of the CCD output signal as shown in FIG.

  When the CCD output signal including the signal component starts to be input, the CDS circuit 4 samples the reference voltage VREF in the field through period as the reference voltage level of the CCD output signal at the rising timing of the pulse signal P, and outputs the pulse. The voltage level of the signal component of the CCD output signal is sampled at the falling timing of the signal P, and the output signal c is generated based on the difference between the reference voltage VREF and the voltage level of the signal component.

  Since the voltage at the input terminal 1 during the field-through period does not always change regardless of whether the CCD output signal includes a signal component, the CCD output signal including the signal component is input to the input terminal 1 Thereafter, the reference voltage level of the CCD output signal at the rising timing and falling timing of the pulse signal P is the same as shown in FIG. Therefore, the CDS circuit 4 is based on the difference between the reference voltage VREF in the field through period and the voltage of the signal component in the signal period even immediately after the CCD output signal including the signal component is input to the input terminal 1. As shown in the range X of FIG. 4E, an output signal c based on the voltage level of the original signal component can be generated.

  As described above, according to the present embodiment, the DC feedback circuit 5 monitors the voltage at the input terminal 1 and controls so that the voltage at the input terminal 1 does not fluctuate during the field-through period. Thereby, even when the CCD output signal changes abruptly, for example, when the CCD output signal changes from a state having no signal component to a state including a signal component, the voltage in the field through period of the input terminal 1 is kept constant. Can keep. As a result, even immediately after the CCD output signal including the signal component starts to be input to the input terminal 1, the voltage level serving as a reference for the CCD output signal at the rise of the pulse signal P and the fall of the pulse signal P The voltage level serving as a reference for the CCD output signal in FIG. 4 is the same as shown in FIG. Therefore, even after the CCD output signal including the signal component starts to be input to the input terminal 1, the original signal component is obtained by calculating the difference between the voltage level of the field output period of the CCD output signal and the voltage level of the signal period. Based on this, an output signal c can be generated. As described above, the DC feedback circuit 5 controls the voltage of the input terminal 1 so as not to fluctuate during the field-through period, thereby preventing the voltage level of the CDS output signal c output from the CDS circuit 4 from being deteriorated transiently. can do. As a result, as shown in FIG. 4 (e), even if the DSP 300 performs image processing based on the CDS output signal c, the video can be output normally, for example, the boundary line between the dark part and the bright part of the video is blurred. Disappear.

  In the present embodiment, the analog front end 200 and the pulse signal generator 400 are formed by the same IC chip. However, whether or not the analog front end 200 and the pulse signal generator 400 are incorporated in the same IC chip can be arbitrarily determined. For example, the analog front end 200 and the pulse signal generator 400 may be formed by separate IC chips. 1 may be formed with the same IC chip as the analog front end 200, and the DSP 300 may be formed with the same IC chip as the analog front end 200. Which of the components of the imaging device shown in FIG. 1 is incorporated in the same IC chip can be arbitrarily determined. For example, all of the components of the imaging device shown in FIG. 1 may be formed of the same chip. .

  According to the analog signal processing circuit of the present invention, it is possible to prevent the level of the output signal of the CDS circuit from being deteriorated transiently even when the output signal of the CCD suddenly changes. It is useful for various imaging devices such as a digital still camera, a video camera, a mobile phone, and a surveillance camera.

The block diagram which shows the imaging device of this invention The figure which shows the internal circuit of the analog signal processing circuit shown in FIG. The figure which shows the operation | movement waveform of the DC feedback circuit shown in FIG. The figure which shows the operation | movement waveform of the analog signal processing circuit shown in FIG. The figure which shows the internal circuit of the conventional analog signal processing circuit The figure which shows the operation waveform of the conventional analog signal processing circuit

Explanation of symbols

1 Input terminal 2 Input impedance 3 Reference voltage source 4 CDS circuit 5 DC feedback circuit 6, 7 Switch 8 Buffer circuit 9 Comparator 100 CCD
200 Analog Front End 210 Analog Signal Processing Circuit 220 A / D Converter 300 DSP
400 Pulse signal generator C1, C2 Capacitor Cin Input coupling capacitor

Claims (6)

An input terminal for inputting a CCD output signal having a feedthrough period and a signal period output from the CCD via an external input coupling capacitor;
A CDS circuit that generates an output signal based on a difference between a voltage level in the feedthrough period of the CCD output signal and a voltage level in the signal period of the CCD output signal;
An input impedance for integrating with the input coupling capacitor;
A reference voltage source connected to the input impedance;
A DC feedback circuit that maintains the voltage level of the input terminal at the voltage of the reference voltage source during the field-through period;
An analog signal processing circuit. The DC feedback circuit includes:
A first switch having one end connected between the input terminal and the CDS circuit;
A buffer circuit in which the other end of the first switch and a non-inverting input terminal are connected, and an inverting input terminal and an output terminal are connected;
A first capacitor connected between a connection point between the first switch and the buffer circuit and a ground potential;
A second switch having one end connected to the output terminal of the buffer circuit;
The other end of the second switch is connected to an inverting input terminal, a non-inverting input terminal is connected between the input impedance and the reference voltage source, and an output terminal is connected between the input terminal and the CDS circuit. Connected comparator,
A second capacitor having one end connected to a connection point between the second switch and the comparator and the other end connected to a ground potential;
The analog signal processing circuit according to claim 1. A CCD for generating a CCD output signal;
A pulse signal generator for generating a pulse signal;
The analog signal processing circuit according to claim 1 or 2, which operates based on the pulse signal and processes the CCD output signal;
A DSP for processing a signal output from the analog signal processing circuit;
An imaging apparatus having   The imaging apparatus according to claim 3, wherein the CCD and the analog signal processing circuit are formed of the same IC chip.   The imaging apparatus according to claim 3, wherein the pulse signal generator and the analog signal processing circuit are formed of the same IC chip.   The imaging apparatus according to claim 3, wherein the DSP and the analog signal processing circuit are formed of the same IC chip.

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