JP2008124484A - Semiconductor device, and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable miniaturization in a semiconductor in which a gate electrode is manufactured using the damascene gate technology etc. <P>SOLUTION: In the semiconductor device, each gate electrode of an N-type MIS transistor and a P-type MIS transistor is formed via a gate insulating film in a recess formed in a semiconductor substrate, wherein one of the gate electrodes of the N-type MIS transistor and the P-type MIS transistor is configured into a laminated structure of a first metal-containing film F1 and a second metal-containing film F2 on the first metal-containing film and the other gate electrode of the N-type MIS transistor and the P-type MIS transistor is configured into a laminated structure of a third metal-containing film F3 and the second metal-containing film F2 on the third metal-containing film F3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to improvement of gate electrodes of N-type MIS transistors and P-type MIS transistors.

  In order to improve the performance of the MIS transistor, it is essential to miniaturize the element. However, since the silicon oxide film currently used as the gate insulating film has a low dielectric constant, there is a problem that the capacity of the gate insulating film cannot be increased. In addition, the polysilicon used as the gate electrode has a problem that it cannot achieve low resistance because of its high resistivity. For each problem, a proposal has been made to use a high dielectric material for the gate insulating film and a metal material for the gate electrode.

  However, these materials have a drawback that they are inferior in heat resistance as compared to materials currently used. Therefore, a damascene gate technique has been proposed as a technique capable of forming a gate insulating film and a gate electrode after performing a high temperature process.

  In the damascene gate technology, a dummy gate is formed in advance in a region where a gate is to be formed, a dummy gate is removed after forming a source / drain diffusion layer, and an electrode material is embedded in the region from which the dummy gate is removed. Is produced.

  When the gate electrode is manufactured using the damascene gate technology, if the same metal is used for the gate electrodes of the N-type and P-type MIS transistors, the work functions of the gate electrodes of both transistors cannot be made different. And the threshold value of each of the P-type MIS transistors cannot be optimized.

  Therefore, a manufacturing process using different gate electrode materials is required for the N-type MIS transistor and the P-type MIS transistor. Hereinafter, an example of such a manufacturing process will be described with reference to FIGS. 20 (a) to 23 (i).

  First, an element isolation 502 having an STI structure is formed on a silicon substrate 501. Subsequently, a silicon oxide film 503 having a thickness of about 6 nm is formed as a dummy insulating film to be removed in the future. Further, as a dummy gate to be removed in the future, a laminated structure of a polysilicon film 504 having a thickness of about 150 nm and a silicon nitride film 505 having a thickness of about 50 nm is formed. These dummy insulating films and dummy gates are formed using ordinary techniques (film formation techniques such as oxidation and CVD, lithography techniques, and RIE techniques). Subsequently, an extension impurity diffusion layer to be the source / drain diffusion layer 506 is formed by ion implantation using the dummy gate (polysilicon film 504 and silicon nitride film 505) as a mask. Subsequently, a gate sidewall insulating film having a width of about 40 nm made of the silicon nitride film 507 is formed by the CVD technique and the RIE technique (FIG. 20A).

  Next, using the dummy gate (polysilicon film 504 and silicon nitride film 505) and gate sidewall insulating film (silicon nitride 507) as a mask, a high-concentration impurity diffusion layer to be the source / drain diffusion layer 508 is formed by ion implantation technology. To do. Further, by a salicide process technique, a silicide film (silicide such as cobalt or titanium) 509 having a thickness of about 40 nm is formed only in the source / drain regions using the dummy gate as a mask (FIG. 20B).

  Next, for example, a silicon oxide film is deposited as the interlayer insulating film 510 by a CVD method. Further, the surface of the silicon nitride films 505 and 507 is exposed by planarizing the interlayer insulating film 510 by CMP (FIG. 20C).

  Next, the silicon nitride film 505 above the dummy gate is selectively removed from the interlayer insulating film 510 using, for example, phosphoric acid. At this time, the silicon nitride film 507 is also etched to the height of the polysilicon film 504. Subsequently, the polysilicon film 504 is selectively removed with respect to the interlayer insulating film 510 and the silicon nitride film 507 by an etching technique using radicals of halogen atoms such as fluorine (FIG. 21D).

Next, the dummy silicon oxide film 503 is removed by wet etching such as hydrofluoric acid to form a groove (concave portion). Subsequently, a Ta ₂ O ₅ film 512 that is a high dielectric insulating film is formed as a gate insulating film by, for example, a CVD method or the like. Subsequently, for example, an aluminum film 513 is deposited as a gate electrode (FIG. 21E).

Next, the Ta ₂ O ₅ film 512 and the aluminum film 513 are planarized by CMP until the interlayer insulating film 510 is exposed (FIG. 21F).

  20A to 21F are performed on both the N-type MIS transistor formation region and the P-type MIS transistor formation region, but only one region is shown in the drawing. From the subsequent steps, both the N-type MIS transistor (N-type MISFET) formation region and the P-type MIS transistor (P-type MISFET) formation region are shown in the drawing.

  After the step of FIG. 21F, the area other than the P-type MIS transistor formation region is covered with a resist 514 using a lithography technique (FIG. 22G).

  Next, the aluminum film 513 is removed only in the P-type region by performing wet etching with phosphoric acid. At this time, the silicon nitride film 507 is exposed, but is hardly etched by phosphoric acid at room temperature (FIG. 22H).

  Next, after removing the resist 514, a cobalt film 515, for example, is deposited on the entire surface as a metal having a work function of about 5 eV (FIG. 23 (i)).

  Next, planarization of the cobalt film 515 is performed using CMP technology until the interlayer insulating film 510 is exposed (FIG. 23J).

  Through the above steps, a C-MIS transistor having an N-type aluminum film 513 and a P-type cobalt film 515 as a gate electrode structure is completed. Since the work function of the aluminum film 513 is about 4.2 eV and the work function of the cobalt film 515 is about 5 eV, the work function of the gate electrode can be optimized in each of the N-type MIS transistor and the P-type MIS transistor. And the threshold voltages of both transistors can be optimized.

  However, the above-described prior art has a big problem with respect to miniaturization. Hereinafter, this problem will be described.

  24 (a), 24 (b), and 24 (c) are plan views schematically showing main parts in FIGS. 22 (g), 22 (h), and 23 (j), respectively. . Let D be the distance between the source and drain of the N-type MIS transistor and P-type MIS transistor, that is, the distance between elements.

  In the step of FIG. 22 (h), when the aluminum film 513 in the P-type region is wet etched using the resist 514 as a mask, the wet etching proceeds isotropically. Therefore, the etching proceeds deeply to the region masked by the resist 514, and the aluminum film 513 is etched to the N-type region as shown in FIG.

  Therefore, the completed transistor structure is as shown in FIG. That is, in the N-type region, the gate electrode is composed of an aluminum film and a cobalt film having different work functions. Therefore, in the N-type MIS transistor, there are regions having different threshold values, and it is impossible to set a low threshold voltage.

  Consider further the issues discussed above. The lateral etching amount E by wet etching is equal to or higher than the height H (see FIG. 22H) of the aluminum film that is normally etched. In the above example, since the height H of the aluminum film is about 150 nm, the lateral etching amount E is 150 nm or more. Therefore, in order to avoid the above-described problem, it is necessary to make the inter-element distance D at least twice the lateral etching amount E, that is, 300 nm or more, and it is extremely difficult to miniaturize. Although a certain degree of miniaturization can be achieved by reducing the height H of the aluminum film, the gate resistance increases due to the reduction of the height H of the aluminum film, so this is not an essential solution.

  Further, the above-described conventional technique causes a serious problem with respect to the reliability of the gate insulating film and the like. Hereinafter, this problem will be described.

  In the prior art described above, after the aluminum film 513 in the P-type region is removed by wet etching in the step of FIG. 22 (h), the cobalt film 515 is formed in the removed region in the step of FIGS. 23 (i) and (j). Form. Therefore, the surface of the gate insulating film 512 is deteriorated due to etching of the aluminum film 513 and the reliability of the gate insulating film is adversely affected.

  As described above, the conventional damascene gate technique has a problem that when the dummy gate is removed by etching, the etching proceeds deeply in the lateral direction, which makes it difficult to reduce the size. Moreover, there is a problem in that the reliability of the gate insulating film or the like is adversely affected by removing the dummy gate by etching.

  The present invention has been made with respect to the above-described conventional problems, and a first object of the present invention is to achieve miniaturization of a semiconductor device in a semiconductor device in which a gate electrode is manufactured using damascene gate technology or the like. A second object is to ensure the reliability of the gate electrode and the like.

  The present invention (Invention A) is a semiconductor device in which the gate electrode of each of an N-type MIS transistor and a P-type MIS transistor is formed in a recess formed in a semiconductor substrate via a gate insulating film, The gate electrode of at least one of the transistor and the P-type MIS transistor is configured by a stacked structure of a plurality of metal-containing films, and the work function of at least a portion of the metal-containing film in contact with the gate insulating film of the N-type MIS transistor is in contact with the gate insulating film (W1) is smaller than the work function (W2) of at least a portion in contact with the gate insulating film of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor.

  The present invention (Invention B) is a method for manufacturing a semiconductor device, wherein the gate electrode of each of an N-type MIS transistor and a P-type MIS transistor is formed in a recess formed in a semiconductor substrate through a gate insulating film. The step of forming an electrode includes a first insulating film formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. Forming the metal-containing film, removing the first metal-containing film formed in one region of the first or second gate formation region, and the other of the first or second gate formation region Forming a second metal-containing film on the first metal-containing film left in the first region and on the gate insulating film in one of the first or second gate formation regions. Formation Of the first and second metal-containing films, of the metal-containing film in contact with the gate insulating film of the N-type MIS transistor, at least a portion in contact with the gate insulating film of the first and second metal-containing films. The work function (W1) is smaller than the work function (W2) of at least a portion in contact with the gate insulating film of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor.

  The present invention (Invention C) is a method of manufacturing a semiconductor device, wherein the gate electrodes of the N-type MIS transistor and the P-type MIS transistor are formed in a recess formed in a semiconductor substrate via a gate insulating film, The step of forming an electrode includes a first insulating film formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. Forming the metal-containing film, removing the first metal-containing film formed in one region of the first or second gate formation region, and the other of the first or second gate formation region Forming a third metal-containing film on the first metal-containing film left in the region and on the gate insulating film in one region of the first or second gate formation region; and the first or second Gate formation region Removing the third metal-containing film formed in the other region; and on the third metal-containing film and the first or second gate left in one region of the first or second gate formation region Forming a second metal-containing film on the first metal-containing film exposed in the other region of the formation region, and filling the recesses in both the first and second gate formation regions, Of the first and second metal-containing films, the work function (W1) of at least the portion of the metal-containing film in contact with the gate insulating film of the N-type MIS transistor that is in contact with the gate insulating film is the gate insulation of the P-type MIS transistor. It is characterized in that it is smaller than the work function (W2) of at least the portion in contact with the gate insulating film of the metal-containing film in contact with the film.

  According to the present invention (Inventions A, B, and C), the work function of the portion in contact with the gate insulating film of the N-type MIS transistor is smaller than the work function of the portion in contact with the gate insulating film of the P-type MIS transistor. The work function of the gate electrode of each of the P-type MIS transistor and the P-type MIS transistor can be optimized, and the threshold voltage of the N-type and P-type MIS transistors can be optimized.

  In addition, according to the present invention (Inventions A, B, and C), at least one gate electrode of the N-type MIS transistor and the P-type MIS transistor is formed of a plurality of metal-containing films, so that the portion in contact with the gate insulating film Even if the resistivity of this film is not low, the resistance of the entire gate electrode can be lowered by providing a low resistivity film on the upper layer side.

  According to the present invention (Inventions B and C), since the second metal-containing film is formed on the first and third metal-containing films, the thickness of the first and third metal-containing films is reduced. can do. Therefore, when removing the metal-containing film (first or third metal-containing film) formed in one region of the first or second gate formation region, the other of the first or second gate formation region is removed. It is possible to prevent the etching from proceeding deeply to this region, and to achieve miniaturization of the semiconductor device.

  In the present invention (Invention A, B, C), the work function W1 is closer to the conduction band than the center of the band gap of the semiconductor used for the semiconductor substrate (position of 1/2 of the band gap). W2 is preferably closer to the valence band than the center of the band gap. In addition, the thickness of the region in contact with the gate insulating film that determines the threshold value of the MIS transistor may be equal to or greater than a thickness at which a desired threshold value is obtained, but is preferably about 10 atomic layers or more. .

  In the present invention (Inventions A, B, and C), the respective portions in contact with the gate insulating film of the N-type and P-type MIS transistors do not necessarily need to be made of different materials. What is necessary is just to make the work functions of both different by making the composition or the crystal structure different between them.

  The present invention (Invention D) is a method for manufacturing a semiconductor device, wherein the gate electrode of each of an N-type MIS transistor and a P-type MIS transistor is formed in a recess formed in a semiconductor substrate via a gate insulating film. The step of forming an electrode includes a first insulating film formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. Forming a metal-containing film, and reacting a substance contained in the first metal-containing film formed in one region of the first or second gate formation region with a substance other than the substance. A step of converting one metal-containing film into a second metal-containing film, and of the first and second metal-containing films, the metal-containing film in contact with the gate insulating film of the N-type MIS transistor The work function of the portion in contact with at least the gate insulating film is equal to or smaller than the work function of the portion in contact with at least the gate insulating film in the direction of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor.

  The present invention (Invention E) is a method for manufacturing a semiconductor device, wherein the gate electrodes of the N-type MIS transistor and the P-type MIS transistor are formed in a recess formed in a semiconductor substrate via a gate insulating film, The step of forming an electrode includes a first insulating film formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. Forming a metal-containing film, and reacting a substance contained in the first metal-containing film formed in one region of the first or second gate formation region with a substance other than the substance. A step of converting one metal-containing film into a second metal-containing film, a substance contained in the first metal-containing film formed in the other region of the first or second gate formation region, and other than the substance Substance and A step of converting the first metal-containing film into a third metal-containing film by reacting, and of the second and third metal-containing films, the one in contact with the gate insulating film of the N-type MIS transistor The work function of at least a portion of the metal-containing film in contact with the gate insulating film is smaller than the work function of at least a portion of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor.

  The present invention (Invention F) is a method for manufacturing a semiconductor device, wherein the gate electrodes of the N-type MIS transistor and the P-type MIS transistor are formed in a recess formed in a semiconductor substrate through a gate insulating film. The step of forming an electrode includes a first insulating film formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. A step of forming the metal-containing film, and a substance other than the substance contained in the first metal-containing film in the first metal-containing film formed in one of the first or second gate formation regions. A step of forming a second metal-containing film by diffusing and precipitating at the interface of the gate insulating film, and of the first and second metal-containing films, the gate insulating film of the N-type MIS transistor The work function of at least the portion in contact with the gate insulating film of the metal-containing film in contact is smaller than the work function of at least the portion in contact with the gate insulating film of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor. And

  The present invention (Invention G) is a method for manufacturing a semiconductor device, wherein the gate electrodes of the N-type MIS transistor and the P-type MIS transistor are formed in a recess formed in a semiconductor substrate via a gate insulating film, The step of forming an electrode includes a first insulating film formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. A step of forming the metal-containing film, and a substance other than the substance contained in the first metal-containing film in the first metal-containing film formed in one of the first or second gate formation regions. A step of forming a second metal-containing film by diffusing and precipitating at the interface of the gate insulating film, and a step of forming the first metal-containing film formed in the other region of the first or second gate formation region First A step of forming a third metal-containing film by diffusing a substance other than the substance contained in the metal-containing film and precipitating it at the interface of the gate insulating film, and among the second and third metal-containing films, The portion of the metal-containing film that is in contact with the gate insulating film of the N-type MIS transistor is at least the portion of the metal-containing film that is in contact with the gate insulating film of the P-type MIS transistor is in contact with the gate insulating film. It is characterized by being smaller than the work function of.

  According to the present invention (Invention D, E, F, G), the work function of the portion in contact with the gate insulating film of the N-type MIS transistor is smaller than the work function of the portion in contact with the gate insulating film of the P-type MIS transistor. The work functions of the gate electrodes of the N-type and P-type MIS transistors can be optimized, and the threshold voltage of the N-type and P-type MIS transistors can be optimized.

  Further, according to the present invention (Invention D, E, F, G), the first metal-containing film is made second by reacting a substance contained in the first metal-containing film with a substance other than the substance. Converting to a third metal-containing film, or diffusing a substance other than a substance contained in the first metal-containing film in the first metal-containing film and depositing it on the gate insulating film interface, the second and second Since the metal-containing film 3 is formed, the gate electrode can be produced without etching the metal-containing film formed on the gate insulating film in the recess, and the deterioration of the reliability of the gate insulating film can be prevented. Is possible.

  In the present invention (Invention D, E, F, G), the work function W1 is closer to the conduction band than the center of the semiconductor band gap used for the semiconductor substrate (position of 1/2 of the band gap). The work function W2 is preferably closer to the valence band than the center of the band gap. In addition, the thickness of the region in contact with the gate insulating film that determines the threshold value of the MIS transistor may be equal to or greater than a thickness at which a desired threshold value is obtained, but is preferably about 10 atomic layers or more. .

  According to the present invention, it is possible to optimize the threshold voltages of the N-type and P-type MIS transistors by optimizing the work functions of the gate electrodes of the N-type and P-type MIS transistors. Further, miniaturization and low resistance of the semiconductor device can be achieved, and the reliability of the gate electrode and the like can be further improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
Hereinafter, an example of the manufacturing process according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 3 (i).

  First, an element isolation 102 having an STI structure is formed on a silicon substrate 101. Subsequently, a silicon oxide film 103 having a thickness of about 2 to 6 nm is formed as a dummy insulating film to be removed in the future. Further, as a dummy gate to be removed in the future, a laminated structure of a polysilicon film 104 with a thickness of about 150 nm and a silicon nitride film 105 with a thickness of about 50 nm is formed. These dummy insulating films and dummy gates are formed using ordinary techniques (film formation techniques such as oxidation and CVD, lithography techniques, and RIE techniques). Subsequently, an extension impurity diffusion layer to be the source / drain diffusion layer 106 is formed by ion implantation using the dummy gate (polysilicon film 104 and silicon nitride film 105) as a mask. Subsequently, a gate sidewall insulating film having a width of about 20 to 40 nm made of the silicon nitride film 107 is formed by the CVD technique and the RIE technique (FIG. 1A).

  Next, using the dummy gate (polysilicon film 104 and silicon nitride film 105) and the gate sidewall insulating film (silicon nitride 107) as a mask, a high-concentration impurity diffusion layer to be the source / drain diffusion layer 108 is formed by ion implantation technology. To do. Furthermore, a silicide film (silicide such as cobalt or titanium) 109 having a thickness of about 40 nm is formed only in the source / drain regions by using the salicide process technique with the dummy gate as a mask (FIG. 1B).

  Next, for example, a silicon oxide film is deposited as the interlayer insulating film 110 by a CVD method. Further, the surface of the silicon nitride films 105 and 107 is exposed by planarizing the interlayer insulating film 110 by CMP technique (FIG. 1C).

  Next, the silicon nitride film 105 above the dummy gate is selectively removed from the interlayer insulating film 110 using phosphoric acid, for example. At this time, the silicon nitride film 107 is also etched to the height of the polysilicon film 104. Subsequently, the polysilicon film 104 is selectively removed with respect to the interlayer insulating film 110 and the silicon nitride film 107 by an etching technique using radicals of halogen atoms such as fluorine (FIG. 2D).

Next, by removing the dummy silicon oxide film 103 by wet etching such as dilute hydrofluoric acid, a groove (recess) 111 is formed. Subsequently, a hafnium oxide film (HfO ₂ film), which is a high dielectric insulating film, is formed on the entire surface as a gate insulating film. This hafnium oxide film is formed by, for example, forming a hafnium nitride film (HfN film) by a CVD method using HfCl ₄ and NH ₃ or a sputtering method using a hafnium nitride (HfN) or a hafnium target. It is obtained by oxidizing the formed hafnium nitride film (FIG. 2 (e)).

  Next, a hafnium nitride film 113 having a work function of about 4 eV is formed on the entire surface with a thickness of about 10 nm, preferably 10 nm or less, using CVD or sputtering (FIG. 2F).

  The steps shown in FIGS. 1A to 2F are performed on both the N-type MIS transistor formation region and the P-type MIS transistor formation region, but only one region is shown in the drawing. From the subsequent steps, both the N-type MIS transistor (N-type MISFET) formation region and the P-type MIS transistor (P-type MISFET) formation region are shown in the drawing.

  After the step of FIG. 2F, the region other than the P-type MIS transistor formation region is covered with a resist 114 using a lithography technique. A plan view of the main part at this time is schematically shown in FIG. 4A (FIG. 3G).

  Next, the hafnium nitride film 113 is removed only in the P-type region by performing wet etching with hydrogen peroxide solution. A plan view of the main part at this time is schematically shown in FIG. Since the hafnium oxide film 112 of the gate insulating film is insoluble in the hydrogen peroxide solution, it is not etched. Further, since the hafnium nitride film 113 is very thin (about 10 nm), unlike the prior art, the hafnium nitride film 113 is not deeply etched up to the N-type region. That is, in this example, the thickness of the hafnium nitride film 113 is about 10 nm, and the lateral etching amount E is also about 10 nm. Therefore, if the inter-element distance D is about 20 nm or more, the problems of the prior art can be solved, and a significant miniaturization can be performed (FIG. 3 (h)).

Next, after removing the resist 114, for example, a cobalt film 115 is deposited on the entire surface as a noble metal film having a work function of about 5 eV. The cobalt film is formed by sputtering or CVD using Co (CO) ₄ , Co ₂ (CO) ₈ , CoF ₂ , CoCl ₂ or CoBr ₂ as a gas source. Thereafter, the cobalt film 115, the hafnium nitride film 113, and the hafnium oxide film 112 are planarized by CMP until the interlayer insulating film 110 is exposed. A plan view of the main part at this time is schematically shown in FIG. 4C (FIG. 3I).

  Through the above steps, a C-MIS transistor having a gate electrode structure having a stacked structure of the hafnium nitride film 113 and the cobalt film 115 for the N type and a single layer structure of the cobalt film 115 for the P type is completed.

  According to the present embodiment, the work function of the portion in contact with the gate insulating film of the N-type MIS transistor can be made smaller than the work function of the portion in contact with the gate insulating film of the P-type MIS transistor (in the above example, The work function of the hafnium nitride film 113 is about 4 eV, and the work function of the cobalt film 115 is about 5 eV.) The work functions of the gate electrodes of the N-type and P-type MIS transistors are optimized to optimize the threshold voltage of both transistors. It is possible to

  In the present embodiment, when removing the hafnium nitride film 113 in the P-type region, the hafnium nitride film 113 is extremely thin, so that the hafnium nitride film 113 is prevented from being etched deeply to the N-type region. Thus, it is possible to perform a significant miniaturization. Furthermore, in this embodiment, since the low-resistance cobalt film 115 is formed on the hafnium nitride film 113 for the gate electrode of the N-type MIS transistor, it is possible to achieve both optimization of work function and low resistance. .

  FIG. 5 shows the dependency of the threshold value (threshold voltage) on the element separation distance (distance between elements, distance D shown in FIG. 4) for the N-type and P-type MIS transistors according to this embodiment and the prior art. Is.

  As for the P-type MIS transistor, in both the present embodiment and the prior art, the threshold is constant and the voltage is low (about −0.2 V) until the element separation distance D is about 400 nm. On the other hand, with respect to the N-type MIS transistor, in the conventional technique, the threshold value starts to increase when the inter-element distance D is 300 nm or less. This is because a part of the N-type MIS transistor is made of a metal having a work function of about 5.0 eV. On the other hand, in the present embodiment, it is understood that the threshold value is constant even when the inter-element distance D is reduced to 40 nm.

  In the above-described example, the case where the gate electrode of the N-type MIS transistor has a stacked structure of a hafnium nitride film and a cobalt film and the gate electrode of the P-type MIS transistor has a single-layer structure of a cobalt film has been described. The present embodiment is not limited to such a gate electrode structure, and various modifications are possible. Therefore, some modifications will be described below.

  There are three basic gate structures in this embodiment: structure A, structure B, and structure C. FIG. 6 corresponds to the structure A, FIG. 7 corresponds to the structure B, and FIG. 8 corresponds to the structure C. Regarding these structures A, B, and C, variations of these structures include, for example, the structure shown in FIG. 9 (referred to as structure D). 6 to 9 schematically show only the gate insulating film and the gate electrode.

  Structure A (see FIG. 6) is composed of a first metal-containing film F1 and a second metal-containing film F2 in which the gate electrode of the N-type MIS transistor is formed on the gate insulating film F0, and the gate of the P-type MIS transistor. The electrode is composed of the second metal-containing film F2 formed on the gate insulating film F0, and the work function of the first metal-containing film F1 is smaller than the work function of the second metal-containing film F2.

  The manufacturing method of the structure A includes a step of forming a first metal-containing film F1 on the gate insulating film F0 in both gate formation regions for N-type and P-type MIS transistors, and a gate formation region for P-type MIS transistors. And removing the first metal-containing film F1 on the first metal-containing film F1 in the gate formation region for the N-type MIS transistor and on the gate insulating film F0 in the gate formation region for the P-type MIS transistor. Forming the second metal-containing film F2 to fill the recesses in the gate formation regions of both the N-type and P-type MIS transistors.

  The structure B (see FIG. 7) is composed of a first metal-containing film F1 and a second metal-containing film F2 in which the gate electrode of the P-type MIS transistor is formed on the gate insulating film F0. The gate electrode is composed of the second metal-containing film F2 formed on the gate insulating film F0, and the work function of the first metal-containing film F1 is smaller than the work function of the second metal-containing film F2.

  The manufacturing method of the structure B includes a step of forming a first metal-containing film F1 on the gate insulating film F0 in both gate formation regions for N-type and P-type MIS transistors, and a gate formation region for N-type MIS transistors. And removing the first metal-containing film F1 on the first metal-containing film F1 in the gate formation region for the P-type MIS transistor and on the gate insulating film F0 in the gate formation region for the N-type MIS transistor. Forming the second metal-containing film F2 to fill the recesses in the gate formation regions of both the N-type and P-type MIS transistors.

  A specific example of the structure A is as shown in FIGS. For the structure B, most of the manufacturing method shown in FIGS. 1 to 3 can be used (the materials suitable for the structure B are used for each constituent material). The main change is that, in the step of FIG. 3G, the P-type MIS transistor region is masked with a resist instead of the N-type MIS transistor region.

  Structure C (see FIG. 8) is composed of a first metal-containing film F1 and a second metal-containing film F2 in which the gate electrode of the N-type MIS transistor is formed on the gate insulating film F0, and the gate of the P-type MIS transistor. The electrode includes a third metal-containing film F3 and a second metal-containing film F2 formed on the gate insulating film F0, and the work function of the first metal-containing film F1 is the work function of the third metal-containing film F3. Smaller than.

  The manufacturing method of the structure C (see FIG. 10) includes a step of forming a first metal-containing film F1 on the gate insulating film F0 in both gate formation regions for N-type and P-type MIS transistors, and a P-type MIS transistor. Removing the first metal-containing film F1 in the gate formation region for the gate, and insulating the gate formation region on the first metal-containing film F1 in the gate formation region for the N-type MIS transistor and the gate formation region for the P-type MIS transistor A step of forming a third metal-containing film F3 on the film F0, a step of removing the third metal-containing film F3 in the gate formation region for the N-type MIS transistor, and a step of forming a gate formation region for the N-type MIS transistor. By forming the second metal-containing film F2 on the first metal-containing film F1 and on the third metal-containing film F3 in the gate formation region for the P-type MIS transistor, N-type and P-type M And a step of embedding the recesses of both the gate formation region of the S transistor.

  The structure A, the structure B, and the structure C include a structure (structure D) in which the second metal-containing film F2 is a laminated film of two or more types. In the example of FIG. 9, corresponding to the example of FIG. 6, the second metal-containing film F2 of the N-type and P-type MIS transistors is configured by a laminated film of metal-containing films F2a and F2b.

  Hereinafter, Structure A to Structure D described above will be further described.

  (1) In the structure A (see FIG. 6), the first metal-containing film F1 is a barrier metal that determines the threshold value of the N-type MIS transistor, and the second metal-containing film F2 is a P-type MIS transistor. Each is used as a barrier metal to determine the threshold.

  The first metal-containing film F1 has a work function (4.6 eV or less, preferably about 4 eV) that can optimize the threshold value of the N-type MIS transistor, and has no damage (wet etching or radical atom). And those capable of performing dry etching using radical molecules). Representative materials include HfN and ZrN. These are expected to have a work function of about 4 eV, and are suitable as an N-type barrier metal.

The second metal-containing film F2 has a work function (4.6 eV or more, preferably about 5 eV) that can optimize the threshold value of the P-type MIS transistor, and has a resistivity that can reduce the resistance of the gate electrode. Use a low one. Many noble metal materials have a work function of about 5 eV and are suitable for the second metal-containing film. From the viewpoint of resistivity, Co is about 5 μΩ · cm, Ni is about 6 μΩ · cm, and Pt is about 10 μΩ · cm. The resistivity of W and CoSi ₂ currently used as gate electrodes is about 5 μΩ · cm and about 20 μΩ · cm, respectively, and Co, Ni, and Pt, especially Co, are suitable as materials for the second metal-containing film. Yes.

The gate insulating film F0 is not particularly limited, but it is desirable to use HfO ₂ when the barrier metal is HfN. This is because a thermal reaction hardly occurs at the interface between HfN and HfO ₂ .

  (2) In the structure B (see FIG. 7), the first metal-containing film F1 is a barrier metal that determines the threshold value of the P-type MIS transistor, and the second metal-containing film F2 is an N-type MIS transistor. Each is used as a barrier metal to determine the threshold.

The first metal-containing film F1 has a work function (4.6 eV or more, preferably about 5 eV) that can optimize the threshold value of the P-type MIS transistor, and has no damage (wet etching or radical atom). And those capable of performing dry etching using radical molecules). Typical materials include WN _x and WSi _x N _y .

  The second metal-containing film F2 has a work function (4.6 eV or less, preferably about 4 eV) that can optimize the threshold value of the N-type MIS transistor, and has a resistivity that can reduce the resistance of the gate electrode. Use a low one. A typical material is Al (or an alloy containing Al).

  (3) In the structure C (see FIG. 8), the first metal-containing film F1 is a barrier metal that determines the threshold value of the N-type MIS transistor, and the third metal-containing film F3 is the threshold value of the P-type MIS transistor. The second metal-containing film F2 is used as a low-resistance electrode material.

The first metal-containing film F1 has a work function (4.6 eV or less, preferably about 4 eV) that can optimize the threshold value of the N-type MIS transistor, and has no damage (wet etching or radical atom). Or HfN is typically used. The third metal-containing film F3 has a work function (4.6 eV or more, preferably about 5 eV) that can optimize the threshold value of the P-type MIS transistor, and can be etched without damage. WN _x is typically used. For the second metal-containing film F2, a low resistance material, typically Al (or an alloy containing Al) is used.

  (4) In the structure corresponding to the structure A or the structure B in the structure D (see FIG. 9), as the second metal-containing film F2 that is a laminated film, the lower film F2a is an N-type or P-type MIS transistor. The upper layer side film F2b has a work function (4.6 eV or less, preferably 4 eV for N type, preferably 4.6 eV or more for P type, preferably 5 eV) for the threshold value. Is required to have low resistance.

  In the structure corresponding to the structure C in the structure D, since the first metal-containing film F1 and the third metal-containing film F3 are under the second metal-containing film F2, the lower side of the second metal-containing film is located. Although there is no merit that the film is used to optimize the threshold value of the transistor, there is an advantage that metal diffusion from the upper layer side to the gate insulating film can be suppressed.

Typically, in the structure D corresponding to the structure A, the first metal-containing film F1 is HfN, the lower layer side F2a of the second metal-containing film is RuO ₂ , and the upper layer side F2b of the second metal-containing film is The thing comprised with Al is mention | raise | lifted.

  (5) In Structure A, Structure B, and Structure C, it is desirable to use a metal compound that is a conductor for the first metal-containing film F1. Examples of the barrier metal for the N-type MIS transistor include hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, tantalum nitride, and niobium nitride. Examples of the barrier metal for the P-type MIS transistor include tungsten nitride and tungsten silicide nitride.

  (6) In Structure A and Structure C, the second metal-containing film F2 is made of platinum, palladium, nickel, cobalt, rhodium, ruthenium, rhenium, iridium, gold, silver, copper, or an alloy containing these metals. It is desirable to use a film containing.

  (7) In the structure A, the structure B, and the structure C, it is desirable to use a film containing a metal compound that is a conductor as the second metal-containing film F2.

  Examples of the metal compound include metal oxides (ruthenium oxide, iridium oxide, rhenium oxide, platinum oxide, rhodium oxide). This is because the noble metal-based oxide is often a conductor and it is easy to obtain a work function suitable for a P-type MIS transistor.

  Secondly, examples of the metal compound include metal silicides (platinum silicide, palladium silicide, nickel silicide). These can obtain a work function suitable for an N-type or P-type MIS transistor (particularly a P-type MIS transistor).

  Thirdly, examples of the metal compound include metal nitrogen compounds (hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, niobium nitride). These can obtain a work function suitable for an N-type MIS transistor.

  (8) In the structure D, it is desirable that at least the lowermost film of the second metal-containing film F2 is a metal compound. As metal compounds, metal oxides (ruthenium oxide, iridium oxide, rhenium oxide, platinum oxide, rhodium oxide), metal silicides (platinum silicide, palladium silicide, nickel silicide), metal nitrogen compounds (Hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, tungsten nitride), tungsten nitride silicide.

  (9) In the structure C, it is desirable to use tungsten nitride or tungsten nitride silicide for the third metal-containing film F3.

(10) In the structures A to D, as the gate insulating film F0, HfO ₂ , ZrO ₂ , TiO ₂ , silicon nitride film, Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , Y ₂ O _3, Examples thereof include a zirconium oxide film containing CeO ₂ and yttrium, a compound film of barium, strontium, titanium, and oxygen, a compound film of lead, zirconium, titanium, and oxygen, and a silicon oxide film.

HfCl ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , Y ₂ O ₃ , CeO ₂ , a zirconium oxide film containing yttrium includes HfCl ₄ , ZrCl ₄ , TiCl ₄ , TaCl ₅ , NbCl ₅ , Y (Thd) ₃ (where Thd means 2,2,6,6-tetramethyl-3,5-heptaneconionate), Ce (Thd) ₄ , There is a method of directly forming a film by a CVD method in which an O ₂ gas is mixed in a mixed gas of Zr (Thd) ₄ and Y (Thd) ₃ .

Further, instead of O ₂ gas, for example, using NH ₃ or the like, first, each metal nitride, that is, a zirconium nitride film containing HfN, ZrN, TiN, TaN, NbN, YN, CeN, yttrium is formed, and then Alternatively, each metal nitride may be converted into an oxide by thermal oxidation. When this thermal oxidation method is used, it is desirable to thermally oxidize nitrides of 5 nm or less or to repeat nitride deposition / oxidation of 5 nm or less a plurality of times so that nitrogen does not remain in the film. When a thick nitride film is thermally oxidized, when the oxidation temperature is a low temperature of 500 ° C. or lower, nitrogen, which is a product from the newly oxidized layer, cannot escape from the inside of the film and remains in the film. This is because it was found out.

  Before forming the above metal oxide, a silicon oxide film by thermal oxidation, an oxynitride film using oxidation in NO gas, or a silicon nitride film by CVD or the like is formed on the silicon substrate. Then, the gate insulating film F0 having a stacked structure may be formed by forming the metal oxide film described above.

(11) When HfN, ZrN, or TiN is used as the lowermost layer of the gate electrode, hydrogen peroxide water can be used for these etchings. It is necessary that the gate insulating film F0 is not etched during the etching using the hydrogen peroxide solution. Zirconium oxide containing HfO ₂ , ZrO ₂ , TiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , Ta ₂ O ₅ , Nb ₂ O ₅ , Y ₂ O ₃ , CeO ₂ , and yttrium as the gate insulating film F0. When a film, a compound film of barium, strontium, titanium and oxygen, a compound film of lead, zirconium, titanium and oxygen, or a silicon oxide film is used, there is no problem because these are insoluble in hydrogen peroxide water.

When TaN or NbN is used as the film on the lowermost layer side of the gate electrode, these are soluble in a mixed solution of hydrochloric acid and nitric acid. Accordingly, HfO ₂ , ZrO ₂ , TiO ₂ , Si ₃ N ₄ , silicon oxide film, silicon oxynitride containing 1% or more of nitrogen, or the like that is insoluble in the mixed solution may be used for the gate insulating film F0. .

When aluminum is used as the film on the lowermost layer side of the gate electrode, aluminum is soluble in a mixed solution of phosphoric acid and nitric acid. Therefore, the gate insulating film F0 includes a zirconium oxide film containing HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O ₅ , Nb ₂ O ₅ , yttrium, a compound of barium, strontium, titanium, and oxygen that is insoluble in the mixed solution. A film, a compound film of lead, zirconium, titanium, and oxygen, or a silicon oxide film may be used.

(12) When the above-described metal nitride (HfN, ZrN, TiN, TaN, NbN) is used as the film on the lowermost layer side of the gate electrode, the combination of the metal nitride film and the gate insulating film is the etching described above. In addition to resistance, it is desirable to satisfy the following conditions. In other words, the Gibbs free energy of the metal oxide comprising the metal element constituting the metal nitride is set to be equal to or less than the Gibbs free energy of the metal oxide film or silicon oxide film used for the gate insulating film. This is because the possibility that the metal nitride reduces the gate insulating film is reduced. Specifically, when the gate insulating film is HfO ₂ , it is desirable to use HfN, ZrN, TiN, TaN, NbN as the metal nitride, and when the gate insulating film is Ta ₂ O ₅ , the metal nitride is used. It is desirable to use TaN or NbN.

(Embodiment 2)
Hereinafter, an example of the manufacturing process according to the second embodiment of the present invention will be described with reference to FIGS. 11 (a) to 14 (l).

  First, the surface of the silicon substrate 201 is thermally oxidized to form a silicon oxide film 202. Thereafter, a silicon nitride film 203 is formed on the silicon oxide film 202 by CVD (FIG. 11A).

  Next, a pattern of a photoresist 204 is formed on the silicon nitride film 203. Subsequently, by using this resist pattern 204 as a mask, the silicon nitride film 203, the silicon oxide film 202, and the silicon substrate 201 are patterned using anisotropic etching to form element isolation trenches (FIG. 11B). ).

Next, the photoresist 204 is ashed and removed. Thereafter, the exposed surface of the element isolation trench is thermally oxidized, for example, at 950 ° C. in an HCl / O ₂ atmosphere to form a silicon oxide film 205. Subsequently, a silicon oxide film 206 is deposited on the entire surface by using the CVD method to fill the element isolation trench. Further, the silicon oxide film 206 is polished by CMP until the surface of the silicon nitride film 203 is exposed (FIG. 11C).

  Next, the silicon nitride film 203 is selectively removed using hot phosphoric acid. Subsequently, the silicon oxide film 202 is removed using a diluted hydrofluoric acid solution. At this time, the silicon oxide film 206 and the silicon oxide film 205 above the element isolation trench are slightly etched, and the surface of the silicon substrate 201 near the upper edge of the element isolation trench is exposed (FIG. 12D).

Next, thermal oxidation is performed, for example, at 900 ° C. in an HCl / O ₂ atmosphere to form a silicon oxide film 207 to be a dummy insulating film. Since the dummy insulating film 207 is formed not only on the MIS transistor formation region but also on the upper edge of the element isolation trench, the exposed surface of the silicon substrate disappears (FIG. 12E).

  Next, after forming a polysilicon film 208 on the entire surface, this polysilicon film 208 is patterned to form a dummy gate (FIG. 12F).

Next, impurity ions are implanted into the surface of the silicon substrate 201 using a dummy gate made of the polysilicon film 208 as a mask. Further, the source / drain diffusion layer 209 is formed in a self-aligned manner with respect to the dummy gate by performing a high-temperature annealing process. Subsequently, an interlayer insulating film 210 is deposited on the entire surface, and the interlayer insulating film 210 is planarized using a CMP method until the polysilicon film 208 is exposed. Thereafter, the exposed polysilicon film 208 is removed by a down flow technique using, for example, CF ₄ / O ₂ gas (FIG. 13G).

Next, in order to adjust the threshold voltages of the N-type and P-type MIS transistors, N-type and P-type impurities are respectively implanted into the silicon substrate 201 via the exposed dummy insulating film 207. Introduced in. Subsequently, by removing the dummy insulating film 207 using a dilute hydrofluoric acid solution, a groove (concave portion) 211 is formed. Thereafter, a Ta ₂ O ₅ film 212 is formed as a gate insulating film. Further, a ruthenium (Ru) film or a palladium (Pd) film 213 is formed with a film thickness of about 10 nm as a gate electrode material of the P-type MIS transistor (FIG. 13H).

  Next, a silicon nitride film 214 having a thickness of 10 nm is formed on the entire surface by plasma CVD. This silicon nitride film 214 is used as a diffusion preventing film for preventing diffusion of indium (In) or tin (Sn) formed in a later step. Thereafter, a pattern of a photoresist 215 is formed on the P-type MIS transistor region (FIG. 13 (i)).

  Next, the exposed silicon nitride film 214 in the N-type MIS transistor region is removed using a down flow method. After the photoresist 215 is removed by ashing, an indium (In) film or a tin (Sn) film is formed on the entire surface as a gate electrode material of an N-type MIS transistor with a thickness of 1 to 2 nm (FIG. 14 (j )).

Next, medium-low temperature annealing is performed at about 200 ° C. to 400 ° C. Since the silicon nitride film 214 is formed in the P-type MIS transistor region, this annealing process selectively diffuses indium or tin only in the N-type MIS transistor region. Indium or tin diffuses through the grain boundaries of the ruthenium film or palladium film 213. As a result, indium or tin is deposited at the interface between the Ta ₂ O ₅ film 212 serving as the gate insulating film and the ruthenium film or palladium film 213. As a result, an indium film or a tin film 216 serving as the gate electrode of the N-type MIS transistor is formed (FIG. 14 (k)).

Next, the indium film or tin film 216 on the P-type MIS transistor region is selectively removed, and the silicon nitride film 214 is further removed using a downflow method. Thereafter, the tungsten film 217 is embedded in the trench in the gate electrode region of the N-type and P-type MIS transistors. Further, the ruthenium film or palladium film 213, the indium film or tin film 216, the Ta ₂ O ₅ film 212 and the tungsten film 217 outside the groove are removed by using the CMP method, and the tungsten film 217 is left only in the groove. Thus, a gate electrode in which a ruthenium film or palladium film 213 is formed in the lowermost layer is formed in the P-type MIS transistor, and a gate electrode in which an indium film or tin film 216 is formed in the lowermost layer is formed in the N-type MIS transistor. Thereafter, the interlayer insulating film 218, the wiring 219, and the like are formed, and the semiconductor integrated circuit is completed (FIG. 14L).

  In the above-described example, the metal M2 constituting the gate electrode of the N-type MIS transistor (indium in the above-described example) in the metal M1 (ruthenium or palladium in the above-described example) constituting the gate electrode of the P-type MIS transistor. Alternatively, metal M2 is deposited on the interface of the gate insulating film of the N-type MIS transistor by diffusing tin), but an alloy of metal M1 and metal M2 is formed by diffusing metal M2 into metal M1. However, the gate electrode of the N-type MIS transistor may be constituted by this alloy (referred to as Modification 1).

  In the above-described example, the silicon nitride film 214 is used as a diffusion mask when diffusing the metal M2 constituting the gate electrode of the N-type MIS transistor in the metal M1 constituting the gate electrode of the P-type MIS transistor. Thus, the metal M2 is selectively diffused into the N-type MIS transistor region. However, the metal M2 is selectively formed only on the metal M1 in the N-type MIS transistor region without forming the silicon nitride film 214. Similarly to the above-described example, the metal M2 may be selectively diffused into the metal M1 only in the N-type MIS transistor region (referred to as Modification 2).

  Further, in the basic example and the first and second modifications described above, the method of depositing the metal M2 on the interface of the gate insulating film or forming an alloy of the metal M1 and the metal M2 is applied to the gate electrode of the N-type MIS transistor. However, the same method may be applied to the gate electrode of the P-type MIS transistor.

  According to the present embodiment, the work function of the portion in contact with the gate insulating film of the N-type MIS transistor can be made smaller than the work function of the portion in contact with the gate insulating film of the P-type MIS transistor. It is possible to optimize the threshold voltage of both transistors by optimizing the work function of the gate electrode of each MIS transistor. Further, in this embodiment, since the metal film formed in the gate electrode forming groove is not removed by etching as in the prior art, it is possible to suppress a decrease in reliability of the gate insulating film.

(Embodiment 3)
Hereinafter, an example of the manufacturing process of the first example according to the third embodiment of the present invention will be described with reference to FIGS. 15 (a) to 17 (h).

First, an element isolation 302 is formed on a silicon substrate 301. Subsequently, a P-type well diffusion layer 303 is formed in the N-type MIS transistor region, and an N-type well diffusion layer 304 is formed in the P-type MIS transistor region (FIG. 15 (a))
Next, the exposed surface of the silicon substrate 301 is oxidized by about 5 nm to form a silicon oxide film 305 to be a dummy insulating film. Thereafter, a polysilicon film 306 to be a dummy gate is deposited and patterned into a gate electrode shape. Subsequently, using the polysilicon film 306 serving as a dummy gate as a mask, arsenic is ion-implanted into the N-type region and boron is implanted into the P-type region, thereby forming a shallow impurity diffusion layer that becomes the source / drain diffusion layer 307. Thereafter, a silicon nitride film 308 is deposited and anisotropically etched to form a sidewall insulating film. Subsequently, using the sidewall insulating film 308 and the polysilicon film 306 as a mask, arsenic is ion-implanted into the N-type region and boron is ion-implanted into the P-type region, thereby forming a deep impurity diffusion layer that becomes the source / drain diffusion layer 309. (FIG. 15B).

  Next, a silicon oxide film is deposited as an interlayer insulating film 310 on the entire surface. Thereafter, the CMP method is used to planarize the silicon oxide film 310 until the polysilicon film 306 is exposed (FIG. 15C).

  Next, the polysilicon film 306 is removed using an isotropic etching technique such as chemical dry etching. Subsequently, the exposed silicon oxide film 305 is etched away by dilute hydrofluoric acid treatment or the like to form a groove 311 for forming a gate electrode in both the N-type and P-type MIS transistor regions (FIG. 16D).

Next, the silicon substrate 301 at the bottom of the gate electrode formation groove 311 is oxidized by thermal oxidation to form a gate insulating film made of the silicon oxide film 312. Subsequently, as a gate electrode material of the N-type MIS transistor, a tungsten silicide (WSi ₂ ) film 313 is deposited on the entire surface by a CVD method. Thereafter, the tungsten silicide film 313 deposited outside the trench 311 for gate electrode formation is removed by CMP, and the tungsten silicide film 313 is left only in the trench 311 for gate electrode formation (FIG. 16E). .

  Next, a silicon nitride film 314 is deposited on the entire surface, and the silicon nitride film 15 is left only in the N-type MIS transistor region by photolithography and etching techniques. Subsequently, a palladium (Pd) film 315 is deposited on the entire surface by sputtering or the like (FIG. 16F).

Next, annealing is performed at 600 ° C. for about 1 minute. As a result, the tungsten silicide film 313 embedded in the gate electrode portion of the P-type MIS transistor region reacts with the palladium film 315. As a result, a palladium silicide (Pd ₂ Si) film 316 is formed in the region where the tungsten silicide film 313 originally exists, and tungsten is discharged into the palladium film on the palladium silicide film 316. Since the silicon nitride film 314 is formed in the N-type MIS transistor region, the tungsten silicide film 313 is not replaced with the palladium silicide film 316. Thereafter, the metal and the silicon nitride film 314 remaining outside the trench for forming the gate electrode are removed by CMP or the like. Thereby, the gate electrode of the P-type MIS transistor is formed by the palladium silicide film 316 (FIG. 17G).

  Next, a silicon oxide film to be an interlayer insulating film 317 is deposited on the entire surface. Subsequently, contact holes reaching the source / drain and gate electrodes of the MIS transistor are formed in the interlayer insulating films 317 and 310. Thereafter, a metal film for the wiring 318 is deposited and patterned to complete N-type and P-type MIS transistor transistors (FIG. 17H).

In the above-described example, a tungsten silicide (WSi ₂ ) film is used as the gate electrode material of the N-type MIS transistor, but molybdenum silicide (MoSi ₂ ), tantalum silicide (TaSi ₂ ), niobium silicide is used instead of tungsten silicide. Silicides such as (NbSi ₂ ) or chromium silicide (CrSi ₂ ) can also be used.

In the above-described example, a palladium (Pd) film is formed on the tungsten silicide film in the P-type MIS transistor region, and the tungsten silicide is converted into palladium silicide (Pd ₂ Si, Pd ₂ Si, PdSi), but instead of palladium, nickel (Ni) or platinum (Pt) is used, and nickel silicide (NiSi, NiSi ₂ ) or platinum silicide (Pt ₂ Si, PtSi) or the like is substituted. It is also possible.

In the above-described examples (the same applies to the following second and third examples), a silicon oxide film obtained by heat treatment is used as the gate insulating film. However, a Ta ₂ O ₅ film formed by a CVD method or the like is used. May be used.

  Next, an example of a manufacturing process of the second example according to the third embodiment of the present invention will be described with reference to FIGS.

  In addition, since it is the same as that of the 1st example mentioned above until the process (process of FIG. 15 (a)-FIG.16 (e)) in the middle, in this example, about the process after the process of FIG.16 (e). explain.

After the step of FIG. 16E, the N-type MIS transistor region is masked with a resist 321 and then germanium ions (Ge ⁺ ) are selectively selectively applied only to the tungsten silicide film 313 in the P-type MIS transistor region by ion implantation. Ions are implanted to form a tungsten silicide film 313a containing germanium. At this time, the concentration of germanium ions introduced into the tungsten silicide film 313 is set to a concentration higher than the solid solubility limit of germanium in the tungsten silicide, for example, about 1 × 10 ¹⁷ cm ⁻³ (FIG. 18A).

Next, the P-type MIS transistor region is masked with a resist 322, and indium ions (In ⁺ ) are selectively ion-implanted only into the tungsten silicide film 313 in the N-type MIS transistor region by ion implantation. The silicide film 313b is used. At this time, the concentration of indium ions introduced into the tungsten silicide film 313 is set to a concentration higher than the solid solubility limit of indium in the tungsten silicide, for example, about 1 × 10 ¹⁷ cm ⁻³ (FIG. 18B).

  Next, by performing heat treatment at 800 ° C. for about 1 minute, germanium and indium implanted into the tungsten silicide film 313 are deposited at the interface between the tungsten silicide film 313 and the silicon oxide film 312 which is a gate insulating film. . As a result, the gate electrode is formed by the stacked structure of the germanium film 323 and the tungsten silicide film 313 in the P-type MIS transistor, and the gate electrode is formed by the stacked structure of the indium film 324 and the tungsten silicide film 313 in the N-type MIS transistor. FIG. 18 (c)).

  Finally, as in the first example, an N-type and P-type MIS transistors are completed by depositing an interlayer insulating film, opening a contact hole, and forming a wiring.

In the above-described example, a tungsten silicide (WSi ₂ ) film is used as a material to be formed in advance in the trench for the gate electrode, but molybdenum silicide (MoSi ₂ ), tantalum silicide ( It is also possible to use TaSi ₂ ), niobium silicide (NbSi ₂ ), or chromium silicide (CrSi ₂ ).

  In the above-described example, germanium (Ge) is used for the P-type MIS transistor and indium (In) is used for the N-type MIS transistor as the material to be deposited on the gate insulating film interface, but germanium, indium, antimony (Sb), An appropriate material may be selected from platinum (Pt), palladium (Pd), etc., and separate materials may be deposited by both P-type and N-type transistors. These materials are deposited only for one of the P-type and N-type transistors (ion implantation is performed only for one transistor), and the original gate electrode material (tungsten silicide in the above example) is used as it is for the other transistor. It may be used as a gate electrode.

  Furthermore, in the above-described example, the ion-implanted material is deposited on the gate insulating film interface by heat treatment. However, different materials are ion-implanted into the gate electrode regions of the P-type and N-type MIS transistors, and the ions are ionized by heat treatment. A reaction product of each of the implanted substances and the gate electrode material originally formed in the gate electrode region is formed, and the work function of the reaction product of the N-type MIS transistor is smaller than the work function of the reaction product of the P-type MIS transistor. You may do it.

  Next, an example of the manufacturing process of the third example according to the third embodiment of the present invention will be described with reference to FIGS. 19 (a) to 19 (c).

  In addition, since it is the same as that of the 1st example mentioned above until the process (process of Fig.15 (a)-FIG.16 (d)) in the middle, in this example, about the process after the process of FIG.16 (d). explain.

  After the step of FIG. 16E, a nickel (Ni) film 331 is buried in the gate electrode formation groove as a gate electrode material of the P-type MIS transistor by using sputtering and CMP (FIG. 19 a)).

  Next, after depositing an amorphous silicon (a-Si) film 332 on the entire surface by sputtering or the like, the amorphous silicon film 332 in a region other than on the N-type MIS transistor region is removed by using a photolithography method, a dry etching method, or the like. (FIG. 19B).

  Next, by applying heat treatment at 400 ° C. for about 1 minute, the nickel film 331 and the amorphous silicon film 332 are reacted in the gate electrode portion of the N-type MIS transistor region to form a nickel silicide (NiSi) film 333. Thereafter, the amorphous silicon film 332 that has not contributed to the reaction is removed by isotropic etching such as chemical dry etching. By changing the nickel film 331 to the nickel silicide film 333 in this way, the work function of the material can be lowered from about 5.0 eV to about 4.36 eV (FIG. 19C).

  Finally, as in the first example, an N-type and P-type MIS transistor transistor is completed by depositing an interlayer insulating film, opening a contact hole, and forming a wiring.

In the example described above, the gate electrode of the P-type MIS transistor is nickel (Ni) and the gate electrode of the N-type MIS transistor is nickel silicide (NiSi, NiSi ₂ ), but cobalt (Co) and cobalt silicide (CoSi _2). ), Chromium (Cr) and chromium silicide (CrSi ₂ ), molybdenum (Mo) and molybdenum silicide (MoSi ₂ ), or the like.

  According to the present embodiment, the work function of the portion in contact with the gate insulating film of the N-type MIS transistor can be made smaller than the work function of the portion in contact with the gate insulating film of the P-type MIS transistor. It is possible to optimize the threshold voltage of both transistors by optimizing the work function of the gate electrode of each MIS transistor. Further, in this embodiment, since the metal film formed in the gate electrode forming groove is not removed by etching as in the prior art, it is possible to suppress a decrease in reliability of the gate insulating film.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. The top view shown about the effect acquired by the manufacturing method of the semiconductor device concerning a 1st embodiment of the present invention. The figure which showed the inter-element distance dependence of the threshold value with respect to the prior art about the MIS transistor obtained by the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which showed typically an example of the basic composition of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which showed typically the other example of the basic composition of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which showed typically the other example of the basic composition of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which showed typically the other example of the basic composition of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure shown about the main manufacturing processes for obtaining the basic composition shown in FIG. Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Process sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Process sectional drawing which showed a part of the process about an example of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the process about an example of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the process about an example of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the process about the other example of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the process about the other example of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on a prior art. Sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on a prior art. Sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on a prior art. Sectional drawing which showed a part of the process about the manufacturing method of the semiconductor device which concerns on a prior art. The top view shown about the problem of the manufacturing method of the semiconductor device which concerns on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Silicon substrate 102 ... Element isolation 103 ... Silicon oxide film 104 ... Polysilicon film 105, 107 ... Silicon nitride film 106, 108 ... Source-drain diffused layer 109 ... Silicide film 110 ... Interlayer insulating film 111 ... Groove 112 ... Hafnium oxide Film 113 ... Hafnium nitride film 114 ... Resist 115 ... Cobalt film 201 ... Silicon substrate 202, 205, 206, 207 ... Silicon oxide film 203, 214 ... Silicon nitride film 204, 215 ... Resist 208 ... Polysilicon film 209 ... Source / drain diffusion layer 210, 218 ... interlayer insulating film 211 ... groove 212 ... Ta ₂ O ₅ film 213 ... Ru film or Pd film 216 ... an In film or Sn film 217 ... tungsten film 219 ... wiring 301 ... silicon substrate 302 ... isolation 303 ... P-type well 304 ... N-type wells 305, 312 ... Silicon oxide film 306 ... Polysilicon film 307, 309 ... Source / drain diffusion layer 308, 314 ... Silicon nitride film 310, 317 ... Interlayer insulating film 311 ... Groove 313 ... Tungsten silicide film 315 ... Palladium Film 316 ... Palladium silicide film 318 ... Wiring 321, 322 ... Resist 323 ... Germanium film 324 ... Indium film 331 ... Nickel film 332 ... Amorphous silicon film 333 ... Nickel silicide film

Claims (3)

A semiconductor device in which a gate electrode of each of an N-type MIS transistor and a P-type MIS transistor is formed through a gate insulating film in a recess formed in a semiconductor substrate,
One gate electrode of the N-type MIS transistor and the P-type MIS transistor is configured by a stacked structure of a first metal-containing film and a second metal-containing film on the first metal-containing film. The other gate electrode of the MIS transistor is configured by a stacked structure of a third metal-containing film and a second metal-containing film on the third metal-containing film, and is in contact with the gate insulating film of the N-type MIS transistor A semiconductor device characterized in that a work function of at least a portion in contact with the gate insulating film is smaller than a work function of at least a portion of the metal-containing film in contact with the gate insulating film of the P-type MIS transistor.   2. The semiconductor device according to claim 1, wherein the resistivity of the second metal-containing film is lower than the resistivity of the first metal-containing film and the resistivity of the third metal-containing film. A method of manufacturing a semiconductor device, wherein a gate electrode of each of an N-type MIS transistor and a P-type MIS transistor is formed in a recess formed in a semiconductor substrate via a gate insulating film, and the step of forming the gate electrode comprises:
A first metal-containing film is formed on the gate insulating film formed in the recesses in both the first gate formation region for the N-type MIS transistor and the second gate formation region for the P-type MIS transistor. Process,
Removing the first metal-containing film formed in one region of the first or second gate formation region;
A third metal-containing film is formed on the first metal-containing film left in the other region of the first or second gate formation region and on the gate insulating film in one region of the first or second gate formation region. Forming, and
Removing the third metal-containing film formed in the other region of the first or second gate formation region;
Second on the third metal-containing film left in one region of the first or second gate formation region and on the first metal-containing film exposed in the other region of the first or second gate formation region. And forming a recess in both the first and second gate formation regions by forming a metal-containing film of
Of the first and third metal-containing films, the work function of at least the portion of the metal-containing film that is in contact with the gate insulating film of the N-type MIS transistor is in contact with the gate insulating film of the P-type MIS transistor. A method of manufacturing a semiconductor device, wherein the work function of at least a portion of the metal-containing film in contact with the gate insulating film is smaller.

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