JP2008123543A - Data transmission method, system and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system by which a high-speed operation between a memory controller and a memory module can be achieved. <P>SOLUTION: In the memory system comprising the memory controller and a memory module mounted with DRAMs, a buffer is mounted on the memory module, the buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring, the DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and clock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules and to cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory system having a configuration capable of operating at high speed, and a data transmission method used in the memory system.

  Conventionally, in this type of memory system, an interface that operates at high speed and with a low signal amplitude has been studied, and SSTL (Stub Series Terminated Transceiver Logic) has been proposed as a standard for this interface. Further, in a memory system including a DRAM as a memory device, data is input / output in synchronization with both rising (leading edge) and falling (rear edge) clock edges in order to operate the DRAM at a higher speed. Thus, there has also been proposed a DDR (Double Data Rate) method that can double the data transmission rate.

  Conventionally, as a memory system adopting the SSTL and DDR described above, there has been proposed a memory system in which a plurality of memory modules are mounted on a motherboard and the plurality of memory modules are controlled by a memory controller called a chip set. In this case, a plurality of DRAMs are mounted on each memory module.

  As this type of memory system, Japanese Patent Laid-Open No. 2001-256772 (hereinafter referred to as Patent Document 1) discloses a memory system in which a plurality of memory modules having a plurality of DRAMs mounted on a motherboard. The disclosed memory module distributes a plurality of DRAMs arranged in parallel in the longitudinal direction of a rectangular memory module substrate, a command / address buffer arranged between the DRAMs, and a clock to each DRAM. PLL chip. Each DRAM on the memory module is connected to module data wiring extending in the short side direction of the module substrate, and the command / address buffer and PLL chip are respectively connected to module command / address wiring and module clock wiring extending in the short side direction of the module substrate. It is connected to the. Further, in order to distribute command addresses and clocks from the command address buffer and PLL chip to each DRAM, module command address distribution lines and module clock distribution lines are drawn out in the long side direction of the module substrate. .

  In this configuration, the data signal is directly supplied from the memory controller provided on the module substrate to the DRAM on each memory module, and the command / address signal and the clock signal are respectively sent from the memory controller to the command / address buffer and It is given to the DRAM on each memory module via a PLL chip. In the memory system using the above memory module, when a single memory module is considered, it is not necessary to form a branch wiring on the memory module with respect to the signal wiring on the mother board. There is an advantage that waveform disturbance due to signal reflection can be reduced. Furthermore, there is an advantage that the access time can be shortened.

  Japanese Patent Laid-Open No. 10-293635 (hereinafter referred to as Patent Document 2) discloses a memory system in which a memory controller and a plurality of memory modules are mounted on a motherboard. The disclosed memory system ensures the setup time and hold time of each memory module by aligning the propagation time of the clock signal and data signal output from the memory controller, and enables high-speed signal transfer. Further, in Patent Document 2, as a method of stably supplying a clock, a clock that is double the input clock is generated in a memory module or memory LSI, and the SDRAM signal and the clock are generated in synchronization with the generated clock. It also describes controlling the output. For this reason, the cited document 2 and FIG. 28 describe that a memory controller generates a clock with a frequency of 2φ, and divides the clock by 2 into a frequency φ and transmits it to the memory module.

  Patent Document 2 and FIG. 34 also describe that the clock frequency from the memory controller is doubled in the memory module and supplied to the memory of the memory module. As described above, in Patent Document 2, a clock having a predetermined frequency is transmitted and received between the memory controller and the memory module, and the clock having the predetermined frequency is doubled in a memory or a memory controller such as an SDRAM. Is disclosed. In other words, Patent Document 2 describes that a frequency lower than the clock frequency in the memory is transmitted and received between the memory module and the memory controller.

JP 2001-256772 A Japanese Patent Laid-Open No. 10-293635

  As in the memory module described in Patent Document 1, module data wiring extending in the short side direction on the module substrate, module command / address distribution wiring and module clock distribution drawn from the command / address buffer and PLL chip onto the DRAM, respectively Since the length is different from the wiring, the data reaches each DRAM at a different timing from the command address and the clock signal, and it is difficult to adjust the timing.

  Further, as in Patent Document 2, if a clock having a frequency lower than the clock frequency in the memory module is transmitted and received between the memory controller and the memory module, the data transfer time becomes long. Furthermore, in the configuration of Patent Document 2, since the data transfer speed cannot exceed the memory operation speed, there is a limit to the number of memory modules that can be increased in speed and mounted. Both references do not disclose any method for transmitting data at high speed between the memory controller and the memory module.

  An object of the present invention is to provide a memory system that can easily adjust the timing of data, command address, and clock signal in each memory module.

  Another object of the present invention is to provide a memory system capable of reducing reflected signals due to branching and impedance mismatch, and consequently operating at high speed.

  Still another object of the present invention is to provide a data transfer method capable of transferring data at high speed between two circuits provided in a module.

  A specific object of the present invention is to provide a data transfer method capable of transferring data at high speed between a buffer in a memory module and a DRAM.

  According to the present invention, it is possible to obtain a memory system in which a buffer having a predetermined function is mounted on a memory module, while a memory controller and a memory module and a point-to-point connection between the memory module and the memory module are obtained. According to this configuration, the signal quality at high frequency can be improved, and each signal wiring on the memory module between the buffer and the DRAM has only another branch that can be ignored electrically and has another branch that has an electrical influence. Connections can be made with no wiring layout, resulting in improved signal quality.

  Furthermore, according to the present invention, a higher-speed memory system can be realized by using a data transmission / reception method based on a bidirectional data phase signal on each memory module.

  Here, a single buffer or a plurality of buffers according to the present invention provided on the memory module will be described. Data wiring between the memory controller and the memory module and between the memory module and the memory module are connected to the buffer provided on the memory module in a grouped form. In a memory system including a plurality of memory modules, buffers on adjacent memory modules are connected to each other in a point-to-point manner by data lines. In this case, the data signal is transmitted onto the data line at an n-times speed with respect to the data frequency of the DRAM. Further, the number of data lines multiplexed by being compressed into packets is reduced to about 1 / n (it is not necessarily 1 / n because it may not be actually divisible).

  On the other hand, the command / address wiring is connected between the memory controller and the buffer of each memory module for each group of data wiring. Like the data wiring, the command / address wiring is connected between the memory controller and the memory module. Are connected to each other point-to-point. The command / address signal is transmitted at a speed of m times the command / address signal frequency of the DRAM, and when compressed into a packet, the number of signal lines is reduced to about 1 / m (in this case also, in practice) Is not necessarily 1 / m because it may not be divisible.)

  The buffer provided on each memory module receives data and command / address signals from the memory controller or the previous memory module, and encodes the data and command / address signal packets to the DRAM on the memory module. , The number of signals corresponding to the DRAM, and the function of transmitting at a frequency of 1 / n, 1 / m times. Further, the buffer has a function of transmitting and transmitting command / address signals to and from the cascaded next-stage memory modules, and a function of bidirectionally receiving and transmitting data signals to and from the next-stage memory modules. Each signal on the memory module is connected in a wiring layout having no branches other than electrical negligible branching. The packet transmission destination of the data and command / address signals is identified by the module ID signal.

  Hereafter, the aspect used as the characteristic of this invention is listed.

  According to the first aspect of the present invention, in a memory system including a module on which a plurality of memory circuits are mounted and a controller that controls the plurality of memory circuits, the module includes a data transmission unit and the controller. At least one buffer connected by data wiring is mounted, and in the module, a memory system is obtained in which the buffer and the plurality of memory circuits are connected by internal data wiring.

  According to a second aspect of the present invention, in the first aspect, the module includes a plurality of the buffers, and each of the plurality of buffers is connected to the controller through the data wiring. A memory system characterized by this can be obtained.

  According to a third aspect of the present invention, there is provided the memory system according to the first or second aspect, wherein the buffer is further connected to the controller by a command / address line and a clock line. can get.

  According to a fourth aspect of the present invention, in the third aspect, the buffer includes each memory circuit of the module by an internal command / address wiring and an internal clock wiring corresponding to the command / address wiring and the clock wiring, respectively. And a memory system characterized by being connected to each other.

  According to a fifth aspect of the present invention, there is provided the memory system according to the fourth aspect, wherein the internal command / address wiring and the internal clock wiring are commonly used for a plurality of memory circuits of the module. can get.

  According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the memory circuit is a DRAM, and the data line between the memory controller and the buffer is bidirectionally connected. A memory system is obtained in which data is transmitted and received.

  According to a seventh aspect of the present invention, in a memory system comprising a plurality of modules each having a plurality of memory circuits mounted thereon and a controller that controls each memory circuit of the plurality of modules, each module includes: At least one buffer is provided, and a buffer of each module is connected to a buffer of another module and / or the controller via a data wiring for data transmission, thereby obtaining a memory system.

  According to an eighth aspect of the present invention, in the seventh aspect, the buffer of each module is connected to a buffer of another module and / or the controller by a command / address wiring and a clock wiring. A memory system is obtained.

  According to a ninth aspect of the present invention, in the seventh or eighth aspect, the data wiring forms a daisy chain by cascading the buffers on the plurality of modules and the memory controller. Is obtained.

  According to a tenth aspect of the present invention, in the seventh aspect, there is provided a memory system, wherein each buffer of the plurality of modules is directly connected to the memory controller by the data wiring. It is done.

  According to an eleventh aspect of the present invention, in the tenth aspect, each buffer of the plurality of modules is further directly connected to the memory controller by a command / address line and a clock line. A memory system is obtained.

  According to a twelfth aspect of the present invention, in the eleventh aspect, with respect to the module buffer connected to the memory controller directly by the data wiring, the command / address wiring, and the clock wiring, A memory system having a buffer arranged on another module cascaded by data wiring, command / address wiring, and clock wiring is obtained.

  According to a thirteenth aspect of the present invention, in any one of the eighth to twelfth aspects, the plurality of memory circuits of each module are divided into a plurality of ranks, and the memories of the plurality of modules belonging to the same rank A memory system is obtained in which the circuits are simultaneously accessed.

  According to a fourteenth aspect of the present invention, in any one of the twelfth and thirteenth aspects, the data transmission speed on the data line is determined on an internal data line between the buffer on each module and each memory circuit. A memory system characterized by being faster than the data transmission rate is obtained.

  According to a fifteenth aspect of the present invention, in the fourteenth aspect, the transmission speeds on the command / address wiring and the clock wiring correspond to the command / address wiring and the clock wiring, respectively. A memory system characterized by being faster than the transmission speed between circuits is obtained.

  According to a sixteenth aspect of the present invention, in the fourteenth aspect, data for a buffer of a plurality of modules is packetized and transmitted to the data wiring, and the packetized data is separated in the buffer. Is obtained.

  According to a seventeenth aspect of the present invention, in the fifteenth aspect, the command address wiring and the clock wiring are packetized and transmitted with command addresses and clocks for buffers of a plurality of modules. A memory system having a function of separating the command and address and dividing the clock is obtained.

  According to an eighteenth aspect of the present invention, a module including a buffer and a memory circuit connected to the buffer, and a memory controller connected to the buffer on the module, the memory controller and the buffer are provided. The memory system is characterized in that the transmission speed between the two is higher than the transmission speed between the buffer on the module and the memory circuit connected to the buffer.

  According to a nineteenth aspect of the present invention, in the eighteenth aspect, a plurality of modules having the buffer are arranged, and the buffer of each module is sequentially connected to the memory controller by data wiring, Cascade connection is performed by command / address wiring and clock wiring, and in each module, the memory circuit and the buffer are connected by internal data wiring, internal command / address wiring and internal clock wiring, and the data A memory system characterized in that the transmission speed on the wiring, command / address wiring, and clock wiring is faster than the transmission speed on the internal data wiring, internal command / address wiring, and internal clock wiring. .

  According to a twentieth aspect of the present invention, in the nineteenth aspect, the memory circuit mounted on each module is a DRAM, and on each module, the buffer between the module and the DRAM is located. The data phase signal is transmitted bidirectionally at a timing that does not collide with each other, and the DRAM and the buffer generate an internal clock based on the received data phase signal, and receive and transmit data according to the internal clock. A memory system can be obtained.

  According to a twenty-first aspect of the present invention, there is provided a first device that receives data according to a first internal clock, and a second device that receives data according to a second internal clock, In the data transmission method for bidirectionally transmitting and receiving data between the first and second devices, the first and second devices are continuously connected to the first and second devices on the same wiring at timings that do not collide with each other. The second data phase signal is transmitted in both directions, and the first device refers to the timing of the first data phase signal to transmit data to the second device, while the second device In the device, there is obtained a data transmission method characterized by transmitting data to the first device with reference to the timing of the second data phase signal.

  According to a twenty-second aspect of the present invention, in the twenty-first aspect, the second device generates the second internal clock according to the received first data phase signal, and generates the second internal clock. The first device receives data from the first device according to a clock, while the first device generates the first internal clock according to the received second data phase signal, According to the clock, the data transmission method is characterized in that the second data phase signal is generated and the data from the second device is received.

  According to a twenty-third aspect of the present invention, in the twenty-first or twenty-second aspect, among the first and second data phase signals transmitted bi-directionally, the first device starts from the first device. The second data device suppresses the first data phase signal to be output, while the second device outputs the first data phase signal transmitted from the second device out of the first and second data phase signals transmitted in both directions. A data transmission method characterized by suppressing two data phase signals is obtained.

  According to a twenty-fourth aspect of the present invention, in any one of the twenty-first to twenty-third aspects, the first and second devices are a buffer and a DRAM, respectively, and an external clock is applied to the DRAM. Thus, the data transmission method is characterized in that the second clock is generated by the external clock and the received first data phase signal.

  According to a twenty-fifth aspect of the present invention, in any one of the twenty-first to twenty-third aspects, the first and second devices use a DLL to determine the second and first data phase signals from the second and first data phase signals. A data transmission method characterized by generating the first and second internal clocks is obtained.

  According to a twenty-sixth aspect of the present invention, in the data transmission system that transmits and receives data to and from the first and second devices, the transmitting side of the first and second devices transmits the data. And means for continuously transmitting a data phase signal representing a predetermined phase of the data irrespective of the transmission of the data, and the receiving side of the first and second devices includes the data phase signal. Based on this, there is provided a data transmission system comprising means for regenerating the internal clock on the receiving side and receiving the data in accordance with the regenerated internal clock.

  According to a twenty-seventh aspect of the present invention, in a data transmission system that transmits and receives data bidirectionally between the first and second devices, each of the first and second devices includes the data A transmission means for transmitting a data phase signal representing a predetermined phase of the data continuously, regardless of the transmission of the data, and transmitting the data based on the data phase; Each of the first and second devices includes receiving means for regenerating the internal clock on the receiving side based on the data phase signal and receiving the data according to the regenerated internal clock. A data transmission system is obtained.

  According to a twenty-eighth aspect of the present invention, in the twenty-seventh aspect, the first and second devices are a buffer and a DRAM, respectively, and the transmission means of the buffer uses the DRAM as the data phase signal. On the other hand, the buffer has a means for outputting a write data phase signal, and the receiving means for the buffer has means for receiving a read data phase signal from the DRAM as the data phase signal. Receiving means comprises means for regenerating the internal clock for receiving the data from the write data phase signal, and means for receiving the data in accordance with the regenerated internal clock, and further comprising the DRAM The transmission means outputs the data phase signal at a timing depending on the received write data phase signal. The data transmission system, characterized in that it has a means for outputting the read data phase signal is obtained.

  According to a twenty-ninth aspect of the present invention, in the twenty-eighth aspect, the write data phase signal and the read data phase signal are transmitted bi-directionally on the same signal line at different timings. A characteristic data transmission system is obtained.

  According to a thirtieth aspect of the present invention, in the twenty-eighth aspect, the write data phase signal and the read data phase signal are transmitted on different signal lines in both directions at different timings. A characteristic data transmission system is obtained.

  According to a thirty-first aspect of the present invention, in any of the twenty-eighth to thirty-third aspects, the read data phase signal receiving means of the buffer has a data reception buffer internal circuit based on a buffer internal clock and the read data phase signal. Means for regenerating the clock, and on the other hand, the read data phase signal output means of the DRAM reproduces the DRAM internal clock that outputs the read data phase signal from the external clock and the received write data phase signal A data transmission system characterized by having:

  In order to increase the speed of the above-described memory system, it is preferable to adopt the following configuration in consideration of skew on each memory module.

  That is, according to an aspect of the present invention, a plurality of memory circuits and a buffer are provided, a command / address signal is transmitted from the buffer to the plurality of memory circuits, and between the buffer and the plurality of memory circuits. In the memory module, a data signal accompanying the command / address signal is transmitted / received, and at least one of the plurality of memory circuits and the buffer includes the memory between the command / address signal and the data signal. A memory module including skew absorbing means for absorbing timing skew generated depending on a circuit mounting position can be obtained. When the memory circuit is a DRAM, the command / address signal is preferably output in alignment with a buffer clock output from the buffer to the memory circuit.

  In the case of adopting such a configuration, the skew absorbing means is provided in each of the plurality of memory circuits and buffers, and the data signal is aligned with a data phase signal representing the phase of the data signal, and the plurality of DRAMs and It is preferably sent and received between buffers.

  In this case, when the DRAM receives a command / address signal from the buffer in alignment with the buffer clock and further receives a write data phase signal (WDPS) from the buffer as the data phase signal, the DRAM The skew absorbing means includes means for generating a plurality of phase clocks for receiving the command / address signal from the buffer clock, means for generating a data reception DRAM internal phase clock from the WDPS, and matching with the phase clock. It is preferable to provide means for domain crossing the received command / address signal to the internal phase clock of the data receiving DRAM for transfer.

  On the other hand, the DRAM outputs a read data phase signal (RDPS) as the data phase signal to the buffer based on the WDPS, and the skew absorbing means of the buffer receives a data reception buffer from the RDPS received from the DRAM. Means for generating an internal phase clock; means for generating a buffer internal phase clock based on the WDPS; and means for superposing a read data signal input in conformity with the RDPS on the buffer internal phase clock. Yes.

  According to another aspect of the present invention, a write data phase signal (WDPS) is supplied from the buffer as the data phase signal to the DRAM, and a data signal is input in conformity with the WDPS. The DRAM skew absorbing means is a means for generating a data reception DRAM internal phase clock from the WDPS, a means for generating a plurality of phase clocks from the buffer clock, and a data reception DRAM internal phase clock in conformity with the reception. There is obtained a memory module comprising means for performing a domain crossing on the plurality of phase signals to the plurality of phase clocks and transferring them.

  Here, when the DRAM outputs a read data phase signal (RDPS) based on the buffer clock, the skew absorbing means of the buffer generates a data reception buffer internal phase clock based on the RDPS; A means for generating a buffer internal phase clock based on the global clock; and a domain crossing that replaces the data signal read from the DRAM and received in accordance with the data reception buffer internal phase clock on the buffer internal phase clock. It is preferable to include means for performing.

  According to still another aspect of the present invention, a plurality of memory circuits and a buffer are provided, a command / address signal is transmitted from the buffer to the plurality of memory circuits, and the buffer and the plurality of memory circuits are A memory module to which a data signal accompanying the command / address signal is transmitted / received, and the data signal is transmitted / received to / from the plurality of memory circuits and buffers in conformity with a data phase signal, and The buffer is provided with a memory module and means for outputting a control signal for defining a transmission time of the data phase signal in the buffer.

  In the present invention, the memory controller and the module are mounted with a buffer along with the memory circuit, and wiring including data wiring with the memory circuit on the module is performed via the buffer, and wiring including the data wiring is performed. Since the wirings need not be branched for each module, reflection due to impedance mismatching can be prevented, and a system capable of operating at high speed at high frequency can be obtained. According to the present invention, the number of modules connected to the memory controller can be increased by making the transmission speed between the memory module and the buffer faster than the transmission speed between the buffer and the memory circuit, and A system independent of the writing / reading speed of the memory circuit can be configured.

  In one embodiment of the present invention, not only the data wiring but also the clock and command / address wiring are connected from the memory controller to the buffer on each module, so that each memory circuit mounted on the module and the memory controller are connected. Since the distances can be made substantially equal, a difference in timing due to a difference in delay time for each wiring can be eliminated. According to another embodiment of the present invention, a load applied to each buffer and wiring can be distributed by providing a plurality of buffers for each module and connecting each of the buffers to a memory circuit in the module. Further, according to another embodiment of the present invention, the number of buffers can be reduced by arranging the memory circuits selected simultaneously in a plurality of modules and wiring the buffers of each module individually with the memory modules. The load applied to each buffer can be distributed without increasing it.

  Referring to FIGS. 1 and 2, there are shown a wiring diagram and an entity diagram of a memory system according to the first embodiment of the present invention, respectively. Further, FIG. 3 shows a partial cross-sectional view of the memory system for explaining the wiring in a part of FIGS. 1 and 2 in detail.

  As is clear from FIG. 2, the memory system according to the first embodiment of the present invention includes a memory controller 101 and a clock generator 102 (FIG. 1) mounted on a motherboard 100. A plurality of memory modules 103 (four memory modules 103a, 103b, 103c, and 103d in FIGS. 2 and 3) are mounted on the motherboard 100 via module connectors 104 (FIG. 3), respectively.

  Each memory module 103 (subscript omitted) includes a buffer 105 mounted on the module substrate and a plurality of DRAMs 110 as shown in FIGS. In the illustrated example, one buffer 105 is arranged for each memory module 103. The memory controller 101 and the buffer 105 include a data wiring (DQ) 111, a command / address wiring (Cmd / Add) 112, and They are connected by a clock wiring (CLK / CLKB) 113. As is clear from this, the data wiring 111 shown in FIGS. 1 and 2 is not directly connected to each DRAM 110 but is connected to the memory controller 101 via the buffer 105.

  These data wiring 111, command / address wiring 112, and clock wiring (CLK / CLKB) 113 are connected from the memory controller 101 to the buffer 105 of the memory module 103a as shown in FIG. 103a is connected to the buffer 105 of the next-stage memory module 103b. Hereinafter, similarly, these wirings are sequentially connected to the buffer 105 of the memory modules 103c and 103d, and the termination is terminated by a termination resistor, thereby forming a daisy chain. In other words, the wiring such as the data wiring 111 is provided between the memory controller 101 and the memory module 103a, between the memory modules 103a and 103b, between the memory modules 103b and 103c, and between the memory modules 103c and 103d. And is cascade-connected in a point-to-point manner with respect to the previous stage and next stage buffers 105.

  As shown in FIG. 2, the data wiring (DQ) 111, the command / address wiring (Cmd / Add) 112, and the clock wiring 113 are respectively connected to the wiring portion on the motherboard and the module wiring portion in the module. Can be classified. Further, in the illustrated memory system, module identification wiring 114 for transmitting a module identification signal MID for identifying each of the memory modules 103 a to 103 d is also provided between the memory controller 101 and the buffer 105 and between the buffers 105. .

  As shown in FIG. 1, the buffer 105 in each memory module 103 and the DRAM 110 mounted in the memory module 103 include an internal data wiring 111 ′, an internal command / address wiring 112 ′, and an internal clock wiring 113. Connected by '. Here, the internal data wiring 111 ′ is individually connected to the DRAM 110 on the memory module 103, while the internal command / address wiring 112 ′ and the internal clock wiring 113 ′ are respectively connected to the left side of the buffer 105 or It is provided in common for the DRAM 110 arranged on the right side.

  Next, it is assumed that the illustrated DRAM 110 is a DRAM of × 8 configuration capable of writing and reading data in units of 8 bits. In each memory module 103, each DRAM 110 and buffer 105 In between, data is transmitted and received in units of 8 bits.

  The memory system shown in the figure will be described in more detail. Each of the memory modules 103a and 103b includes eight DRAMs 110, and these eight DRAMs 110 are provided on the left and right sides of the buffer 105 of each of the memory modules 103a and 103b. , Four each are arranged. Further, the data wiring 111 between the memory controller 101 and the buffer 105 and between the buffers 105 has a 32-bit width. When one of the memory modules 103a and 103b is selected by the command / address signal and the module identification signal MID, for example, the selected eight DRAMs 110 on the memory module 103a are activated, and data having a total 64-bit width is obtained. The eight DRAMs 110 and the buffer 105 are ready for transmission / reception.

  On the other hand, when the DRAM 110 indicated by the broken line in FIG. 1 and FIG. 2 is added to each memory module 103, four DRAMs 110 are arranged on the left side of the buffer 105 and five DRAMs are arranged on the right side. The data wiring 111 between the buffer 105 and the buffer 105 has a 36-bit width. In this configuration, when one of the memory modules 103a and 103b is selected by the command / address signal and the module identification signal MID, the selected nine DRAMs 110 on the memory module 103a are activated, for a total of 72 bits. The width data can be transmitted and received between the nine DRAMs 110 and the buffer 105.

  Thus, it can be seen that in the memory system shown in FIGS. 1 and 2, eight or nine DRAMs 110 on each of the memory modules 103a and 103b form a rank that can be accessed simultaneously.

  Next, the wiring between the memory controller 101 and the memory module 103a and the wiring between adjacent memory modules 103 will be further described with reference to FIGS. First, the data wiring 111 will be described. Even though 64-bit or 72-bit data is transmitted / received between the buffer 105 and the DRAM 110 via the internal wiring 111 ′, between the memory controller 101 and the buffer 105, and As shown in FIGS. 1 and 2, the data wiring 111 between the buffers 105 has a 32-bit width or a 36-bit width.

  This means that a data signal is transmitted / received on the data wiring 111 by being multiplexed or compressed into packets at a data frequency of the DRAM 110, that is, at a transmission speed higher than the operation speed. In the illustrated example, data is transmitted on the data wiring 111 at a speed n times the operation speed of the DRAM 110 (where n is a positive integer). In this way, when compressed into packets, the number of data lines is reduced to about 1 / n (not necessarily 1 / n because there are cases where it is not actually divisible).

  On the other hand, the command / address wiring 112 performs point-to-point connection between the memory controller 101 and the memory module 103 and between adjacent memory modules 103 in the same manner as the data wiring 111. A command / address signal is transmitted to the command / address wiring 112 at a speed m times the command / address signal frequency of the DRAM 110 (m is a positive integer). The number of lines is reduced to about 1 / m (also in this case, it is not always 1 / m because it may not be actually divisible).

  A buffer 105 provided on each memory module 103 receives data and command / address signals from the memory controller 101 or the preceding memory module 103, and sends data, command / address signals to the DRAM 110 on each memory module 103. It has a function of encoding an address signal packet to obtain the number of signals corresponding to the DRAM. The buffer 105 has a function of dividing the encoded data and the command / address signal into 1 / n and 1 / m times the frequency and transmitting them to the DRAM 110.

  Further, the buffer 105 transmits and transmits a command / address signal to and from the cascaded next-stage memory module 103, receives and transmits the next-stage memory module and data signals in both directions, and data and commands. A function of identifying a module identification signal MID representing a packet transmission destination of the address signal is also provided. Functions such as frequency division and identification in the buffer 105 can be easily realized by using a normal technique, and will not be described in detail here. In any case, each wiring on the memory module 103 is connected in a wiring layout having no other branch than can be ignored electrically.

  Next, a specific example of the transmission rate in each wiring will be described with reference to FIG. First, it is assumed that the DRAM 110 on each memory module 103 is an SDRAM and adopts a DDR (Double Data Rate) system that inputs and outputs data in synchronization with both the leading edge and the trailing edge of the clock. To do. Furthermore, assuming that an internal clock frequency of 666 MHz is provided on the internal clock wiring 113 ′ between the buffer 105 and each DRAM 110 in each memory module 103, a data transmission rate of 1.33 Gbps is provided on the internal data wiring 111 ′. That is, data is transmitted and received at a data frequency of 1.33 GHz, and a command / address signal of 666 Mbps is supplied from the buffer 105 to the internal command / address wiring 112 ′.

  In this example, it is assumed that a clock 113 having a clock frequency of 1.33 GHz obtained by multiplying the internal clock frequency by 2 is supplied from the memory controller 101 to the clock wiring 113 wired on the motherboard 100. As shown in FIG. 2, data and command / address signals are supplied to the data wiring 111 and the command / address wiring 112 at a transmission speed of 2.66 Gbps equal to twice the clock frequency, and the internal data wiring The transmission speeds of 111 'and internal command / address wiring 112' are 1.33 Gbps and 666 Mbps, respectively. Therefore, it can be seen that the example shown is for n = 2 and m = 4.

  Thus, the number of wirings on the mother board can be reduced by multiplexing signals on the mother board and performing high-frequency transmission. The data wiring 111 can be reduced to ½ by duplicating the signal, and the command / address wiring 112 can be reduced to ¼ by quadrupling the signal. Further, by duplicating data, a 32-bit data wiring (or 36-bit data wiring) can be operated as a memory system having a 64-bit (or 72-bit) configuration.

  The memory system shown in FIGS. 1 to 3 requires a layout configuration for inputting / outputting 32 or 36-bit data signals to / from the buffer 105 from the module connector 104 (FIG. 3). As described above, the internal data wiring 111 ′, the internal clock wiring 113 ′, and the command / address wiring 112 ′ on the memory module 103 are connected with a wiring layout that has no branches other than electrical negligible branching. Since the number of DRAMs connected to the internal data wiring 111 ′, the internal clock wiring 113 ′ and the command / address wiring 112 ′ are different from each other, a difference in signal propagation time due to a difference in load becomes a problem during high frequency operation. Is also possible. As is clear from FIGS. 1 and 2, since the clock and command / address signals are applied to all DRAMs 110 on each memory module 103, the total input load is large, and problems may occur during high-frequency operation. Conceivable.

  Referring to FIGS. 4 and 5, the memory system according to the second embodiment of the present invention has a configuration that can alleviate the problem according to the first embodiment described above. The illustrated memory system is different from the memory system according to the first embodiment in that each of the memory modules 103a to 103d (FIG. 5) includes two buffers 105a and 105b. More specifically, the buffers 105a and 105b of the memory modules 103a and 103b include a plurality of DRAMs 110a arranged on the left and right sides thereof, an internal data wiring (DQ) 111 ′, an internal command / address wiring 112 ′, and an internal They are connected by a clock wiring 113 ′.

  In the illustrated example, the DRAM 110a in each memory module 103 is individually connected to the buffer 105a or 105b by an internal data wiring (DQ) 111 ′, and further by an internal command / address wiring 112 ′ and an internal clock wiring 113 ′. Are connected in common to the left and right of the buffer 105a or 105b.

  Further, the buffers 105 a and 105 b in each memory module 103 are constituted by the memory controller 101 or the next stage memory module, the data wiring 111, the command / address wiring 112, and the clock wiring 113, as in the first embodiment. It is connected. This configuration is the same as the connection relation shown in FIG. 3, and as a result, the buffers 105a and 105b of each memory module 103 are point-to-point with the buffers 105a and 105b of the other memory modules 103, respectively. It is connected. That is, the data wiring 111, the command / address wiring 112, and the clock wiring 113 are sequentially cascade-connected to the next-stage buffers 105a and 105b to form a daisy chain.

  In the example shown in FIG. 5, a DRAM 110a having a × 8 configuration for inputting / outputting data in units of 8 bits is mounted on each memory module 103, and each DRAM 110a has a clock frequency given via an internal clock wiring 113 ′. Input / output operation is performed according to a 666 MHz clock. As a result, a command / address signal and data are transmitted to the internal command / address wiring 112 ′ and the internal data wiring 111 ′ at transmission rates of 666 MHz and 1.33 GHz, respectively.

  On the other hand, the memory controller 101 and the buffers 105a and 105b of the memory module 103a are connected by a data line 111, a command / address line 112, a clock line 113, and a module identification line 114. Further, these wirings extend to the buffers 105a and 105b of the next-stage memory module 103b, and are further connected to the buffers 105a and 105b of the memory modules 103c and 103d shown at the rear of FIG. As described above, the data wiring 111 is connected to the two buffers 105a and 105b together with the command / address wiring 112 and the clock wiring 113 in a concentrated manner, that is, in groups.

  In FIG. 5, a clock having a frequency of 1.33 GHz is applied to the clock wiring 113, and a command / address signal and data are transmitted to the command / address wiring 112 and the data wiring 111 at a transmission speed of 2.66 Gbps. Input / output. Therefore, each of the buffers 105a and 105b parallelizes the clock, command address signal, and data from the memory controller 101 into 2 or 4 signals, thereby converting the internal clock, the internal command address signal, and the internal data. It can be seen that it can be generated.

  In this configuration, by simultaneously operating the buffers 105a and 105b of each memory module 103, a memory system that inputs / outputs data with a 32-bit width or a 36-bit width is configured as in the first embodiment. Can do. In the case of a memory system that transmits and receives 32-bit width data, two x8 DRAMs 110a are arranged on both sides of each of the buffers 105a and 105b of the memory module 103. When each memory module 103 is selected, both buffers 105a and 105b activate a total of eight DRAMs 110a on each memory module 103, and 64-bit data can be transmitted and received between the buffers 105a and 105b and the eight DRAMs 110a. In the illustrated example, the memory controller 101 and the buffers 105a and 105b are each connected by a data wiring 111 having a 16-bit width, and the data wiring 111 is also connected to a buffer of a memory module arranged behind. . As is clear from this, data is multiplexed and transmitted on the data wiring 111 as in the first embodiment.

  On the other hand, in a memory system that transmits and receives data with a 36-bit width, data with a 72-bit width can be transmitted and received between the nine DRAMs 110a and the buffers 105a and 105b on each memory module 103. In the example shown in FIG. 5, 40-bit width data is transmitted and received between the buffer 105a and the five DRAMs 110a arranged on the left and right of the buffer 105a. 32-bit width data is transmitted to and received from the arranged DRAM 110a.

  In this case, the data wiring 111 between the memory controller 101 and the buffer 105a and the data wiring 111 between the memory controller 101 and the buffer 105b have a 20-bit width and a 16-bit width, respectively. In the same manner as in the first embodiment, the multiplexed command, that is, the data compressed in the packet and the command address signal are transmitted and received on the command / address wiring 112.

  The illustrated memory system can halve the number of DRAMs 110a driven by the buffers 105a and 105b compared to the first embodiment, and can reduce the number of wires in the buffers 105a and 105b on the memory module 103. The wiring length can be shortened. Further, since the number of DRAMs 110a serving as loads for the buffers 105a and 105b can be reduced, the difference in input load between the internal data wiring 111 ′, the internal command / address wiring 112 ′ and the internal clock wiring 113 ′ can be reduced, and high frequency operation A memory system suitable for the above can be configured.

  In the memory system shown in FIG. 4, in a memory system that transmits and receives 36-bit width data between the memory controller 101 and the buffers 105a and 105b, as shown in FIG. It goes without saying that the DRAM 110a connected is connected.

  The memory system according to the second embodiment shown in FIGS. 4 and 5 can be variously modified. For example, as a DRAM arranged on both sides of two buffers, a × 4 configuration DRAM that inputs and outputs data in units of 4 bits or a × 16 configuration DRAM that transmits and receives data in units of 16 bits is used. Also good. The present invention can be applied not only to a memory system in which a DRAM is arranged on only one surface of a module substrate of each memory module, but also to a memory system in which a DRAM is arranged on the front and back. Furthermore, the present invention can be similarly applied to a system in which a plurality of DRAMs arranged in each memory module are divided into a plurality of ranks.

  In the memory system according to the above-described embodiment, since the command / address signal given to each memory module is individually given to a plurality of buffers, the number of pins for the command / address signal is the number of buffers, Since the command address signal is multiplexed, the increase is not large.

  Referring to FIG. 6, an example of a memory system according to the third embodiment of the present invention is shown. The illustrated memory system has a configuration in which the number of internal data wirings between the module connector 104 (FIG. 3) and the buffers can be reduced without increasing the number of buffers in each memory module. More specifically, the memory system shown in FIG. 6 includes a memory controller 101 and a plurality of memory modules 103 (only 103a and 103b are shown in the figure). 16 DRAMs 110 (subscript omitted) are mounted on the front and back of each. It is assumed that the illustrated DRAM 110 is a DRAM of x8 configuration in which writing and reading are performed in units of 8 bits. Further, buffers 105 (11) and 105 (21) are respectively arranged in the centers of the memory modules 103a and 103b. Among them, the buffer 105 (11) includes a 16-bit data wiring (DQ) 111, a command / address wiring (Cmd / Add) 112, a clock wiring (CLK) 113, and a module identification wiring (MID) 114. On the other hand, similarly to the buffer 105 (21), a 16-bit width data wiring (DQ) 111, a command / address wiring (Cmd / Add) 112, a clock wiring (CLK) 113, and Module identification wiring (MID) 114 is connected. The above-described wirings of the buffers 105 (11) and 105 (21) are connected to a buffer of a memory module (not shown) to form a daisy chain.

  In this embodiment, a total of 32 DRAMs 110 in the two memory modules 103a and 103b are grouped into 8 DRAMs, respectively, and operate as ranks 1 to 4. In this relationship, wiring from the buffers 105 (11) and 105 (21) to the DRAM 110 in the memory modules 103a and 103b is wired in common to the corresponding DRAMs 110 on the front and back of the memory modules 103a and 103b. , 103b are connected to each other, and connected to the same DQ terminal of each of the buffers 105 (11) and 105 (21). That is, the DRAMs 110 used for ranks 1 and 3 and ranks 2 and 4 are located on the front and back sides of the memory modules 103a and 103b, and the DRAM of the same rank is activated by the address bits for selecting the ranks. The In view of this, in FIG. 6, the DRAM 110 belonging to rank 1 is given the subscript r1, and the DRAMs 110 of ranks 2 to 4 are similarly characterized by r2 to r4.

  In this configuration, when the rank 1 DRAM 110 is operated, if four DRAMs 110r1 of the memory modules 103a and 103b are selected, the buffers 105 (11) and 105 (21) and the DRAM 110r1 of the memory modules 103a and 103b are selected. In this state, 32-bit width data is transmitted and received via the internal data wiring 111 ′. In this state, the buffers 105 (11) and 105 (21) are each connected to the memory controller 101 by the data wiring 111 having a 16-bit width, and transmit / receive data to / from the memory controller 101 as a total of 32-bit data wiring. Become.

  In this way, the two memory modules 103a and 103b are set as one group to form four ranks, and the wirings in the memory modules 103a and 103b of rank 1 and rank 3, and rank 2 and rank 4 are shared. Therefore, the number of wirings in the memory modules 103a and 103b can be reduced.

  Here, the memory system shown in FIG. 6 includes the buffers 105 (11) and 105 (21) that are directly connected to the memory controller 101, respectively, and therefore the memory system according to the first embodiment. The memory according to the second embodiment is different in that the single buffers 105 (11) and 105 (21) of each of the memory modules 103a and 103b are connected by a data wiring 111 having a 16-bit width. It is also different from the system.

  Further, in the configuration shown in FIG. 6, a chip select signal (CS) is used to identify ranks 1 to 4, but a bit for identifying ranks 1 to 4 may be added separately. good.

  Next, the operation of the memory system shown in FIG. 6 will be described. When one command / address signal is output from the memory controller 101, the command / address signal is, in this example, two memory modules 103a, 103b. In this case, it goes without saying that the command / address signal is output from the memory controller 101 in synchronization with the clock. By the command / address signal, eight DRAMs in the same rank in the two memory modules 103a and 103b, for example, the DRAM 110r1 in rank 1 are activated, and the activated eight DRAMs 110r1 and the two memory modules 103a, Data write and read operations are performed with respect to 103b. In this case, the four DRAMs 110r1 on the memory module 103a are activated, and 32-bit width data can be transmitted to and received from the buffer 105 (11), while the four DRAMs 110r1 on the memory module 103b are available. Is activated, and 32-bit width data can be transmitted to and received from the buffer 105 (21).

  Since the buffers 105 (11) and 105 (21) are connected to the memory controller 101 by the data wiring 111 having a 16-bit width, respectively, between the memory controller 101 and each of the buffers 105 (11) and 105 (21). The data is multiplexed and transmitted in the same manner as in the above-described embodiment.

  A daisy chain can be configured by connecting buffers of other memory modules (not shown) to the buffers 105 (11) and 105 (21) provided in the memory modules 103a and 103b, respectively. Therefore, the buffer of the illustrated memory system can be represented by 105 (12 to 1k) and 105 (22 to 2k) (where k is a positive integer of 3 or more). As is apparent from this, the memory modules of the illustrated memory system can be added as necessary.

  In the memory system according to the third embodiment shown in FIG. 6, when the same DRAM 110 as that of the memory system according to the first embodiment is provided, the rank number of the DRAM 110 is increased from 2 to 4. In this embodiment, since the DRAM in each memory module has a rank configuration, the wiring in each memory module can be shared, so the degree of freedom in layout on each memory module 103 is increased, and the buffer chip There is an advantage that the number can be reduced as compared with the second embodiment. Further, as shown in FIG. 6, the data from the memory controller 101 is directly supplied to the buffer 105 (21) of the memory module 103b without passing through another buffer to the memory module 103b. Therefore, as compared with the memory systems according to the first and second embodiments that transmit and receive data via the two buffers 105, the logic delay due to the buffers can be reduced.

  FIG. 7 shows a modification of the memory system according to the third embodiment of the present invention. This memory system is composed of only two memory modules 103a and 103b, and is a memory system that does not consider the addition of memory modules. In this example, the buffers 105 respectively installed in the memory modules 103a and 103b do not form a daisy chain with respect to other memory modules, and are terminated by a terminating resistor. In other words, in the illustrated example, there is no other cascaded memory module, so the buffers of the memory modules 103a and 103b in FIG. 7 are denoted by reference numerals 105 (1) and 105 (2), respectively. It is shown. However, the 16 DRAMs 110 provided on the front and back of each memory module 103a, 103b are divided into four ranks, and each of the memory modules 103a, 103b in rank 1 and rank 3, and rank 2 and rank 4 respectively. The common wiring is the same as in FIG.

  Referring to FIG. 8, another modification of the memory system according to the third embodiment of the present invention is shown. This modification has four memory modules 103a to 103d each having a single buffer 105, and the buffers 105 (1) to (4) (buffers 105 (3) and 105 (4) of these memory modules are 6 is different from the memory system of FIGS. 6 and 7 in that it is directly connected to the memory controller 101. For this reason, each buffer 105 of the memory system shown in FIG. 8 is connected to the memory controller 101 by the number of data lines corresponding to one-fourth of the 32-bit width, and on each of the memory modules 103a to 103d. The DRAM 110 having the × 8 configuration is divided into 8 ranks, and thereby the degree of freedom in layout of the memory modules 103a to 103d can be improved.

  As described above, in the present embodiment, the four memory modules 103a to 103d are combined into a set of eight ranks. Sixteen DRAMs 110 are mounted in each of the memory modules 103a to 103d, and the four DRAMs arranged in the table on the right side of each memory module are ranks 1 to 4, respectively, and four DRAMs arranged on the back side on the right side. DRAMs are configured as ranks 5 to 8, respectively, four DRAMs arranged in the left side table are arranged as ranks 1 to 4, and four DRAMs arranged on the left side back are arranged as ranks 5 to 8, respectively. Rank 1 and rank 5, rank 2 and rank 6, rank 3 and 7, rank 4 and rank 8 are at corresponding positions on the front and back of the memory module, and the wiring from each buffer 105 (1) to (4) to the DRAM is Common and connected by vias. When the memory system shown in FIG. 8 is compared with the embodiment shown in FIG. 6, the data wiring to each memory module 103 (a)-(d) of the memory system shown in FIG. 6 differs from FIG. 6 in that the memory system as a whole has 32-bit data wiring.

  As described above, the DRAMs 110 of the memory modules 103a and 103b are divided into eight ranks. In order to clarify this, in FIG. 8, the DRAMs 110 of ranks 1 to 8 are denoted by reference numerals 110r1 to 110r8, respectively. Show.

  In this configuration, when an address signal is given as a command / address signal (Cmd / Add) from the memory controller 101, two DRAMs 110r1 of the same rank, for example, rank 1, in the memory modules 103a to 103d are activated, and each buffer 105 (1) to 105 (4) are in a state in which 16-bit width data can be transmitted and received, and the four buffers 105 (1) to 105 (4) as a whole can transmit and receive data having a total 64-bit width. Become. The data line 111 of each of the memory modules 103a to 103d is 8 bits wide as shown in the figure, and the multiplexed data is connected to the memory controller 101 and each of the data lines 111 of the memory modules 103a to 103d. Data is transmitted to and received from the buffers 105 (1) to (4).

  Referring to FIG. 9, yet another modification of the memory system according to the third embodiment of the present invention is shown, and two memory modules 103a and 103b are made into one set to form a two-rank memory system. The memory system shown in FIG. 6 is configured such that 16 DRAMs arranged on the front side of the two memory modules 103a and 103b constitute Rank 1 and 16 DRAMs on the back side constitute Rank 2, and each DRAM 110 uses × 4 DRAM. Is different. Further, in FIG. 9, eight DRAMs 110 mounted on the front surface of each memory module 103a, 103b are ranked 1, and eight DRAMs 110 mounted on the back surface are ranked 2. In this relation, in FIG. 9, 16 DRAMs 110 belonging to rank 1 and arranged in the memory modules 103a and 103b are represented by reference numeral 110r1, while 16 DRAMs 110 belonging to rank 2 are represented by reference numeral 110r2. Yes. The rank 1 and rank 2 DRAMs 110r1 and 110r2 arranged on the front and back of the memory modules 103a and 103b are commonly connected by an internal data wiring having a 4-bit width.

  On the other hand, the buffer 105 of each memory module 103a, 103b is connected to the memory controller 101 by a 16-bit data line 111, and multiplexed data is transmitted on each data line 111 in another example. It is the same. According to this configuration, similarly to the memory system shown in FIG. 6, 32-bit-wide data is transmitted between the eight DRAMs 110r1 and 110r2 of the memory modules 103a and 103b and the buffer 105. 16-bit width data is multiplexed and transmitted between the memory 105 and the memory controller 101.

  Referring to FIG. 10, as another modification of the memory system according to the third embodiment of the present invention, an example having a 36-bit bus width with parity bits is shown.

  In this example, nine × 4 DRAMs 110 are mounted on the front and back of each of the memory modules 103a and 103b, and between the buffer 105 and the memory controller 101 of each of the memory modules 103a and 103b. 9 is different from the memory system shown in FIG. 9 in that the data line 111 is 18 bits wide. More specifically, each of the memory modules 103a and 103b shown in FIG. 10 has four DRAMs 110 on the left and right sides of the buffer 105, and five DRAMs 110 on the right and back sides of the buffer 105, respectively. Has been. Here, it is assumed that the DRAMs 110 arranged on the right and left ends of the memory modules 103a and 103b are used as parity DRAMs.

  Similarly to FIG. 9, this example is also a two-rank memory system in which two memory modules 103a and 103b are paired. In addition, 18 DRAMs arranged on the front side of the two memory modules 103a and 103b constitute rank 1, and 18 DRAMs 110 arranged on the back side constitute rank 2. In this relationship, the DRAMs of ranks 1 and 2 are represented by reference numerals 110r1 and 110r2. It is to be noted that the internal data wirings of the rank 1 and 2 DRAMs 110r1 and 110r2 arranged on the front and back sides are the same as in FIG.

  Further, the buffers 105 of the memory modules 103a and 103b are respectively connected to the memory controller 101 by the data wiring 111 corresponding to an 18-bit width, and are connected in cascade to the buffers of the memory modules (not shown), respectively. It is composed.

  In this configuration, data with parity is multiplexed and transmitted / received between the memory controller 101 and the memory module 103a or 103b.

  Comparing the first and second embodiments and the third embodiment described above, in the first and second embodiments, there is a difference between the DRAM on the cascaded second memory module and the memory controller. Since data transmission / reception is performed via two buffer chips, the logic delay required for the transmission / reception processing in the buffer chip is twice that of the third embodiment. On the other hand, the third embodiment has an advantage that the number of buffers to be passed is reduced, but it is necessary to increase the number of ranks of the DRAM on the memory module.

  With reference to FIG. 11, a signal transmission method between the memory controller (MC) 101 and each memory module 103 in the memory system described above will be described in more detail. In the illustrated example, in order to simplify the description, it is assumed that the buffers 105a and 105b in the memory module 103a and the memory module 103b are connected in cascade. In this system, the memory controller 101 transmits a command / address signal (CA) in synchronization with a clock signal, and the command / address (CA) signal and the clock signal are sent to the buffers 105a and 105b of the memory modules 103a and 103b. Are received sequentially.

  On the other hand, the data (DQ) signal is transmitted / received by the buffers 105a and 105b and the memory controller 101 in synchronization with a plurality of bidirectional clock signals (complementary) CLK and CLKB. That is, when data is written from the memory controller 101 to the DRAMs of the memory modules 103a and 103b, the data is transmitted to the buffers 105a and 105b in synchronization with the clock output from the memory controller 101, and from the DRAMs of the memory modules 103a and 103b. When reading data, the buffers 105a and 105b of the memory modules 103a and 103b generate a clock from the internal clock of the DRAM and output read data from the DRAM to the memory controller 101 in synchronization with the clock. At the time of packet transmission of the command / address signal and data signal, the module identification signal MID is sent from the memory controller 101 simultaneously with the command / address signal and data signal, and the buffers 105a and 105b receive the signal of the signal MID. Valid head data and a memory module as a transmission / reception destination are identified.

  Referring to FIG. 12, the timing relationship in the system shown in FIG. 11 is shown. In the illustrated example, a clock having a frequency of 1.33 GHz (that is, a period of 0.75 ns) is generated from the memory controller (MC) 101 (see FIG. 12, the first line), and the leading and trailing edges of the clock are generated. Data is transmitted from the memory controller (MC) 101 to the buffer in synchronization with the edge (see the third line). As a result, the data is sent from the memory controller (MC) 101 to the buffers 105a and 105b at a transmission speed of 2.66 Gbps.

  On the other hand, an internal clock having a frequency of 666 MHz (cycle of 1.5 ns) is generated from each of the buffers 105a and 105b (refer to the second line), and after the internal latency time of the buffer has elapsed, In synchronization with the leading and trailing edges, the data received in the buffer is written to the DRAM at a transmission rate of 1.33 Gbps (see line 4).

  Next, the command address signal (CA) is output from the memory controller (MC) 101 to the buffers 105a and 105b in synchronization with the leading and trailing edges of the clock having a frequency of 1.33 GHz (see the fifth line). The command address signal (CA) is output from the buffer to the DRAM in synchronization with the leading edge of the internal clock after the latency time in the buffer has elapsed (see the sixth line). Therefore, the command / address signal (CA) is output from the memory controller (MC) to the buffers 105a and 105b at a transmission rate of 2.66 Gbps, and is output from the buffer to the DRAM at a transmission rate of 666 Mbps. The The module identification signal MID is output from the memory controller (MC) from the memory controller (MC) to the buffer at a transmission speed of 2.66 Gbps in synchronization with the leading and trailing edges of the 1.33 GHz clock. ing.

  As is clear from this, between the memory controller (MC) 101 and the buffers 105a and 105b, data is twice as high as the data frequency of the DRAM and command / address signal (CA) is four times as high as the memory controller. (MC) and the buffer are transmitted. Therefore, in the buffer on each memory module, the data and the command / address signal are reduced to a frequency of 1/2 and 1/4 by a frequency divider or the like, and transmitted to the DRAM.

  Here, it is assumed that the memory system processes 8-bit continuous data (burst). That is, from the memory controller (MC) 101 to the buffer, 16-bit continuous data is output to each of the 32-bit data buses at a transmission speed of 2.66 Gbps, and the 16-bit continuous data is alternately output to the DRAM 2 in the buffer. Assume that 8-bit continuous data having a transmission rate of 1.33 Gbps is output to two DQ pins.

  The command / address signal is output from the MC to the buffer at a transmission speed of 2.66 Gbps. For example, 4-bit data on one command / address signal line has four command / address signal lines in the buffer. And is supplied to the DRAM at a transmission rate of 666 Mbps.

  Next, the above-described operation will be described in more detail by dividing it into data write and read operations and command / address signal transfer operations. FIG. 13 shows a data write operation from the memory controller (MC) to the DRAM. As described above, the memory controller (MC) 101 outputs a 1.33 GHz clock to the buffer 105 (first line). In synchronization with this clock, a module identification signal MID and data DQ0m are output from the memory module 101 (see the third and fourth lines).

  Here, the module identification signal MID includes a valid data head identification signal and a destination address, and the data DQ0m includes two series of data strings DQ0 and DQ1 to be distributed to the two DQ pins of the DRAM. It is included. Here, the data string DQ0 includes continuous 8-bit data DQ00, 10, 20, 30,. . . 70, on the other hand, the data string DQ1 includes continuous 8-bit data DQ01, 11, 21, 31. . . 71. As shown in the fourth line of FIG. 13, in the data DQ0m, the unit data of the data strings DQ0 and DQ1 are alternately synchronized with the leading and trailing edges of the clock shown in the first line. The data DQ0m is output from the memory controller (MC) 101 to the buffer 105a in synchronization with the clock. Here, when there are a total of 32 data lines from the memory controller (MC) to the buffer, data is supplied from each data line to the two DQ terminals of the DRAM. Continuous data will be processed. When the first-stage buffer 105a identifies that the module identification data MID is not addressed to the memory module 103a to which the buffer 105a belongs, the module identification data MID is transferred to the next-stage memory module 103b together with the data DQ0m (third and fourth). See line).

  Next, as shown in the second line, the buffer 105a in the memory module 105a generates an internal clock of 666 MHz obtained by dividing the 1.33 GHz clock by 2, and outputs it to the DRAM. When the memory module 103a is designated by the module identification signal MID described above, the illustrated data DQ0m is written to a predetermined DRAM in synchronization with the internal clock after the buffer latency elapses. In the illustrated example, the data strings DQ0 and DQ1 are output from the buffer 105a to the two DRAMs as shown in the fifth and sixth lines, in synchronization with the leading and trailing edges of the internal clock.

  Next, with reference to FIG. 14, an operation for reading data DQ0m from the DRAM will be described. In this case, it is assumed that the data DQ0m is read from the DRAM of the memory module 103a to the memory controller (MC) 101 through the buffer 105a. First, the buffer 105a outputs an internal clock of 666 MHz (second line in FIG. 14) to the DRAM, and on the other hand, a clock (second clock) having a frequency of 1.33 GHz to the memory controller (MC) 101. (See 1 line). In this state, data strings DQ0 and DQ1 are read from the two DQ terminals of the DRAM. Here, the data strings DQ0 and DQ1 are unit data D00, 10, 20,. . . 70 and unit data D01, 11, 21. . . 71 (see the fifth and sixth lines). These unit data are sent from the two DQ terminals to the buffer 105a in synchronization with the internal clock. The buffer 105a outputs a module identification signal MID representing the memory module 103a to which the buffer 105a belongs as a valid data head identification signal to the memory controller (MC) (see the third line). Subsequently, the continuous 8-bit unit data of the data strings DQ0 and DQ1 from the two DQ terminals are alternately combined and multiplexed, and in synchronization with the clock between the buffer 105a and the memory controller 101, the memory controller 101 has 16-bit data. Output as read data DQ0m. Further, in the case of a buffer at the subsequent stage of the buffer 105a, such as the buffer 105b, the data DQ0m is given to the memory controller (MC) through the buffer 105a at the previous stage.

  Thus, it can be seen that the data transmission speed and clock frequency between the memory controller (MC) 101 and the buffers 105a and 105b are faster than the data transmission speed and clock frequency between the buffers 105a and 105b and the DRAM. . With this configuration, the number of wires between the memory controller (MC) 101 and the buffer can be reduced, and data can be written and read at a transmission speed corresponding to the operation speed of each DRAM.

  Further, FIG. 15 shows an operation when a command / address signal is given from the memory controller (MC) 101 to the memory module. As described above, a clock having a frequency of 1.33 GHz is supplied from the memory controller (MC) 101 to the buffers 105 a and 105 b (see the first line), and 666 MHz is provided between each buffer 105 and the DRAM 110. Are used (see the second line). In this case, the module identification signal MID includes the head identification signal and the destination address signal of the command / address signal CA0m, and the head identification signal and the destination address signal of the command / address signal CA0m are before the clock of 1.33 GHz. The MID is output from the memory controller (MC) 101 in synchronization with the edge and the rear edge (see the third line), and this MID is also transferred to the buffer 105a of the preceding memory module 103a and the buffer 105b of the next memory module 103b. Has been.

  Simultaneously with the module identification signal MID, in this example, as the command / address signal CA0m, the address signals A0 to A3 are multiplexed in synchronization with the leading and trailing edges of the 1.33 GHz clock, and the memory controller (MC ) 101 to the buffer 105a, and then transferred to the buffer 105b (see the fourth line). In the buffer 105 of the memory module 103 designated by the module identification signal MID described above, the address signals A0 to A3 are given to the DRAM mounted on the designated memory module 103 in synchronization with the internal clock. In FIG. 15, only one command / address signal is shown, but a plurality of command / address signals given to the buffer are each composed of four command / address signals, for example, RAS, CAS, WE, bank address, The remaining address signal is converted. As a result, the operation mode in the designated memory module, the DRAM, and the memory cell in the DRAM are selected.

  In the above description, signal transmission between the memory controller (MC) 101 and the memory module 103 has been mainly described. However, signal transmission can be performed at high speed between each memory module 103 and the DRAM in the memory module 103. It is desirable.

  Therefore, the present invention proposes a method for transmitting data at high speed between the buffer 105 and the DRAM. In the following description, a case where the data transmission method according to the present invention is applied to the memory system according to the first to third embodiments of the present invention described above will be described. However, the present invention is not necessarily limited to the memory system described above. Not.

  Referring to FIG. 16, the DRAM 110 and the buffer 105 in the memory module 103 of the memory system described above are shown.

  In FIG. 16, the DRAM 105 performs data transmission / reception between the buffer 105 and the DRAM 110 by a data strobe signal DQS (and complementary DQS *) (only DQS will be described below). In this case, the data strobe signal DQS is generated in synchronization with the clock, and is transmitted in the transmission direction of the data DQ when the data DQ is transmitted bidirectionally. For example, when data DQ is transmitted from the DRAM 110 to the buffer 105, the data strobe signal DQS is also output from the DRAM 110 to the buffer 105. The same applies when data is transmitted from the buffer 105 to the DRAM 110.

  Next, referring to FIG. 17A, FIG. 16 shows an operation when data is written from the buffer 105 to the DRAM 110, and FIG. 17B shows an operation when data is read from the DRAM 110. Has been. First, as shown in FIG. 17A, in the case of data writing, after a write command (WRT) and an address (Add) are given from the buffer to the DRAM, it is synchronized with the leading and trailing edges of the clock. Data is written together with the data strobe signal DQS, and this writing operation is continued while the strobe signal DQS is applied. For this reason, data is written after a predetermined latency time has elapsed (WL = 4 in the figure) after generation of the command / address signal.

  As shown in FIG. 17B, also in the case of data reading, a read command (RED) and an address (Add) are supplied from the buffer to the DRAM, and the data is synchronized with the leading and trailing edges of the clock. Data is read together with the strobe signal DQS.

  As described above, when the data strobe signal DQS is used, the data is transmitted with the timing matched to the data strobe signal DQS and is received by the data strobe signal DQS. As described above, in the transmission / reception method using the data strobe signal, it is necessary to match the logic and layout delay of the data strobe signal DQS and the data DQ in the receiving device. However, if the delay changes due to temperature fluctuations and voltage fluctuations, the signal setup and hold time that can be received by the device deteriorates. Since a shorter setup and hold time is required for higher frequency operation, the method of transmitting the data strobe signal bidirectionally has a limitation in speeding up.

  In order to perform data transmission / reception between the DRAM 110 and the buffer 105 at a higher speed, in the present invention, instead of the data strobe signal DQS described above, the data is always transmitted bidirectionally at the timing of the data signal, and transmitted / received by the DRAM 110 and the buffer 105, respectively. It is proposed to use a signal (here called the data phase signal DPS). In this way, by using the data phase signal DPS that is always transmitted and received bidirectionally, the transmission / reception clock can be regenerated using the DLL in each device. Further, when DLL is used, first, temperature fluctuation and voltage fluctuation can be canceled by the replica delay, and the clock can be set at the optimum timing, so that data can be received without interposing delay logic. Therefore, a shorter setup and hold time can be achieved.

  Referring to FIG. 18, there is shown a schematic configuration of a data transmission system that performs data transmission between the DRAM 110 and the buffer 105 using the data phase signal DPS described above. As is apparent from comparison with FIG. 16, in the data transmission system shown in FIG. 18, instead of the data strobe signal DQS, the data phase signal DPS is transmitted and received bidirectionally between the buffer 105 and the DRAM 110. The data phase signal DPS is supplied to the other device as a timing signal for data DQ transmitted from the buffer 105 or the DRAM 110. Specifically, when data DQ is written from the buffer 105 to the DRAM 110, the write data phase signal DPS is supplied from the buffer 105 to the DRAM 110 together with the write data DQ at a predetermined write timing. When reading DQ, a read data phase signal DPS generated at a timing different from the write timing is supplied from the DRAM 110 to the buffer 105 together with the read data DQ.

  The DRAM 110 and the buffer 105 extract the write data phase signal and the read data phase signal (DPS) by identifying the write timing and the read timing, respectively, and the extracted write data phase signal and read data phase signal (DPS). Thus, the data DQ is written or read. As is clear from this, the buffer 105 and the DRAM 110 include a circuit for identifying the timing of the write data phase signal and the read data phase signal (DPS) in addition to the above-described DLL.

  Referring to FIG. 19, the driver circuit and the receiver circuit (that is, the transmission / reception circuit) of the buffer 105 and the DRAM 110 used when the data phase signal DPS is transmitted / received between the buffer 105 in the one-rank configuration and the DRAM 110 in the one-rank configuration. )It is shown. As shown in the figure, the drivers of the buffer 105 and the DRAM 110 each include an N-channel MOS transistor having an open drain configuration. A variable resistor is connected as a termination resistor to the drain of the N-channel MOS transistor of the DRAM 110, while a fixed resistor is connected as a termination resistor to the drain of the N-channel MOS transistor of the buffer 105. Thus, when a variable resistor is connected, the resistance value can be adjusted by the rank configuration on the DRAM side. Although the termination resistor is provided inside the device of the DRAM 110 and the buffer 105, it goes without saying that it may be provided outside the device. The data phase signal DPS transmission signal lines connected to the drains of both transistors in the DRAM 110 and the buffer 105 are connected to internal circuits of the DRAM 110 and the buffer 105 through amplifiers, respectively.

  In the configuration shown in FIG. 19, a timing signal is given to the gate of the N-channel MOS transistor of the buffer 105 at a predetermined timing and cycle, and the N-channel MOS transistor of the buffer 105 is turned on / off by this timing signal, The embedded data phase signal DPS is supplied from the buffer 105 to the DRAM 110 and is also supplied to the inside of the buffer 105. On the other hand, the gate of the N-channel MOS transistor of the DRAM 110 is given a timing signal having a phase different from that of the timing signal of the buffer 105 and generated in the same cycle. The N-channel MOS transistor of the DRAM 110 receives the timing signal. As a result, the read data phase signal DPS is supplied from the DRAM 110 to the buffer 105 and also supplied to the DRAM 110. As shown in the figure, the drivers in the DRAM 110 and the buffer 105 are open drain, so the bus has a so-called wired OR configuration, and the data phase signal DPS from the DRAM 110 and the buffer 105 has different timings. Therefore, even if both signals are output on the same signal line, they do not collide with each other.

  Referring to FIG. 20, there is shown a data phase signal DPS transmission / reception driver circuit when two DRAMs 110 are connected to the buffer 105 in a two-rank configuration. As is apparent from the figure, it is different from FIG. 19 in that the drivers of two DRAMs 110 are connected to a single data phase signal DPS signal line, but the configuration in each DRAM 110 is the same. is there. Note that a variable resistor is connected to the drain of the N-channel MOS transistor in the DRAM 110. In this example, the resistance value is adjusted to a value suitable for the two-rank DRAM 110.

  Referring to FIGS. 21A and 21B together with FIG. 18, an operation when data DQ is written to DRAM 110 (ie, a write operation) and an operation when data DQ is read from DRAM 110 (ie, Each of the read operations will be described. As shown in FIG. 21A, during the write operation, the buffer 105 supplies a write (write) command (WRT) and an address signal (Add) to the DRAM 110 in synchronization with the clock. At this time, a write data phase signal WDPS is transmitted from the buffer 105 to the DRAM 110 as the data phase signal DPS (see the fourth line). The illustrated write data phase signal WDPS is characterized by the leading edge (rising) timing of each pulse in a pulse train having a quarter period of the clock.

  On the other hand, the read (read) data phase signal RDPS is multiplexed from the DRAM 110 to the buffer 105 on the same signal line at a timing that does not collide with the write data phase signal WDPS (here, a timing shifted by two clocks). Has been sent in the form. As shown in the fourth line of FIG. 21 (b), the read data phase signal RDPS is generated by the leading edge (rising edge) timing of a pulse train having a cycle of 1/4 of the clock, like the write data phase signal WDPS. Characterized and placed in the middle of the write data phase signal WDPS. In this way, the timings of the write data phase signal WDPS and the read data phase signal RDPS are shifted to prevent the two from colliding on a single signal line. In the illustrated example, the timing of the write data phase signal WDPS and the read data phase signal RDPS is shifted by two clocks, but it is needless to say that the timing is not limited to this when the two do not collide. .

  Further referring to FIG. 21A, in the write operation from the buffer 105, the clock 105 and the write data phase signal (WDPS) are in phase in the buffer 105, but the read data phase signal ( RDPS) are out of phase. Data DQ is written after the write latency time has elapsed (WL = 4) so that the rising edge (leading edge) and the falling edge (rear edge) of the clock become the center of signal validity.

  During the read operation shown in FIG. 21B, the DRAM 110 regenerates the clock in the DRAM 110 from the read data phase signal (RDPS). The data DQ is transmitted from the DRAM 110 to the buffer 105 in synchronization with the regenerated clock. In the illustrated example, the data timing is matched with the clock edge, but the center of the effective width may be aligned with the clock edge.

  In the above-described example, the DRAM 110 and the buffer 105 always transmit the data phase signal DPS on the same signal line in both directions during normal operation, that is, during operation other than the power save mode. In addition, since the drivers of the DRAM 110 and the buffer 105 operate at different timings by two clocks and adopt an open drain configuration as shown in FIGS. 19 and 20, the bus has a so-called wired OR configuration. It will be a bus fight.

  21A and 21B, the timing relationship between the clock at the time of writing (writing) and at the time of reading (reading), the writing and reading data phase signals WDPS and RDPS, the data, and the clock The timing relationship with the data phase signals (WDPS, RDPS) has been described. In the DRAM 110 and the buffer 105 that have received these data phase signals (WDPS, RDPS), data transmission / reception is internally performed from the data phase signals (WDPS, RDPS). Need to regenerate the clock.

  Next, referring to FIG. 22, at the start of the memory system operation, the DRAM 110 and the buffer 105 are internally used for data transmission / reception from the data phase signal DPS (write or read data phase signals WDPS, RDPS) according to the present invention. A procedure for reproducing the clock will be described.

  First, the buffer 105 transmits a clock to the DRAM 110 (see the first line). In this example, a clock having a frequency of 666 MHz is generated in the buffer 105. In this state, the buffer 105 transmits the write data phase signal WDPS (see the second line) in synchronization with the clock. The illustrated write data phase signal WDPS is generated by dividing the clock by four, resulting in the write data phase signal WDPS having a frequency of (666/4) MHz (ie, four quarters of the clock). The write data phase signal WDPS is delayed in time and input to the DRAM 110 (see the third line).

  The DRAM 110 generates an internal clock that determines the timing for receiving data (DQ) from the write data phase signal WDPS as a reproduction clock by using a DLL provided therein (see the fourth line). The illustrated internal clock has a frequency of 666 MHz.

  Further, as shown in FIG. 22, after reproducing the data (DQ) reception clock as an internal clock, the DRAM 110 shifts the internal clock by two clocks from the write data phase signal WDPS and the internal clock. The read data phase signal RDPS indicated by the solid line is generated, and the read data phase signal RDPS is transmitted to the buffer 105 (see the fifth line). As shown in FIG. 22, read data phase signal RDPS has a quarter cycle of the internal clock and is generated so as not to collide with write data phase signal WDPS indicated by a broken line.

  Read data buffer signal RDPS is received by buffer 105 with a time delay (see the sixth line). Buffer 105 receives data from DRAM 110 in buffer 105 from received read data buffer signal RDPS. The 666 MHz data (DQ) reception clock is reproduced (see the seventh line). Note that the timing chart shown in FIG. 22 conceptually explains the timing relationship between the data phase signal DPS and the clock. In practice, as will be described later, the internal clock for data reception and data output DRAM Are generated at the optimal internal timing. Further, the illustrated clock may not be a quarter period of the data phase signal DPS, and may be a multiphase clock.

  In any case, the transmission / reception clock in the DRAM 110 and the buffer 105 is regenerated from the data phase signals WDPS and RDPS.

  With reference to FIG. 23, a specific configuration of DRAM 110 performing the above-described operation will be described. In the figure, only the interface for transmitting and receiving the data phase signal DPS and data (DQ) to and from the buffer 105 is shown, and the memory cell area for writing and reading data (DQ) is omitted in FIG. Yes. The memory cell area of the DRAM 110 is connected to the data (DQ) output driver 201 and the data receiver 202, and data (DQ) is read and written. Further, the illustrated DRAM 110 includes a clock recovery phase adjustment and multiplication circuit 205 configured by a DLL, and a write data phase signal WDPS is input to the DLL 205 while a read data phase from the DLL 205 is input. The signal RDPS is output via the DPS output driver 206. As is clear from this, the illustrated DLL 205 also includes a delay line including a plurality of delay cells, a phase detector, an integrator, and a frequency multiplier.

  More specifically, the DLL 205 is supplied with a data phase signal DPS including write and read data phase signals WDPS and RDPS. The data phase signal is received by the reception phase comparison circuit 206 and the output phase comparison circuit 209. Is also given. The DLL 205 regenerates the data reception DRAM internal clock from the write data phase signal WDPS and generates a data reception feedback clock. The data receiving DRAM internal clock is supplied to the data receiver 202 and used to write the data DQ, while the data receiving feedback clock is supplied to the receiving replica 208 and is divided by 4 by the receiving replica 208. A replica signal of the received write data phase signal WDPS is output to the reception phase comparison circuit 206. The reception phase comparison circuit 206 suppresses the read data phase signal RDPS with the replica signal from the reception replica 208 and receives only the write data phase signal WDPS from the DPS output DRAM internal clock. Is output to the DLL 205.

  Further, the illustrated DLL 205 further delays the data reception DRAM internal clock by 2 clocks, thereby causing the read data phase signal RDPS output DRAM internal clock, the data output feedback clock, and the data output DRAM internal clock. Is output. Among these, the DPS output DRAM internal clock is supplied to the DPS output driver 207 and the output phase comparison circuit 209, and the data output DRAM internal clock is supplied to the data output driver 201. Further, the data output feedback clock is supplied to the output replica 210, and the output replica 210 outputs a replica signal of the read data phase signal RDPS to the output phase comparison circuit 209. The DPS force driver 207 sends a read data phase signal RDPS to the buffer 105 in response to the DPS output DRAM internal clock.

  The output phase comparison circuit 209 compares the phases of the read data phase signal RDPS and the output of the DLL 205 with the read replica signal supplied from the output replica 210 while suppressing the timing of the write data phase signal WDPS, and compares the result. An output phase adjustment signal corresponding to the above is output to the DLL 205. As a result, the read data phase signal RDPS is transmitted from the illustrated DRAM 110 to the buffer 105.

  In this manner, in the illustrated DRAM 110, when the DRAM 110 transmits the read data phase signal RDPS, the DPS output DRAM internal clock is output and the write data phase signal WDPS is received so that the phase comparison is not performed. In this case, the DPS output DRAM internal clock is input to the reception phase comparison circuit 206 to prohibit the feedback of the comparison value to the DLL 205.

  Referring to FIG. 24, a specific configuration of buffer 105 that transmits / receives data to / from DRAM 110 shown in FIG. 23 will be described. Similarly to the DRAM 110 shown in FIG. 23, the buffer 105 includes a DQ output driver 301 for outputting data to the DRAM 110, a data receiver 302 for receiving read data from the DRAM 110, and a data phase signal DPS transmission / reception. And a DLL 305 constituting a clock recovery phase adjustment and multiplication circuit. Further, in the illustrated buffer 105, a DPS output buffer internal clock is generated by a clock generator (not shown), and the DPS output buffer internal clock is supplied to the DPS output driver 307 and the reception phase comparison circuit 306. ing. The DPS output driver 307 divides a given clock by four and outputs a write data phase signal DPS (ie, WDPS) to the DRAM 110, and the write data phase signal WDPS includes the DLL 305 in the buffer 105 and the reception phase. A comparison circuit 306 is also provided.

  In this state, when the read data phase signal RDPS is received from the DRAM 110, the DLL 305 of the buffer 105 generates a data reception buffer internal clock and a data reception feedback clock, and outputs them to the data receiver 302 and the reception replica 308, respectively. To do. Reception replica 308 outputs a replica signal of read data feedback signal RDPS to reception phase comparison circuit 306 from the data reception feedback clock. As a result, reception phase comparison circuit 306 ignores write data phase signal WDPS output from buffer 105 and outputs a reception phase adjustment signal to DLL 305 for the phase of read data phase signal RDPS.

  In the buffer 105 shown in the figure, the DPS output buffer internal clock signal is input to the reception phase comparison circuit 306 so as to regenerate the clock from the read data phase signal RDPS from the DRAM 110, and the feedback of the comparison value to the DLL is prohibited. ing.

  FIG. 25 shows a timing chart at the start of operation of the DRAM 110 shown in FIG. 23, and FIG. 26 shows a timing chart at the time of normal operation of the DRAM 110. At the start of the operation shown in FIG. 25, read data phase signal RDPS is not output from buffer 110 to buffer 105. In FIG. 25, similarly to FIG. 22, a 666 MHz DPS output buffer internal clock is generated by the buffer 105, the clock is divided by 4 by the DPS output driver 307 (FIG. 24), and the write data phase signal WDPS is clocked. (FIG. 25, second line). The write data phase signal WDPS is delayed in time and input to the DRAM 110 (third line). Further, in the DRAM 110, the DLL 205 receives a data reception feedback clock whose phase is advanced with respect to the received WDPS. Is generated (fourth line) and output to the reception replica 208, and a replica signal of WDPS is output from the reception replica 208 to the reception phase comparison circuit 206 (see the fifth line).

  The DLL 205 of the DRAM 110 outputs a data reception DRAM internal clock to the data receiver 202 in accordance with the reception phase adjustment signal from the reception phase comparison circuit 206 and the received WDPS (see the sixth line). Further, the DLL 205 of the DRAM 110 outputs a data output feedback clock having a leading phase with respect to the internal clock to the output replica 210 (see the seventh line), while synchronizing with the data output feedback clock, the data output DRAM An internal clock is supplied to the DQ output driver 201 (see the ninth line). 25, the output replica 210 supplies a data output feedback signal as a replica signal to the output phase comparison circuit 209, and the presence of this replica signal. The phase comparison is performed, and the DPS output DRAM internal clock as shown in the tenth line is output to the DPS output driver 207.

  Next, a normal operation of the DRAM 110 shown in FIG. 23 will be described with reference to FIG. In this case, as shown in the second line and the third line in FIG. 25, the write data phase signal WDPS is output from the buffer 110, while the read data phase signal RDPS (see thick line) is output from the DRAM 110. . In this case, the DPS output clock is generated in the buffer 105, and the write data phase signal WDPS synchronized with this is transmitted to the DRAM 110. In the DRAM 110, the data reception feedback clock, the replica signal of the data reception feedback clock, the data The reception DRAM internal clock, the data output feedback clock, and the data output DRAM internal clock are generated as in FIG. 25 (see the fourth, fifth, sixth, seventh, and eighth lines). Further, as shown in the ninth line, when the data output DRAM internal clock is generated, the DLL 205 generates the DPS output DRAM internal clock by delaying the internal clock by two clocks, and according to the clock. Then, the read data phase signal RDPS is generated from the DPS output driver 207 as indicated by the bold line of the tenth line, and the RDPS is received by the buffer 105 as indicated by the second line.

  FIG. 27 shows a timing chart of the buffer 105 (FIG. 24) when the above-described RDPS is received, and the data transmitted from the DRAM 110 is aligned with the edge of the read data phase signal RDPS in this embodiment. In this relationship, the buffer 105 shifts the phase of the internal clock of the reception buffer by ¼ with respect to the phase of the replica signal from the reception replica 308 obtained from the data reception feedback clock. Yes.

  In the above embodiment, when the internal clock signal is recovered from the data phase signal, the clock recovery directly from the data phase signal is shown.

  Referring to FIGS. 28 and 29, there are shown modifications of the DRAM 110 and the buffer 105 shown in FIGS. 23 and 24, respectively. The DRAM 110 shown in FIG. 28 is different from the DRAM 110 shown in FIG. 23 in that the clock CLK is supplied to the DLL 205 from the outside and the data phase signal DPS is not supplied to the DLL 205. In this relationship, the illustrated DLL 205 not only operates as a clock recovery phase adjustment circuit but also operates as a frequency dividing circuit that divides the clock. In this configuration, it can be seen that during clock recovery, the external clock signal CLK is supplied to the DLL 205 as a clock source, and only the phase of the clock is adjusted by the DLL 205. As described above, the data reception DRAM internal clock and the data reception feedback clock can be reproduced from the received write data phase signal WDPS by applying the external clock CLK to the DLL 205 and adjusting the phase of the clock by the DLL 205. In addition, the DPS output DRAM internal clock can be generated and the read data phase signal RDPS can be transmitted to the buffer 105.

  The buffer 105 shown in FIG. 29 is also different from the buffer 105 shown in FIG. 24 in that the buffer internal clock signal is supplied to the DLL 305 operating as a clock phase adjustment circuit. When the buffer 105 having the configuration shown in FIG. 29 is used, the DLL 305 adjusts the phase of the clock in accordance with the reception phase adjustment signal from the reception phase comparison circuit 306, and the data reception buffer internal clock and the data reception feedback. A clock can be generated.

  The operation of the buffer 105 and the DRAM 110 shown in FIGS. 28 and 29 will be described with reference to FIG. In this example, the operation of the DRAM 110 in the initial state in which the read data phase signal RDPS is not output is shown. Compared to FIG. 25, the example shown in FIG. 30 is different from FIG. 25 in that an external clock of 666 MHz is generated in the DRAM 110 as in the buffer 105 (see the third line). Other operations are the same as those in FIG. 25 except that the operations are performed with reference to the external clock, and thus description thereof is omitted here.

  With reference to FIGS. 31 to 33, another example of the transmission method between the buffer 105 and the DRAM 110 in the memory system according to the present invention will be described. In the example described above, the case where the data phase signal DPS is output from both sides of the buffer 105 and the DRAM 110 as the write and read data phase signals WDPS and RDPS has been described, but in FIG. 31, the write data phase signal WDPS is output. It can be seen that the read data phase signal RDPS is output from the buffer 105 and the DRAM 110 on different signal lines. Other clocks (CLK), command addresses (Cmd / Add), and data DQ are the same as those in FIG. By adopting this configuration, it is not necessary to multiplex the two data phase signals WDPS and RDPS on a single signal line, so that the configuration of the DLL used for the buffer 105 and the DRAM 110 can be simplified.

  Referring to FIG. 32, an operation at the time of data writing of DRAM 110 shown in FIG. 31 will be described. In this case, a write command WRT and an address (Add) are output from the buffer 105 to the DRAM 110 in synchronization with the clock. At this time, the write data phase signal WDPS is transmitted from the buffer 105 to the DRAM 110 in the form of dividing the clock CLK by 4 (FIG. 32, fourth line). In DRAM 110, data DQ is written into DRAM 110 after a predetermined latency time (WL) in accordance with an internal clock generated based on write data phase signal WDPS (see the fifth line).

  On the other hand, in DRAM 110, read data phase signal RDPS is output on a signal line different from write data phase signal WDPS at a timing different from the reception timing of write data phase signal WDPS.

  As shown in FIG. 33, when the DRAM 110 receives the read command (RED) and the address (Add), the DRAM 110 follows the internal clock (first line) generated based on the read data phase signal RDPS (fourth line). Read data DQ (fifth line) is output from the DRAM 110 to the buffer 105. As is apparent from the figure, the output timing of the read data phase signal RDPS is different from the reception timing of the write data phase signal WDPS. In this example, the write data phase signal WDPS and the read data phase signal RDPS are shifted by two clocks between them in order to avoid output noise such as mutual interference and crosstalk between them.

  Next, specific examples of the DRAM 110 and the buffer 105 shown in FIG. 31 will be described with reference to FIG. 34 and FIG. Comparing the DRAM 110 shown in FIG. 34 with the DRAM 110 shown in FIG. 23, the write data phase signal WDPS and the read data phase signal RDPS are input to the DRAM 110 of FIG. It is different from the DRAM 110 of FIG. 23 in that it is output. In this relationship, the read data phase signal output driver 207 ′ is connected to the read data phase signal RDPS transmission signal line and is disconnected from the DLL 205 of the DRAM 110 and the signal line of the write data phase signal WDPS. The other components are the same as those in FIG.

  35, the write data phase signal WDPS transmission driver is connected to the write data phase signal transmission signal line from the read data phase signal RDPS reception signal line and the DLL 305 of the buffer 105. 24 is different from the buffer 105 in FIG. 24 in that the other components are the same as those in FIG.

  Here, the timing relationship between the DRAM 110 and the buffer 105 shown in FIGS. 34 and 35 will be schematically described with reference to FIG. First, as shown in FIG. 36, the buffer 105 generates a clock having a frequency of 666 MHz (first line), divides the clock by four, and outputs the write data phase signal WDPS on the write data phase signal line. (Second line). Write data phase signal WDPS is received by DRAM 110 as shown in the third line with a time delay. The DRAM 110 multiplies the received write data phase signal WDPS by 4 to generate an internal clock having a frequency of 666 MHz (fourth line), shifts it by two clocks, and divides it by four so that it is shown in the fifth line. Read data phase signal RDPS is output onto the read data phase signal line. The read data phase signal RDPS is received by the buffer 105 at the timing shown in the sixth line. In the buffer 105, an internal clock for data reception is generated from the received read data phase signal RDPS as shown in the seventh line.

  Referring also to FIG. 37, the normal operation of DRAM 110 shown in FIG. 34 will be described in more detail. The operation at the start of the operation is the same as that of the DRAM 110 of FIG. 34 and the DRAM 110 of FIG. The write data phase signal WDPS is supplied from the buffer 105 to the DRAM 110 shown in FIG. 34 via the write data phase signal line (see FIG. 37, the third line), and the write data phase signal WDPS is shown in FIG. 34 DLL 205, reception phase comparison circuit 206 and output phase comparison circuit 209. As a result, the write data phase signal WDPS as shown in the fifth and eighth lines in FIG. 37 is supplied as an input signal to the reception phase comparison circuit 206 and the output phase comparison circuit 209, respectively.

  The DLL 205 also refers to the reception phase adjustment signal and the output phase adjustment signal from the reception phase comparison circuit 206 and the output phase comparison circuit 209, and the data reception feedback clock and the sixth line as shown in the fourth line of FIG. The data reception DRAM internal clock as shown in FIG. 4 is output to the reception replica 208 and the data receiver 202, respectively.

  Further, the DLL 205 supplies a data output feedback clock and a data output DRAM internal clock as shown in the seventh and ninth lines to the output replica 210 and the DQ output driver 201, respectively. Among them, the data output DRAM internal clock is divided by 4 in the DLL 205, and is supplied to the RDPS output driver 207 ′ as the RDPS output DRAM internal clock, as shown in the tenth line, from the output driver 207 ′. The read data phase signal RDPS as shown in the eleventh line is output to the buffer 105.

  With reference to FIGS. 35 and 38, the operation at the time of receiving the read data in the buffer 105 will be described. The write data phase signal WDPS is output onto the signal line (second line) by the WDPS output buffer internal clock (third line), and the read data phase signal RDPS is sent to the DLL 305 of the buffer 105 via the read data phase signal line. And provided to the reception phase comparison circuit 306 (fifth line). The DLL 305 refers to the reception phase adjustment signal from the reception phase comparison circuit 306, receives the data reception feedback clock and the data reception buffer internal clock as shown in the fourth line and the sixth line, the reception replica 308 and the data receiver. 302 is supplied. Here, the illustrated data reception buffer internal clock is shifted by ¼ phase with respect to read data phase signal RDPS.

  With reference to FIGS. 39 and 40, another example of the DRAM 110 and the buffer 105 capable of realizing the transmission scheme shown in FIG. 31 will be described. The DRAM 110 shown in FIG. 39 is different from the DRAM 110 in FIG. 34 in that the clock CLK is externally applied as in FIG. 28. On the other hand, the DLL 305 of the buffer 105 shown in FIG. It is different from the buffer 105 shown in FIG. 35 in that a buffer internal clock signal is given. In FIG. 39, the external clock is supplied to the DLL 205 in the DRAM 110, while the write data phase signal WDPS is supplied to the reception phase comparison circuit 206 and the output phase comparison circuit 209. Also with this configuration, the same operation as in FIG. 34 can be realized.

  Also, the read data phase signal RDPS from the DRAM 110 is given to the reception phase comparison circuit 306 of the buffer 105 shown in FIG. 40, and the DLL 305 receives the reception phase adjustment signal from the reception phase comparison circuit 306 and the buffer internal clock signal. Therefore, the data reception feedback clock and the data reception buffer internal clock are generated. Also with this configuration, the same operation as in FIG. 35 is possible.

  In the transmission system described above, the data transmission between the buffer mounted on the module and the DRAM has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a memory circuit other than a DRAM, for example, a ROM. Furthermore, the present invention can perform data transmission at high speed even when applied to a system that transmits data bidirectionally or a system that requires a strobe signal.

  In the memory system described above, a buffer and a plurality of DRAMs are mounted on each memory module, and transmission / reception of data signals to / from the DRAM on the memory modules, transmission of clocks to the DRAM, and address command signals are all performed on each memory module. Is done through the buffer. Furthermore, in the above description, the one-to-one data transmission / reception between the buffer and each DRAM in each memory module has been mainly described.

  However, in order to actually operate the memory module described above at high speed, it is necessary to further process the timing skew between the data signal generated depending on the position of the DRAM on the memory module, the clock, and the command / address signal. In addition, it is necessary to perform clock timing matching in the buffer for data transmitted from each DRAM in the buffer and arriving at different timings.

  Here, the above point will be described more specifically with reference to FIG. 41. On the illustrated memory module 103, a buffer 105 and a plurality of DRAMs 110 are mounted. The package size of each DRAM 110 mounted on the memory module 103 usually has a width of about 14 mm, and this size is considered to be maintained even when generations progress. As shown in the figure, when the DRAM 110 having such a size is mounted with an interval of, for example, 5 mm and 9 mm, a clock, a command address between the far end DRAM 110 (indicated by 110F) and the buffer 105 are provided. The wiring length of the DQ signal line is 65 mm, and the wiring length of the clock, command address, and DQ signal line with the near-end DRAM 110 (indicated by 110N) is 9 mm.

  When the memory module 103 having such a dimension is driven at a high frequency of 800 MHz, the operation frequency (1250 ps) of the high frequency operation (800 MHz) in the far-end DRAM 110F is caused by the difference in the signal propagation time of the clock, command / address signal, and DQ signal. However, timing skew of a level that cannot be ignored occurs.

  More specifically, since the clock and command / address signals are input from the buffer 105 to each DRAM 110 through the common wiring, an input capacitance of about 1.5 pF × 2 × 5 is provided on the wiring for the clock and command / address signals. Will be distributed. Therefore, the signal unit propagation time (tPD) of the clock and command / address signal is about 14 ps / mm. On the other hand, since the DQ signal is transmitted and received between the buffer 105 and each DRAM 110 via a one-to-one or one-to-two wiring, an input capacitance of about 2.5 pFx2 is distributed on the wiring for the DQ signal. Will be. Therefore, the signal unit propagation time tPD of the DQ signal is about 8 ps / mm, which is shorter than the signal unit propagation time of the clock and command / address signals.

  Due to the difference in signal propagation time between the clock, command / address signal, and DQ signal, the far-end DRAM 110F generates a timing skew that cannot be ignored with respect to the operation period (1250 ps) of the high-frequency operation (800 MHz). Referring to the illustrated memory system, the clock and address command signal propagation time to the far-end DRAM 110F at the time of writing is 910 (= 14 × 65) ps, while the signal propagation time of the DQ signal is 520 (= 8 × 65) ps. As a result, in the far end DRAM 110F, a timing skew of 390 ps occurs between the clock, the address command signal, and the DQ signal.

  When a write command is given to the far-end DRAM 110F in a state where such timing skew occurs, the write command (WRT) is taken into the DRAM at the phase of the buffer clock signal from the buffer 105.

  On the other hand, the data write operation in each DRAM 110 is performed in synchronization with the buffer clock signal after receiving the write command. This means that the data taken in at the rising edge of the data reception DRAM internal clock needs to be replaced with the phase timing of the buffer clock signal during one cycle.

  For example, data captured at the rising edge of the data receiving DRAM internal clock is replaced with the clock signal phase timing at the falling edge of the buffer clock signal, while data captured at the falling edge is clocked at the rising edge of the buffer clock signal. Changed to phase timing. As a result, internal data is generated alternately. When such data is transferred from one clock to another timing, setup time and hold time are required.

  In the system shown in FIG. 41, the setup time and hold time in the near-end DRAM 110N for transferring to the buffer clock timing of the data fetched by the data receiving DRAM internal clock are 679 ps and 571 ps, respectively. The setup time and hold time of the far-end DRAM 110F are 1015 ps and 235 ps, respectively.

  As is apparent from this, the near-end DRAMN has a small timing skew of the clock signal and the DQ signal of 54 ps, so that an equal margin is obtained in the setup time and the hold time. However, the far-end DRAM 110F has a skew of 390 ps. Therefore, the hold time becomes as short as 235 ps (0.19 clock cycle), and a sufficient time margin cannot be obtained.

  Further, the DQ signal transmitted from each DRAM by a read (READ or RED) command has different arrival times in the buffer 105 due to the difference in the propagation time of the clock signal (same as the propagation time of the command) and the propagation time of the DQ signal. Yes. For example, the propagation time of the clock signal (command) to the near-end DRAM 110N is 126 ps, the propagation time of the DQ signal from the near-end DRAM 110N to the buffer 105 is 72 ps, while the propagation of the clock signal (command) to the far-end DRAM 110F. The time is 910 ps, and the propagation time of the DQ signal from the far-end DRAM to the buffer 105 is 520 ps.

  Further, the latency from the read command to the data output in each DRAM 110 is equal, and here, assuming that it is 8 clocks, the total signal round-trip propagation time in the near-end DRAM 110N is 198 ps, and the signal round-trip propagation time in the far-end DRAM 110F is 1430 ps. Yes, the difference is 1230 ps.

  Therefore, in the buffer 105, it is necessary to transfer data of different arrival times to the memory controller in accordance with the timing of the clock signal again. Furthermore, as is apparent from the foregoing, data from near-end and far-end DRAMs 110N and 110F arrives across different clock cycles in buffer 105. Therefore, it is necessary to identify in the buffer 110 which cycle should be matched for each data from each DRAM 110.

  Hereinafter, embodiments of the present invention in consideration of the above-described skew will be described with reference to the drawings.

  In the following embodiment, the frequency of a clock signal (herein referred to as a buffer clock signal) supplied to the DRAM is the clock supplied to the buffer 105 (herein referred to as a global clock) in order to process the skew. It is assumed that the DPS signal is generated by dividing by 1/2, and the DPS signal is transmitted at the same frequency as the divided buffer clock signal. Therefore, the command / address signal is transmitted / received in synchronization with the rise and fall of the clock signal. Furthermore, the data signal is received and transmitted at a transfer rate four times the frequency of the clock signal in synchronization with the DPS signal.

  Referring to FIG. 42, there is shown a configuration of a DRAM used in the memory system according to the first embodiment of the present invention. Here, the write / read data phase signals (WDPS / RDPS) are wired differently. An example of inputting and outputting via the interface is shown.

  The DRAM 110 shown in FIG. 42 is different from the DRAM 110 shown in other figures in that it includes a command / address receiving clock generation circuit (DLL) 500 and a domain crossing circuit 501. The illustrated clock generation circuit (DLL) 500 and domain crossing circuit 501 operate by receiving a 400 MHz buffer clock signal and a command / address signal from the buffer, respectively.

  In the illustrated embodiment, a command / address signal is fetched into the DRAM 110 at the timing of a buffer clock signal (hereinafter also referred to simply as a clock signal), and the internal data of the DRAM 110 generated based on the data phase signal (WDPS). Pass to phase clock. As a result, the command / address signal becomes an internal command generated based on the data phase (WDPS), and thereafter, the internal read / write operation of the DRAM 110 is performed by the internal command. This indicates that the internal read / write operation of the DRAM 110 is performed in synchronization with the data phase of WDPS.

  Here, the WDPS signal is represented by one clock of the global clock (represented by 1 tCK) in the buffer 105 so that the margin of the clock phase in the DRAM 110 is allocated to the setup time and the hold time with respect to the phase of the WDPS of the transfer destination. , Delayed by 180 degrees of the divided clock.

  Referring to FIG. 43, a specific configuration of the domain crossing circuit 501 provided in the DRAM 110 is shown. The illustrated domain crossing circuit 501 is a circuit for causing the command / address signal to undergo domain crossing from the phase of the buffer clock signal to the WDPS phase, and includes a first latch circuit 511 and a second latch circuit 512. . Specifically, the first latch circuit 511 includes two receivers that receive and latch command signals in response to a 0 degree phase clock and a 180 degree phase clock, while the second latch circuit 512 includes: Two flip-flop circuits that hold the command signal from the first latch circuit 511 are provided according to the data phase clocks of 0 degrees and 180 degrees.

  Here, the phase clocks of 0 degrees and 180 degrees are generated by the command / address receiving clock generation circuit 500 shown in FIG. 42, and respectively represent the phases of 0 degrees and 180 degrees of the received buffer clock signal. . On the other hand, the 0 degree and 180 degree data phase clocks represent the 0 degree and 180 degree phases of the write data phase signal (WDPS).

  As shown in FIG. 42, the 0 degree and 180 degree data phase clocks are generated by a clock recovery and phase adjustment circuit (DLL) 205 that operates in response to WDPS.

  As is clear from this, in the illustrated domain crossing circuit 501, the command signal (or address signal) is changed from 0 degree or 180 degrees phase of the buffer clock signal to 0 degree or 180 degrees of the data phase signal (WDPS). It can be seen that it is output as a DRAM internal command / address signal in synchronism with the phase.

  Referring to FIG. 44, there is shown a specific configuration of the DRAM 110 shown in FIG. 42 and the buffer 105 constituting the first embodiment of the present invention. The buffer 105 includes the DRAM 110 of FIG. 42 and the data signal DQ. Send and receive. The illustrated buffer 105 includes a clock frequency division / phase comparison adjustment circuit 601 that operates in response to a global clock supplied from a memory controller (not shown). The clock frequency division / phase adjustment comparison circuit 601 receives a global clock. The buffer clock divided by two is output to the DRAM 110 as a clock signal, while the WDPS for DRAM is output. In the figure, only the portion that outputs the WDPS for the far-end DRAM 110F is shown.

  The illustrated clock division / phase adjustment comparison circuit 601 further internally outputs the data output buffer internal clock and the WDPS buffer internal phase clock to the DQ output driver 301 and the domain crossing circuit 602, respectively. Here, the phase clock in the WDPS buffer represents 0, 90, 180, and 270 degrees of WDPS for the far-end DRAM 110.

  On the other hand, the clock recovery / phase adjustment circuit 305 that operates in response to the RDPS that is the data phase signal from the far-end DRAM 110F is a data reception buffer internal phase clock that represents the phases of 0, 90, 180, and 270 degrees of the RDPS. Is generated and supplied to the domain crossing circuit 602.

  The domain crossing circuit 602 in the buffer 105 includes a first-stage data latch circuit 611 and a second-stage data latch circuit 612. Specifically, the domain crossing circuit 602 performs domain clocking from the RDPS phase to the WDPS phase. As shown in FIG. 45, the data signal DQ read from the DRAM 110 is converted to 0, 90, The outputs of the first-stage data latch circuit 611 and the first-stage data latch circuit 611 that receive and latch in accordance with the buffer internal phase clock generated in synchronization with the phases of 180 and 270 degrees. And a second-stage data latch circuit 612 for latching. The data latch circuit 612 in the second stage latches according to the WDPS buffer internal phase clock (270, 0, 90, 180 degrees) generated by the clock frequency division / phase comparison adjustment circuit 601 shown in FIG. It has a flip-flop circuit, latches the output from the first stage data latch circuit 611 at the phase of the internal phase clock, and outputs it as a buffer internal data signal.

  With reference to FIG. 46, an operation at the time of writing according to the illustrated embodiment will be described. Here, the operation at the time of writing between the buffer 105 and the near-end DRAM 110N will be described. Here, in order for each DRAM 110 to transfer the command / address signal from the global clock, that is, from the phase domain of the buffer clock to the phase domain of the WDPS, the buffer 105 is delayed by one system clock time phase (1250 ps) and the WDPS is changed. The data is output to the near-end DRAM 110N, and the write latency (WL) is 6 system clocks.

  As shown in the drawing, when an 800 MHz global clock (first line) is received, the clock frequency division / phase comparison adjustment circuit 601 of the buffer 105 outputs a 400 MHz buffer clock to the DRAM 110 (second line). A write command (WRT) is output to the near-end DRAM 110N in synchronization with the buffer clock. On the other hand, a phase of 1 global clock (1250 ps), that is, a 400 MHz write phase signal (WDPS) is output to the near-end DRAM 110N with a ½ phase delay of the buffer clock signal. After WL, the write data signal (DQ) is output to the near-end DRAM 110N in synchronization with WDPS.

  On the other hand, the buffer clock and the write command (WRT) arrive at the near-end DRAM 110N in the propagation time after 126 ps as described above, and the WDPS arrives in the propagation time as short as 54 ps.

  As shown in FIG. 42, in the near-end DRAM 110N, the command / address reception clock generation circuit 500 generates 0 degree and 180 degree phase clocks representing 0 and 180 degrees of the received buffer clock. Further, the clock recovery / phase adjustment circuit 205 of the near-end DRAM 110N that receives the WDPS generates 0 degree and 180 degree phase data phase clocks representing the 0 and 180 degree phases of the WDPS.

  In the illustrated example, the command / address signal received by the DRAM in synchronization with the clock signal is domain-crossed from a 0 degree phase clock (buffer clock phase) to a 0 degree phase data phase clock (WDPS 0 degree phase). As a result, an internal write command (WRT) is generated in synchronization with the 0 degree phase data phase clock. This means that the domain crossing from the buffer clock phase to the WDPS phase has been performed. In response to the internally generated write command (WRT), the write operation of the data signal (DQ) is performed after 6 WL. Is done.

  The setup time and hold time for passing the command / address signal from the clock phase to the data phase of the near-end DRAM 110N having this configuration are 1196 and 1304 ps, respectively, and it can be seen that a sufficient time margin can be obtained.

  In the near-end DRAM 110N, an RDPS having the same phase as the received WDPS is generated and output to the buffer 105, and reaches the buffer 105 after a propagation time of 144 ps.

  FIG. 47 shows an operation at the time of writing between the buffer 105 and the far-end DRAM 105F of the memory system according to the above-described embodiment. As shown in the figure, the write command (WRT) is output in synchronization with the 400 MHz buffer clock, while the WDPS is output with a 1/2 phase delay of the 1250 ps delayed buffer clock signal with respect to the buffer clock. Yes. The write command (WRT), buffer clock, and WDPS have reached the far end DRAM 110F after the lapse of different delay times. The above-mentioned 390 ps skew is generated between the buffer clock and the WDPS, and is received by the far-end DRAM 110F. The far-end DRAM 110F replaces the received write command WRT with the received WDPS timing, generates a DRAM internal command (WRT) in synchronization with the received WDPS, and after 6 WL from the DRAM internal command, the data signal (DQ) Is written.

  As shown in the figure, the hold time for command / address signal passing from the clock phase to the data phase of the far-end DRAM having this configuration can be 1640 ps, and the setup time can be 860 ps. Thus, it can be seen that a sufficient timing margin can be obtained even in the far-end DRAM 110F.

  Further, as shown in the figure, the far-end DRAM 110F that has received the WDPS outputs RDPS having the same phase to the buffer 105 in synchronization with the WDPS, and the buffer 105 generates the far-end DRAM 110F at the time when 1040 ps has elapsed after the generation of WDPS. The corresponding RDPS from the corresponding phase is received. In the present embodiment, RDPS having the same phase as that of WDPS is associated. That is, the 0 degree phase of RDPS corresponds to the 0 degree phase of WDPS, the 90 degree phase of RDPS corresponds to the 90 degree phase of WDPS, and 180 degrees and 270 degrees of WDPS are similarly 180 degrees and 270 degrees of WDPS. Corresponding to

  Next, with reference to FIG. 48, a description will be given of the case of a read operation in which the buffer 105 outputs a read command (RED) to the far-end DRAM 110F in synchronization with the buffer clock in the memory system according to the above-described embodiment. As described above, when 1040 ps elapses after WPDS transmission, RDPS having a corresponding phase arrives at the buffer 105 from the far-end DRAM 110F.

  On the other hand, the far-end DRAM 110F side outputs RDPS having the same phase to the buffer 105 in synchronization with the received WDPS. The buffer 105 outputs a read command (RED) to the far end DRAM 110F in synchronization with the buffer clock. The far-end DRAM 110F takes in the read command at the timing of the buffer clock signal and transfers it to the data phase clock generated based on the WDPS. As a result, the read command signal becomes an internal command generated based on the data phase (WDPS), and thereafter, the internal read operation of the DRAM 110F is performed by the internal read command. After 8 global clocks have elapsed from the received RED, the data signal (DQ) is read out. The read data signal is output from the far-end DRAM 110F to the buffer 105 in synchronization with the RDPS, and is received by the buffer 105 after 520 ps.

  In this configuration, the domain crossing timing margin from the RDPS phase to the WDPS phase in the buffer 105 is 835 ps, and it can be seen that a sufficient timing margin can be obtained.

  Further, with reference to FIGS. 49 and 44, the operation at the time of reading in the buffer 105 in the above embodiment will be described. Here, it is assumed that the data signal (DQ) is read from the far-end DRAM 110F. Buffer 105 receives the read data signal (DQ) in synchronization with the received RDPS. The buffer 105 shown in FIG. 44 generates a 4-phase data reception buffer internal clock (0, 90, 180, 270 degrees) representing the phase of the RDPS from the RDPS, and the first stage of the domain crossing circuit 602. To the data latch circuit 611. Therefore, the data signal (DQ) from the far-end DRAM 110F is stored in the first-stage data latch circuit 611 in synchronization with these four-phase data reception buffer internal clocks, and then the second-stage data latch. This is supplied to the circuit 612.

  The second-stage data latch circuit 612 is supplied with a 4-phase buffer internal phase clock obtained from the WDPS (global clock) generated by the buffer 105 from the clock frequency division / phase comparison adjustment circuit 601. The output of the first-stage data buffer 611 is stored in the second-stage data latch circuit 612 according to the four-phase buffer internal phase clock. As a result, the data signal (DQ) read from the far-end DRAM 110F is output from the buffer 105 to the memory controller in the form of being replaced with the internal clock generated in the buffer 105.

  Next, the operation of the buffer 105 when processing the data signal (DQ) from the near-end and far-end DRAMs 110N and 110F during the read operation will be described with reference to FIG. Assume that the near-end and far-end DRAMs 110N and 110F output a WDPS delayed by 1/2 phase with respect to the read command (RED) and the buffer clock from the buffer 105 in synchronization with the buffer clock. In this case, as shown in the figure, the RDPS signal having the same phase is input to the buffer 105 at a timing delayed by 144 ps from the corresponding phase of the WDPS signal from the near-end DRAM 110N, and delayed by 1040 ps from the far-end DRAM 110F. Input at the timing. Here, when the (8 + 2.5) global clock time has elapsed after the generation of the read command (RED), it is assumed that the buffer 105 is set to start the data capturing operation. The hold time for changing the timing from the RDPS phase to the WDPS phase, ie, the clock phase, of the data signal (DQ) read out in synchronization with the RDPS of the far-end DRAM is 770 and 1665 ps, and the setup time is 1731 and 835 ps, respectively. It can be seen that a sufficient time margin is secured.

  More generally, the above-described operation will be described. A buffer clock signal obtained by dividing a system clock (global clock) signal by n and a data phase signal (WDPS) having the same frequency as the buffer clock signal are supplied from the buffer 105 to the DRAM. Is done. On the other hand, the command / address signal is transmitted from the buffer 105 in alignment with the buffer clock signal. When the command address signal transferred within the period is m times at the maximum, each command address signal is received by one of the internal clock signals generated from the timing of the buffer clock signal every 1 / m phase in the DRAM. The

  On the other hand, in each DRAM 110, the internal data phase clock internally generated for each 1 / m phase from the timing of the data phase signal (WDPS) transmitted from the buffer 105 is received by one associated in advance. Passed to generate an internal command address signal.

  The data signal written in each DRAM 110 is transmitted from the buffer 105 to the DRAM 110 in synchronization with the timing of the data phase signal (WDPS). When the data signal transferred within the cycle is k times at the maximum, the DRAM 110 receives the data signal from the buffer 105. The data is received and stored in each DRAM 110 by one of internal clock signals generated every 1 / k phase from the timing of the transmitted data phase signal (WDPS).

  On the other hand, the data signal read from the DRAM 110 is transmitted from the DRAM 110 in alignment with the timing of the data phase signal (RDPS), and is 1 / k phase from the timing of the data phase signal (RDPS) transmitted from the DRAM 110 in the buffer 105. It is received by one of the internal clock signals generated every time. This RDPS is transferred to one of the internal clocks internally generated for each 1 / k phase from the timing of the data phase signal (WDPS) originally generated in the buffer 105, and is read internally. A data signal is generated.

  In this case, the command / address signal is transmitted from the buffer 105 in synchronization with the rising and falling edges of the buffer clock signal, and is taken into the DRAM in synchronization with the rising and falling edges of the buffer clock signal.

  Referring to FIG. 51, there is shown a DRAM 110 used in a memory system according to a second embodiment of the present invention. The DRAM 110 according to this embodiment has a configuration in which a data signal is taken into the DRAM 110 with a phase clock generated from the WDPS and transferred to the phase clock generated from the buffer clock signal. Therefore, the illustrated DRAM 110 includes a clock recovery / phase adjustment circuit 521 that operates in response to WDPS, and the clock recovery / phase adjustment circuit 521 is connected to the reception replica 523 and the reception phase comparison circuit 525. The clock recovery / phase adjustment circuit 521 shown in the figure is under the control of the reception phase adjustment signal from the reception phase comparison circuit 525, and the four-phase data reception DRAM internal phase clock (0, 90, 180, 270 degrees) from the WDPS. Is supplied to the data latch circuit 527 at the first stage of the domain crossing circuit 501.

  On the other hand, the buffer clock signal is supplied to a clock recovery / phase adjustment circuit (DLL) 205, and the clock recovery / phase adjustment circuit 205 generates a four-phase phase clock, and the phase clock is supplied to the second of the domain crossing circuit 501. This is supplied to the data latch circuit 529 at the stage.

  Referring also to FIG. 52, the data latch circuit 527 of the first stage of the domain crossing circuit 501 is supplied with the data signal (DQ) from the buffer 105, and further, a four-phase data receiving DRAM generated from the WDPS. An internal phase clock is supplied from the clock recovery / phase adjustment circuit 521. Therefore, the first-stage data latch circuit 527 constituted by four receivers / latches receives and latches the data signal (DQ) at the timing of the four-phase data receiving DRAM internal clock, and outputs four signals respectively. The data is output to the second-stage data latch circuit 529 composed of a flip-flop circuit.

  The four flip-flop circuits of the second-stage data latch circuit 529 are each supplied with a four-phase DRAM internal phase clock, and the output from the first-stage data latch circuit 527 is the four-phase DRAM. Stored in accordance with the internal phase clock and output as a DRAM internal data signal.

  Further, the clock recovery / phase adjustment circuit 205 generates a two-phase clock of 0, 180 degrees from the buffer clock signal and supplies it to the command address receiver 531. The command address receiver 531 takes in the command / address signal in accordance with the two-phase phase clock and outputs it as an internal command / address signal. Thus, the internal command / address signal is generated in the buffer clock phase, and the internal read / write operation of the DRAM is performed in synchronization with the buffer clock phase.

  Referring to FIG. 53, a specific example of the buffer 110 used in connection with the DRAM 110 is shown. A clock division / phase comparison / adjustment circuit 601 included in the illustrated buffer 110 supplies a four-phase clock inside the buffer to the domain crossing circuit 602, and further sends a four-phase internal data output buffer to the DQ driver 301. It differs from the buffer 105 shown in FIG. 44 in that it outputs a clock. Further, the illustrated domain crossing circuit 602 is provided with a data reception buffer internal four-phase clock generated based on the RDPS by the clock recovery / phase adjustment circuit 305.

  Referring also to FIG. 54, the first-stage data latch circuit 611 of the domain crossing circuit 602 shown in FIG. 53 receives and latches the data signal (DQ) with the internal phase clock of the four-phase data reception buffer. Four receivers are provided, and the output of each receiver is supplied to four flip-flop circuits constituting the second stage data latch circuit 612. These flip-flop circuits latch the output of the first-stage data latch circuit according to the four-phase buffer internal phase clock. As shown in the figure, the data latch circuit 611 in the first stage receives and latches with a data reception buffer phase clock of 0, 90, 180, and 270 degrees, that is, a clock representing the phase of RDPS. The output is latched in the second-stage data latch circuit 612 by internal phase clocks of 270, 0, 90, and 180 degrees, respectively, and it can be seen that the data signals are latched by different phase clocks. In other words, in the illustrated example, it can be seen that the phase is changed to a phase that is 90 degrees ahead in the phase of the buffer clock signal.

  A write operation between the buffer 105 and the near-end DRAM 110N will be described with reference to FIG. The buffer 105 outputs WDPS to the near-end DRAM 110N. This WDPS is only 90 degrees (1/2 clock of global clock; 625 ps) with respect to the buffer clock signal in order to secure a time margin for transferring the data signal (DQ) from the WDPS phase domain to the clock phase domain in the DRAM 110. It has a preceding phase.

  In the figure, the write command WRT is output from the buffer 105 to the near-end DRAM 110N in synchronization with the buffer clock. On the other hand, the data signal (DQ) is output from the buffer 105 in synchronization with WDPS after a write latency of 6 clocks with the global clock.

  The buffer 105 outputs a buffer command and a write command (WRT) synchronized with the buffer clock, and outputs the WDPS in alignment with the buffer clock. In this case, the write command (WRT) and the WDPS (ie, DQ) are received by the near-end DRAMN with a propagation delay difference of 54 ps.

  When the data signal (DQ) is output from the buffer 105 in synchronization with WDPS after 6 write latencies (WL) from the received write command, it is taken into the DRAM 110N with the data phase clock generated from WDPS, and the buffer clock It is passed to the phase clock generated from the signal. Here, the hold time and setup time for domain crossing from the data phase to the clock phase are 1821 ps and 679 ps, respectively. The near-end DRAMN shown in the figure outputs the RDPS to the buffer 105 at the timing of the received buffer clock, and the RDPS is input to the buffer 105 after 72 ps, that is, 198 ps after the phase of the corresponding global clock.

  Referring to FIG. 56, a write operation for the far end DRAMF is shown. In this case, if a skew propagation delay time difference of 390 ps exists between the write command (WRT) received by the far-end DRAMF and the data signal (DQ), the buffer clock and the WDPS There is a similar skew. Considering this, the phase of WDPS is advanced 90 degrees, and domain crossing from the WDPS phase to the buffer clock phase is performed. As a result, also in the far-end DRAMF, as shown in the drawing, a hold time of 1485 ps and a setup time of 1015 ps are secured for domain crossing from the data phase to the clock phase, and a sufficient timing margin is obtained.

  At the time of reading, as shown in FIG. 57, the DRAM 110 transmits RDPS to the buffer 105 in the same phase as the buffer clock phase, and the data signal (DQ) is sent to the buffer 105 in alignment with the RDPS. Then, the data signal is captured by a phase clock signal generated from RDPS. In this way, by passing to the phase clock signal generated based on the clock signal in the buffer 105, it is possible to align with the clock phase in the buffer 105.

  In the buffer 105, the RDPS phase in the buffer 105 is transferred so that the RDPS of 0 degrees and the clock signal of 270 degrees correspond to each other so that a margin is allocated to the setup time and the hold time with respect to the phase of the transfer destination clock. I do.

  With this operation, as shown in FIG. 58, when read data from the near and far end DRAMs is received by the buffer 105, sufficient setup time and hold time are secured. In the illustrated example, the near-end DRAM N can secure a hold time of 823 ps and a setup time of 1677 ps, while the far-end DRAM F can secure a hold time of 2055 ps and a setup time of 445 ps. In the illustrated example, in the data signal read operation, the total latency is equal to the sum of the read time in the DRAM and 1.5 clocks.

  As is clear from the foregoing, the command / address receiving clock generation circuits 500 and 521, the domain crossing circuit 501, and the clock recovery / phase adjustment circuit 205 in the DRAM 110 shown in FIGS. It operates as a DRAM side circuit that absorbs a skew with the address signal, and on the other hand, the clock frequency division / phase comparison adjustment circuit 601, the domain crossing circuit 602, and the clock reproduction / phase of the buffer 105 in FIGS. The adjustment circuit 305 operates as a buffer side circuit that absorbs skew.

  In the two embodiments described above, the clock signal and data phase signal (W / RDPS) supplied to the DRAM are generated by dividing the system clock signal (ie, global clock) by 2 in the buffer 105. Further, in the DRAM and in the buffer 105, a clock phase signal and a data phase signal are generated every 1/2 phase for a command / address signal and 1/4 phase for a data signal. In addition, internally generated clock phase signals and data phase signals having different phases are associated with each other, and timing between clocks of received signals is transferred. In this case, since the cycle of the signal of each associated phase is twice that of the system clock signal, it is possible to secure a margin for the setup time and hold time with respect to the transfer destination phase signal as described above.

  In this case, it is ideal that the margin for the setup time and hold time is such that the edge of the phase signal that captures the signal to be delivered is exactly in the middle of the phase signal of the delivery destination. In order to approach it, the phase of the WDPS in the buffer may be adjusted by delaying or leading the phase with respect to the clock signal.

  Also, when aligning DQ signals from DRAMs in the buffer, select the phase signal on the delivery side so that the RDPS edge from the far end and near end approaches the middle of the WDPS or clock signal that is the phase signal of the delivery destination Just do it. In the above-described embodiment, it is clear that the DQ timing from the DRAM is aligned by making the WDPS or 270 degree phase signal of the clock signal correspond to the 0 degree phase signal of the RDPS.

  Further, the flight time not synchronized with the clock on the module until the DQ signal is transmitted from the DRAM to the buffer is the time for the data signal to reciprocate between the buffer and the DRAM in the case of the first embodiment. In the case of the embodiment, it is the sum of the time required for transmitting the read command from the buffer to the DRAM and the time required for transmitting the data signal from the DRAM to the buffer. In the first embodiment described above, the maximum (in the case of a far-end DRAM) is 1040 ps, and in the second embodiment, the maximum is 1430 ps. By dividing the system clock signal by 2, processing is performed in one cycle (2500 ps) ( To the original clock phase on the buffer).

  A memory system according to the third embodiment of the present invention will be described with reference to FIG. In this embodiment, DPS (Data Phase Signal) is used, and transmission / reception of a differential signal DPS is enabled while suppressing an increase in the number of wires. In this embodiment, the RDPS transmitted from the DRAM and the WDPS transmitted from the buffer 105 are transmitted and received through a common signal line, and a control signal (indicate) is transmitted from the buffer 105 to the DRAM 110. Different from the other embodiments. This control signal (indicate) is a signal for switching on the DRAM 110 side between a period for receiving the data phase signal (WDPS) from the buffer 105 and a period for transmitting the data phase signal (RDPS) to the buffer 105. On the other hand, the buffer 105 switches transmission / reception of the data phase signal (DPS) in the buffer 105 according to its own control signal (indicate).

  Since the control signal can be shared by the DRAM 110 on the module as shown in FIG. 59, only one wiring for the control signal (indicate) is added.

  In the memory system (that is, the memory module 103) according to the third embodiment described above, when the signal line is shared between the RDPS and the WDPS, the drive circuit needs to be in an open drain format. It is possible to use a push-pull (CMOS driver), and it can be a differential signal, thereby improving the timing accuracy.

  Referring to FIG. 60, the configuration of DRAM 110 used in this embodiment is shown, while in FIG. 61, the configuration of buffer 105 is shown. As is clear from FIG. 61, a DPS control signal generation circuit 701 is provided in the buffer 105, a control signal (indicate) is transmitted from the control signal generation circuit 701 to the DRAM 110, and an internal control signal is transmitted to the DPS control signal generation circuit. 701 is output to the clock frequency division / phase comparison adjustment circuit 601, the clock recovery / phase adjustment circuit 305, and the reception phase comparison circuit 306.

  The DRAM 110 shown in FIG. 60 receives a control signal (indicate), switches the mode of the DPS driver 207, and changes the state of the clock recovery / phase adjustment circuit 521 and the reception phase comparison circuit 525. It has. Other components have already been described and will not be described in detail here.

  Referring to FIG. 62, there is shown a timing at which a period for transmitting the data phase signal from the buffer 105 and a period for transmitting the data phase signal from the DRAM are switched by a control signal (indicate) transmitted from the buffer 105. In the illustrated example, both periods are switched alternately.

  FIG. 63 shows a case where the indicate switching period is lengthened in order to lock on the DLL at the time of initialization, and the switching period is made shorter than that at the time of initialization for fine adjustment during normal operation. As described above, the buffer 105 can be locked on the DLL by lengthening the switching period at the time of initialization, and can cope with fluctuations due to noise of the operation by shortening the switching period at the time of normal operation. it can. In this configuration, the phase holding time in the DRAM becomes long at the initialization for fine adjustment, but there is no problem because the phase fluctuation due to operation noise is small.

  In the above embodiment, the global clock cycle, that is, the effective operating frequency is set to 800 MHz, and the setup time and hold time are estimated. However, if the frequency is relaxed, the setup time and hold time are also relaxed accordingly. What is necessary is just to perform the said phase adjustment with the highest frequency anticipated at the time of module design.

  In the above-described embodiment, only the memory system including the buffer on the memory module has been described. In other words, only the memory system in which memory modules can be added has been described above. However, the present invention can be similarly applied to a memory system having a configuration in which a single memory module in which no buffer is mounted on the memory module is controlled by a memory controller. In such a memory system, the buffer function in the above-described embodiment may be performed by a memory controller.

  Referring to FIG. 64, an example of the above-described memory system is shown as still another embodiment of the present invention. The illustrated memory system 1000 includes a memory controller 1011, a clock generator 102, and a single module 1031. On the module 1031, there are four (1 to 4) on the left side and five (1 to 1) on the right side. The DRAM 110 of “˜5”) is mounted. In other words, the illustrated memory system is substantially equivalent to a memory system provided with a memory controller 1031 instead of the buffer 105 in the memory system 1000 shown in the other figures. In the illustrated example, the memory controller 1031 and the DRAM 110 are connected by an equal-length data wiring DQ, and the arrival time of the data signal DQ from the memory controller 1011 in each DRAM 110 is substantially the same.

  The left four DRAMs 110 (1 to 4) on the module 1031 are connected to the memory controller 1011 via the common clock wiring and command / address wiring, and the right five DRAMs 110 (1 ′ to 5 ′). ) Is also commonly connected to the memory controller 1011 via a separate clock line and command / address line. That is, it can be seen that the left and right DRAMs 110 (1 to 4) and (1 'to 5') are connected by separate clock lines and command / address lines.

  In the DRAMs 110 (4) and (5 ′) arranged at the far end in the memory system having the illustrated topology, the lengths of clock and address / command lines between the memory controller 1011 and the memory controller 1011 There is a large difference in wiring length between the data wiring DQ.

  Therefore, the propagation delay difference from the memory controller 1011 between the clock signal (command / address signal) and the data signal DQ in the DRAMs 110 (4) and (5 ') is larger than the propagation delay difference in the module.

  For example, in the illustrated example, if the DRAM pitch is 13 mm and the signal unit propagation time tPD is 14 ps / mm, the delay of the command / address signal on the module 1031 is 728 ps (13 × 4 × 14) in the DRAM 110 (4). On the other hand, in the DRAM 110 (5 ′), it becomes 910 ps (13 × 5 × 14). If the propagation delay of the data signal DQ and the clock and command / address signal from the memory controller 1011 to the input terminal of the module 1031 are equal, the delay on the module 1031 described above is between the command / address signal and the data signal DQ. It becomes a skew difference.

  The fourth embodiment of the present invention is a memory system 1000 that processes the above-described skew difference using a domain crossing technique using the above-described DPS (data phase signal). Referring to FIG. 65, a write operation in the memory system 1000 shown in FIG. 64 is shown. First, the clock generator 102 generates an 800 MHz reference clock (that is, a system clock) and supplies it to the memory controller 1011. The memory controller 1011 divides the reference clock (system clock) by 1/2 to generate a 400 MHz system clock, and generates a write command (WRT) in alignment with the system clock.

  Further, the memory controller 1011 shown in FIG. 64 generates DPS (WDPS) 90 degrees ahead of the clock signal, and this WDPS is transmitted to the DRAM 110. In FIG. 65, only the case where the WDPS is transmitted to the DRAM 110 (1 ′ to 5 ′) is shown. In this way, by generating a DPS having a preceding phase with respect to the clock signal, the setup time and hold time for domain crossing from the clock phase of the command / address signal to the DPS, that is, the data signal DQ phase in the DRAM 110 are reduced. Both can secure a margin. That is, the timing adjustment for the domain crossing can be performed by using the DPS whose phase is shifted with respect to the clock signal.

  In FIG. 65, when the DRAM 110 (1 ′) receives a signal that matches the write command (WRT), the WRT is replaced with the DPS received by the DRAM 110 (1 ′) and matches the received DPS. WRT is generated as a DRAM internal command (DRAM internal Command). After the generation of the internal command, the DRAM 110 (1 ') performs a data signal write operation after six write latency times.

  On the other hand, the clock signal and WRT delayed from the DRAM 110 (1 ') are given to the DRAM 110 (5'), and further, DPS is given 965ps later than the clock signal. In this state, the DRAM 110 (5 ′) fetches WRT in conformity with the DPS and generates it as an internal command (DRAM InternalCommand). As is clear from FIG. 65, it is understood that sufficient setup time and hold time are secured in the DRAMs 110 (1 ') and (5') by performing the above-described domain crossing.

  Referring to FIG. 66, a read operation in the memory system 1000 shown in FIG. 64 is shown. Similar to the write operation, the memory controller (MC) 1011 generates a read command (RED) in alignment with a 400 MHz clock signal. The memory controller (MC) 1101 also generates a DPS (RDPS) having a phase that is 90 degrees ahead of the clock signal.

  The clock signal (CLK) and the read command (RED) from the memory controller 1011 arrive at the DRAM 110 (1 ′ to 5 ′) after different propagation delay times, respectively, while the DPS passes through the equal-length data wiring. The DRAM 110 (1 ′ to 5 ′) arrives at substantially the same timing.

  The remote DRAM 110 (5 ') will be described as an example. The DRAM 110 (5') receives a read command (RED) in alignment with a clock signal and receives a DPS. The DPS is generated by the memory controller (MC) and is supplied to the remote DRAM 110 (5 ') after a delay time of 700 ps, like the DPS given to the other DRAM 110. The RED received in alignment with the clock signal is generated in the remote DRAM 110 (5 ') as an internal command signal (DRAM Internal Command) by being replaced with the DPS received in the remote DRAM 110 (5'). Thus, domain crossing is performed from the timing of the clock signal to the timing of DPS.

  On the other hand, in the memory system 1000 shown in FIG. 64, the arrival time of the data signal DQ from the memory controller 1011 in each DRAM 110 is substantially the same. However, the memory controller 1011 needs to identify which read command (RED) the data signal DQ received from each DRAM 110 corresponds to. Therefore, the memory controller 1011 receives the DPS from the DRAM 110 and changes the timing of the received DPS to the timing of the WDPS of the memory controller (MC), that is, performs domain crossing. The memory controller (MC) 1011 receives the data signal DQ read from the DRAM 110 in conformity with the DPS (R) from the DRAM 110, and the data signal DQ is received from the DPS (W) of the memory controller (MC) 1011. It will be transferred to the timing. That is, the data signal DQ received by the memory controller (MC) 1011 in the phase of DPS (R) is returned to the phase of DPS (W), that is, the phase of the clock signal.

  Therefore, the memory controller (MC) 1011 can identify which read command (RED) corresponds to the data signal DQ by counting the number of clocks from the issue of the read command (RED).

  In FIG. 66, it is assumed that the distance between the memory controller (MC) 1011 and the module 1031 is 100 mm. In this case, in the memory controller (MC) 1011, the delay time from transmission of DPS (W) to reception of DPS (R) of the corresponding phase is 1400 ps. In this case, setup for domain crossing is performed. The time and hold time are 1400 ps and 1100 ps, respectively, and a sufficient timing margin can be obtained.

  In FIG. 66, DPS (W) is transmitted from the memory controller (MC) 1011 to the DRAM 110, and the DPS (R) is transmitted to the memory controller (MC) 1011 in the same phase as the received DPS (W). .

  Therefore, it can be seen that in this embodiment, a method of transmitting DPS bidirectionally on the same DPS wiring is adopted. Therefore, in practice, a configuration is adopted in which the DPS is alternately transmitted between the memory controller (MC) 1011 and the DRAM 110 and the internal clock signal is regenerated based on the received DPS.

  In the embodiment shown in FIG. 64, two sets of command / address signals and clock signals are generated from the memory controller (MC) 1011 to the memory module 1031. A similar operation can be performed by generating a clock signal from the memory controller (MC) 1011.

  Referring to FIG. 67, the memory system 1000 according to the fifth embodiment of the present invention has a configuration in which nine DRAMs 110A (1) to (9) are mounted on a module 1031 as in FIG. A command / address signal and a clock signal common to all the DRAMs 110 are supplied to the DRAMs 110 from the memory controller 1011 through the left end of the module 1031. That is, the nine DRAMs 110 share a command / address signal and a clock signal. In this case, assuming that the same propagation delay as in FIG. 64 occurs, the farthest end DRAM 110 (9) uses (728 + 910) ps (= 1638 ps) as the command address signal and clock signal for the data signal DQ. Difference in propagation delay occurs. Even when domain crossing is performed at a clock signal period of 2500 ps obtained by dividing the large propagation delay difference by 2, it is difficult to secure a sufficient timing margin for domain crossing. Therefore, in order to ensure a sufficient timing margin for domain crossing, it is conceivable to use a frequency-divided clock having a period longer than the frequency division by two.

  As another method for securing a sufficient time margin necessary for domain crossing by using the divided clock as it is, as shown in FIG. 67, the DRAM 110 is arranged in two groups (here, the first group). It is conceivable to divide into 1 and 2 DQ channels). In this case, the memory controller (MC) 1011 shifts the phase of DPS (W) applied to the first and second DQ channels with respect to the clock signal. That is, in the illustrated memory controller (MC) 1011, the phase offset value with respect to the DPS (W) clock signal is set to a value suitable for the first and second DQ channels.

  In the illustrated example, for the first DQ channel, the phase of DPS (W) is 90 degrees ahead of the clock signal, and for the second DQ channel, DPS (W) is clock signal. And transmit in the same phase.

  Referring to FIG. 68, the write operation in DRAMs 110 (1) to (4) belonging to the first DQ channel will be described. First, the memory controller (MC) 1011 generates a 400 MHz clock signal by dividing the 800 MHz reference clock signal generated by the clock generator 102 by 2, and this clock signal is the DRAM 110 belonging to the first DQ channel. (1) to (4) are supplied via a clock wiring. Further, the memory controller (MC) 1011 further supplies a write command WRT onto the command / address wiring in alignment with the clock signal.

  On the other hand, DPS (W) is supplied to the DRAMs 110 (1) to (4) of the first DQ channel via DPS wiring having a length of about 100 mm. In this case, as is clear from FIG. 68, the phase of DSP (W) precedes the phase of the clock signal by 90 degrees (ie, 625 ps).

  The DPS (W) generated by the memory controller (MC) 1011 reaches the DRAMs 110 (1) to (4) of the first DQ channel via the DPS wiring. On the other hand, the clock signal and the write command (WRT) arrive at the DRAMs 110 (1) to (4) of the first DQ channel via the clock wiring and the command / address wiring. Since the clock wiring and the command / address wiring are longer than the DPS wiring, the propagation delay time of the clock signal and the write command (WRT) becomes longer, and the propagation delay time difference between the DPS and the write command (WRT) in the DRAM 110 (1). Has spread to 807 ps. The DRAM 110 (1) generates a DRAM internal command (Internal Command) when 1693 ps has elapsed after receiving WRT. This indicates that in the DRAM 110 (1), the write command (WRT) matched with the clock signal is replaced with the received DPS timing.

  Further, among the DRAMs 110 belonging to the first DQ channel, the propagation delay time difference between the DPS (W) and the clock signal in the DRAM 110 (4) located at the far end is 1353 ps. Also in this case, a time margin of 1147 ps can be secured by replacing the write command (WRT) with the DPS timing. This time margin ensures the setup and hold time required for domain crossing.

  Referring to FIG. 69, a read operation in DRAMs 110 (1) to (4) belonging to the first DQ channel is shown. Also in this example, the read command (RED) is supplied from the memory controller (MC) 1011 to the DRAMs 110 (1) to (4) in alignment with the clock signal, and the DPS is generated in a form 90 degrees ahead of the clock signal. This is the same as the case of the write command. Here, assuming that the distance between the memory controller (MC) 1011 and the module 1031 is 100 mm and the signal unit propagation time tPD is 7 ps / mm, the DPS is 700 ps later, and then the DRAM 110 (here, (4)). To reach. The DRAM 110 (4) generates an internal read command (Internal Command) by replacing the read command (RED) with the DPS, while transmitting the DPS (R) to the memory controller (MC) 1011, and the DPS (R) Is received by the memory controller (MC) 1011 after 1400 ps has elapsed since the generation of the DPS (W). The data signal DQ from the DRAM 110 (4) is received by the memory controller (MC) 1011 at a timing matched with DPS (R).

  The memory controller (MC) 1011 changes the timing of the data signal DQ to the timing of the DPS (W) by subjecting the received DPS (R) timing to the DPS (W) timing. As a result, a time margin of (1400 + 1100), that is, 2500 ps can be obtained even during the read operation.

  Next, with reference to FIG. 70, a write operation of DRAMs 110 (5) to (9) belonging to the second DQ channel in memory system 1000 shown in FIG. 67 will be described. As is apparent from FIG. 70, the memory controller (MC) 1011 generates a 400 MHz clock signal and a write command WRT that matches the clock signal for the second DQ channel, and has the same phase as the clock signal. DPS (W) is generated. Thus, in this embodiment, the DPS (W) for the DRAMs 110 (5) to (9) belonging to the second DQ channel is replaced with the DPS (W) for the DRAMs 110 (1) to (4) belonging to the first DQ channel. On the other hand, an offset value corresponding to 90 degrees of the clock signal is set so that domain crossing can be performed even if there is a large propagation delay difference between the clock signal and the data signal DQ.

  More specifically, the clock signal (CLK) and WRT from the memory controller (MC) 1011 reach the DRAMs 110 (5) to (9) of the second DQ channel through long wires, respectively, while DPS (W ) Is provided to each of the DRAMs 110 (5) to (9) via a relatively short DPS wiring. FIG. 70 shows only the operations of the DRAMs 110 (5) and (9).

  As is clear from FIG. 67, the DPS (W) arrives at the DRAM 110 (5) earlier by 910 ps than the clock signal and WRT, and after 1590 ps, the DPS (W) is received by the DRAM 110 (5). Can be replaced. Therefore, in the DRAM 110 (5), the setup and hold time necessary for domain crossing can be secured.

  On the other hand, in the farthest end DRAM 110 (9) of the second DQ channel, as apparent from FIG. 67, the clock signal and WRT are generated by the memory controller (MC) 1011 and then 1638 ps from DPS (W). Only later arrives at the DRAM 110 (9). The farthest end DRAM 110 (9) generates an internal command (Internal Command) by replacing the received WRT with the received DPS (W). At this time, since there is a time margin of 862 ps between WRT and DPS (W), it can be seen that setup and hold times necessary for domain crossing are secured.

  A read operation in the second DQ channel DRAM 110 (5) to (9) will be described with reference to FIG. Also in this case, the clock signal and the read command (RED) are transmitted from the memory controller (MC) 1011 to the DRAMs 110 (5) to (9) in the same phase as the DPS (W).

  Of the second DQ channel DRAM 110, DPS (W) reaches 1638 ps earlier than RED to the farthest end DRAM 110 (9), as in the case of WRT. As a result, RED corresponds to the timing of the clock signal. It is replaced with the DPS (W) timing received by the DRAM 110 (9).

  On the other hand, when the DPS (W) is generated by the memory controller (MC) 1011, the DPS (W) arrives at the DRAM 110 (9) after 700 ps, and the received DPS (W) is directly used as the DRAM 110 (9). Is transmitted to the memory controller (MC) 1011 as DPS (R), and the DPS (R) delayed by 1400 ps is generated by the memory controller (MC) 1011.

  The data signal DQ from the DRAM 110 (9) is transmitted to the memory controller (MC) 1011 at the timing of the DPS (R). As shown in FIG. 71, the memory controller (MC) 1011 changes the data signal DQ sent at the timing of DPS (R) to the timing of DPS (W) in the memory controller (MC) 1011. The time margin at this time is 2500 ps as shown in the figure, and it can be seen that a time margin sufficient for performing the domain crossing can be secured.

  As described above, in the memory controller (MC) 1011, the read data signal DQ has a time difference corresponding to an offset between channels, but a time margin necessary for domain crossing from the DPS (R) to the clock phase is sufficiently secured. .

  As described above, the memory controller 1011 operates in response to the system clock from the clock generator 102 and can perform the same operation as the buffer in the first to third embodiments. The global clock and the system clock given to each can be collectively called a main clock.

1 is a block diagram for explaining a memory system according to a first embodiment of the present invention. FIG. 2 is a schematic actual wiring diagram for explaining an actual structure of the memory system shown in FIG. 1. FIG. 3 is a cross-sectional view for more specifically explaining wiring of the memory system shown in FIGS. 1 and 2. It is a block diagram which shows the memory system which concerns on the 2nd Embodiment of this invention. FIG. 5 is a schematic substantial wiring diagram showing the memory system shown in FIG. 4. It is a block diagram which shows the memory system which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the 1st modification of the memory system which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the 2nd modification of the memory system which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the 3rd modification of the memory system which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the 4th modification of the memory system which concerns on the 3rd Embodiment of this invention. In the 1st thru | or 3rd embodiment of this invention, it is a block diagram explaining the transmission system between a memory controller and a buffer. 12 is a time chart for explaining the operation of the transmission method shown in FIG. 12 is a time chart for explaining an operation at the time of writing in the transmission method shown in FIG. 12 is a time chart for explaining an operation at the time of reading in the transmission system shown in FIG. 12 is a time chart for explaining an operation related to a command / address signal of the transmission method shown in FIG. It is a block diagram explaining the transmission system between the buffer used for the memory system which concerns on the 1st thru | or 3rd embodiment of this invention, and DRAM. (A) And (b) is a time chart explaining the write-in and read-out operation | movement in the transmission system of FIG. 16, respectively. FIG. 18 is a block diagram illustrating a transmission scheme of the present invention that can further speed up the transmission scheme described with reference to FIGS. 16 and 17. It is a circuit diagram which shows the structure of the buffer part which employ | adopted the transmission system of FIG. 18, and the driver part of DRAM. FIG. 19 is a circuit diagram illustrating another configuration example of a buffer and a driver portion of a DRAM adopting the transmission method of FIG. 18. (A) And (b) is a time chart explaining the write-in and read-out operation | movement at the time of employ | adopting the transmission system of FIG. 20, respectively. FIG. 19 is a time chart schematically illustrating signal timing relationships in the transmission method of FIG. 18. FIG. It is a block diagram explaining the structure of DRAM which can implement | achieve the transmission system shown by FIG. It is a block diagram explaining the structure of the buffer which can implement | achieve the transmission system shown by FIG. 24 is a timing chart for explaining a timing relationship at the start of operation in the DRAM shown in FIG. 24 is a timing chart for explaining a timing relationship during normal operation in the DRAM shown in FIG. FIG. 25 is a time chart for explaining a timing relationship at the time of reading from the buffer shown in FIG. 24. FIG. It is a block diagram which shows the example of DRAM which can implement | achieve the transmission system based on this invention. FIG. 29 is a block diagram of a buffer that can send and receive signals to and from the DRAM shown in FIG. 28. FIG. 29 is a time chart for explaining the operation of the DRAM shown in FIG. 28. FIG. It is a block diagram explaining the modification of the transmission system between a buffer and DRAM. FIG. 32 is a timing chart for explaining an operation during reading of the DRAM shown in FIG. 31. FIG. FIG. 32 is a timing chart illustrating an operation during writing of the DRAM illustrated in FIG. 31. FIG. FIG. 32 is a block diagram specifically illustrating a configuration of a DRAM shown in FIG. 31. FIG. 32 is a block diagram specifically illustrating a configuration of a buffer illustrated in FIG. 31. FIG. 36 is a timing chart for explaining a timing relationship in the DRAM and buffer of FIGS. 34 and 35. FIG. 35 is a timing chart for more specifically explaining the operation of the DRAM shown in FIG. 36 is a timing chart for explaining the operation of the buffer shown in FIG. 35. FIG. 32 is a block diagram illustrating another example of a DRAM that can be applied to the transmission method illustrated in FIG. 31. FIG. 40 is a block diagram illustrating an example of a buffer that can cooperate with the DRAM illustrated in FIG. 39. 1 is a block diagram for explaining a memory module according to an embodiment of the present invention. It is a block diagram explaining DRAM used for the memory module concerning the 1st example of the present invention. FIG. 43 is a block diagram specifically illustrating a domain crossing circuit in the DRAM illustrated in FIG. 42. FIG. 44 is a block diagram for explaining a buffer constituting the memory module according to the first embodiment together with the DRAM shown in FIG. 43. FIG. 45 is a block diagram showing a domain crossing circuit in the buffer of FIG. 44. 44 is a timing explaining a write operation of a buffer and a near-end DRAM used in the memory system shown in FIGS. This is a timing for explaining the write operation of the buffer and the far-end DRAM used in the memory system shown in FIGS. It is a time chart explaining the read operation between a far end DRAM and a buffer. 6 is a timing chart for explaining the operation of a buffer during a read operation. 6 is a timing chart for explaining the operation of the buffer when reading data from the near-end and far-end DRAMs is read. It is a block diagram which shows DRAMM used for the memory system which concerns on the 2nd Example of this invention. FIG. 52 is a block diagram showing a specific configuration of a domain crossing circuit used in the DRAM shown in FIG. 51. FIG. 52 is a block diagram showing a buffer constituting the second embodiment of the present invention together with the DRAM shown in FIG. 51. FIG. 54 is a block diagram showing a specific configuration of a domain crossing circuit used in the buffer shown in FIG. 53. 10 is a timing chart for explaining a write operation between a buffer and a near-end DRAM in the second embodiment. It is a timing chart explaining the write operation between the buffer and the far-end DRAM in the second embodiment. It is a timing chart explaining the read operation between the buffer and the far-end DRAM in the second embodiment. 6 is a timing chart for explaining the operation of a buffer for processing read data signals from the near-end and far-end DRAMs. It is a block diagram explaining the memory system which concerns on 3rd Example of this invention. FIG. 60 is a block diagram showing a configuration of a DRAM used in the embodiment shown in FIG. 59. It is a block diagram which shows the structure of the buffer used for a 3rd Example. It is a timing chart explaining the operation | movement in a 3rd Example. 12 is a timing chart for explaining a case where the operation at the time of DRAM initialization and the operation at the time of normal operation are different from each other in the third embodiment. It is a block diagram explaining the memory system which concerns on the 4th Example of this invention. FIG. 67 is a time chart for explaining a write operation in the memory system shown in FIG. 64. FIG. FIG. 67 is a time chart for explaining a read operation in the memory system shown in FIG. 64. FIG. It is a block diagram explaining the memory system which concerns on the 5th Example of this invention. FIG. 68 is a time chart for explaining a write operation of the first DQ channel portion of the memory system shown in FIG. 67. FIG. It is a time chart explaining the read operation of the first DQ channel portion. 68 is a time chart for explaining a write operation of a second DQ channel portion of the memory system shown in FIG. 67. It is a time chart explaining the read operation of the second DQ channel portion.

Explanation of symbols

100 Motherboard 101 Memory Controller 102 Clock Generator 103 Module 105 Buffer 110 DRAM
111 Data wiring 112 Command / address wiring 113 Clock wiring 111 ′ Internal data wiring 112 ′ Internal command / address wiring 113 ′ Internal clock wiring

Claims (17)

  A first device that receives data in accordance with a first internal clock; and a second device that receives data in accordance with a second internal clock; and between the first and second devices, In a data transmission method for transmitting and receiving data in both directions, first and second data phase signals are continuously transmitted in both directions on the same wiring between the first and second devices at a timing that does not collide with each other. In addition, the first device refers to the timing of the first data phase signal and transmits data to the second device, while the second device transmits the data of the second data phase signal. A data transmission method, wherein data is transmitted to a first device with reference to timing.   2. The second device according to claim 1, wherein the second device generates the second internal clock according to the received first data phase signal, and data from the first device according to the second internal clock. On the other hand, the first device generates the first internal clock according to the received second data phase signal, and generates the second data phase signal according to the first internal clock. A data transmission method comprising generating and receiving data from a second device.   3. The first device according to claim 1, wherein the first device suppresses the first data phase signal output from the first device among the first and second data phase signals transmitted bidirectionally. On the other hand, the second device suppresses the second data phase signal output from the second device among the first and second data phase signals transmitted bidirectionally. Data transmission method.   4. The device according to claim 1, wherein the first and second devices are a buffer and a DRAM, respectively, and an external clock is supplied to the DRAM, and the external clock and the received first first device are received. A data transmission method characterized in that the second clock is generated by a data phase signal.   4. The method according to claim 1, wherein the first and second devices generate first and second internal clocks from the second and first data phase signals using a DLL. Characteristic data transmission method.   In the data transmission system that transmits and receives data to and from the first and second devices, the transmission side of the first and second devices continuously transmits the data regardless of the data transmission. And means for transmitting a data phase signal representing a predetermined phase of the data, and the receiving side of the first and second devices regenerates the internal clock of the receiving side based on the data phase signal And a means for receiving the data according to the regenerated internal clock.   In a data transmission system in which data is transmitted and received bidirectionally between the first and second devices, the first and second devices are independent of the data transmission when transmitting the data, respectively. Continuously transmitting a data phase signal representing a predetermined phase of the data, and transmitting means for transmitting the data based on the data phase, wherein the first and second devices are respectively A data transmission system comprising: receiving means for regenerating an internal clock on the receiving side based on a data phase signal and receiving the data according to the regenerated internal clock.   8. The method according to claim 7, wherein the first and second devices are a buffer and a DRAM, respectively, and the transmission means of the buffer outputs a write data phase signal to the DRAM as the data phase signal. And receiving means for receiving the read data phase signal from the DRAM as the data phase signal. The receiving means for the DRAM receives the write data phase signal from the write data phase signal. And means for regenerating the internal clock for data reception, and means for receiving the data in accordance with the regenerated internal clock, and further, the transmission means of the DRAM is configured to receive the write data phase received A read data phase signal is output as the data phase signal at a timing depending on the signal. Data transmission system, characterized in that it includes means.   9. The data transmission system according to claim 8, wherein the write data phase signal and the read data phase signal are transmitted bi-directionally on the same signal line at different timings.   9. The data transmission system according to claim 8, wherein the write data phase signal and the read data phase signal are transmitted on different signal lines in both directions at different timings.   11. The read data phase signal receiving means of the buffer according to claim 8, further comprising means for regenerating a data reception buffer internal clock from the buffer internal clock and the read data phase signal. The read data phase signal output means includes means for reproducing a DRAM internal clock for outputting the read data phase signal from an external clock and the received write data phase signal. system.   A device comprising: means for transmitting and receiving data; and means for transmitting and receiving first and second data phase signals defining the transmission and reception timing of the data at different timings.   13. The device according to claim 12, further comprising means for identifying the first and second data phase signals.   14. The device according to claim 12, wherein the device is used for the buffer and the memory circuit in a memory module including the buffer and the memory circuit.   In a memory module that includes a buffer and a memory circuit and transmits and receives data between the buffer and the memory circuit, each of the buffer and the memory circuit includes means for transmitting and receiving data, and a data transmission and reception timing that defines the transmission and reception timing of the data. A memory module comprising means for transmitting and receiving the first and second data phase signals at different timings.   16. The memory module according to claim 15, further comprising means for identifying the first and second data phase signals.   17. The memory module according to claim 15, further comprising means for generating an internal clock from the received second data phase signal.

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