JP2008116821A - Display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily identify a failure part of a drive circuit in a display panel of integrated drive circuit type. <P>SOLUTION: In the display panel of integrated drive circuit type in which a data processing circuit 4, a clock generation circuit 5, and so forth are also integrated on a glass substrate, an inspection pixel 7 is connected to each of circuit blocks 51, 52, 53, 54 of an input signal 6, the data processing circuit 4, and the clock generation circuit 5. Because the inspection pixel 7 is thereby driven according to the operation status of a signal of each circuit block, it is checked through the inspection pixel 7 whether or not the signal of each circuit block is normal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display panel integrated with a drive circuit.

  Conventionally, a driver circuit composed of a simple shift register has been integrated on a glass substrate of a display panel using polycrystalline silicon. In a display panel in which a drive circuit composed of only a simple shift register is integrated, most of the defects are pixel defects and wiring defects. In the case of a point defect or a line defect, since the defect occurrence site can be specified only by observing the display image with a microscope, defect analysis is relatively easy. A technique described in Patent Document 1 is known as a technique for efficiently finding a defect in a driver circuit of a liquid crystal device.

  In recent years, a display panel integrated with a driving circuit in which an interface circuit and a timing generation circuit incorporated in an externally attached IC are integrated on a glass substrate has been developed (for example, see Patent Document 2).

  FIG. 8 is a block diagram showing the configuration of a conventional display panel integrated with a drive circuit. The display panel shown in the figure includes a thin film transistor at an intersection of a signal line and a scanning line arranged in a matrix, a pixel portion 1 that displays an image by applying an electric field to liquid crystal by conducting the thin film transistor, and a signal A signal line driving circuit 2 for supplying video signals to the lines, a scanning line driving circuit 3 for driving the scanning lines, a data processing circuit 4 and a clock generation circuit 5, and the pixel unit 1 and various circuits are made of glass. It is a display panel integrated with a drive circuit integrated on a substrate. Hereinafter, the operation of the conventional drive circuit integrated display panel will be described.

  An input signal 6 is input to the data processing circuit 4 and the clock generation circuit 5. In the data processing circuit 4, the input RGB data is latched, serial-parallel converted, and output to the signal line driving circuit 2 as a video signal. The clock generation circuit 5 generates various timing signals and outputs them to the signal line driving circuit 2, the scanning line driving circuit 3, and the like.

  The video signal input to the signal line driving circuit 2 is latched by the sampling latch circuit 22 by the timing signal generated by the shift register 21 based on the clock signal input from the clock generation circuit 5. The video signal sequentially latched by the sampling latch circuit 22 is latched at the same timing by the load latch circuit 23, and the video signal is selected by the selection switch 24. The selected video signal is converted into an analog signal by the digital-analog conversion circuit 25, amplified to a voltage for driving the liquid crystal, and output to the pixel unit 1.

  In the scanning line driving circuit 3, the clock signal generated in the clock generation circuit 5 is input to the shift register 31, and the scanning line signal for selecting the scanning line is controlled. The scanning line signal is converted in voltage by the level shifter 32 and applied to the scanning line via the gate buffer 33.

In the pixel portion 1, when a scanning line signal is given to the scanning line, the video signal applied to the signal line is written to the pixel electrode, and an electric field is applied to the liquid crystal.
JP 2001-318113 A JP 2002-174823 A

  In such a display panel integrated with a driving circuit, when a defect occurs in the clock generation circuit 5 or the data processing circuit 4, the display is not displayed at all, or even if the display is displayed, the image is distorted. Therefore, it is impossible to specify the defect occurrence site.

  In order to specify such a defect in the circuit integrated on the glass substrate, it is necessary to investigate whether a signal is normally output for each circuit block of the clock generation circuit 5 and the data processing circuit 4. In order to investigate the output signal of the circuit block, it is realized by providing a test pad in the circuit and probing, but in order to perform probing from the completed display panel, it is necessary to disassemble it and it is very difficult. is there.

  The present invention has been made in view of the above, and an object of the present invention is to provide a display panel integrated with a drive circuit that can identify a defective portion without disassembling the display panel.

  A display panel according to the present invention is a display panel integrated with a drive circuit in which a display region having a plurality of pixels and a drive circuit for driving the display region are formed on the same substrate. It has the pixel for a test | inspection connected to this circuit block.

  In the present invention, the operation state of the signal of the circuit block can be visually confirmed through the inspection pixel by connecting the inspection pixel to the circuit block in the drive circuit. It is possible to specify the defect occurrence site without doing so.

  In the display panel, it is desirable that the circuit block and the inspection pixel are connected to each other through a frequency dividing circuit in order to drive the inspection pixel.

  In the display panel, the inspection pixels are arranged on the outer periphery of the display area.

  By disposing the inspection pixels on the outer periphery of the display area, it is not necessary to use the pixels in the display area as inspection pixels, so that the display area is not affected.

  In the display panel, a polarizing plate is disposed so as to cover the display region, and the inspection pixel is covered with the polarizing plate.

  By covering the inspection pixel with the polarizing plate, the display of the inspection pixel can be confirmed without using the inspection polarizing plate or the polarizing microscope.

  According to the present invention, it is possible to provide a display panel integrated with a drive circuit capable of specifying a defective portion without disassembling the display panel.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration of a display panel in this embodiment. The display panel shown in the figure is different from the conventional display panel shown in FIG. 7a, 7b, 7c, 7d, 7e, 7f are connected to each other, and the data processing circuit 4, the clock generation circuit 5, and the like are integrated on a glass substrate and are a display panel integrated with a driving circuit. The inspection pixels 7a, 7b, 7c, 7d, 7e, 7f are formed on the glass substrate via the buffers 71a, 71b, 71c, 71d, 71e, 71f and the frequency dividing circuits 72a, 72b, 72c, 72d, 72e, 72f. Connected to an integrated circuit.

  As shown in the circuit diagram of FIG. 2, a signal input to the inspection pixel 7 is synthesized by taking the logical sum of the sampling signal of the circuit block to be inspected and YCK (Y driver clock pulse). As shown in the waveform diagram of FIG. 3, the alternating current waveform for driving the inspection pixel 7 is created by synthesizing the sampling signal and YCK.

  Thus, by sampling the signal of each circuit block and driving the inspection pixel 7, the operation state of the signal of each circuit block can be confirmed by the display of the inspection pixel 7. When the signal of each circuit block is normal, it is displayed in light gray. When the display of the inspection pixel 7 is black or white, it can be determined that the signal of the circuit block is abnormal.

  Since the signal of each circuit block has a high frequency of several MHz, it is necessary to reduce the frequency to a frequency that can drive the inspection pixel 7 (about a few dozen kHz). Therefore, the circuit block and the inspection pixel 7 Are connected via a frequency divider circuit 72. For example, as shown in the circuit diagram of FIG. 4, a divide-by-2 circuit composed of an inverter or a clocked inverter is connected in series as shown in the block diagram of FIG. Can be obtained. Hereinafter, the arrangement of the inspection pixels 7 will be described.

  FIG. 6 is a plan view of the display panel in the present embodiment. As shown in the figure, the pixel portion 1 is covered with a polarizing plate 11, and the change in the alignment of the liquid crystal is visualized by the polarizing plate 11. The inspection pixel 7 is disposed in a portion covered with the polarizing plate 11 in the peripheral portion of the pixel portion 1, or the inspection pixel 7 is disposed in a portion not covered with the polarizing plate 11. When the inspection pixel 7 is arranged in a portion not covered with the polarizing plate 11, the display of the inspection pixel 7 is confirmed by a polarizing plate, a polarizing microscope, or the like.

  FIG. 7 is a cross-sectional view of the display panel showing the arrangement of the inspection pixels 7. As shown in the figure, the display panel has a configuration in which a liquid crystal layer 80 is sandwiched between two glass substrates 81 a and 81 b and bonded together with a sealing material 85. On the glass substrate 81a, the pixel portion 1 and various drive circuits are formed, and an insulating film 82 and a pixel electrode 83a are formed. In addition, the pixel electrode 83c of the inspection pixel 7 is disposed outside the pixel electrode 83a forming the display region. The glass substrate 81b is electrically connected to the glass substrate 81a via the transfer portion 86, and a counter electrode 83b is formed on the glass substrate 81b. By generating an electric field between the pixel electrodes 83a and 83c and the counter electrode 83b, the liquid crystal molecules of the liquid crystal layer 80 are controlled to display an image. Alignment films 84a and 84b are disposed on the pixel electrodes 83a and 83c formed on the glass substrate 81a and the counter electrode 83b formed on the glass substrate 81b. The alignment films 84a and 84b align the liquid crystal molecules in the liquid crystal layer 80.

  Therefore, according to the present embodiment, the input signal 6, the data processing circuit 4, and the clock generation circuit 5 in the display panel integrated with the drive circuit in which the data processing circuit 4, the clock generation circuit 5 and the like are also integrated on the glass substrate. By connecting the inspection pixel 7 to each of the circuit blocks 51, 52, 53, and 54, the inspection pixel 7 is driven according to the operation state of the signal of each circuit block, so that the signal of each circuit block is normal. It can be confirmed by the display of the inspection pixel 7 whether or not.

  According to the present embodiment, since the frequency of the signal input to the inspection pixel 7 can be lowered by connecting the frequency dividing circuit 72 to the inspection pixel 7, even a signal having a high frequency can be used for the inspection. This can be confirmed by the pixel 7.

  According to the present embodiment, by disposing the inspection pixels 7 in the peripheral portion of the pixel portion 1, it is not necessary to use the pixels formed in the pixel portion 1, so that the display area is not affected.

It is a block diagram which shows the structure of the display panel in one embodiment. It is a circuit diagram which shows the signal input into the test | inspection pixel of the said display panel. It is a wave form diagram which shows the signal input into the circuit shown in FIG. 2, and the signal combined. It is a circuit diagram which shows the 2 frequency divider circuit connected to the pixel for a test | inspection of the said display panel. It is a block diagram which shows a mode that the 2 frequency dividing circuit of FIG. 4 was arrange | positioned in series. It is a top view which shows arrangement | positioning of the pixel part and inspection pixel of the said display panel. It is sectional drawing which shows arrangement | positioning of the pixel part and inspection pixel of the said display panel. It is a block diagram which shows the structure of the conventional display panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel part 2 ... Signal line drive circuit 3 ... Scan line drive circuit 4 ... Data processing circuit 5 ... Clock generation circuit 6 ... Input signal 7, 7a, 7b, 7c, 7d, 7e, 7f ... Inspection pixel 11 ... Polarization Plate 21 ... Shift register 22 ... Sampling latch circuit 23 ... Load latch circuit 24 ... Select switch 25 ... Digital-analog conversion circuit 31 ... Shift register 32 ... Level shifter 33 ... Gate buffer 51, 52, 53, 54 ... Circuit blocks 71a, 71b, 71c, 71d, 71e, 71f... Buffer 71, 72a, 72b, 72c, 72d, 72e, 72f... Dividing circuit 80... Liquid crystal layer 81a, 81b ... Glass substrate 82 ... Insulating film 83a, 83c ... Pixel electrode 83b ... Counter electrode 84a, 84b ... Alignment film 85 ... Sealing material 86 ... Transfer part

Claims (4)

A display panel including a plurality of pixels and a drive circuit for driving the display area are formed on the same substrate, and is a display panel integrated with a drive circuit,
A display panel comprising inspection pixels connected to a circuit block in the driving circuit.   The display panel according to claim 1, wherein the circuit block and the inspection pixel are connected via a frequency divider circuit.   The display panel according to claim 1, wherein the inspection pixels are arranged on an outer periphery of the display area.   4. A display panel according to claim 1, wherein a polarizing plate is disposed so as to cover the display area, and the inspection pixel is covered with the polarizing plate. .

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