JP2008112565A - Electronic apparatus and double data rate synchronous dynamic random access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus constituted so that exchange of data can surely be carried out even though a strobe period becomes short, as the electronic apparatus provided with a semiconductor storage device. <P>SOLUTION: As strobe signals, complementary strobe signals QS<SB>OUT'</SB>/QS<SB>OUT'</SB>QS<SB>IN'</SB>/QS<SB>IN</SB>are used, and even when rise time and fall time of the complementary strobe signals QS<SB>OUT'</SB>/QS<SB>OUT'</SB>QS<SB>IN'</SB>/QS<SB>IN</SB>are different, the definitive time of the strobe is made constant, and the definitive time of data DQ<SB>OUT'</SB>DQ<SB>IN</SB>is made constant. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic device including a semiconductor memory device and a double data rate synchronous dynamic random access memory.

  FIG. 15 is a circuit diagram showing a part of an example of a conventional electronic device. In FIG. 15, 1 is an example of a conventional double data rate synchronous dynamic random access memory (hereinafter referred to as DDR-SDRAM) that operates in synchronization with the rising edge and falling edge of the clock signal. The electronic device includes a plurality of DDR-SDRAMs having the same configuration and a control chip for controlling the plurality of DDR-SDRAMs.

  Further, 2 is a normal phase clock signal line for transmitting the normal phase clock signal CLK, 3 is a reverse phase clock signal line for transmitting a negative phase clock signal / CLK having a reverse phase relationship with the normal phase clock signal CLK, and 4 is a command signal. A command bus for transmitting, 5 is an address bus for transmitting row address signals and column address signals, and 6 is a data bus for transmitting data.

Further, 7 transmits an output strobe signal QS _OUT indicating the acquisition timing of the output data DQ _OUT outputted together with the output data DQ _OUT from DDR-SDRAM such as DDR-SDRAM 1 to the control chip, the input data DQ _IN from the control chip This is a strobe signal line for transmitting an input strobe signal QS _IN notifying the timing of taking in the output input data DQ _IN to a DDR-SDRAM such as the DDR-SDRAM 1.

  FIG. 16 is a circuit diagram showing a main part of the DDR-SDRAM 1. In FIG. 16, 9 is a command buffer for inputting a command signal transmitted through the command bus 4, and 10 is a command output from the command buffer 9. A command decoder 11 decodes the signal, and 11 is a controller that receives the command decode signal output from the command decoder 10 and controls the internal circuit in accordance with the contents of the command.

  Reference numeral 12 denotes an address buffer for inputting a row address signal and a column address signal transmitted through the address bus 5, and reference numerals 13-1 and 13-m denote a row address signal and a column address signal output from the address buffer 12, respectively. It is an address latch that latches.

  14-1 and 14-m are banks. In the bank 14-1, 15-1 is a memory cell array in which memory cells are arranged, 16-1 is a row address signal latched in the address latch 14-1. A row decoder that decodes and selects a word line.

  Reference numeral 17-1 denotes a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged, and 18-1 denotes a column latched by the address latch 13-1. This is a column decoder that decodes an address signal and selects a column.

  In the bank 14-m, 15-m is a memory cell array in which memory cells are arranged, and 16-m is a row decoder that selects a word line by decoding a row address signal latched in the address latch 13-m. is there.

  Reference numeral 17-m denotes a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged, and 18-m denotes a column latched by the address latch 13-m. This is a column decoder that decodes an address signal and selects a column.

  Reference numeral 19-1 denotes a data bus buffer for amplifying read data output from the bank 14-1 to the core data bus CDB1, and 20-1 denotes a write buffer for outputting write data to the core data bus CDB1.

  Reference numeral 19-m denotes a data bus buffer for amplifying read data output from the bank 14-m to the core data bus CDBm, and 20-m denotes a write buffer for outputting write data to the core data bus CDBm.

Further, DB is a peripheral data bus, 21 is a data output buffer for outputting output data DQ _OUT to the outside, and 22 is a data input buffer for inputting input data DQ _IN having a parallel N-bit configuration from the outside.

Reference numeral 23 denotes a strobe output buffer for outputting the output strobe signal QS _OUT, and reference numeral 24 denotes a strobe input buffer for inputting the input strobe signal QS _IN and controlling the input data DQ _IN fetch timing.

FIG. 17 is a waveform diagram showing the relationship among complementary clock signals CLK, / CLK, output strobe signal QS _OUT , and output data DQ _OUT when data is output from DDR-SDRAM 1.

  In FIG. 17, tCKQS is a QS access time (QS Access Time from CLK // CLK) from the cross point of the clock signal CLK and the anti-phase clock signal / CLK, tQSPRE is a QS preamble time (QS Preamble Time), and tQSPST is QS This is the QS Postamble Time.

  TQSQ is the output data skew from the strobe signal QS (Data Output Skew from QS), and tAC is the data access time from the cross point of the clock signal CLK and the anti-phase clock signal / CLK (Data Access Time from CLK / / CLK), tDV is the output data valid time.

FIG. 18 is a waveform diagram showing the relationship between complementary clock signals CLK, / CLK, input strobe signal QS _IN , and input data DQ _IN when data is input to DDR-SDRAM 1.

  In FIG. 18, tDH is an input data setup time from the strobe signal QS (Data Input set up time from QS), and tDS is an input data hold time from the strobe signal QS (Data Input hold time from QS).

This electronic device is provided with a strobe signal line 7 having the same environment as that of the data bus 6, transmits the output strobe signal QS _OUT together with the output data DQ _OUT from the DDR-SDRAM, and outputs the output data DQ as viewed from the output strobe signal QS _OUT. The fixed time of _OUT is fixed, the reception of output data DQ _OUT by the control chip is facilitated, the input strobe signal QS _IN is transmitted from the control chip together with the input data DQ _IN , and the input viewed from the input strobe signal QS _IN The fixed time of the data DQ _IN is fixed, and the reception of the input data DQ _IN by the DDR-SDRAM is facilitated.
JP-A-7-244985

However, if the rise time and the fall time of the strobe signals QS _OUT and QS _IN are different, the strobe cycle is not constant. For this reason, the determination time of the data DQ _OUT and DQ _IN is not constant, and the data DQ _OUT If the timing of DQ _IN capture is difficult and the strobe cycle is shortened, for example, if the strobe cycle is 4 ns or less, there is a problem that the exchange of data DQ _OUT and DQ _IN may be uncertain.

  In view of the above, the present invention is an electronic device having a semiconductor memory device, which can reliably exchange data even when the strobe period is shortened, and such an electronic device. An object of the present invention is to provide a DDR-SDRAM that can be used in a device.

  An electronic device according to the present invention includes a semiconductor memory device, a controller chip, a normal phase clock signal line that transmits a normal phase clock signal, and a reverse phase that transmits a negative phase clock signal that is in a reverse phase relationship with the normal phase clock signal. A clock signal line; a command bus for transmitting a command signal between the semiconductor memory device and the controller chip; an address bus for transmitting a row address signal and a column address signal between the semiconductor memory device and the controller chip; A data bus for transmitting data between the semiconductor memory device and the controller chip, a positive phase strobe signal line for transmitting a positive phase strobe signal between the semiconductor memory device and the controller chip, the semiconductor memory device and the semiconductor chip Anti-phase strobe that transmits anti-phase strobe signals between controller chips The semiconductor memory device receives the normal phase clock signal and the reverse phase clock signal, and operates in synchronization with the rising edge and the falling edge of the normal phase clock signal. A SDRAM which decodes a command signal input from the controller chip via the command bus and determines a read mode or a write mode; a plurality of banks each including a memory cell array; A parallel / serial conversion circuit that converts a plurality of parallel data read from a selected bank of the plurality of banks into serial data in the read mode, and a serial from the parallel / serial conversion circuit in the read mode Receive data and read data via the data bus The cross-point between the data output buffer to be output to the controller chip and the positive phase output strobe signal and the negative phase output strobe signal in the negative phase relationship in the read mode is the edge point of the read data. A strobe output buffer for outputting the positive phase output strobe signal and the negative phase output strobe signal to the controller chip via the positive phase strobe signal line and the negative phase strobe signal line so as to synchronize with each other. A data input buffer for inputting a plurality of serially input write data from the controller chip via the data bus, and a negative phase relationship between the positive phase input strobe signal and the positive phase input strobe signal in the write mode The cross-point with the negative-phase input strobe signal at A strobe input buffer in which the positive phase input strobe signal and the negative phase input strobe signal are input from the controller chip via the positive phase strobe signal line and the negative phase strobe signal line so as to be synchronized with the center point of the data. And a serial / parallel conversion circuit that converts serial data from the data input buffer into parallel data and transfers the parallel data to a selected bank of the plurality of banks in the write mode. It is that.

  The DDR-SDRAM of the present invention receives a positive phase clock signal and a negative phase clock signal having a negative phase relationship with the positive phase clock signal, and operates in synchronization with rising and falling edges of the positive phase clock signal. An SDRAM, which decodes a command signal input from the outside and determines a read mode or a write mode, a plurality of banks each including a memory cell array, and a plurality of banks in the read mode. A parallel / serial conversion circuit that converts a plurality of parallel data read from the selected bank into serial data, and receives serial data from the parallel / serial conversion circuit in the read mode and outputs the read data as read data to the outside. The data output buffer to output and the positive phase output The positive-phase output strobe signal and the negative-phase output strobe signal are set so that the cross point of the positive-phase output strobe signal and the negative-phase output strobe signal in the negative-phase relationship with each other is synchronized with the edge point of the read data. A strobe output buffer for outputting, a data input buffer for inputting a plurality of serially inputted write data from the outside in the write mode, and a positive phase input strobe signal and the positive phase input strobe signal in the write mode; A strobe input buffer to which the positive-phase input strobe signal and the negative-phase input strobe signal are input so that a cross point with a negative-phase input strobe signal having a negative phase relationship is synchronized with a center point of the write data; Converts serial data from the data input buffer to parallel data in mode Those having a serial / parallel conversion circuit for transferring the parallel data to a selected bank of the plurality of banks, a.

  According to the electronic device of the present invention, since the complementary output strobe signal is used as the output strobe signal, the period of the complementary output strobe signal is different even when the rise time and the fall time of the complementary output strobe signal are different. (Time between cross points of complementary output strobe signals) is constant. Therefore, the fixed time (definite width) of the output data can be made constant.

  In addition, since the complementary input strobe signal is used as the input strobe signal, even if the rise time and the fall time of the complementary input strobe signal are different, the period of the complementary input strobe signal (crossing of the complementary input strobe signal) The time between points is constant. Therefore, the fixed time (definite width) of the input data can be made constant.

  Thus, according to the electronic device of the present invention, since the complementary strobe signal is used as the strobe signal, the strobe period is kept constant even when the rise time and the fall time of the complementary strobe signal are different. Since the data confirmation time can be made constant, data can be exchanged reliably even if the strobe cycle is shortened.

  According to the DDR-SDRAM of the present invention, a strobe output buffer for outputting a complementary output strobe signal is provided as a strobe output buffer, and a strobe for controlling input data input by inputting a complementary input strobe signal as a strobe input buffer. Since it has an input buffer, it can be used in the electronic device of the present invention.

  As described above, according to the DDR-SDRAM of the present invention, since the complementary strobe signal is used as the strobe signal, even when the rise time and the fall time of the complementary strobe signal are different, the strobe cycle is changed. Since the data determination time can be made constant, data can be exchanged reliably even if the strobe cycle is shortened.

  Hereinafter, an embodiment of an electronic device of the present invention and an embodiment of a DDR-SDRAM of the present invention will be described with reference to FIGS.

  FIG. 1 is a block circuit diagram showing a part of an embodiment of an electronic device of the present invention. In FIG. 1, reference numeral 26 denotes a first cycle random access memory (hereinafter referred to as FCRAM) which is a kind of DDR-SDRAM, which is an embodiment of the DDR-SDRAM of the present invention. One embodiment of the electronic device of the present invention includes a plurality of FCRAMs having the same configuration and a control chip for controlling the plurality of FCRAMs.

  27 is a normal phase clock signal line for transmitting the normal phase clock signal CLK, 28 is a reverse phase clock signal line for transmitting the reverse phase clock signal / CLK having a reverse phase relationship with the normal phase clock signal CLK, and 29 is a command signal. A command bus 30 for transmitting data, an address bus 30 for transmitting row address signals and column address signals, and a data bus 31 for transmitting data.

Also, 32 may transmit a positive phase output strobe signal QS _OUT indicating the acquisition timing of the output data DQ _OUT outputted together with the output data DQ _OUT from like FCRAM26 the control chip, and output with the input data DQ _IN from the control chip input This is a positive phase strobe signal line for transmitting the positive phase input strobe signal QS _IN for notifying the timing of taking in the data DQ _IN to the FCRAM 26 or the like.

33 transmits a negative phase output strobe signal / QS _OUT having a negative phase relationship with the positive phase output strobe signal QS _OUT output from the FCRAM 26 or the like to the control chip, and a positive phase input strobe signal QS output from the control chip. _This is a negative phase strobe signal line for transmitting the negative phase input strobe signal / QS _IN having a negative phase relationship with _IN to the FCRAM 26 or the like.

  2 is a circuit diagram showing the main part of the FCRAM 26. In FIG. 2, 35 is a command buffer for inputting a command signal transmitted through the command bus 29, and 36 is a command signal output from the command buffer 35. A command decoder for decoding.

  Reference numeral 37 denotes an address buffer for inputting a row address signal and a column address signal transmitted through the address bus 30, and 38-1 and 38-m denote a row address signal and a column address signal output from the address buffer 37, respectively. It is an address latch that latches.

  Reference numerals 39-1 and 39-m denote banks. In the bank 39-1, 40-1 is a memory cell array in which memory cells are arranged, 41-1 is a row address signal latched in the address latch 38-1. A row decoder that decodes and selects a word line.

  42-1 is a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged, and 43-1 is a column latched by the address latch 38-1. This is a column decoder that decodes an address signal and selects a column.

  Reference numeral 44-1 denotes an active pre-controller that receives a command decode signal output from the command decoder 36 and controls the column decoder 43-1 and the sense amplifier array 42-1 according to the contents of the command.

  In the bank 39-m, 40-m is a memory cell array in which memory cells are arranged, and 41-m is a row decoder that selects a word line by decoding a row address signal latched in an address latch 38-m. is there.

  42-m is a sense amplifier array in which sense amplifiers for amplifying data read from the memory cell selected by the selected word line are arranged, and 43-m is a column latched by the address latch 38-m. This is a column decoder that decodes an address signal and selects a column.

  44-m is an active pre-controller that receives a command decode signal output from the command decoder 36 and controls the column decoder 43-m, the sense amplifier array 42-m, etc. according to the contents of the command.

  For example, the FCRAM 26 can set a plurality of burst lengths. In this case, when reading, the FCRAM 26 operates so that a plurality of data is read in parallel from the selected bank. In writing, a plurality of parallel data can be written to a selected bank.

  Reference numeral 45-1 denotes a data bus buffer for amplifying read data output from the bank 39-1 to the core data bus CDB1, and reference numeral 46-1 denotes a write buffer for outputting write data to the core data bus CDB1.

  45-m is a data bus buffer for amplifying read data output from the bank 39-m to the core data bus CDBm, and 46-m is a write buffer for outputting write data to the core data bus CDBm.

Reference numeral 47 is a parallel / serial conversion circuit for serializing parallel data transmitted from the data bus buffer corresponding to the selected bank, and 48 is a serialized parallel N-bit output from the parallel / serial conversion circuit 47. a data output buffer for outputting the output data DQ _OUT 1~DQ _OUT N configuration outside.

Further, 49 data input buffer for inputting the input data DQ _IN 1~DQ _IN N parallel N-bit structure from the outside, 50 denotes an input data DQ _IN. 1 to a parallel N-bit configuration which is output from the data input buffer 49 This is a serial / parallel conversion circuit that parallelizes each of DQ _IN N.

A strobe output buffer 51 outputs the positive phase output strobe signal QS _OUT to the positive phase strobe signal line 32 and outputs the negative phase output strobe signal / QS _OUT to the negative phase strobe signal line 33.

Reference numeral 52 denotes a strobe input buffer for inputting a normal phase input strobe signal QS _IN transmitted through the normal phase strobe signal line 32 and a negative phase input strobe signal / QS _IN transmitted through the negative phase strobe signal line 33. .

FIG. 3 is a circuit diagram showing the configuration of the data output buffer 48 and the strobe output buffer 51. In FIG. 3, mCLK is an internal clock, DE is a data enable signal, mDQ _OUT 1, mDQ _OUT 2, and mDQ _OUT N are internal output data, and mQS _OUT is an internal output strobe signal.

  In the data output buffer 48, 54 and 55 are nMOS transistors whose internal clock signal mCLK is turned on and off, 56 is an inverter that inverts the internal clock signal mCLK, and 57 and 58 are turned on and off by the output of the inverter 56. Is a controlled pMOS transistor.

  A latch circuit 59 includes inverters 60 and 61 that latch the data enable signal DE. A latch circuit 62 includes inverters 63 and 64 that latch the output of the latch circuit 59.

65-1 is a NAND circuit that NANDs the internal output data mDQ _OUT 1 and the output of the latch circuit 62; 65-2 is a NAND circuit that NANDs the internal output data mDQ _OUT 2 and the output of the latch circuit 62; 65-N is a NAND circuit that NANDs the internal output data mDQ _OUT N and the output of the latch circuit 62.

Further, 66-1,66-2,66-N, respectively, output the inverted amplifying the output of the NAND circuit 65-1,65-2,65-N data _{DQ OUT 1, DQ OUT 2,} DQ OUT N Is a three-state inverter.

In the strobe output buffer 51, 67 is a NAND circuit that NANDs the internal output strobe signal mQS _OUT and the data enable signal DE, 68 is an inverter that inverts the internal output strobe signal mQS _OUT , and 69 is an output and data of the inverter 68. This is a NAND circuit that performs NAND processing on the enable signal DE.

Reference numeral 70 denotes a three-state inverter that inverts and amplifies the output of the NAND circuit 67 and outputs the positive phase output strobe signal QS _OUT. Reference numeral 71 inverts and amplifies the output of the NAND circuit 69 to output the negative phase output strobe signal / QS _OUT . It is a three-state inverter.

In the data output buffer 48 and the strobe output buffer 51 configured as described above, when the data enable signal DE = H level and the internal clock mCLK = H level, the NAND circuits 67 and 69 are activated in the strobe output buffer 51. ized, internal output strobe signal MQS _OUT complementary output strobe signal corresponding to QS _OUT, / QS _OUT is output.

In the data output buffer 48, the output of the latch circuit 59 becomes L level, the output of the latch circuit 62 becomes H level, the NAND circuits 65-1 to 65-N are activated, and the internal output data mDQ _{OUT 1 to} mDQ. Output data DQ _OUT 1 to DQ _OUT N corresponding to _OUT N are output.

FIG. 4 is a circuit diagram showing the configuration of the data input buffer 49 and the strobe input buffer 52. In FIG. 4, in the strobe input buffer 52, reference numerals 73 and 74 are differential amplifiers for generating the strobe clock QS-CLK. The differential amplifier 73 receives the positive phase input strobe signal QS _{IN at the} positive phase input terminal. The negative phase input strobe signal / QS _IN is input to the negative phase input terminal, and the differential amplifier 74 has the negative phase input strobe signal / QS _IN input to the positive phase input terminal and the positive phase input to the negative phase input terminal. The strobe signal QS _IN is input.

Further, in the data input buffer 49, 75-1,75-2,75-N in synchronization with the strobe clock QS-CLK output from the strobe input buffer 52, respectively, the input data DQ _IN 1, DQ _IN 2, This is a synchronous flip-flop circuit (SFF) that latches DQ _IN N.

FIG. 5 is a waveform diagram showing the relationship between complementary clock signals CLK and / CLK, complementary output strobe signals QS _OUT and / QS _OUT , and continuous 2-bit output data DQ _OUT = RD1 and RD2 when data is output from FCRAM 26. It is.

That is, in one embodiment of an electronic device of the present invention, the complementary output strobe signal QS _OUT, / QS complementary output strobe signal QS _OUT indicating the start of the period of the _OUT, / QS _OUT beginning a fixed time before the cross point of the The preamble time is tQSPRE.

In the preamble time tQSPRE, the normal phase output strobe signal QS _OUT = L level and the negative phase output strobe signal / QS _OUT = H level are set, and this level is set with the read command RD-CMD as a trigger.

Thus, in the preamble time TQSPRE positive phase output strobe signal QS _OUT = L level, by a reverse-phase output strobe signal / QS _OUT = H level, the positive-phase output strobe signal QS _OUT and the negative phase output strobe signal When the circuit receiving / QS _OUT is a differential amplifier, the internal level can be determined and the output data DQ _OUT can be received.

Further, the complementary output strobe signal QS _OUT, / QS _OUT complementary output strobe signal QS _OUT indicating the end of the period of the / QS _OUT predetermined time after the cross point of the postamble time TQSPST, this time, the positive phase output The strobe signal QS _OUT and the negative phase output strobe signal / QS _OUT are set to have different levels.

  Further, the transistors of the FCRAM 26 that drive the normal phase strobe signal line 32 and the negative phase strobe signal line 33 are the standby time other than the preamble time tQSPRE, the output strobe determination time, the period in which the cycle of the input strobe signal continues, and the postamble time tQSPST. In the meantime, the off-phase strobe signal line 32 and the negative-phase strobe signal line 33 are set in a floating state and in a high impedance state (Hi-Z) or a low impedance state (Low-Z).

In the embodiment of the present invention, the cross points of the complementary output strobe signals QS _OUT and / QS _OUT are set so as to provide an edge trigger point of the output data DQout.

Note that the levels of the complementary output strobe signals QS _OUT and / QS _{OUT at} the preamble time tQSPRE are set so that the head output data DQ _OUT == QQ _OUT = QQS _OUT when there is data latency with respect to the read command RD-CMD. It may be set a certain time before the output of RD1 (for example, one clock or half clock before).

In the case where the complementary input strobe signal line and a complementary output strobe signal line is provided separately, the complementary output strobe signal QS _OUT, / QS _OUT, as shown in FIG. 7, a continuous output data DQ _OUT is In the case of even data, the same level as in the postamble time tQSPST is maintained during the standby time, that is, the positive phase output strobe signal QS _OUT = H level and the negative phase output strobe signal / QS _OUT = L level are maintained. However, there is no problem with making the controller chip ready for reception.

In the case where the complementary output strobe signal line and the complementary input strobe signal line are provided separately, the complementary output strobe signals QS _OUT and / QS _OUT have the output data DQ _OUT of 1 as shown in FIG. Or, in the case of continuous odd data, during the waiting time, the same level as in the postamble time tQSPST, that is, the positive phase output strobe signal QS _OUT = H level and the negative phase output strobe signal / QS _OUT = L level are maintained. In the case of controlling to return to the original level at the start of the preamble time tQSPRE at the next read, there is no problem with setting the controller chip to the receivable state.

Further, the cross points of the complementary output strobe signals QS _OUT and / QS _OUT may be set so as to give the center point of the output data DQ _OUT as shown in FIG.

FIG. 10 is a waveform diagram showing the relationship between complementary clock signals CLK and / CLK, complementary input strobe signals QS _IN and / QS _IN , and continuous 2-bit input data DQ _IN = WD1 and WD2 when data is input to the FCRAM 26. It is.

That is, in one embodiment of an electronic device of the present invention, the complementary input strobe signal QS _IN, / QS complementary input strobe signal QS _IN indicating the start of the period of the _IN, / QS _IN beginning a fixed time before the cross point of the The preamble time is tQSPRE.

In the preamble time tQSPRE, the positive phase input strobe signal QS _IN = L level and the negative phase input strobe signal / QS _IN = H level are set, and this level is set with the write command WR-CMD as a trigger.

Thus, in the preamble time TQSPRE positive phase input strobe signal QS _IN = L level, by a reverse-phase input strobe signal / QS _IN = H level, the positive-phase input strobe signal QS _IN and the negative phase input strobe signal When the circuit that receives / QS _IN is a differential amplifier, the internal level can be determined and input data DQ _IN can be received.

Also, the complementary input strobe signal QS _IN, / QS _IN complement indicating the end of the period of the input strobe signal QS _IN, / QS _IN predetermined time after the cross point of the the post-amble time TQSPST, this time, the positive phase input The strobe signal QS _IN and the anti-phase input strobe signal / QS _IN are set to have different levels.

  The transistors of the controller chip that drive the positive phase strobe signal line 32 and the negative phase strobe signal line 33 are turned off during the standby time, and the positive phase strobe signal line 32 and the negative phase strobe signal line 33 are floating. The state is set to a high impedance state (Hi-Z) or a low impedance state (Low-Z).

In one embodiment of the present invention, the cross points of the complementary input strobe signals QS _IN and / QS _IN are set so as to provide an edge trigger point of the input data DQ _IN .

Note that the levels of the complementary input strobe signals QS _IN and / QS _{IN at} the preamble time tQSPRE are as shown in FIG. 11, when there is data latency with respect to the write command WR-CMD, leading input data DQ _IN = It may be set a predetermined time before the output of WD1.

When the complementary output strobe signal line and the complementary input strobe signal line are provided separately, the complementary input strobe signals QS _IN and / QS _IN are output data DQ _IN continuously as shown in FIG. In the case of even data, the same level as in the postamble time tQSPST is maintained during the waiting time, that is, the positive phase input strobe signal QS _IN = L level and the negative phase input strobe signal / QS _IN = H level are maintained. However, there is no problem with making the FCRAM ready for reception.

Further, when the complementary output strobe signal line and the complementary input strobe signal line are provided separately, the complementary input strobe signals QS _IN and / QS _IN have the input data DQ _IN of 1 as shown in FIG. Or, in the case of continuous odd data, during the waiting time, the same level as in the postamble time tQSPST, that is, the positive phase input strobe signal QS _IN = H level, the negative phase input strobe signal / QS _IN = L level, At the start of the preamble time tQSPRE at the time of the next read, there is no problem with setting the FCRAM to the receivable state when controlling to return to the original level.

Further, the cross points of the complementary input strobe signals QS _IN and / QS _IN may be set so as to give the center point of the input data DQ _IN as shown in FIG.

As described above, in the embodiment of the electronic device of the present invention, the complementary output strobe signals QS _OUT and / QS _OUT are used as the output strobe signals. Therefore, the complementary output strobe signals QS _OUT and / QS _OUT even when the rise and fall times different, complementary output strobe signal QS _OUT, / QS _OUT of cycle (complementary output strobe signal QS _OUT, / QS _OUT time between the cross points) is constant, the output The determination time (determination range) of data DQ _OUT can be made constant.

Further, since the complementary input strobe signals QS _IN and / QS _IN are used as the input strobe signals, even when the rising time and the falling time of the complementary input strobe signals QS _IN and / QS _IN are different, The period of the complementary input strobe signals QS _IN and / QS _IN (time between the cross points of the complementary output strobe signals QS _IN and / QS _IN ) is made constant, and the decision time (definite width) of the input data DQ _IN is made constant. Can do.

Therefore, according to one embodiment of the electronic device of the present invention, even when the strobe period is shortened, for example, even when the strobe period is 4 ns or less, the data DQ _OUT and DQ _IN can be exchanged reliably. .

Further, the FCRAM 26 is configured to read in parallel the bit length data corresponding to the burst length from the selected bank, transmit it to the parallel / serial conversion circuit 47, serialize it, and transfer it to the data output buffer 48. However, as described above, the period of the complementary output strobe signals QS _OUT and / QS _OUT can be made constant and the fixed time of the output data DQ _OUT can be made constant. The operation of the parallel / serial conversion circuit 47 can be given a margin.

Further, FCRAM26 the serial / parallel conversion circuit 50 provided after the data input buffer 49, and transfers the input data DQ _IN bit length corresponding the data input buffer 49 to the burst length sequentially to the serial / parallel conversion circuit 50, These are parallelized and transmitted to a selected bank so that writing can be performed in parallel, thereby speeding up the write operation. As described above, the complementary input strobe signal QS _IN , / QS _IN can be made constant and the input data DQ _IN can be fixed at a constant time, so that the operation of the serial / parallel conversion circuit 50 can be given a margin.

It is a circuit diagram which shows a part of one Embodiment of the electronic device of this invention. It is a circuit diagram which shows the principal part of FCRAM (one Embodiment of DDR-SDRAM of this invention) with which one Embodiment of the electronic device of this invention is provided. It is a circuit diagram which shows the structure of the data output buffer and strobe output buffer with which FCRAM (one Embodiment of DDR-SDRAM of this invention) with which one Embodiment of the electronic device of this invention is equipped is provided. It is a circuit diagram which shows the structure of the data input buffer with which FCRAM (one Embodiment of DDR-SDRAM of this invention) with which one Embodiment of the electronic device of this invention is provided is provided, and a strobe input buffer. Relationship between complementary clock signal, complementary output strobe signal, and continuous 2-bit output data at the time of data output from FCRAM (an embodiment of the DDR-SDRAM of the present invention) provided in the electronic device of the present invention FIG. To describe another example of a method for setting a level of a complementary output strobe signal in a preamble time at the time of data output from an FCRAM (an embodiment of a DDR-SDRAM of the present invention) included in an embodiment of an electronic device of the present invention FIG. It is a wave form diagram for demonstrating the other example of the level setting method of the complementary output strobe signal in the waiting time of FCRAM (one Embodiment of DDR-SDRAM of this invention) with which one Embodiment of the electronic device of this invention is equipped. FIG. 12 is a waveform diagram for explaining still another example of the level setting method of the complementary output strobe signal in the standby time of the FCRAM (one embodiment of the DDR-SDRAM of the present invention) included in one embodiment of the electronic device of the present invention. . It is a wave form diagram which shows the case where the cross point of a complementary output strobe signal gives the center point of output data. Relationship between complementary clock signal, complementary input strobe signal, and continuous 2-bit input data at the time of data input to FCRAM (an embodiment of the DDR-SDRAM of the present invention) provided in an electronic device of the present invention FIG. To describe another example of a method for setting a level of a complementary input strobe signal in a preamble time at the time of data input to an FCRAM (an embodiment of a DDR-SDRAM of the present invention) included in an embodiment of an electronic device of the present invention FIG. It is a wave form diagram for demonstrating the other example of the level setting method of the complementary input strobe signal in the standby time of the controller chip with which one Embodiment of the electronic device of this invention is provided. It is a wave form diagram for explaining the other example of the level setting method of the complementary input strobe signal in the waiting time of the controller chip with which one embodiment of the electronic device of the present invention is provided. It is a wave form diagram which shows the case where the cross point of a complementary input strobe signal gives the center point of input data. It is a circuit diagram which shows a part of example of the conventional electronic device. FIG. 16 is a circuit diagram showing a main part of a DDR-SDRAM included in the conventional electronic device shown in FIG. 15. FIG. 16 is a waveform diagram illustrating a relationship between a complementary clock signal, an output strobe signal, and output data when data is output from a DDR-SDRAM included in the conventional electronic device illustrated in FIG. 15. FIG. 16 is a waveform diagram showing a relationship between a complementary clock signal, an input strobe signal, and input data when data is input to a DDR-SDRAM included in the conventional electronic device shown in FIG. 15.

Explanation of symbols

CLK, / CLK clock signal QS _OUT , / QS _OUT complementary output strobe signal DS _IN , / DS _IN complementary input strobe signal 1... DDR-SDRAM
2 ... Normal phase clock signal line 3 ... Reverse phase clock signal line 4 ... Command bus 5 ... Address bus 6 ... Data bus 7 ... Strobe signal line 9 ... Command buffer 10 ... Command decoder 11 ... Controller 12 ... Address buffer 13-1, 13-m ... address latches 14-1, 14-m ... banks 15-1, 15-m ... memory cell arrays 16-1, 16-m ... row decoders 17-1, 17-m ... sense amplifiers 18-1, 18 -M ... column decoder 19-1, 19-m ... data bus buffer 20-1, 20-m ... write buffer 21 ... data output buffer 22 ... data input buffer 23 ... strobe output buffer 24 ... strobe input buffer 26 ... FCRAM ( Embodiment of DDR-SDRAM of the present invention)
27 ... Normal phase clock signal line 28 ... Reverse phase clock signal line 29 ... Command bus 30 ... Address bus 31 ... Data bus 32 ... Normal phase strobe signal line 33 ... Reverse phase strobe signal line 35 ... Command buffer 36 ... Command decoder 37 ... Address buffers 38-1, 38-m ... Address latches 39-1, 39-m ... Banks 40-1, 40-m ... Memory cell arrays 41-1, 41-m ... Row decoders 42-1, 42-m ... Sense Amplifiers 43-1, 43-m ... Column decoders 44-1, 44-m ... Active pre-controllers 45-1, 45-m ... Data bus buffers 46-1, 46-m ... Write buffers 47 ... Parallel / serial conversion Circuit 48... Data output buffer 49... Data input buffer 50... Serial / parallel conversion circuit 51. Trobe output buffer 52 ... Strobe input buffer 54, 55 ... nMOS transistor 56 ... Inverter 57, 58 ... pMOS transistor 59 ... Latch circuit 60, 61 ... Inverter 62 ... Latch circuit 63, 64 ... Inverter 65-1, 65-2, 65 -N: NAND circuit 66-1, 66-2, 66-N ... Three-state inverter 67 ... NAND circuit 68 ... Inverter 69 ... NAND circuit 70, 71 ... Three-state inverter 73, 74 ... Differential amplifier 75-1, 75 -2, 75-N ... Synchronous flip-flop circuit

Claims (16)

Double data rate synchronous dynamic that operates in synchronization with the rising edge and falling edge of the positive phase clock signal, receiving the positive phase clock signal and the negative phase clock signal that is in reverse phase relation to the positive phase clock signal A random access memory,
A command decoder that decodes a command signal input from the outside and determines whether it is a read mode or a write mode;
A plurality of banks each including a memory cell array;
A parallel / serial conversion circuit for converting a plurality of parallel data read from a selected bank of the plurality of banks into serial data in the read mode;
A data output buffer for receiving serial data from the parallel / serial conversion circuit and outputting the read data to the outside during the read mode;
In the read mode, the positive-phase output strobe signal is synchronized with the edge point of the read data so that the cross-point between the positive-phase output strobe signal and the negative-phase output strobe signal having a negative phase relationship with the positive-phase output strobe signal is synchronized with the edge point of the read data And a strobe output buffer for outputting the negative phase output strobe signal,
A data input buffer for inputting a plurality of serially input write data from the outside during the write mode;
In the write mode, the positive phase input strobe signal is synchronized with the center point of the write data so that the cross point of the positive phase input strobe signal and the negative phase input strobe signal having a negative phase relationship with the positive phase input strobe signal is synchronized with the center point of the write data. And a strobe input buffer to which the negative phase input strobe signal is input,
A serial / parallel conversion circuit for converting serial data from the data input buffer into parallel data and transferring the parallel data to a selected bank of the plurality of banks in the write mode;
A double data rate synchronous dynamic random access memory. A predetermined period before the first cross point indicating the start of the normal phase output strobe signal and the negative phase output strobe signal is defined as a first preamble time. During this time, the normal phase output strobe signal is low level, and the negative phase output The strobe signal is high,
2. The double data rate synchronous dynamic random according to claim 1, wherein both the positive phase output strobe signal and the negative phase output strobe signal are in a floating state before the first preamble time. Access memory. A predetermined period before the first cross point indicating the start of the normal phase input strobe signal and the negative phase input strobe signal is defined as a second preamble time. During this time, the normal phase input strobe signal is low level, and the negative phase input The strobe signal is high,
3. The double data rate synchronous dynamic according to claim 1, wherein both the positive phase input strobe signal and the negative phase input strobe signal are in a floating state before the second preamble time. • Random access memory. A latch circuit for holding the data enable signal in response to the internal clock;
The double data signal according to any one of claims 1 to 3, wherein the data enable signal is held in the latch circuit and activates the data output buffer and the strobe output buffer. Rate-synchronous dynamic random access memory. 5. The double strobe output according to claim 1, wherein the strobe output buffer generates the positive phase output strobe signal and the negative phase output strobe signal from one internal output strobe signal. Data rate synchronous dynamic random access memory. The double strobe signal according to any one of claims 1 to 5, wherein the strobe input buffer generates one internal input strobe signal from the positive phase input strobe signal and the negative phase input strobe signal. Data rate synchronous dynamic random access memory. 7. The double data rate synchronous dynamic random access memory according to claim 6, wherein the data input buffer latches the plurality of write data in synchronization with the internal input strobe signal. 8. The double data rate synchronous dynamic random access memory according to claim 1, wherein the number of data of the read data and the write data is set. A semiconductor memory device;
A controller chip;
A positive phase clock signal line for transmitting a positive phase clock signal;
A negative phase clock signal line for transmitting a negative phase clock signal having a negative phase relationship with the normal phase clock signal;
A command bus for transmitting a command signal between the semiconductor memory device and the controller chip;
An address bus for transmitting a row address signal and a column address signal between the semiconductor memory device and the controller chip;
A data bus for transmitting data between the semiconductor memory device and the controller chip;
A positive phase strobe signal line for transmitting a positive phase strobe signal between the semiconductor memory device and the controller chip;
An electronic device comprising a negative phase strobe signal line for transmitting a negative phase strobe signal between the semiconductor memory device and the controller chip;
The semiconductor memory device
A double data rate synchronous dynamic random access memory that receives the normal phase clock signal and the reverse phase clock signal and operates in synchronization with a rising edge and a falling edge of the normal phase clock signal. And
A command decoder for decoding a command signal input from the controller chip via the command bus and determining a read mode or a write mode;
A plurality of banks each including a memory cell array;
A parallel / serial conversion circuit for converting a plurality of parallel data read from a selected bank of the plurality of banks into serial data in the read mode;
A data output buffer for receiving serial data from the parallel / serial conversion circuit and outputting the read data to the controller chip via the data bus during the read mode;
In the read mode, the positive-phase output strobe signal is synchronized with the edge point of the read data so that the cross-point between the positive-phase output strobe signal and the negative-phase output strobe signal having a negative phase relationship with the positive-phase output strobe signal is synchronized with the edge point of the read data And a strobe output buffer for outputting the negative phase output strobe signal to the controller chip via the positive phase strobe signal line and the negative phase strobe signal line,
A data input buffer for inputting a plurality of serially input write data from the controller chip via the data bus during the write mode;
In the write mode, the positive phase input strobe signal is synchronized with the center point of the write data so that the cross point of the positive phase input strobe signal and the negative phase input strobe signal having a negative phase relationship with the positive phase input strobe signal is synchronized with the center point of the write data. And a strobe input buffer in which the negative phase input strobe signal is input from the controller chip via the positive phase strobe signal line and the negative phase strobe signal line,
A serial / parallel conversion circuit for converting serial data from the data input buffer into parallel data and transferring the parallel data to a selected bank of the plurality of banks in the write mode;
An electronic device comprising: a double data rate synchronous dynamic random access memory. A fixed period before the first cross point indicating the start of the positive phase output strobe signal and the negative phase output strobe signal is set as a preamble time. During this time, the positive phase output strobe signal is low level, and the negative phase output strobe signal is Is at a high level,
10. The electronic device according to claim 9, wherein both the positive phase output strobe signal and the negative phase output strobe signal are in a floating state before the preamble time. A predetermined period before the first cross point indicating the start of the normal phase input strobe signal and the negative phase input strobe signal is defined as a second preamble time. During this time, the normal phase input strobe signal is low level, and the negative phase input The strobe signal is high,
11. The electronic device according to claim 9, wherein both the positive phase input strobe signal and the negative phase input strobe signal are in a floating state before the second preamble time. A latch circuit for holding the data enable signal in response to the internal clock;
12. The electronic device according to claim 9, wherein the data enable signal is held by the latch circuit and activates the data output buffer and the strobe output buffer. The electronic device according to any one of claims 9 to 12, wherein the strobe output buffer generates the normal phase output strobe signal and the negative phase output strobe signal from one internal output strobe signal. . The electronic device according to claim 9, wherein the strobe input buffer generates one internal input strobe signal from the normal phase input strobe signal and the negative phase input strobe signal. . 15. The electronic device according to claim 14, wherein the data input buffer latches the plurality of data in synchronization with the internal input strobe signal. 16. The electronic device according to claim 9, wherein the number of data of the read data and the write data is set.

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