JP2008112324A - Data transfer method and data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce useless cycles on a PCI (Peripheral Component Interconnect) bus to improve read transfer performance of continuous data of the PCI bus. <P>SOLUTION: In this data transfer method, when a PM_block 101 performs a retry response, an MM_block 102 reads the data from a memory 200, and reads the next data. When a PCI read request is newly performed, a data transfer device 100 transfers the data. Because a free space is generated in a DB_block 104 when transferring the data, the MM_block 102 automatically reads the next data from the memory 200, and stores them into the DB_block 104. When receiving a PCI read request of the following data, the data transfer device 100 distinguishes whether the request data to the PCI read request is present in the DB_block 104 or not. When the data are already present, the data are transferred. The data transfer device 100 manages an address in the memory of the data read from the memory by a DM_block 103. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer method and a data transfer apparatus for transferring data via a PCI bus.

  A personal computer or the like is provided with a PCI (Peripheral Component Interconnect) bus. With the recent development of digital technology, the amount of data to be processed has increased, and the need for technology to improve the processing speed has increased. Therefore, various techniques for improving the data transfer speed on the PCI bus have been proposed (see, for example, Patent Document 1).

  Patent Document 1 describes a data control device that improves the data transfer speed by minimizing the latency over the entire bus. The data transfer control device described in Patent Document 1 holds information on frequently accessed addresses as a preset address and periodically reads the data. As a result, the data transfer device can improve the data transfer rate to some extent.

JP 2004-054527 A (paragraphs 0037-0041, FIGS. 3 and 4)

  In PCI bus read transfer, control may be performed in which the PCI master performs prefetch read using a PCI bus command such as a memory read line to improve transfer performance. At that time, a useless cycle (for example, a retry cycle or a wait cycle) is executed on the PCI bus due to the difference in the size of the data buffer between the PCI master and the PCI slave. FIG. 8 is a sequence diagram showing a simplified process of the data transfer method by the master device and the slave (target) device. Here, a case where a master device (hereinafter referred to as a PCI master) is about to read 32-byte data will be described. Further, it is assumed that the size (buffer size) of the buffer memory included in the slave device (hereinafter referred to as PCI slave) is 16 bytes. The size of the buffer memory included in the PCI master is assumed to be 8 bytes.

  When the PCI master needs data in the memory from which the PCI slave reads data, the PCI master outputs a read request (PCI read 1) to the PCI slave (step S801).

  The PCI slave executes a process of reading data from the memory (memory read 1) (step S802). PCI slaves cannot read data from memory immediately. Therefore, data cannot be output immediately to the PCI master. Therefore, the PCI slave makes a retry response (retry response 1) (step S803).

  The PCI slave reads data from the memory (read data 1), and further executes a next data read process (memory read 2 prefetch) (step S804). The amount of data read from the memory by the PCI slave depends on the buffer size (16 bytes in this example) of the PCI slave. Although the PCI slave may have a plurality of buffers, in the example shown in FIG. 8, it is assumed that the PCI slave has one buffer.

  The PCI master again outputs a PCI read request command (PCI read 1 re-request) to the PCI slave after several cycles (step S805). If there is a PCI read re-request after the PCI slave completes reading of data from the memory (that is, ready for data transfer), the PCI slave transfers the data to the PCI master (data transfer 1). (Step S806). When the PCI master receives data corresponding to the buffer size of the PCI master, the PCI master ends the data transfer.

  The PCI master outputs a PCI read request command (PCI read 2) to request subsequent data (step S807). And the process similar to step S801-806 is performed.

  For example, in the example shown in FIG. 8, the PCI master receives only 8 bytes of data after outputting the PCI read request command (PCI read 1). Since a normal PCI slave does not manage the address of the data stored in the buffer memory, it accepts the PCI read request 2 as a new request. Therefore, the PCI slave reads again the same data as the 8 bytes remaining in the buffer memory (step S808). Therefore, in order for the PCI slave to transfer 32-byte data, the same processing as steps S801 to S806 must be executed four times.

  FIG. 9 is a flowchart showing a simplified operation of the PCI slave. In the example shown in FIG. 9A, when the PCI slave inputs an instruction to read data stored in the memory from the PCI master (step S901), the PCI slave inserts a wait cycle (step S902). When reading of data from the memory is completed, the PCI slave transfers data to the PCI master (step S903).

  In the example shown in FIG. 9B, when the PCI slave inputs an instruction to read data stored in the memory from the PCI master (step S901), it sends a PCI retry response (step S904). When the PCI read re-request is input after the data reading from the memory is completed (step S905), the PCI slave transfers the data to the PCI master (step S903). This example corresponds to the example shown in FIG.

From the above, it can be seen that the data transfer method shown in FIGS. 8 and 9B has the following problems.
(1) In order for the PCI master to complete one PCI read request command, it is necessary to perform two PCI read request commands (for example, step S801 and step S805 in the example shown in FIG. 8) each time. . That is, a retry response is executed every time data is transferred to the PCI master.
(2) The PCI slave reads the same data twice (for example, step S804 and step S808 in the example shown in FIG. 8).

  The problems in the above (1) and (2) are caused by the fact that the start address and the data amount depend on the PCI master in the data transfer by PCI. As a result, a useless cycle (for example, a retry cycle or a wait cycle) is executed on the PCI bus.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer method and a data transfer device that can reduce the generation of useless cycles in the PCI bus and improve the read transfer performance of continuous data on the PCI bus. .

  A data transfer method according to the present invention is a data transfer method for transferring continuous data on a PCI bus, and in response to a PCI read request command, reading requested data from a storage means and storing it in a buffer memory; Storing the address in the storage means of the data stored in the buffer memory, and controlling the data to be transferred to the PCI master device based on the address.

  A data transfer method according to the present invention includes a step of determining whether data corresponding to a PCI read request command is stored in a buffer memory based on a stored address when a PCI read request command is input. When it is determined that the data corresponding to the read request command is stored in the buffer memory, it is preferable to transfer the data stored in the buffer memory to the PCI master device.

  The data transfer method according to the present invention includes a step of determining whether or not the data stored in the buffer memory is valid, and is requested when it is determined that the data stored in the buffer memory is invalid. Preferably, the step of reading the data from the storage means and storing it in the buffer memory is performed.

  The data transfer method according to the present invention may be configured to invalidate the data stored in the buffer memory when the data stored in the buffer memory is transferred to the PCI master device.

  Also, in the data transfer method according to the present invention, when there is a PCI read request command, a predetermined amount of data is read from the storage means and stored in the buffer memory, and the PCI requesting data not stored in the storage means is requested. Until the read request command is input, the next data may not be read from the storage unit.

  A data transfer apparatus according to the present invention is a data transfer apparatus for executing continuous data transfer on a PCI bus, and includes a control means for controlling the PCI bus according to a PCI read request command from a PCI master device, and a PCI request command. In response to the request, the data is read from the storage means and stored in the buffer memory, and the control information storage means for storing the address in the storage means of the data stored in the buffer memory by the data read means is provided. The means controls data to be transferred based on the address.

  In the data transfer apparatus according to the present invention, when the PCI read request command is input from the PCI master device, whether the data corresponding to the PCI read request command is stored in the buffer memory based on the address stored by the information management unit If it is determined that the data corresponding to the PCI read request command is stored in the buffer memory, it is preferable to transfer the data stored in the buffer memory to the PCI master device.

  The management information storage means in the data transfer apparatus according to the present invention stores valid information indicating whether or not the data stored in the buffer memory is valid, and the data read means is when the valid information indicates invalidity, It is preferably configured to read data from the storage means.

  The control means in the data transfer apparatus according to the present invention may be configured to put the valid information in a state indicating invalidity when the data stored in the buffer memory is transferred to the PCI master device. Further, the control means indicates that invalid information is invalid when data at an address different from the address in the memory means for storing data stored in the buffer memory is requested by a PCI read request command from the PCI master device. You may be comprised so that it may become.

  The data reading means in the data transfer apparatus according to the present invention reads a predetermined amount of data from the storage means and stores it in the buffer memory when there is a PCI read request command from the PCI master device, and stores the data in the buffer reading memory. May be configured not to execute reading of the next data from the storage unit until a PCI read request command for requesting data not stored in the storage unit is input.

  A data transfer device according to a preferred embodiment of the present invention includes a block for reading data from a memory (for example, MM_block 102), and a block for managing the address of the data read from the memory and the validity / invalidity of the data (for example, DM_ And a block (for example, PM_block 101) for controlling the PCI bus based on information obtained from the DM_block 103. With such a configuration, useless cycles on the PCI bus can be reduced, and read transfer performance of continuous data on the PCI bus can be improved.

  According to the present invention, useless cycles on the PCI bus can be reduced, and the transfer rate of continuous data on the PCI bus can be improved.

Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a system configuration diagram showing a configuration example of a data transfer system including a data transfer apparatus according to the present invention. The data transfer apparatus 100 includes a PM_block (PCI management block) 101, an MM_block (memory management block) 102, a DM_block (data management block) 103, and a DB_block (buffer memory) 104. The PM_block 101 and the DB_block 104 are connected to the PCI bus 300. In addition, the MM_block 102 can access the memory 200.

  The PM_block 101 has a function of controlling the PCI bus according to information from the DM_block 103. Specifically, the PM_block 101 inputs a PCI read request command from the PCI master via the PCI bus 300, and executes processing such as a PCI retry response. For example, the PM_block 101 controls the PCI bus according to a delayed transaction. When the PM_block 101 receives the PCI read request command, the PM_block 101 requests the MM_block 102 to read data from the memory 200. That is, the PM_block 101 corresponds to a control unit that causes the MM_block 102 to perform memory access according to the input PCI command, and sends the data stored in the DB_block 104 to the PCI bus.

  The MM_block 102 controls memory access according to the request from the PM_block 101 and the information from the DM_block 103. Specifically, the MM_block 102 reads data from the memory 200 when the PM_block 101 requests to read data from the memory 200 based on the input of the PCI read request command. Data read from the memory 200 is stored in the DB_block 104. The MM_block 102 is a management unit that stores an address in the memory 200 of the data stored in the DB_block 104 in a DM_block (data management block) 103 serving as a management information storage unit.

  The PM_block 101 and the MM_block 102 are realized by, for example, a hardware circuit (logic circuit) that realizes a control function and a management function.

  The DM_block 103 stores an address of data read from the memory 200 in the memory 200, information on validity / invalidity of data (hereinafter referred to as valid information), and the like. The valid information is information indicating whether data that can be transferred to the PCI master exists in the DB_block 104. That is, it is information indicating whether or not the DB_block 104 has a free area. When the valid information indicates “valid”, it indicates that data that can be transferred to the PCI master exists in the DB_block 104, and when the valid information indicates “invalid”, the PCI master indicates This indicates that there is no data that can be transferred in the DB_block 104. In other words, it indicates that an empty area exists in the DB_block 104. Note that any information may be used as valid information as long as it is information that can specify whether or not there is a free area in the DB_block 104. In the example shown in FIG. 2 to be described later, the valid information is set to the invalid state by transferring the data to the PCI master. It should be noted that the fact that the valid information is invalid indicates that new data may be overwritten in the area of the DB_block 104.

  The DB_block 104 may have a FIFO function or may be a simple buffer. In the present embodiment, it is assumed that the DM_block 103 includes an 8-byte first buffer memory and an 8-byte second buffer memory. The valid information includes first valid information corresponding to the first buffer memory and second valid information corresponding to the second buffer memory.

  Next, the operation of the data transfer apparatus 100 of this embodiment will be described. FIG. 2 is a sequence diagram for explaining processing of the data transfer system including the data transfer apparatus 100. In FIG. 2, the same reference numerals as those in FIG. 8 are attached to the same operations as those in the data transfer method shown in FIG. A case will be described in which a master device (hereinafter referred to as a PCI master) is about to read 32-byte data. The buffer size in the PCI master is 8 bytes, and the PCI master inputs data from the PCI slave by 8 bytes.

  When the PCI master needs data in the memory 200 from which the data transfer device 100 reads data, the PCI master outputs a read request command (PCI read 1) to the data transfer device 100 (step S801). The PM_block 101 inputs a PCI read request command.

  The MM_block 102 executes a process of reading data from the memory 200 (memory read 1) (step S802). The MM_block 102 cannot read data from the memory 200 immediately. That is, data cannot be output immediately to the PCI master. Therefore, the PM_block 101 makes a retry response (retry response 1) (step S803). The MM_block 102 reads data from the memory 200 when the valid information indicates invalidity, but in the initial state, the valid information indicates invalidity.

  The MM_block 102 reads data (for example, 8-byte data) from the memory 200 (read data 1), and further executes a read process (memory read 2 prefetch) of the next data (for example, 8-byte data). (Step S804). The read data is stored in the DB_block 104. In the present embodiment, the MM_block 102 reads data from the memory 200 until there is no free area in the DB_block 104. Therefore, in this example, data is stored in both the first buffer memory and the second buffer memory. Further, the MM_block 102 sets the first valid information stored in the DM_block 103 to a valid state and sets the second valid information to a valid state.

  The DM_block 103 stores the address in the memory 200 of the read data. For example, the address in the memory 200 of the data stored at the head of the first buffer memory is stored, and the address in the memory 200 of the data stored at the head of the second buffer memory is stored. In this embodiment, the information related to the address stored in the DM_block 103 is only the address of the data stored at the head. However, such control is an example, for example, stored at the head. In addition to the data address, information indicating how many bytes of valid data are stored in the buffer memory may be stored.

  The PCI master again outputs a PCI read request command (PCI read 1 re-request) to the PM_block 101 after several cycles (step S805). If there is a PCI read re-request after the MM_block 102 has finished reading data from the memory 200 (ie, ready for data transfer), the data is transferred from the DB_block 104 to the PCI master. In the example shown in FIG. 2, since the data read from the memory 200 by the MM_block 102 has been completed, the data transfer apparatus 100 makes a data transfer response (data transfer 1) (step S806).

  When the PCI master receives data corresponding to the buffer size of the PCI master, the PCI master ends the data transfer from the data transfer apparatus 100. That is, the PCI master ends the transaction according to the PCI bus protocol.

  When the data is transferred, the DB_block 104 becomes empty, so the MM_block 102 automatically reads the next data (read data 3) from the memory 200 (step S101). The MM_block 102 reads data from the address next to the address of the data that has already been read. That is, the MM_block 102 reads the next data (read data 3) from the memory 200. Note that when the data read from the memory 200 is stored in the buffer memory, the MM_block 102 regards the data stored in the buffer memory as valid. That is, the valid information is set to a valid state. Further, the PM_block 101 regards the data stored in the buffer memory as invalid when the data is transferred to the PCI master. That is, the valid information corresponding to the buffer memory in which the data is stored is set to a state indicating invalidity.

  When the PCI master receives data from the data transfer apparatus 100, the PCI master outputs a PCI read request command (PCI read 2) for the subsequent data to the data transfer apparatus 100 (step S807). When a PCI read request command is input, the PM_block 101 already has request data for the PCI read request command (PCI read 2) (data at the address requested to be transferred by the PCI read request command) in the DB_block 104. Judge whether or not. Specifically, the PM_block 101 determines whether the request data exists in the DB_block 104 based on the address and valid information that the DM_block 103 has. In the example in FIG. 2, since the requested data has already been read (read data 2), the PM_block 101 makes a data transfer response (data transfer 2) (step S102).

  Since the data transfer apparatus 100 manages the address information of the data read from the memory 200 stored in the DM_block 103, the second PCI read request command (PCI read 2) is sent to the new PCI read. It is not considered a request command. For example, in the example shown in FIG. 2, since the address in the memory 200 of the data read from the memory 200 is stored in the DM_block 103, the MM_block 102 sends the data without making a retry response to the PCI master. Can be transferred.

  Therefore, the same data is not read twice unlike the data transfer method shown in FIG. As a result, the data transfer apparatus 100 can improve the read transfer performance of continuous data.

  Next, the operation of the PM_block 101 will be described. FIG. 3 is a flowchart showing the operation of the PM_block 101. When a PCI read request command is input from the PCI master, the PM_block 101 determines whether the request data is stored in the DB_block 104. Specifically, the PM_block 101 makes a determination based on the information (address and valid information) stored in the DM_block 103 (step S301). Note that when the data stored in the DB_block 104 is valid, the PM_block 101 is requested for data at an address different from the address stored in the DM_block 103 by the PCI read request command from the PCI master. In the case where it is found, the valid information is changed to a state indicating invalidity, and the process proceeds to step S304.

  If it is determined that the request data is stored in the DB_block 104 (step S301: YES), the PM_block 101 controls the request data to be transferred from the DB_block 104 to the PCI master (step S302). Then, the data stored in the DB_block 104 is invalidated. That is, the PM_block 101 sets the valid information stored in the DM_block 103 corresponding to the transferred data to a state indicating invalidity (step S303). Thereafter, the MM_block 102 can store the data read from the memory 200 in the area of the DB_block 104 corresponding to valid information indicating an invalid state.

  When it is determined that the request data is not stored in the DB_block 104 (when the valid information is invalid or when data of an address different from the address stored in the DM_block 103 is requested and the valid information is invalid (Step S301: NO), the PM_block 101 makes a PCI retry response to the PCI master (step S304). Then, the PM_block 101 issues a request to read data from the memory 200 to the MM_block 102 (step S305).

  Next, the operation of the MM_block 102 will be described. FIG. 4 is a flowchart showing the operation of the MM_block 102. When the MM_block 102 receives a PCI read request command from the PM_block 101, the MM_block 102 reads data from the memory 200.

  First, the MM_block 102 determines whether or not there is a vacancy in the DB_block 104 (step S401). For example, the MM_block 102 determines whether the DB_block 104 is free by determining whether the valid information corresponding to the data stored in the DB_block 104 is invalid. When valid information indicating invalidity exists in the DM_block 103, the MM_block 102 determines that there is a free space in the DB_block 104.

  If the DB_block 104 is empty (step S401: YES), the MM_block 102 reads data from the memory 200 (step S402).

  As described above, since the data transfer apparatus 100 manages the address in the memory 200 of the data read from the memory 200 based on the information stored in the DM_block 103, the second PCI read request command (for example, The PCI read 2) in FIG. 2 is not regarded as a new PCI read request command. Therefore, the data transfer apparatus 100 can transfer data to the PCI master without executing a useless retry response (for example, retry response 2 in the data transfer method shown in FIG. 8).

  As described above, the data transfer apparatus 100 according to the present embodiment can reduce useless PCI cycles when the PCI master executes continuous data reading divided into several transactions. As a result, the data transfer performance is improved.

  Further, since the data transfer apparatus 100 can reduce useless access to the memory 200 (for example, memory read 2 in step S808 in FIG. 8), the performance of other resources sharing the memory 200 can be improved. it can.

  In the present embodiment, the PM_block 101 manages valid information in units of prefetch buffers, that is, corresponding to each of the first buffer memory and the second buffer memory. The valid information is managed (from a state indicating validity to a state indicating invalidity, or from a state indicating invalidity to a state indicating validity). However, such a management method is an example. You may manage by another arbitrary unit, for example, 1 byte, 4 byte unit, and multiple buffer memory unit (for example, 2 buffer memory unit).

Embodiment 2. FIG.
Next, a second embodiment will be described with reference to the drawings. FIG. 5 is a sequence diagram for explaining processing in the data transfer system including the data transfer apparatus according to the second embodiment. The data transfer apparatus 100 reads a predetermined amount of data from the memory 200 in response to a single PCI read request command from the PCI master. In FIG. 5, the same reference numerals as those in FIG. 8 are given to the same processes as those in the data transfer method shown in FIG.

  In the data transfer system, the processes in steps S801 to S806 are executed as in the first embodiment. Unlike the first embodiment, the data transfer apparatus 100 is configured to perform a memory read prefetch (after the process in step S806) after transferring data even if the valid information is invalid. Step S101 in FIG. 2 is not executed. When the data transfer apparatus 100 receives a PCI read request command (PCI read 2) from the PCI master (step S807), the data transfer apparatus 100 transfers the data stored in the DM_block 103 to the PCI master (step S201).

  The PM_block 101 makes valid information stored in the DM_block 103 invalid when all data stored in the DM_block 103 is transferred to the PCI master.

  When the PCI master receives data from the data transfer apparatus 100, the PCI master outputs a PCI read request command (PCI read 3) to the data transfer apparatus 100 in order to request subsequent data (step S202). When PM_block 101 requests to read data from memory 200 in response to input of a PCI read request command, MM_block 102 determines whether the requested data for the request already exists in DB_block 104. .

  The MM_block 102 determines whether or not the request data is stored in the DB_block 104 by determining whether or not the valid information corresponding to the data stored in the DB_block 104 is valid. To do. When valid information indicating a valid state exists in the DM_block 103, the MM_block 102 determines that the request data is stored in the DB_block 104.

  In the example in FIG. 5, since the requested data has not been read, there is valid information indicating a state of invalidity, and the MM_block 102 executes a process of reading data from the memory 200 (memory read 3) (step 3). S203).

  Note that the MM_block 102 cannot immediately read the requested data from the memory 200. That is, since the PM_block 101 cannot immediately output data to the PCI master, it makes a retry response (retry response 3) (step S204). Then, the MM_block 102 reads data from the memory 200 (read data 3), and further executes a next data read process (memory read 4 prefetch) (step S205).

  As described above, the MM_block 102 reads a predetermined amount of data from the memory 200 in response to one PCI read request command. In this example, 16-byte data that is the sum of the size of the first buffer memory and the size of the second buffer memory is read from the memory 200.

  Next, the operation of the MM_block 102 will be described. FIG. 6 is a flowchart showing the operation of the MM_block 102. When the PM_block 101 requests to read data from the memory 200 in response to the input of the PCI read request command, the MM_block 102 executes a process of reading a predetermined amount of data from the memory 200.

That is, the MM_block 102 until a determined amount of data is read from the memory 200 (step S601). The process of reading data from the memory 200 (step S602) is repeated. The read data is stored in the DB_block 104.

  Next, the operation of the PM_block 101 will be described. FIG. 7 is a flowchart showing the operation of the PM_block 101. In FIG. 7, the same reference numerals as those in FIG. 3 are assigned to the same operations as those of the PM_block 101 of the first embodiment shown in FIG.

  When a PCI read request command is input from the PCI master, the PM_block 101 determines whether the request data is stored in the DB_block 104 (step S301). Specifically, the PM_block 101 makes a determination based on information (address and valid information) that the DM_block 103 has.

  If it is determined that the request data is stored in the DB_block 104 (step S301: YES), the PM_block 101 controls the request data to be transferred from the DB_block 104 to the PCI master (step S302). .

  When it is determined that the request data is not stored in the DB_block 104 (step S301: NO), the PM_block 101 sends a PCI retry response to the PCI master (step S304). Then, the PM_block 101 issues a request to read data from the memory 200 to the MM_block 102 (step S305).

  As described above, the data transfer apparatus 100 according to the present embodiment reads a predetermined amount of data from the memory 200 in response to a single PCI read request command from the PCI master. Then, reading of the next data from the memory 200 is not performed until a PCI read request command for requesting data not stored in the DB_block 104 is input. Similarly to the case of the first embodiment, when data that can be output is stored in the DB_block 104 when a PCI read request command is input, the data is immediately output to the PCI master. In this embodiment, the PCI master inputs data of a certain address block (a plurality of areas having consecutive addresses), performs processing based on the input data, and transfers data of other address blocks according to the processing result. This is meaningful in the case of repeatedly executing control that performs input and processes based on the input data.

  In this embodiment, the validity information is changed to an invalid state when all data stored in the DM_block 103 is transferred to the PCI master. However, the validity information is changed even if the data is transferred to the PCI master. The information is not changed to an invalid state, and the valid information is changed to a state indicating invalid when data of an address different from the address stored in the DM_block 103 is requested by a PCI read request command from the PCI master. You may do it. Further, management may be performed in an arbitrary unit, for example, 1 byte or 4 byte unit, one buffer memory unit, or a plurality of buffer memory units.

Embodiment 3 FIG.
The blocks of the data transfer apparatus 100 shown in FIG. 1 may be multiplexed to improve the data transfer performance.

  When the blocks are multiplexed, the data transfer apparatus 100 is configured to have a plurality of DM_blocks 103, for example. In such a configuration, the data transfer device 100 can read data in parallel from the memory 200, and can further improve the data transfer performance.

  The present invention is applied to an apparatus or system having a PCI bus.

1 is a system configuration diagram illustrating a configuration example of a data transfer system including a data transfer device. It is a sequence diagram for demonstrating the process of a data transfer system. 4 is a flowchart showing the operation of the PM_block 101. 5 is a flowchart showing an operation of an MM_block 102. It is a sequence diagram for demonstrating the process of the data transfer system containing the data transfer apparatus 100 in 2nd Embodiment. It is a flowchart which shows operation | movement of the MM_block 102 of 2nd Embodiment. It is a flowchart which shows operation | movement of PM_block 101 of 2nd Embodiment. It is a sequence diagram which simplifies and shows the process of the data transfer method by a master device and a slave device. FIG. 9 is a flowchart showing a simplified operation of a PCI slave in the example shown in FIG. 8.

Explanation of symbols

100 Data Transfer Device 101 PM_Block 102 MM_Block 103 DM_Block 104 DB_Block 200 Memory 300 PCI Bus

Claims (11)

A data transfer method for transferring continuous data on a PCI bus,
In response to a PCI read request command, reading the requested data from the storage means and storing it in the buffer memory;
Storing the address in the storage means of the data stored in the buffer memory,
A data transfer method, comprising: controlling data to be transferred to a PCI master device based on the address. Determining whether data corresponding to the PCI read request command is stored in the buffer memory based on the stored address when a PCI read request command is input;
The data transfer method according to claim 1, wherein when it is determined that data corresponding to the PCI read request command is stored in the buffer memory, the data stored in the buffer memory is transferred to a PCI master device. Determining whether the data stored in the buffer memory is valid,
The data transfer device according to claim 1 or 2, wherein when it is determined that the data stored in the buffer memory is invalid, the step of reading the requested data from the storage means and storing it in the buffer memory is executed. . The data transfer method according to claim 3, wherein when the data stored in the buffer memory is transferred to the PCI master device, the data stored in the buffer memory is invalidated. When there is a PCI read request command, a predetermined amount of data is read from the storage means and stored in the buffer memory.
The reading of the next data from the said memory | storage means is not performed until the PCI read request command which requests | requires the data which are not stored in the said memory | storage means is input. Data transfer method. A data transfer device that performs continuous data transfer on a PCI bus,
Control means for controlling the PCI bus according to a PCI read request command from the PCI master device;
Data reading means for reading data requested in response to the PCI request command from a storage means and storing the data in a buffer memory;
Management information storage means for storing addresses in the storage means of the data stored in the buffer memory by the data reading means,
The data transfer apparatus, wherein the control means controls data to be transferred based on the address. When a PCI read request command is input from the PCI master device, the control means determines whether data corresponding to the PCI read request command is stored in the buffer memory based on the address stored by the information management means. ,
The data transfer device according to claim 6, wherein when it is determined that data corresponding to the PCI read request command is stored in the buffer memory, the data stored in the buffer memory is transferred to the PCI master device. The management information storage means stores valid information indicating whether or not the data stored in the buffer memory is valid,
The data transfer device according to claim 6 or 7, wherein the data reading unit reads data from the storage unit when the valid information indicates invalidity. The data transfer apparatus according to claim 8, wherein the control means sets the valid information to a state indicating invalidity when the data stored in the buffer memory is transferred to the PCI master device. The control means puts the valid information in a state indicating invalidity when requested by the PCI read request command from the PCI master device for data at an address different from the address in the data storage means stored in the buffer memory. The data transfer device according to claim 8. When there is a PCI read request command from the PCI master device, the data reading means reads a predetermined amount of data from the storage means and stores it in the buffer memory.
The said data reading means does not perform reading of the next data from the said memory | storage means until it inputs the PCI read request command which requests | requires the data which are not stored in the said memory | storage means. The data transfer apparatus according to any one of claims.

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