JP2008108361A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size a control circuit for a nonvolatile semiconductor storage device, and achieve high speed operation/low power consumption by preparing micro computer control and a hardware wiring for resetting a register for the micro computer. <P>SOLUTION: A command analysis circuit 16 outputs a reset signal via a signal line 102 in accordance with a stop signal from the micro computer 20. The reset signal stops operation of the micro computer 20 and a power supply 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  The flash memory inputs an operation command from the outside and performs operation control such as data writing and erasing to the memory cell array. The operation command is a command with contents such as writing and block erasing, for example. The operation commands are standardized by JEDEC (for example, see Non-Patent Document 1).

  The operation control is generally performed by a write state machine built in the flash memory (see Non-Patent Document 1, for example). The reason why the write state machine is used is that flash memory that stores binary values of 0 or 1 in a memory cell is the mainstream, and the number of storage states that can be controlled by the write state machine. Because there was.

  On the other hand, with the expansion of storage applications, there is an increasing demand for increasing the memory capacity. Furthermore, in the portable storage market where flash memory has become extremely popular, due to the nature of portable, the memory capacity has been expanded, but the mounting area of the flash memory has been made compact, high-speed operability to improve operational convenience, There is a particularly high demand for low power consumption to improve battery life.

  Among them, as a method for increasing the memory capacity with a compact mounting area, there is a flash memory having multi-valued memory cells such as storing four values of 00, 01, 10, and 11, which meets the market demand. It is becoming mainstream in the future.

  Let us look at the operation control of a flash memory having multi-valued memory cells. For example, in the case of a flash memory storing four values, in addition to the increase in the storage state of the memory cell from two values to four values as compared with the conventional two values, for example, management of threshold voltage for each storage state, The state itself is increasing (see, for example, Patent Document 1). Further, it is necessary to control the state of a device unique to multi-values, such as detecting the storage state of a memory cell and transitioning to the next storage state. That is, in addition to an increase in the number of states, the state control processing is increased by orders of magnitude compared to a binary flash memory.

  Therefore, when the control unit of the multi-level flash memory is assembled by a write state machine by extending the binary flash memory, a control signal between the write state machine and a controlled circuit such as a memory cell array There is a problem that the number of lines increases and a compact mounting area cannot be realized.

  In addition, in a light state machine with a fixed control means, hardware changes are required to change or modify the control means, so work such as tuning the control means and adding control means in line with the detailed requirements of the market , There is a problem that can not be addressed immediately. At the same time, there is a problem that the cost of the design / manufacturing process increases.

As a method for solving these problems, a method of performing flash memory rewrite control with a microcomputer and firmware has been proposed (see, for example, Patent Document 2). However, the control means uses a general microcomputer instruction to control a new register, which is optimal for controlling a flash memory having multi-valued memory cells and has a compact mounting area. It has not gone into realization.
SHARP Flash Memory 8Mbit Product Model LH28F800BJE-PTTL70 Data Sheet Refer to page 5 From the SHARP electronic device website, access the product lineup data sheet list, and from the following URL for IC, April 14, 2005 (Thursday) Download at 11:00 http://www.sharp.co.jp/products/device/lineup/data/ic/index.html JP 2000-298992 A JP 2002-269065 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device that realizes high-speed operation and low power consumption with a compact mounting area.

In order to achieve the above object, a nonvolatile semiconductor memory device according to one embodiment of the present invention includes:
A nonvolatile semiconductor memory device having a storage area and a peripheral circuit area,
A memory cell array formed in the storage area;
A power supply circuit portion that is formed in the peripheral circuit region and supplies a read voltage, a write voltage higher than the read voltage, or an erase voltage higher than the read voltage to the memory cell array portion;
A first register unit storing data indicating an operation state of the memory cell array unit;
A second register unit storing data indicating whether the power supply circuit unit generates the read voltage, the write voltage, or the erase voltage;
When the data stored in the first register unit is read from the peripheral circuit region and the memory cell array unit determines that either the write state or the erase state has ended, the power supply circuit unit Storing the data for generating the read voltage in the second register unit, and then outputting a stop signal;
A clock generation circuit unit that is formed in the peripheral circuit region and supplies a clock to the microcomputer unit;
A command analysis circuit unit that is formed in the peripheral circuit region and outputs a reset signal in response to the stop signal output from the microcomputer unit, wherein the microcomputer unit and the clock generation circuit unit are configured to perform the command analysis. The operation is stopped according to the reset signal output from the circuit unit.

  The present invention can provide a nonvolatile semiconductor memory device that achieves high-speed operation and low power consumption with a compact mounting area.

(Configuration of flash memory)
Hereinafter, embodiments in which a nonvolatile memory device of the present invention is applied to a NOR flash memory will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the flash memory of this embodiment.

  The flash memory 1 of this embodiment has a storage area 2 and a peripheral circuit area 3.

(Storage area configuration)
The storage area 2 includes a memory cell array unit 4, a row decoder 5, a column decoder 6, a column gate 7, a sense amplifier 8, and an address bus 110.

  In the memory cell array unit 4, a plurality of NOR type memory cells are arranged in a matrix.

  The row decoder 5 decodes an address input via the address bus 110 and selects a word line (WL) in the memory cell array unit 4 corresponding to the input address.

  The column decoder 6 decodes the address input via the address bus 110, selects the column gate 7 corresponding to the input address, and converts the bit line (BL) in the memory cell array unit 4 to the sense amplifier 8 or It is connected to a verify circuit 16 described later.

  The sense amplifier 8 amplifies the data output from the memory cell array unit 4 via the column gate 7. The sense amplifier 8 has a sense amplifier register 9.

(Configuration of peripheral circuit area)
The peripheral circuit area 3 includes an address buffer unit 10, a data I / O buffer unit 12, a power supply circuit unit 14, a verify circuit unit 16, a command analysis circuit unit 18, a clock generation circuit unit 19, a microcomputer unit 20, and a bus 109. .

  The address buffer unit 10 outputs an address for designating a memory cell of the memory cell array unit 4 input from the outside to the address bus 110. In addition, an address for an operation command input from the outside is output to the command analysis circuit unit 18. The address buffer unit 10 has an address buffer unit register 11.

  The data I / O buffer unit 12 outputs externally input data to the verify circuit unit 16 and the command analysis circuit unit 18. Further, the data amplified by the sense amplifier 8 is output to the outside.

  The power supply circuit unit 14 supplies a voltage for executing data read / data write / data erase to the memory cell array unit 4. The power supply circuit unit 14 has a power supply circuit unit register 15.

  The verify circuit unit 16 generates data to be written to the memory cell array unit 4 from the data input from the data I / O buffer unit 12 during data write to the memory cell array unit 4, and outputs the data to the column gate 7. Further, the write data read from the sense amplifier 8 is compared with the input data, and it is confirmed whether the two data match or do not match. This verify circuit section 16 has a verify circuit section register 17.

  The command analysis circuit unit 18 analyzes the operation command input from the data I / O buffer unit 12, operates an interrupt signal to the microcomputer unit 20 through the signal line 104, and operates to the microcomputer unit 20 through the signal line 105. A vector number indicating the contents is output. In addition, the command analysis circuit unit 18 outputs a reset signal and a reset release signal to the signal line 102.

  The clock generation circuit unit 19 outputs an operation clock to the microcomputer unit 20 through the signal line 103.

  The microcomputer unit 20 controls the execution of data write or data erase to the memory cell array unit 4, for example, based on the interrupt signal and the vector number output from the command analysis circuit unit 18. This control operation is executed when the microcomputer unit 20 sets predetermined data in, for example, the register 9, the register 11, the register 15, and the register 17 via the bus 109.

  The microcomputer unit 20 includes a processor unit 21 and an instruction storage unit 22. The processor unit 21 operates based on the interrupt signal output from the command analysis circuit unit 18 via the signal line 104 and the vector number output via the signal line 105. An operation clock is input to the processor unit 21 from the clock generation circuit unit 19 via the signal line 103.

  The instruction storage unit 22 is a device that stores an instruction code for the processor unit 21. The processor unit 21 outputs an instruction address for designating an instruction code to the instruction storage unit 22 via the signal line 106 based on the vector number transmitted from the command analysis circuit. The instruction storage unit 22 outputs an instruction code to the processor unit 21 via the signal line 107 in accordance with the instruction address.

(Register configuration)
In this embodiment, the microcomputer unit 20 sets predetermined data in the sense amplifier register 9, the address buffer unit register 11, the power supply circuit register 14, and the verify circuit unit 16 register 17 via the bus 109. Thus, for example, data erase is executed. The register 9, the register 11, the register 15, and the register 17 will be described.

  The sense amplifier register 9 is a register in which the microcomputer unit 20 reads and writes data for designating operation stop or operation start of the sense amplifier 8 via the bus 109.

  When the signal line 102 is connected to the register 9 and a reset signal is output from the command analysis circuit unit 18, data in the initial state is written corresponding to the reset signal. The data in the initial state is data for designating the operation stop of the sense amplifier 8, and the sense amplifier 8 enters the operation stop state.

When a reset release signal is output from the command analysis circuit unit 18, data corresponding to the reset release signal is not written to the register 9, and the register 9 does not change.
The address buffer unit register 11 is a register for designating data for setting whether or not the address buffer unit 10 accepts external address input and an address set by the microcomputer unit 20. The register 11 is read / written by the microcomputer unit 20 via the bus 109. The signal line 102 is not connected to the register 11, and the reset signal / reset release signal from the command analysis circuit unit 18 is not input.

  The power supply circuit register 15 is a register in which the microcomputer unit 20 reads and writes data for setting the voltage supplied from the power supply circuit unit 14 via the bus 109. By changing the setting data to the register 15, a detailed voltage for data write or data erase is supplied from the power supply circuit unit 14. The data in the initial state is set data for supplying a data read voltage from the power supply circuit unit 14.

  A signal line 102 is connected to the register 15, and when a reset signal is output from the command analysis circuit unit 18, data in an initial state is written corresponding to the reset signal. Therefore, when the reset signal is output, the power supply circuit unit 14 is set to supply a data read voltage.

When a reset release signal is output from the command analysis circuit unit 18, data corresponding to the reset release signal is not written to the register 15, and the register 15 does not change.
The register 17 for the verify circuit unit 16 includes first data indicating whether the result of data write or data erase to the memory cell array unit 4 is OK or NG, second data designating update of the first data, Third data designating resetting of the first data is stored. Any of the first to third data can be read out by the microcomputer unit 20 via the bus 109.

  The verify data unit 16 writes the first data to the register 17. The microcomputer 20 writes the second data and the third data into the register 17 via the bus 109. When the second data is written to the register 17, the verify circuit unit 16 writes the first data to the register 17. When the third data is written to the register 17, the first data is reset, and the result of the data write / data erase becomes a value indicating NG.

  The signal line 102 is connected to the register 17, and when the reset signal is output from the command analysis circuit unit 18, the initial state data is written corresponding to the reset signal. The data in the initial state is the third data. Accordingly, the first data in the register 17 is reset in response to the reset signal, and the result of the data write / data erase becomes a value indicating NG.

When a reset release signal is output from the command analysis circuit unit 18, data corresponding to the reset release signal is not written in the register 17, and the register 17 does not change.
In the present embodiment, the register 9 is formed in the storage area 2 and the register 11, the register 15 and the register 17 are formed in the peripheral circuit area 3. However, if the above contents are shown, the storage area 2 or the peripheral circuit area 3 is formed. Other configurations may be possible.

(Processor configuration)
Next, a detailed configuration of the processor unit 21 in FIG. 1 will be described. FIG. 2 is a block diagram for explaining the configuration of the processor unit 21.

  The processor unit 21 includes a processor control unit 30, a fetch control circuit 33, a program counter 34, an instruction address selector 35, and a processor calculation unit 40.

  The processor control unit 30 receives an instruction code 31 received from the instruction storage unit 22 via the signal line 107, and receives an operation code output from the instruction register via the signal line 200, and decodes the operation code. And an instruction decode circuit 32. The fetch control circuit 33 accepts an operation start instruction signal output from the instruction decode circuit 32 via the signal line 207 when the processor unit 21 executes a NOP instruction to be described later.

  The program counter 34 increments the address value in the instruction storage unit 22 of the instruction code currently being executed by the processor unit 21 and outputs the incremented address value to the instruction address selector 35. The instruction address selector 35 outputs an address value output from the instruction register 31 via the signal line 301, an address value output from the instruction decode circuit 32 via the signal line 303, and is output from the program counter 34 via the signal line 304. The address value is received, and any one of these three address values is output to the instruction storage unit 22 and the program counter 34.

  The fetch control circuit 33, the program counter 34, and the instruction address selector 35 constitute a circuit having a function of outputting an instruction address value for executing the next instruction based on the calculation result of the processor calculation unit 40. The fetch control circuit 33 is controlled from the instruction decode circuit 32 via the signal line 207 and the instruction address selector 35 is controlled via the signal line 208.

  The processor operation unit 40 is a circuit that performs an operation based on the control contents from the processor control unit 30, and is an X multiplexer (X-MUX) 41, a Y multiplexer (Y-MUX) 42, an ALU (Arithmetic Logic Unit) 43, a pipeline register. 44, a status register 45, a general-purpose register 46, a 0 determination circuit 47, and a branch determination circuit 48.

  The X-MUX 41 is a numerical value output from the instruction register 31 via the signal line 300, a numerical value output from the general-purpose register 46 via the signal line 310, and a numerical value output from the pipeline register 44 via the signal line 308. And one of these numerical values is output to the X input terminal of the ALU 43 via the signal line 305.

  The Y-MUX 42 receives a numerical value output from the general-purpose register 46 via the signal line 310 and outputs the numerical value to the Y input terminal of the ALU via the signal line 306.

  The ALU 43 is a logical operation unit that performs an operation on a numerical value input to the X input terminal and a numerical value input to the Y input terminal, and outputs the result to the signal line 307 from the Z output terminal.

  The pipeline register 44 is a register used for the pipeline operation of the processor unit 21, and its contents are always updated according to the operation result output from the ALU 43. The pipeline register 44 stores the calculation result output from the ALU 43 via the signal line 307 and outputs the stored calculation result to the X-MUX 41 and the 0 determination circuit 47 via the signal line 308.

  The status register 45 is a dedicated register that stores a value indicating the status that the flash memory 1 of the present embodiment is executing. The status register 45 stores the calculation result output from the ALU 43 via the signal line 307 and outputs the stored calculation result to the branch determination circuit 48 via the signal line 309.

  The general-purpose register 46 is a register used at the time of general calculation. The general-purpose register 46 stores the calculation result output from the ALU 43 via the signal line 307, and outputs the stored calculation result to the X-MUX 41, Y-MUX 42, and branch determination circuit 48 via the signal line 310.

  The 0 determination circuit 47 is a circuit that determines whether the output value of the pipeline register 44 is 0 or not. When the output value of the pipeline register 44 is 0, the 0 determination circuit 47 outputs that fact to the fetch control circuit 33 via the signal line 210.

  The branch determination circuit 48 compares the value output from the instruction register 31 via the signal line 302 with the value output from the status register 45 via the signal line 309 and outputs a result indicating whether or not they match. Circuit. The result of the coincidence is output to the instruction address selector 35 via the signal line 211.

  The instruction decode circuit 32 controls the X-MUX 41 via the signal line 201, the Y-MUX 42 via the signal line 202, and the ALU 43 via the signal line 203. The general-purpose register 46 is controlled by the instruction decode circuit 32 via the signal line 204, the status register 45 is controlled via the signal line 205, and the branch determination circuit 48 is controlled via the signal line 206.

(Data read, data write, data erase, suspend, resume operation)
Next, operations of data read, data write, data erase, suspend, and resume in the flash memory of this embodiment will be described.

  Data read is an operation of reading data from the flash memory. Data write is an operation of writing data to the flash memory. Data erase is an operation of erasing data stored in the flash memory.

  Suspend is an operation for temporarily interrupting a data write / data erase operation during data write / data erase in order to read data from the flash memory. Resume is an operation to end the suspend and return to the data write / erase operation.

  The flash memory according to the present embodiment operates according to an operation command input from the outside in the same manner as a general flash memory. That is, it operates according to an operation command indicating any one of data read, data write, data erase, suspend, and resume from the outside.

  First, the operation at the time of data reading will be described.

  The data I / O buffer unit 12 outputs an operation command for designating data read input from the outside to the command analysis circuit unit 18 through the signal line 101. The command analysis circuit unit 18 analyzes the operation command and does not output a reset release signal in the case of data read. Therefore, the reset of the clock generation circuit unit 19 and the microcomputer unit 20 is not released and does not operate.

  The address buffer unit 10 outputs an address input from the outside to the bus 110 via the signal line 100. In the row decoder 5 and the column, the coder 6 decodes the input address and outputs it to the memory cell array unit 4 and the column gate 7, respectively. The column gate 7 reads data from the memory cell array unit 4 based on the decoder result from the column decoder. The column gate 7 outputs read data to the sense amplifier 8. The sense amplifier 8 amplifies the read data and outputs it to the data I / O buffer unit 12. The data I / O buffer unit 12 outputs the amplified data to the outside.

  Next, the operation during data write / erase will be described.

  The data I / O buffer unit 12 outputs an operation command input from the outside to the command analysis circuit unit 18 through the signal line 101. The command analysis circuit unit 18 analyzes the operation command, and outputs a reset release signal via the signal line 102 in the case of data write / data erase.

  The reset release signal releases the reset of the clock generation circuit unit 19 and the microcomputer unit 20 and starts the operation. The reset release signal holds the initial settings of the sense amplifier register 9, the power circuit register 15, and the verify circuit register 17, and the sense amplifier 8, the power circuit 14, and the verify circuit 16 comply with the initial settings. It becomes an operation state. Subsequently, the command analysis circuit unit 18 analyzes the operation command, outputs an interrupt signal to the microcomputer unit 20 through the signal line 104, and a vector number indicating the operation content of the microcomputer unit 20 through the signal line 105. Is output.

  The microcomputer unit 20 operates each circuit in the peripheral circuit area 3 in accordance with the contents of the operation command. At this time, the microcomputer unit 20 always operates the verify circuit and the power supply circuit.

  When the data write / data erase operation is completed, the microcomputer unit 20 outputs a stop signal via the signal line 108 to the command analysis circuit unit 18 as the end operation. The command analysis circuit unit 18 outputs a reset signal via the signal line 102 in response to the stop signal. The reset signal stops the operation of the clock generation circuit unit 19 and the microcomputer unit 20. The reset signal returns the settings of the sense amplifier register 9, the power supply circuit register 15, and the verify circuit register 17 to the initial settings. At this point, the data write / data erase operation ends.

  The operation start and end during the data write / erase will be described in detail later.

  Next, the operation during suspend / resume will be described.

  The data I / O buffer unit 12 outputs an operation command input from the outside to the command analysis circuit unit 18 through the signal line 101. The command analysis circuit unit 18 analyzes the operation command, interrupts the microcomputer unit 20, and instructs execution of suspend. The microcomputer unit 20 stops after interrupting the data write or data erase operation being executed, for example.

  Next, when returning to the interrupted data write or data erase operation, the data I / O buffer unit 12 outputs an operation command designating resume input from the outside to the command analysis circuit unit 18 via the signal line 101. . The command analysis circuit unit 18 analyzes the operation command and instructs the microcomputer unit 20 to execute the resume. The microcomputer unit 20 resumes the interrupted data write or data erase operation.

(Operation stop / restart procedure)
In the flash memory according to the present embodiment, when the data write / data erase operation of the memory cell array unit 4 is completed, the voltage supplied from the power supply circuit unit 14 is set as a read voltage and accepts an operation command from the outside. Other than the circuit necessary for the above, the initial state data is set in the register and immediately stopped. Next, it has a function of resuming the operation when an operation command for operating the flash memory 1 is received from the outside. The operation stop / resume procedure will be described below.

  First, the procedure when the operation of the flash memory 1 is stopped will be described with reference to FIGS. FIG. 3 is a flowchart for explaining the operation stop procedure of the flash memory 1.

  First, the verify circuit unit 16 executes a data verify operation in each of the data write / data erase operations. Next, the microcomputer unit 20 writes the second data in the register 17. Next, according to the second data, the verify circuit unit determines that the data write / data erase operation to the memory cell array unit 4 is OK when it is determined that the data has been correctly written / erased. First data shown is written to the register 17.

  When the data write / data erase operation to the memory cell is completed, the microcomputer unit 20 reads the first data indicating the operation state of the memory cell array unit 4 set in the register 17 for the verify circuit unit 16 (step S1). .

  The microcomputer unit 20 reads the register 17 and confirms the state of the memory cell array unit 4. When it is determined in step S 1 that the memory cell array unit 4 has completed any of the data write / data erase operations, the microcomputer unit 20 generates a read voltage to the power supply circuit unit 14 register 15 via the bus 109. The indicated data is set (step S2). In accordance with this data setting, the power supply circuit unit 14 sets the voltage supplied to the memory cell array unit 4 to an initial read voltage.

  The flash memory of this embodiment first performs data erase at the time of data write, and then performs data write. Therefore, a data erase operation is executed for both data write and data erase. The voltage for data erasure may exceed 10V. If the voltage is lowered by suddenly stopping the operation of the power supply circuit unit 14 from the voltage in the data erase state, the data held in the memory cell array unit 4 is destroyed. Alternatively, the elements constituting the flash memory 1 may be destroyed.

  On the other hand, the voltage at the time of data reading is not high enough to be supplied at the time of data erasing, and there is no destruction of the retained data or the element. Therefore, when the data reading is completed at the time of data reading, the operation of the power supply circuit unit 14 is It is possible to terminate immediately. For this reason, when the memory cell array unit 4 determines that the data write / data erase operation has been completed, the microcomputer unit 20 uses the data supplied to the memory cell array unit 4 for data reading so that the held data destruction and element destruction do not occur. The power supply circuit unit 14 register 15 is set so that the voltage is

  After a predetermined time has elapsed since the read voltage generation data is set in the register 15, the microcomputer unit 20 outputs a stop signal to the command analysis circuit unit 18 via the signal line 108 (step S3). Here, the predetermined time is the time required for the power supply circuit 14 to actually start outputting the read voltage after data indicating the generation of the read voltage is set in the register 15.

  When the stop signal is received, the command analysis circuit unit 18 sends a reset signal via the signal line 102 to the processor unit 21, the clock generation circuit unit 19, the sense amplifier 8 register 9, the power supply circuit unit 14 register 15, and the verify circuit unit 16. The data are collectively output to the register 17 (step S4).

  The processor unit 21 and the clock generation circuit unit 19 stop operating when receiving the reset signal. When the data corresponding to the reset signal is set in the register 9, the register 15, and the register 17, the operation of the sense amplifier 8 is stopped as described in (Register configuration), and the power supply circuit unit 14 receives the data read voltage. Is maintained, and the first data in the register 17 is reset (step S5). Note that the command analysis circuit unit 18 is operating and is in a state of accepting an operation command from the outside.

  Thus, the data write / data erase end operation is completed.

  In a general microcomputer, data used at the time of use is set in the used register instead of data in the initial state. In order to return to the initial state in preparation for the next operations, it is necessary to set the initial state data by designating the registers one by one from the microcomputer.

  Further, in order to set the initial state data in the register, it is necessary to set the initial state data by specifying the register to be returned to the initial state by using an instruction for setting data in the register, for example, a transfer instruction. . That is, in order to set the initial state data in the register, at least two steps of data setting and data transfer to the register are required. Therefore, the instruction storage capacity for the processor tends to increase.

  In addition, in general microcomputers, as the number of registers to be returned to the initial state increases, it is necessary to repeat the steps of register designation and data setting as many times as the number of registers, and the processing time tends to increase. It is in.

  On the other hand, in this embodiment, since the initial state data is collectively set in each register using a dedicated signal line called a reset signal, it is not necessary to specify each register from the microcomputer unit 20. It is possible to reduce the step of setting initial data in the register.

  Furthermore, since the initial data is set in the register all at once, the execution time is shortened in addition to a general processor.

  Therefore, in the flash memory according to the present embodiment, the storage capacity of the instruction storage device unit 22 in which the program for operating the processor unit 21 is stored can be reduced, and the execution time to stop the operation is fast.

  Next, a procedure for restarting the operation of the flash memory 1 according to the present embodiment will be described with reference to FIGS.

  FIG. 4 is a flowchart showing an operation resumption procedure of the flash memory 1.

  As described above, when the operation of the flash memory 1 is stopped, the command analysis circuit unit 18 is operating and is in a state where it can accept an operation command input via the data I / O buffer unit 12.

  In this state, when the data I / O buffer unit 12 receives an operation command from the outside, the data I / O buffer unit 12 outputs the operation command received through the signal line 102 to the command analysis circuit unit 18 (step 11).

  When the operation command is input, the command analysis circuit unit 18 analyzes the operation command and determines whether the operation command indicates data write / data erase or other operation (step S12).

If it is determined that the operation command indicates either data write / data erase, the command analysis circuit unit 18 outputs a reset release signal via the signal line 102 (step S13).
The reset release signal output from the command analysis circuit unit 18 is supplied to the microcomputer unit 20 and the clock generation circuit unit 19 via the signal line 102.

  When receiving the reset release signal, the clock generation circuit unit 19 restarts the output of the operation clock. When the microcomputer unit 20 receives the reset signal, it receives an interrupt signal and a vector number from the command analysis circuit unit 18 and starts an operation (step S14).

  The flash memory 1 returns to the operable state in accordance with the above operation restart procedure.

  A general microcomputer has no concept of operation stop and executes some instruction code. For example, when the predetermined operation is not performed, some other instruction code is being executed. Therefore, some other instruction code is stored in an instruction storage device for a general microcomputer. Therefore, the capacity of an instruction storage device for a general microcomputer is increased by another instruction code. In addition, since the microcomputer is always operating, power consumption increases.

  On the other hand, the flash memory according to the present embodiment has a mechanism in which the clock generation circuit unit 19 and the microcomputer processor unit 20 are stopped until an operation command is input at the start of operation. Therefore, it is not necessary to cause the microcomputer unit 20 to execute an extra instruction code, and the storage capacity of the instruction storage unit 22 inside the microcomputer unit 20 can be reduced.

  In addition, since the time during which the clock generation circuit unit 19 and the microcomputer unit 20 operate can be reduced, power consumption can be reduced.

(NOP instruction execution control)
Next, execution control of the NOP instruction in the flash memory 1 of the present embodiment will be described with reference to FIGS.

  FIG. 5 is a flowchart for explaining NOP instruction execution.

  The NOP instruction is a non-operation instruction that does not change data or writes to a register, and is an instruction executed by the microcomputer to create a waiting time until the next processing of the microcomputer.

  It is not necessary to execute the next instruction, such as when the processor unit 21 needs to execute the NOP instruction, that is, during voltage boosting by the power supply circuit unit 14 or during data erase of the memory cell array unit 4. When the state is not satisfied, an instruction code for a NOP instruction (hereinafter referred to as a NOP instruction) is output from the instruction storage unit 22 to the instruction register 31 via the signal line 107. This NOP instruction is in the format of operation code + NOP count information (step S31).

  When the instruction register 31 receives the NOP instruction, the instruction code of the NOP instruction is divided into an operation code and NOP count information. Next, the instruction register 31 outputs the separated opcode to the instruction decode circuit 32 via the signal line 200. Further, the instruction register 31 outputs the separated NOP count information to the X-MUX 41 via the signal line 300 (step S32).

  Next, the instruction decode circuit 32 performs the following four control operations.

(1) The value input via the signal line 300 is selected as the input of the X-MUX 41.

(2) Stop the operation of Y-MUX42.

(3) Set the ALU 43 to the -1 operation mode and set Z = X-1.

(4) The operation of the fetch control circuit 33 is started via the signal line 207.

  As a result of (4), the fetch circuit 33 stops the operation of the instruction register 31 and the program counter 34 until the 0 determination result of the 0 determination circuit 47 becomes “0” (step 33).

  The instruction decode circuit 32 determines the number of calculations based on the number of clocks by the pipeline operation (step S34). If it is determined that the number of calculations is the first calculation, the input value of the X-MUX 41 set in step S33 is output to the ALU 43.

  When the instruction decode circuit 32 determines that the number of calculations is the second or later, the instruction decode circuit 32 sets the output value from the pipeline register 44 as the input of the X-MUX 41 in the X-MUX 41 (step S35).

  The ALU 43 performs an operation of Z = X−1 on the output value from the X-MUX 41, and outputs the value of Z as the operation result to the pipeline register 44 via the signal line 307 (step S36).

  The pipeline register 44 outputs the Z value output from the ALU 43 to the X-MUX 41 and the 0 determination circuit 47 via the signal line 308 (step S37).

  The 0 determination circuit 47 determines whether or not the Z value output from the pipeline register 44 is 0 (step 38). If it is not 0, the process returns to step S34, and the operations from step S34 to S38 are repeated. In the case of 0, the 0 determination circuit 47 outputs the fact to the fetch control circuit 33 via the signal line 309.

  When the notification that the Z value is 0 is received from the 0 determination circuit 47, the fetch control circuit 33 starts the operation of the instruction register 31 and the program counter 34 (step S39).

  Conventionally, when the microcomputer is made to wait for a predetermined time, the number of NOP instructions cannot be specified, so it has been necessary to list a number of NOP instructions corresponding to the predetermined time. If this method is adopted as it is in a NOR type nonvolatile semiconductor memory device in which a microcomputer is formed in the peripheral circuit area, the number of NOP instructions becomes enormous because subtle timing control is required and many standby times must be set. The ROM capacity is increased, leading to an increase in chip area.

  This embodiment has a NOP instruction that can specify the number of times, and since the number of times can be specified while describing the NOP instruction once, it is not necessary to list NOP instructions. Accordingly, the storage capacity of the instruction storage unit 22 can be reduced.

  Further, since the processor unit 21 can perform an operation of stopping the operation during n clocks, for example, it can perform precise time control such as time control corresponding to n clocks.

(SW command execution control)
The SW instruction is an instruction that determines an instruction to be executed next by referring to and comparing the value of the status register 45.

  The SW instruction is an instruction that is operated when the suspend is executed and the data write or data erase state is returned by the resume operation.

  The SW instruction is in the form of an operation code + branch address value + comparison value. Here, the branch address value is an instruction address value output to the instruction storage unit 22 and the instruction replacement circuit 20 via the signal line 106. The comparison value is a value set in the branch determination circuit 48.

  The execution control of this SW instruction in the flash memory 1 of the present embodiment will be described with reference to FIGS.

  In this embodiment, in preparation for suspend execution, when data erasure / data write is executed, data indicating how far data erasure / data write has been executed, for example, a set value of an address or a boost of power supply Data indicating the state is temporarily stored in the state register as a state value. When returning to data erase or data write by the resume operation, the operation is resumed with reference to the state value held in the state register.

When the state value is set in the state register, for example, when the charge pump of the power supply circuit 14 is activated, data is being written to the memory cell array unit 4, or the verify circuit unit 16 is the result of data write / data erase. The operation procedure described above when switching to the next operation, such as after is written in the register 17, will be described below.

  First, when executing data erase and data write, a status value indicating how far data erase and data write have been executed is always set in the status register. In the flash memory 1 of the present embodiment, the state value is set in the state register using, for example, a transfer instruction.

  This setting procedure will be described with reference to FIG.

  FIG. 6 is a flowchart for explaining a setting method for setting a value indicating the state executed by the processor unit 21 in the state register 45, and FIG. 7 is a flowchart for explaining execution of the SW instruction.

  The instruction storage unit 22 outputs an instruction code for a transfer instruction (hereinafter referred to as a transfer instruction) to the instruction register 31 via the signal line 107 (step S41). This transfer instruction is in the form of opcode + transfer destination information + status value.

  When receiving the transfer instruction, the instruction register 31 separates the transfer instruction into an operation code, transfer destination information, and a status value. Next, the instruction register 31 outputs the separated operation code and transfer destination information to the instruction decoding circuit 32 via the signal line 200. The instruction register 31 outputs the separated state value to the X-MUX 41 via the X input value signal 300 (step S42).

  The instruction decode circuit 32 receives the operation code and transfer destination information and performs the following four operations (step S34).

(1) A value input via the signal line 300 is selected as an input of the X-MUX 41.

(2) Stop the operation of Y-MUX42.

(3) The ALU 43 is set to the transfer mode, and Z = X is set.

(4) The operation of the status register 45 is started.

  The ALU 43 executes the operation of Z = X according to the setting of the instruction decode circuit 32, and outputs the value of Z as the operation result to the status register 45 through the signal line 307 (step S44).

  The ALU 43 outputs the Z value, and the state value is set in the state register 45 (step S45).

  This completes the setting of the state value in the state register 45.

  Next, it is assumed that the data erase or data write operation to the flash memory 1 is interrupted by the suspend command, and the data erase or data write operation is resumed by the resume command.

  For example, it is assumed that the processor unit 21 is interrupted during data erase of the memory cell array 4 and returns to the interrupted data erase operation after performing data read.

  At this time, the data erase operation is restored by the SW instruction.

  The execution order of SW instructions will be described with reference to FIGS.

  First, the instruction storage unit 22 outputs an instruction code for an SW instruction (hereinafter referred to as an SW instruction) to the instruction register 31 via the signal line 107 (step S51). As described above, the SW instruction is in the form of an operation code + branch address value + comparison value.

  Upon receiving the SW instruction, the instruction register 31 separates the SW instruction into an operation code, a branch address value, and a comparison value, and performs the following three operations (step S52).

(1) The operation code is output to the instruction decode circuit 32 via the signal line 200.

(2) The branch address value is output to the instruction address selector 35 via the signal line 301.

(3) The comparison value is output to the branch determination circuit 48 via the signal line 302.

  When receiving the operation code, the instruction decode circuit 32 starts the operation of the branch determination circuit 48 (step S53). As a result, the branch determination circuit 48 takes in the comparison value and the state value set in the state register 45.

  The branch determination circuit 48 compares the captured comparison value with the state value, and determines whether or not the comparison value and the state value match (step S54). The branch determination circuit 48 outputs the comparison result to the instruction address selector 35 via the signal line 211.

  If the comparison result is “match”, the instruction address selector 35 selects a branch address value, and outputs this branch address value to the instruction storage unit 22 via the signal line 106 (step S55).

  If the result of the comparison is “mismatch”, the instruction address selector 35 selects the value of the program counter 34 and outputs the value of the program counter 34 to the instruction storage unit 22 via the signal line 106 (step S56).

  This completes the execution operation of the SW instruction.

  In a general processor, in order to perform a branch operation similar to the SW instruction of the present embodiment, two instructions “value setting to the branch determination circuit 48” and “comparison with the value of the status register 45” are necessary. On the other hand, in this embodiment, since it can be realized by one instruction, the number of instruction codes stored in the instruction storage unit can be reduced, and the mounting area can be reduced by reducing the capacity of the instruction storage unit 22.

  Further, the SW instruction of this embodiment can determine the instruction to be executed next by using the value of the status register 45. Therefore, the SW instruction can be used as a branch instruction corresponding to the value of the status register 45. For example, if the status register 45 is 3 bits, 128 values can be secured as the value of the status register 45 according to the operation location to be interrupted, and a fine high-speed return operation is possible.

(Instruction replacement operation)
Next, the instruction replacement operation of the flash memory according to the present embodiment will be described with reference to FIGS. FIG. 8 is a block diagram showing an internal configuration of the instruction storage unit 22 shown in FIG. FIG. 9 is a flowchart for explaining an instruction replacement operation in the instruction storage unit 22 of FIG.

  First, the configuration of the instruction storage unit 22 will be described.

  The instruction storage unit 22 includes an instruction storage device 50, an instruction address comparison circuit register 51, an instruction address comparison circuit 52, a replacement instruction storage device 53, and an instruction selector 54.

  The instruction storage device 50 stores an instruction code for the processor unit 21 as an instruction code before replacement. This pre-substitution instruction code is all the instruction codes for the processor unit 21. Based on the instruction address input from the processor unit 21 via the signal line 106, the instruction code before replacement is selected by the instruction storage device 50, and the selected instruction code before replacement is selected by the instruction selector 54 via the signal line 400. Is output.

  The instruction address comparison circuit register 51 includes a register in which data indicating whether the operation of the instruction address comparison circuit 52 is “valid” or “invalid” is set and a register that stores a replacement instruction address. This replacement instruction address is an instruction address for an instruction code to be replaced. The processor unit 21 can read and write the contents of the register 51 via the bus 109.

  When the operation setting is “valid”, the instruction address comparison circuit 52 compares the instruction address input from the processor unit 21 via the signal line 106 with the replacement instruction address input from the register 51 via the signal line 401. The result of “match” or “mismatch” is detected. The comparison result in the instruction address comparison circuit 52 is output to the instruction selector 51 via the signal line 402.

  When the operation setting is “invalid”, the instruction address comparison circuit 52 always outputs a result of “mismatch” to the instruction selector 51.

  The replacement instruction storage device 53 is a volatile instruction storage device that stores an instruction code for the processor unit 21 as a replacement instruction code. Here, the replacement instruction code is an instruction code for replacing a part of the instruction code for the processor unit 21. Further, the replacement instruction storage device 53 outputs this replacement instruction code to the instruction selector 51 via the signal line 403.

  The instruction selector 51 selects one of the pre-replacement instruction code and the replacement instruction code, and outputs the selected instruction code to the processor unit 21 via the signal line 107.

  The instruction selector 51 selects and outputs a replacement instruction code when the result from the instruction address comparison circuit 52 is “match”, and selects and outputs the pre-replacement instruction code when it is “mismatch”.

  Next, the instruction replacement operation will be described with reference to FIGS.

  It is assumed that the replacement instruction address and the replacement instruction code are stored in the register 51 and the replacement instruction storage device 53, respectively, before the operation starts.

  First, the processor unit 21 outputs an instruction address to the instruction storage device 50 and the instruction address comparison circuit 52 via the signal line 106 (step S61).

  When the instruction address comparison circuit 52 receives the instruction address from the processor unit 21, the instruction address comparison circuit register 51 stores data indicating that the operation of the instruction address comparison circuit 52 is "valid" or "invalid". It is determined whether or not data indicating the presence is stored (step S62).

  In the case of “valid”, the instruction address comparison circuit 52 compares the instruction address input from the processor unit 21 via the signal line 106 with the replacement instruction address input via the signal line 401, and both addresses are identical. It is detected whether or not they match (step S63).

  If the two addresses match, the instruction address comparison circuit 52 outputs data indicating “match” to the instruction selector 54 via the signal line 402 (step S64).

  If it is determined in step S62 that the instruction address comparison circuit register 51 stores data indicating that the operation of the instruction address comparison circuit 52 is “invalid”, or in step S63, the instruction address comparison circuit 52 However, when it is determined that both addresses are “mismatch”, the instruction address comparison circuit 52 outputs data indicating “mismatch” to the instruction selector 51 via the signal line 402 (step S65).

  When the data indicating “match” is output from the instruction address comparison circuit 52, the instruction selector 54 selects the instruction code for replacement input from the replacement instruction storage device 53 via the signal line 403 as the instruction code, and the signal line The data is output to the processor unit 21 via 107 (step S66).

  When data indicating “match” is output from the instruction address comparison circuit 52, the instruction selector 54 selects the instruction code before replacement input from the instruction storage device 50 via the signal line 107 as an instruction code, and the signal line 107 To the processor unit 21 (step S67).

  In this embodiment, the instruction code is replaced mainly for use in debugging. As a means for replacing or rewriting the instruction code, a method using a part of the flash memory cell is conceivable, but the flash memory cell cannot be used in the debugging stage for verifying the operation of the flash memory cell itself. Therefore, an instruction storage device other than the flash memory is required.

  In a general processor, when replacing an instruction code, the entire instruction code is rewritten. Therefore, an instruction storage device in a general processor is configured by an electrically rewritable nonvolatile memory. This electrically rewritable nonvolatile memory usually has a larger area than a non-rewritable nonvolatile memory.

  In the present embodiment, a non-rewritable nonvolatile semiconductor memory device in which data is stored in advance is employed as the instruction memory device 50 for storing instruction codes. Further, a volatile semiconductor memory device is adopted as the replacement instruction storage device 53 for replacing a part of the instruction code.

  Since both the nonvolatile semiconductor memory device and the volatile semiconductor memory device that cannot be electrically rewritten are smaller in area than the nonvolatile memory, the instruction storage device unit 21 itself is compact.

  As a result, the instruction storage unit 21 itself becomes compact, and even when the hardware is changed after the end of debugging, the influence on the circuits other than the instruction storage unit 21 can be eliminated.

(Other embodiments)
As described above, the present invention has been described using the embodiments. However, the discussion and the drawings that form a part of this disclosure exemplify apparatuses and methods for embodying the technical idea of the present invention. Therefore, the technical idea of the present invention does not limit the structure, arrangement, etc. of the component parts to the form described above. The technical idea of the present invention can be variously modified within the scope of the claims.

1 is a block diagram showing a configuration of a flash memory. The block diagram which shows the structure of a processor. The flowchart for demonstrating the execution order at the time of operation | movement stop. The flowchart for demonstrating the execution order at the time of an operation | movement start. The flowchart for demonstrating the execution order of a NOP instruction | indication. The flowchart for demonstrating the execution order which sets the value which shows the state which the processor part is performing to a status register. The flowchart for demonstrating the execution order of SW instruction. The block diagram which shows the inside of a command memory | storage device part. The flowchart for demonstrating the execution order of instruction replacement.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory 2 Memory area 3 Peripheral circuit area 4 Memory cell array part 5 Row decoder 6 Column decoder 7 Column gate 8 Sense amplifier 9 Sense amplifier register 10 Address buffer part 11 Address buffer part register 12 Data I / O buffer part 14 Power supply Circuit section 15 Power supply circuit section register 16 Verify circuit section 17 Verify circuit section register 18 Command analysis circuit section 19 Clock generation circuit section 20 Microcomputer section 21 Processor section 22 Instruction storage section 30 Processor control section 31 Instruction register 32 Instruction decode Circuit 33 Fetch control circuit 34 Program counter 35 Instruction address selector 40 Processor operation unit 41 X input MUX
42 MUX for Y input
43 ALU
44 Pipeline register 45 Status register 46 General-purpose register 47 0 decision circuit 48 Branch decision circuit 50 Instruction storage device 51 Instruction address comparison circuit register 52 Instruction address comparison circuit 53 Replacement instruction storage device 54 Instruction selector 109 Bus 110 Address bus

Claims (6)

A nonvolatile semiconductor memory device having a storage area and a peripheral circuit area,
A memory cell array formed in the storage area;
A power supply circuit portion that is formed in the peripheral circuit region and supplies a read voltage, a write voltage higher than the read voltage, or an erase voltage higher than the read voltage to the memory cell array portion;
A first register unit storing data indicating an operation state of the memory cell array unit;
A second register unit storing data indicating whether the power supply circuit unit generates the read voltage, the write voltage, or the erase voltage;
When the data stored in the first register unit is read from the peripheral circuit region and the memory cell array unit determines that either the write state or the erase state has ended, the power supply circuit unit Storing the data for generating the read voltage in the second register unit, and then outputting a stop signal;
A clock generation circuit unit that is formed in the peripheral circuit region and supplies a clock to the microcomputer unit;
A command analysis circuit unit that is formed in the peripheral circuit region and outputs a reset signal in response to the stop signal output from the microcomputer unit, wherein the microcomputer unit and the clock generation circuit unit are configured to perform the command analysis. A nonvolatile semiconductor memory device, wherein operation is stopped in response to a reset signal output from a circuit portion. The command analysis circuit unit outputs a reset release signal when an external write command or erase command is received for the memory cell array unit, and the microcomputer unit and the clock generation circuit unit are connected to the command analysis circuit unit. 2. The non-volatile semiconductor memory device according to claim 1, wherein the operation is resumed in response to an output reset cancel signal. A nonvolatile semiconductor memory device that operates in response to an operation command input from the outside,
A memory cell array unit;
A first register unit storing data indicating an operation state of the memory cell array unit;
A power supply circuit section for supplying a first voltage or a second voltage higher than the first voltage to the memory cell array section;
A second register unit storing data indicating whether the power supply circuit unit generates the first voltage or the second voltage;
The operation state of the memory cell array unit is recognized by reading the data stored in the first register unit via the bus, and the second register unit is connected to the power supply circuit unit via the bus. A non-volatile semiconductor memory device, comprising: a microcomputer unit that stores data indicating whether the first voltage is generated or the second voltage is generated. A nonvolatile semiconductor memory device having a storage area and a peripheral circuit area,
A microcomputer section that is formed in the peripheral circuit area and controls the storage area;
A processor unit formed in the microcomputer unit;
An instruction storage unit for storing the instruction code, which is formed in the microcomputer unit and outputs an instruction code for the processor unit to the processor unit in response to an instruction address signal output from the processor unit;
A program counter that is formed in the processor unit and specifies an instruction code to be executed next by the processor unit;
A processor control unit that is formed in the processor unit and controls execution of the instruction code;
An instruction register formed in the processor control unit for holding and analyzing the instruction code from the instruction storage unit;
An arithmetic unit that is formed in the processor unit and performs an arithmetic operation according to the control of the processor control unit;
An arithmetic unit that is formed in the arithmetic unit and executes arithmetic operations;
A third register unit formed in the arithmetic unit, which holds an arithmetic result of the arithmetic unit and can be used as an input of the arithmetic unit again;
A 0 determination circuit for determining whether or not the value held in the third register unit is 0,
The operation of the instruction register and the program counter is stopped for the number of times by calculating the number of times designated from the outside using the arithmetic unit, the third register, and the 0 determination circuit. Nonvolatile semiconductor memory device characterized by A nonvolatile semiconductor memory device having a storage area and a peripheral circuit area,
A microcomputer section that is formed in the peripheral circuit area and controls the storage area;
A processor unit formed in the microcomputer unit;
An instruction storage unit for storing the instruction code, which is formed in the microcomputer unit and outputs an instruction code for the processor unit to the processor unit in response to an instruction address signal output from the processor unit;
A program counter that is formed in the processor unit and specifies an instruction code to be executed next by the processor unit;
A processor control unit that is formed in the processor unit and controls execution of the instruction code;
An instruction register formed in the processor control unit for holding and analyzing the instruction code from the instruction storage unit;
An arithmetic unit that is formed in the processor unit and performs an operation according to the control of the processor unit;
A fourth register unit that is formed in the arithmetic unit and stores data indicating the execution content of the instruction code;
According to the data formed in the processor unit and stored in the fourth register unit, either one of a value set from the program counter or a value set from the instruction register is selected, and an instruction is selected. A non-volatile semiconductor memory device comprising a selector for outputting the instruction address in a memory device section. A nonvolatile semiconductor memory device having a storage area and a peripheral circuit area,
A microcomputer section that is formed in the peripheral circuit area and controls the storage area;
A processor unit that is formed in the microcomputer unit and executes an instruction code;
An instruction storage unit for storing the instruction code, which is formed in the microcomputer unit and outputs the instruction code to the processor unit in accordance with an instruction address output from the processor unit;
An instruction storage device that is formed in the instruction storage unit and stores the instruction code;
An instruction replacement circuit unit that is formed in the instruction storage unit and stores a replacement instruction code that replaces a part of the instruction code;
The instruction replacement circuit unit corresponds to the instruction code for the replacement circuit when the instruction code for replacement is stored, and the instruction code when the replacement improvement instruction code is not stored, according to the instruction address. , Output to the processor unit, a nonvolatile semiconductor memory device

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