JP2008103489A - Malfunction preventing circuit, semiconductor integrated circuit device and electronical apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance ESD immunity by preventing malfunctions of a circuit due to power supply noise, caused by a circuit operating with other power supply surely. <P>SOLUTION: A noise canceller 300 is provided between a first circuit 100 operating with other power supply and a second circuit 110. A power supply noise detection circuit 200 detects either of positive polarity/negative polarity power supply noises (1), (2), superimposed on a power supply voltage (VD1) on the high level side and a positive polarity power supply noise (3), superimposed on a power supply voltage (VSS1) on the low level side, and operates the noise canceller 300. Consequently, transmission of a wrong signal, caused by power supply noise, is surely blocked. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a malfunction prevention circuit, a semiconductor integrated circuit device, and an electronic apparatus.

  When an electronic device such as a mobile phone is exposed to electrostatic discharge from a charged operator, a transistor of an integrated circuit device built in the electronic device may be electrostatically damaged. In order to prevent such electrostatic breakdown, the integrated circuit device is generally provided with a protective element (protective diode or the like) for preventing electrostatic breakdown.

  On the other hand, although electrostatic breakdown of the transistor does not occur due to electrostatic discharge from the operator, malfunctions such as an abnormal display state of the display panel of the electronic device may occur. When such a malfunction occurs, the reliability of the electronic device is impaired. Therefore, in recent years, resistance to malfunction due to electrostatic discharge (ESD) (ESD immunity) tends to be emphasized. Therefore, in recent years, an ESD immunity test is frequently performed on an integrated circuit device.

  FIG. 11 is a diagram for explaining an example of the ESD immunity test. In FIG. 11, static electricity (electrostatic discharge: ESD) is intentionally applied to the display device 6 in which the display panel 8 and the integrated circuit device (display driver) 10 are incorporated by the static electricity applying device 4. It is checked whether a malfunction (for example, an abnormality occurs in the display of the display panel 8) occurs.

  As a conventional circuit for preventing malfunction caused by an ESD pulse, there is a circuit described in Patent Document 1, for example. In Patent Document 1, when an abnormal signal is output from an output pin due to an ESD pulse, an abnormality of the output pin is detected via a feedback path, and a reset signal is generated. By resetting the electronic device or the like, the electronic device is recovered from the abnormal state.

Patent Document 2 discloses a spike noise removal circuit that removes spike noise using a delay gate, an AND gate, and an OR gate.
JP 2003-234647 A JP-A-5-191226

  As described above, in recent years, ESD immunity of integrated circuit devices tends to be emphasized. Then, ESD immunity tests have become diversified, special conditions that have not existed in the past have been set, and it has sometimes been necessary to ensure that no malfunction occurs under such conditions.

  Conventionally, as shown in FIG. 11, a test was performed simply by applying an electrostatic pulse. For example, a critical path (a path where a serious malfunction is likely to occur due to electrostatic discharge) is used in all cases. In some cases, it is important to reliably prevent malfunction.

  From this point of view, the inventor of the present invention examined the malfunction that occurs when noise caused by electrostatic discharge is superimposed only on the power supply, with respect to the interface of the circuit block that operates with a separate power supply.

FIG. 12 is a circuit diagram for explaining a malfunction of a circuit caused by power supply noise in two circuit blocks operating with different power supplies.
As shown in the figure, it is assumed that the first circuit (block A) 100 and the second circuit (block B) 110 are connected and signal transmission is performed from the first circuit 100 to the second block 110. To do.

  The first circuit 100 operates between the first high-level power supply voltage (VD1) and the first low-level power supply (VSS1), and functions as an inverter (INV1) as a whole. The second circuit 110 operates between the second high-level power supply voltage (VD2) and the second low-level power supply (VSS2), and functions as an inverter (INV2) as a whole. . A signal Vin is input to the first circuit 100, and a signal Vout is output from the second circuit 110.

  Here, it is assumed that the input signal Vin and the power supply voltage (VD2, VSS2) of the second circuit 110 are normal, and only the power supply voltage (either VD1 or VSS1) of the first circuit 100 is an ESD pulse. Consider the case where it fluctuates depending on Further, it is assumed that the input signal Vin is fixed to the first high-level power supply voltage (VD1: that is, “H”).

  In this state, when positive ESD noise (power supply noise) is applied to the high-level power supply voltage (VD1) of the first circuit 100, the threshold level of the inverter (INV1) of the first circuit 100 ( Since the threshold level (Vth) rises, the input signal (Vin), which has been regarded as “H” until now, is determined to be “L”. As a result, the first circuit 100 erroneously inverts the logic. A signal is output to the node Q, and the erroneous signal is input to the second circuit 110. As a result, an erroneous signal Vout is output from the second circuit 110, which causes a serious malfunction in the electronic device (for example, the electronic device is reset and initialized, or the previous display disappears completely). Action)

FIG. 13 is a timing diagram showing how a malfunction occurs due to power supply noise in the circuit system shown in FIG.
As shown in the figure, power supply noise is applied at time t10, and the threshold level (vth) of the inverter (INV1) rises instantaneously. As a result, the logic of the node Q in the period from time t11 to t12 is shown. The level is inverted, and the logic level of the output signal (Vout) is inverted correspondingly.

  In such an interface between circuit blocks operating with different power supplies, a situation where only the power supply voltage fluctuates due to an ESD pulse has not been assumed in the past, and in conventional circuits, this is caused by such power supply noise. Therefore, it is impossible to prevent malfunction of the circuit.

  For example, in the technique of Patent Document 1, since the signal for resetting the electronic device is generated by detecting the output of the abnormal signal from the output pin, the abnormal signal is output to the electronic device. Cannot be prevented.

  Further, when considering the cancellation of power supply noise using the technique of Patent Document 2, the signal on which the power supply noise is superimposed is branched into two, and one of them is delayed by a predetermined time, whereby two inputs / one output are obtained. The noise is canceled by preventing the two input terminals of the logic gate from being simultaneously set to the same level. However, the duration of the power supply noise (ESD pulse width) is unknown, and when the pulse width exceeds the delay amount of the delay line, the two input terminals of the logic gate are at the same level at the same time. Eventually, power noise is output.

  As described above, according to the conventional technology, it is impossible to surely prevent the malfunction of the circuit due to the power supply noise in the special environment described above. Further, unlike a normal signal processing system, a power supply circuit is a circuit that handles the highest voltage of the circuit, and inherently it is difficult to perform signal processing and noise cannot be easily removed.

That is, even if an attempt is made to prevent malfunction of the circuit due to power supply noise shown in FIG. 12, the following inherent difficulties exist in terms of handling the power supply voltage, and it is difficult to cope with the conventional technology. .
(1) Since the voltage level to be handled is high, it cannot be handled easily like a signal of a normal signal processing system.
(2) When a positive pulse is further superimposed on the positive power supply voltage, an excessive voltage may be generated, and the circuit is required to have both high-speed operation and breakdown resistance. The design is difficult.
(3) The potential fluctuation of the power supply line is expected to continue for a while after the ESD pulse disappears, and the application period of the power supply pulse cannot be predicted.
(4) The power supply system circuit has a significant influence on many other circuits. Therefore, it is necessary to pay close attention so that the circuit provided to eliminate power supply noise does not give noise to other circuits (or cause malfunction of other circuits). There is.

  The present invention has been made based on such consideration, and an object of the present invention is to reliably prevent malfunction of a circuit due to power supply noise in a circuit operating with a separate power supply.

  The malfunction prevention circuit of the present invention detects a power supply noise superimposed on a power supply voltage of the first circuit and outputs a power supply noise detection signal, the first circuit, and the first circuit, Is provided between the first circuit and the second circuit that operates with a separate power source, and an erroneous signal is transmitted from the first circuit to the second circuit during a period when the power noise detection signal is active. And a noise cancellation circuit for blocking.

  A noise canceller is provided between the first circuit and the second circuit that operate with separate power supplies, the power supply noise detection circuit detects the power supply noise of the first circuit, and the noise cancellation circuit is operated based on the detection signal. During the period when the power supply noise is detected, signal transmission from the first circuit to the second circuit is blocked, and when the power supply noise is not detected, the normal state is restored. Since the power cancellation noise is actually detected and the noise cancellation circuit is operated, transmission of an erroneous signal (noise) can be surely prevented in advance regardless of the duration of the power supply noise.

  In one aspect of the malfunction prevention circuit of the present invention, the first circuit operates between a first high-level power supply voltage and a first low-level power supply voltage, and the second circuit The circuit operates between a second high-level power supply voltage and a second low-level power supply voltage, and the power supply noise detection circuit has a positive polarity applied to the first high-level power supply voltage. Both power supply noise and negative power supply noise can be detected.

  Since the polarity of the power supply noise superimposed on the high-level power supply of the first circuit can be both positive and negative, it can cope with power supply noise of either polarity.

  According to another aspect of the malfunction prevention circuit of the present invention, the power supply noise detection circuit detects both positive power supply noise and negative power supply noise applied to the first high-level power supply voltage. In addition, it is also possible to detect positive power supply noise applied to the first low-level power supply voltage.

  As the power supply of the first circuit, there are a high-level power supply and a low-level power supply (for example, ground), and even when positive power supply noise is superimposed on the low-level power supply, the threshold value of the first circuit Misrecognition occurs due to level fluctuations. Therefore, it is possible to cope with power supply fluctuations of the low-level side power supply, and in any case, the malfunction of the circuit can be surely prevented.

  In another aspect of the malfunction prevention circuit of the present invention, the first power supply noise detection circuit includes positive power supply noise, negative power supply noise applied to the first high-level power supply voltage, It has a gate circuit that detects any input of positive power supply noise applied to the first low-level power supply voltage and generates a detection pulse.

  If any of three types of power supply noise (positive power supply noise superimposed on the high-level power supply, negative power supply noise, or positive power supply noise superimposed on the low-level power supply) is input, A detection pulse is generated by a circuit.

  In another aspect of the malfunction prevention circuit of the present invention, the power supply noise detection circuit includes a timing adjustment circuit for adjusting a timing of the power supply noise detection signal, and the timing adjustment circuit is configured to detect the power supply noise. In response to the detected timing, the power supply noise detection signal is set in an active state, and thereafter, the power supply noise detection signal in the active state is turned off after a predetermined time delay from the timing at which the power supply noise is not detected. Transition to the active state.

  When power supply noise is detected, it is necessary to turn on the noise cancellation circuit immediately. Therefore, when power supply noise is detected, the power supply noise detection signal is shifted to the active state at that timing. On the other hand, even after the power supply noise is no longer detected, the potential fluctuation of the power supply line may continue for a while, and a delay occurs until the output signal of the first circuit is input to the noise cancellation circuit. There may be cases. Therefore, the transition of the power supply noise detection signal to the inactive state should be performed carefully. From this viewpoint, after the power supply noise is not detected, the power supply noise detection signal is deactivated after a predetermined delay time. It is what I did. With this timing control, noise cancellation can be performed more reliably.

  In another aspect of the malfunction prevention circuit of the present invention, a delay of a predetermined time is given to the output signal of the first circuit, and the delay time causes the power supply noise detection signal in the active state to be in an inactive state. Is set to be shorter than the delay time given by the timing adjustment circuit.

  As soon as power supply noise is detected, the power supply noise detection signal becomes active and the noise cancellation circuit operates to shut off the signal. On the other hand, the normal signal (incorrect signal) reaches the noise cancellation circuit with a slight delay. Therefore, erroneous signal transmission is reliably prevented. On the other hand, when power supply noise is no longer detected, after the regular signal arrives at the noise canceller, the power supply noise detection signal becomes inactive and the signal block of the noise cancellation circuit is released. Therefore, transmission of an erroneous signal can be prevented more reliably.

  In another aspect of the malfunction prevention circuit of the present invention, the noise cancellation circuit outputs a signal from the first circuit as it is during a period in which the power supply noise detection signal is inactive, and the power supply In a period in which the noise detection signal is output, a holding circuit that outputs the signal immediately before being held is provided instead of the signal from the first circuit.

  The noise cancellation circuit is configured by a holding circuit (so-called through latch). That is, the holding circuit as the noise canceling circuit outputs the input signal as it is in a normal state, and outputs the signal immediately before being held when the input signal is cut off. A noise canceling circuit can be configured by a simple circuit having versatility, which contributes to space saving and the like.

  In another aspect of the malfunction prevention circuit of the present invention, the power supply noise detection circuit operates between the first high-level power supply voltage and the first low-level power supply voltage. The second circuit operates between a second high-level side power supply voltage and a second low-level side power supply voltage, and has a positive polarity applied to the first high-level side power supply voltage. In order to detect the power supply noise, a gate is connected to the second high-level power supply voltage, and a voltage obtained by stepping down the first high-level power supply voltage is input to one end, and When the power supply noise is superimposed, the input voltage rises, and when the relationship between the potential of the one end and the potential of the gate is different from the normal state, the power supply noise is superimposed. The switch that outputs the input voltage from the other end A pull-down element having one end connected to the other end of the switching transistor and grounded at the other end; the second high-level power supply voltage; and the other end of the switching transistor and the pull-down And a logic gate having one end connected to a common connection point with the element.

When positive power supply noise is added to the high-level power supply of the first circuit, it becomes an excessive abnormal voltage exceeding the power supply voltage, and a large current flows instantaneously. How to detect the power supply noise Is a big problem. Therefore, a circuit configuration that can detect power supply noise at a high speed with a simplified configuration and can quickly release excessive surge energy to ensure surge resistance is adopted. The power supply noise is detected by a gate-grounded switching transistor excellent in high frequency response. That is, the switching transistor is turned on at high speed by reversing the potential relation between the source and gate, and the power supply noise is grounded via a pull-down element (including a pull-down circuit using an active element (so-called active pull-down) in addition to a pull-down resistor). It is absorbed quickly. On the other hand, when a surge current is flowing, one end of the pull-down resistor is at a high level. Therefore, a change in the voltage level is detected by a logic gate, thereby detecting power supply noise. The pull-down element provides a function to provide a discharge path for excessive surge current and a function to detect power supply noise in addition to the function to fix the input terminal of the logic gate to a low level during normal operation (when there is no power supply noise). To do. With a simplified circuit configuration, excessive power supply noise can be detected quickly and efficiently, and there is no concern that the power supply noise detection circuit itself is destroyed by an excessive voltage.

  According to another aspect of the malfunction prevention circuit of the present invention, the switching transistor is a floating potential type MOS transistor in which the potential of the semiconductor substrate immediately below the gate is not fixed, and the switching transistor is in an on state. And a potential adjusting circuit for adjusting the potential of the semiconductor substrate immediately below the gate to a predetermined potential both when the switching transistor is in the off state. In such a case, the semiconductor substrate immediately below the gate is adjusted to be maintained at a predetermined potential, and when the switching transistor is on, the one end of the switching transistor and the semiconductor substrate are set to the same potential.

  When the switching transistor is turned on by the input of power supply noise, for example, a substrate current flows instantaneously, which should not cause latch-up or adversely affect the operation of other circuits. Therefore, a floating method in which the substrate potential of the switching transistor is not fixed is adopted, and the substrate potential is always optimized. When a switching transistor is turned on and a large current flows, if a parasitic diode between the source and the substrate turns on and a voltage drop corresponding to the forward voltage of the diode occurs, this may adversely affect other circuits. Therefore, when the switching transistor is turned on, the source and the substrate are set to the same potential to prevent the parasitic diode from being turned on. Even when the switching transistor is off, it is desirable that the substrate potential is stable, so that the substrate is biased and maintained at a predetermined potential. Since the substrate potential of the switching transistor is stabilized, other circuits are not adversely affected even when an excessive surge is input. Therefore, the malfunction prevention circuit of the present invention can be used with confidence.

  The semiconductor integrated circuit device according to the present invention is caused by the first circuit, the second circuit operated by a power supply different from the first circuit, and power supply noise of the first circuit. And a malfunction prevention circuit according to the present invention for preventing a generated erroneous signal from being transmitted from the first circuit to the second circuit.

  By mounting the malfunction prevention circuit of the present invention, malfunction of the semiconductor integrated circuit device due to power supply noise is surely prevented.

  The electronic device of the present invention is equipped with the semiconductor integrated circuit device of the present invention.

  By mounting the semiconductor integrated circuit device of the present invention, a serious malfunction of the electronic device due to power supply noise (for example, a malfunction that the display on the panel disappears) does not occur. Therefore, the reliability of the electronic device is improved.

Thus, according to the embodiment of the present invention, for example, the following main effects can be obtained.
(1) Since power supply noise is detected and signal transmission is interrupted by the noise cancellation circuit during the period when the power supply noise continues, an erroneous signal between circuits operating on different power supplies regardless of the duration of the power supply noise. Transmission can be reliably prevented.
(2) It is possible to cope with both positive / negative power supply noise superimposed on the high-level power supply and positive power supply noise superimposed on the low-level power supply.
(3) Further, when generating the power supply noise detection signal, the first edge / second edge timing is controlled, and in particular by combining with the delay of the input signal to the noise cancellation circuit, Transmission of an erroneous signal (noise) to the circuit can be prevented more reliably.
(4) By configuring the noise cancellation circuit with a holding circuit (through latch), noise can be removed with a simple circuit.
(5) In addition, as a method of detecting noise in which a positive pulse is superimposed on the high-level power supply voltage, a gate-grounded switching transistor is used, and the switching transistor is turned on at high speed by comparing the source potential and the gate potential. Simplified configuration by rapidly discharging power supply noise to the discharge path formed by the pull-down element and detecting the power supply noise by detecting the potential rise at one end of the pull-down element with a logic gate Thus, power supply noise can be detected at high speed and efficiently while protecting the circuit from destruction.
(6) In addition to a floating switching transistor, the substrate potential directly under the gate is always stabilized (optimized) so that no adverse effects are exerted on other circuits when power supply noise is input. Therefore, the malfunction prevention circuit of the present invention can be used with peace of mind.
(7) Since the malfunction prevention circuit of the present invention has a small number of elements and is compact, it can be easily arranged in an I / O cell such as a gate array or an internal logic circuit.
(8) According to the present invention, it is possible to reliably prevent malfunctions caused by power supply noise in the semiconductor integrated circuit device and the electronic apparatus, and the reliability is improved.
(9) The present invention is effective in improving ESD immunity (electrostatic discharge resistance) of integrated circuit devices, which tend to be especially emphasized in recent years.

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
FIG. 1 is a block diagram showing an example of a malfunction prevention circuit of the present invention.
As illustrated, the malfunction prevention circuit includes a power supply noise detection circuit 200, and a noise cancellation circuit (hereinafter, referred to as a noise cancellation circuit provided between the first circuit 100 (block A) and the second circuit 110 (block B)). 300).

  The power supply noise detection circuit 200 includes positive / negative power supply noise superimposed on the first high-level power supply voltage VD1, and positive power supply superimposed on the first low-level power supply voltage (VSS1). Noise is detected and the noise canceller 300 is operated to prevent transmission of an erroneous signal (noise) due to the power supply noise from the first circuit 100 to the second circuit 110.

  Since power supply noise is detected by the power supply noise detection circuit 200 and signal transmission is interrupted by the noise canceller 300, erroneous signal transmission between circuits operating with different power supplies can be reliably prevented regardless of the duration of power supply noise. Can do. This reliably prevents malfunction of the integrated circuit device and the electronic device. Further, both positive / negative power supply noise superimposed on the high level power supply and positive power supply noise superimposed on the low level power supply can be dealt with.

  For example, by providing the malfunction prevention circuit of the present invention for each critical path (signal line in which erroneous signal transmission may seriously affect the electronic apparatus), the malfunction of the integrated circuit device (electronic apparatus) is ensured. Can be prevented.

  Here, the “power noise” includes, for example, pulse noise caused by ESD (electrostatic discharge), but is not limited to this, and includes power fluctuation due to other causes. For example, even when the power supply is shaken by a rush current when the power supply is turned on, an erroneous signal may be transmitted, so that the application of the present invention is desirable.

  The power supply of the first circuit 100 and the second circuit 110 must be different power supplies (power supply lines are separated), and the power supply potential does not matter (that is, the voltage level of each power supply is not limited). The present invention can be applied even if they are the same).

  In the case where the power supply voltages of the first circuit 100 and the second circuit 110 are different, the first circuit 100 is an input interface circuit of the integrated circuit device, and the second circuit is formed inside the integrated circuit device. The case of a high-speed logic circuit can be assumed. In other words, when a signal from an external circuit that operates with a high-voltage power supply is level-shifted by an input interface circuit that also operates with a high-voltage power supply, and then transmitted to an internal high-speed logic circuit that operates with a low-voltage power supply It is.

  In particular, when a positive surge is applied to a high-level power supply voltage, a large amount of energy is applied to the integrated circuit device, so it is highly likely to cause various problems, and the application of the present invention is extremely effective. . Assuming that the power supply voltages of the first circuit and the second circuit are at the same level, it is assumed that both the first and second circuits are high-speed logic circuits formed inside the integrated circuit device. can do. That is, both the first and second circuits (100, 110) are internal circuits, and each internal circuit is supplied with power of the same voltage from separate power supply lines. When power supply noise occurs in the voltage, an error occurs in the signal processing of the second circuit 110 due to erroneous signal transmission, so that the application of the present invention is effective.

(Second Embodiment)
In the present embodiment, a specific circuit configuration of the malfunction prevention circuit of the present invention shown in FIG. 1 will be described. FIG. 2 is a circuit diagram showing a specific circuit configuration example of the malfunction prevention circuit of the present invention. In FIG. 2, the same reference numerals are given to the portions common to FIG.

  As illustrated, the noise detection circuit 200 includes a first path 210a for detecting positive noise (1) superimposed on the first high-level power supply voltage (VD1), and a first high-level power supply. A second path 210b for detecting negative noise (2) superimposed on the voltage (VD1) and a third path for detecting positive noise superimposed on the first low-level power supply voltage (VSS1). Path 210c, a three-input one-output gate circuit 212, and a timing circuit 250.

  The first path 210a for detecting positive noise (1) superimposed on the first high-level power supply voltage (VD1) is a step-down circuit that steps down the first high-level power supply voltage (VD1). 202, a gate-grounded switching transistor MP connected to the second high-level power supply voltage (VD2) at the gate (this switching transistor MP functions as the power supply noise detection gate 204), a pull-down resistor 206, and a pull-down resistor And an inverter (logic gate) 208 connected to one end of the resistor.

  The output signal of the first circuit (first block A) 100 is given a predetermined delay by the timing circuit 252 and then the noise canceller 300 (specifically, the holding circuit (through latch) 302). It reaches the D terminal.

  Further, the power supply noise detection signal from the power supply noise detection circuit 200 is input to the C terminal of the holding circuit 302 as the noise canceller 300. When no power supply noise detection signal is input to the C terminal, the holding circuit 302 outputs the signal input to the D terminal as it is from the M terminal. On the other hand, during the period when the power supply noise detection signal is input to the C terminal, the signal immediately before being held is continuously output from the M terminal. This prevents the transmission of noise signals.

  In the circuit of FIG. 2, what is particularly important is the operation when positive power supply noise (1) is added to the first high-level power supply voltage (VD1). That is, at this time, an excessive abnormal voltage exceeding the power supply voltage is applied, and a large current flows instantaneously, so how to detect the power supply noise is a big problem. Therefore, a circuit configuration is employed that can detect power supply noise at a high speed with a simplified configuration, and can quickly release excessive surge energy to ensure surge resistance.

  That is, power supply noise is detected by a gate-grounded P-channel MOS transistor (MP) excellent in high-frequency response. A voltage obtained by stepping down the first high-level power supply voltage VD1 is applied to the source (point A2 in the figure) of the PMOS transistor (MP), and the second high-level power supply voltage VD2 is applied to the gate. In general, the gate potential is higher than the potential of the source (point A2). Therefore, the PMOS transistor MP is off.

  Here, when positive noise (1) is applied, the potential of the source (point A2) rises and the potential of the source (point A2) exceeds the gate potential. As a result, the source / drain voltage of the PMOS transistor (MP) is generated, and the PMOS transistor (MP) is quickly turned on. The positive noise applied to the point A2 (or point A3) is released to the ground via the pull-down resistor 206. Therefore, the PMOS transistor (MP) itself is not destroyed by the surge.

  While the noise current is flowing, the potential at one end (point A3) of the pull-down resistor 206 is at a high level. By detecting this potential change by the inverter 208, positive power supply noise (1) Can be detected. The pull-down resistor 206 has a function of providing a discharge path for power supply noise and a function of detecting power supply noise in addition to a function of maintaining the potential of the input terminal of the inverter 208 at a low level during normal operation. Thus, power supply noise can be detected efficiently. That is, excessive power supply noise can be detected quickly and efficiently with a simplified circuit configuration. Further, there is no fear that the power supply noise detection circuit itself is destroyed by an excessive voltage.

  Further, the transmission of noise is more reliably prevented by the action of the timing circuit (250, 252). This point will be described later with reference to FIG.

  FIG. 3 is a circuit diagram showing a more specific circuit configuration example of the malfunction prevention circuit shown in FIG. In FIG. 3, parts that are the same as those in FIG. 2 are given the same reference numerals in principle. However, the first high-level power supply voltage (VD1) in FIG. 2 is represented as HVDD (= 3.3 V) in FIG. Similarly, the second high-level power supply voltage (VD2) in FIG. 2 is expressed as LVDD (= 1.8V).

  In FIG. 3, the first circuit (block A) is provided with a plurality of inverters (101, 102) as an input interface, and a level shifter 103 and an output buffer 104 are provided as output interfaces. It has been.

  In the power supply noise detection circuit 200, the step-down circuit 202 includes n-stage diode-connected MOS transistors (M1 to Mn).

  The switching transistor (noise detection means 204) is configured by a PMOS transistor (MP) in which the substrate potential is floated.

  The gate circuit 212 includes a NAND gate 214, a NOR gate 216, and an inverter 218. Normally, the output level of the NAND gate 214 is “L”, but when a positive or negative power supply noise is applied to HVDD, the output level changes to “H”, and the output of the NOR gate 216 is “ It changes from “H” to “L”. Thereby, it is possible to detect power supply noise superimposed on HVDD.

  Similarly, when positive noise is superimposed on VSS1, the output of the NOR gate 216 changes from “H” to “L”. Therefore, it is possible to detect noise superimposed on VSS1.

  The timing circuit 250 includes a NOR gate 255 and inverters (251 to 254, 256). The four-stage inverters 251 to 255 are inserted in order to adjust timing so that the power supply noise detection signal shifts to a low level after a predetermined delay period elapses after power supply noise is no longer detected.

  The timing circuit 252 is composed of two stages of inverters 253 and 254. The delay time of the timing circuit 252 is set shorter than the delay time of the timing circuit 250.

  4A to 4C are diagrams for explaining a specific configuration and characteristic operation of a switching transistor as a noise detecting means.

  The switching transistor (MP) in FIG. 4 (a) has the device configuration shown in FIG. 4 (b). The switching transistor (MP) is formed on the semiconductor substrate 310, and includes a polysilicon gate 326, a gate insulating film 324, and a P-type impurity introduction region (source region and drain region) formed in the N well region 320. 322a and 322b. D1 and D2 are parasitic diodes.

  When the switching transistor (MP) is turned on by the input of power supply noise, when the parasitic diode D1 is turned on and the substrate current flows instantaneously, the potential of the N well drops by the forward voltage of the diode D1, which is latched. It cannot be said that there is no fear of causing an increase or adversely affecting the operation of other circuits. Therefore, as shown in FIG. 4C, a floating N-well method in which the potential of the N well 320 is not fixed is adopted, and the potential of the N well (substrate) is always optimized.

  That is, in order to stabilize the potential of the N well 320, PMOS transistors M10 and M11 are provided as shown in FIG. The PMOS transistor M10 equivalently serves as a diagram switch SW1 (indicated by a dotted line in the figure), and is turned on when power supply noise is input (that is, the switch SW1 is closed). The parasitic diode D1 cannot be turned on by setting the anode and cathode of the parasitic diode D1 to the same potential. On the other hand, when the power supply noise is not detected, the PMOS transistor M11 is turned on, and the N well 320 (the cathodes of the parasitic diodes D1 and D2) is charged through the route indicated by the dotted arrow in the figure, and the potential is set to the second level. Is maintained at the high level power supply voltage (LVDD).

  As described above, when the switching transistor (MP) is turned on and a large current flows, the parasitic diode D1 between the source and the N-well is turned on and a voltage drop corresponding to the forward voltage of the diode occurs. When the switching transistor (MP) is turned on, the source 322a and the N well 320 are set at the same potential to prevent the parasitic diode D1 from being turned on. Even when the switching transistor (MP) is off, it is desirable that the N-well potential is stable, so that the N-well is biased and maintained at the second high-level power supply voltage (LVDD). In this way, since the substrate potential of the switching transistor (MP) is always stabilized, even when an excessive surge is input, other circuits are not adversely affected. A circuit can be used.

  FIGS. 5A to 5C are diagrams for explaining a specific circuit configuration and operation of the holding circuit 302 functioning as the noise canceller 300. FIG. For ease of understanding, the transfer switches (T10, T20) are depicted as mechanical switches in FIGS. 5 (b) and 5 (c).

  As shown in FIG. 5A, the holding circuit 302 includes a plurality of inverters (INV10 to INV15) and transfer switches (T10, T20). Then, during the period when the power supply noise detection signal is not input to the C terminal, the signal input to the D terminal is output from the M terminal as it is, as indicated by the solid line arrow in FIG. On the other hand, during the period when the power supply noise detection signal is input to the C terminal, the signal immediately before being held circulates as shown by the dotted arrow in FIG. 5C, and the signal immediately before that is output from the M terminal. Continue to be.

6A to 6C are circuit diagrams for explaining the operation of the timing circuit shown in FIG. 3 and the effects thereof.
When power supply noise is detected, one input terminal of the NAND gate 255 rises to a high level, so that the power supply noise detection signal is held without delay through the route indicated by the solid line arrow in FIG. 302. At this time, the signal from the first circuit 100 arrives at the D terminal of the holding circuit 302 after being delayed through the two-stage inverters (253, 254). Therefore, when the input signal arrives at the D terminal, the holding circuit 302 is always switched to the holding mode (blocking mode).

  On the other hand, when the power supply noise is not detected, the output level is not reversed unless both the two input terminals of the NAND gate 255 are at the low level. As a result, the route passes through the route indicated by the dotted line in FIG. Then, after a delay of four stages of inverters (251 to 254), the signal arrives at the C terminal of the holding circuit 302 later than the signal from the first circuit 100. Therefore, after the noise is settled, the holding mode (shutoff mode) of the holding circuit 302 is released with a sufficient margin, and an erroneous signal (noise) due to power supply noise is transmitted to the second circuit 110. There is nothing.

  FIG. 6C shows changes in the voltages at the nodes A8, A9 and A10 in FIGS. 6A and 6B. In the figure, DT1 indicates a margin when power supply noise is detected and the holding circuit 302 is set to the holding mode, and DT2 cancels the holding mode of the holding circuit 302 when power supply noise is not detected. The margin (margin) is shown. Thus, by performing the timing adjustment, transmission of an erroneous signal (noise) due to power supply noise is reliably prevented.

(Third embodiment)
In this embodiment, an example of the arrangement (layout) of the malfunction prevention circuit of the present invention in an integrated circuit device (LSI) will be described.

(Example of providing a noise canceller between the interface circuit and internal circuit)
FIG. 7 is a block diagram showing an example of a mounting configuration of the malfunction prevention circuit of the present invention (an example of preventing noise transmission from the input interface circuit to the internal circuit).
As shown in the figure, a signal from the output terminal (W11) of the external circuit (IC) 400 operating between the first high-level power supply voltage (HVDD) and the first low-level power supply voltage (VSS1) is obtained. , And input to the input terminal (W20) of the IC500.

  The IC 500 includes an I / O cell 506 that operates between a first high-level power supply voltage (HVDD) and a first low-level power supply voltage (VSS2), and a second high-level power supply voltage (LVDD). And an internal logic circuit (high-speed logic circuit composed of a gate array, a standard cell, or the like) 110 that operates between the second low-level power supply voltage (VSS2). The IC 500 also includes a power cell 502 that supplies a first high-level power supply voltage (HVDD) and a power cell 504 that supplies a second high-level power supply voltage (LVDD).

  The interface circuit 100 includes two-stage inverters (101, 102) that constitute a level shifter. The first-stage inverter 101 operates with the first high-level power supply voltage (HVDD), and the next-stage inverter 102 operates with the second high-level power supply voltage (LVDD). The threshold voltage (Vth) of the inverter 101 fluctuates due to the application of power supply noise to the first high-level power supply voltage (HVDD) or the first low-level power supply voltage (VSS1). An incorrect signal is output from the inverter 101. If noise cancellation is not performed, the erroneous signal is output to the outside as an output signal (Vout) via the inverter 101 and the inverter 103 in the internal logic circuit 110, which is a serious electronic device. May cause malfunction.

  Therefore, erroneous signal transmission is blocked by the noise canceller 300 (302) arranged at the output stage of the I / O cell 506. On the other hand, the noise detection circuit 200 is built in the power cell 502. The noise detection circuit 200 is one of power supply noise superimposed on the first high-level power supply voltage (HVDD), the second high-level power supply voltage (LVDD), and the first low-level power supply voltage (VSS1). And the noise canceller 300 (302) is operated. Thus, it is possible to reliably prevent erroneous signal transmission caused by power supply noise.

(Example of noise canceller provided between internal circuits)
FIG. 8 is a block diagram showing another example of the mounting configuration of the malfunction prevention circuit of the present invention (an example of preventing noise transmission from the internal logic to the internal logic).
As illustrated, the IC 600 includes an I / O cell (606, 608), a core circuit 610, and a power cell (602, 604) that supplies a second high-level power supply voltage (LVDD). .

  The core circuit 610 includes internal logic (110a, 110b), and the noise canceller 300 (302) is provided between the internal logics (110a, 110b). The noise detection circuit 200 is provided in the power cell 602. When the power supply voltage (LVDD, ground potential) supplied to the internal logic 110a fluctuates due to power supply noise, an incorrect signal (noise) is transmitted from the inverter 620 in the internal logic 110a to the inverter 621 in the internal logic 110b. When power supply noise is detected by the power supply noise detection circuit 200, the noise canceller 300 (302) blocks the transmission of the noise.

(Example of providing a noise canceller for both the input interface and internal logic)
FIG. 9 is a block diagram showing another example of mounting the malfunction prevention circuit of the present invention (an example in which a noise canceller is provided in both the input interface and the internal logic). In FIG. 9, the same reference numerals are given to the portions common to the above-mentioned drawings.

  As shown in the figure, the power cell 502 is a power cell for supplying the first high-level power supply voltage (HVDD), and is equipped with a power noise detection circuit 200a. The I / O cell 506a is equipped with a noise canceller 300a. When power supply noise detection circuit 200a detects power supply noise, it operates noise canceller 300a in the I / O cell to prevent noise transmission from I / O cell 506a to internal logic 110c.

  The power cell 602a includes a power noise detection circuit 200b. The noise canceller 300b is provided between the internal logic 110a and the internal logic 110b. The power cells 602a and 602b supply the second high-level power supply voltage (LVDD) to the internal logics 110a and 110b, respectively. When detecting the power supply noise, the power supply noise detection circuit 200b operates the noise canceller 300b to prevent noise transmission from the internal logic 110a to the internal logic 110b.

(Fourth embodiment)
In this embodiment, an example of an electronic device equipped with an integrated circuit device incorporating the malfunction prevention circuit of the present invention will be described. Although this electronic device is ultra-compact and lightweight, it does not malfunction due to the input of an ESD pulse (electrostatic discharge pulse) by an operator (user), and reliability against ESD is guaranteed.

FIGS. 10A to 10C are diagrams each showing an external appearance of an example of an electronic device equipped with the malfunction prevention circuit of the present invention.
FIG. 10A illustrates an example of an external view of a mobile phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 10B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an image output unit 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 10C illustrates an example of an external view of a portable information device (PDA) 970 that is one of the electronic devices. The portable information device (PDA) 970 includes a keyboard 972 that functions as an input unit, an image output unit 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  In addition, it is possible to apply this invention besides what is shown to Fig.10 (a), (b), (c). For example, the present invention can be applied to electronic devices such as personal computers, pagers, electronic desk calculators, devices equipped with touch panels, projectors, word processors, viewfinder type or monitor direct view type video tape recorders, car navigation devices, and the like. Is possible.

As described above, according to the embodiment of the present invention, the following main effects can be obtained.
In other words, because power noise is detected and signal transmission is interrupted by the noise cancellation circuit during the period when power noise continues, incorrect signal transmission between circuits operating on different power sources regardless of the duration of power noise Can be reliably prevented.

  Further, both positive / negative power supply noise superimposed on the high level power supply and positive power supply noise superimposed on the low level power supply can be dealt with.

  Further, when generating the power supply noise detection signal, the timing control of the first edge / second edge is performed, and in particular, by combining with the delay of the input signal to the noise cancellation circuit, the first circuit to the second circuit is controlled. Transmission of an erroneous signal (noise) can be prevented more reliably.

  By configuring the noise cancellation circuit with a holding circuit (through latch), noise can be removed with a simple circuit.

  In addition, as a method for detecting noise in which a positive pulse is superimposed on the high-level side power supply voltage, a gate-grounded switching transistor is used, and the switching transistor is turned on at high speed by comparing the source potential with the gate potential. By quickly discharging power supply noise to the discharge path formed by the above and adopting a method of detecting power supply noise by detecting a potential rise at one end of the pull-down resistor by a logic gate, It is possible to detect power supply noise efficiently at high speed while protecting the circuit from destruction.

  In addition, by using a floating switching transistor and constantly stabilizing (optimizing) the substrate potential directly under the gate, there is no adverse effect on other circuits when power noise is input. The malfunction prevention circuit of the present invention can be used.

  Since the malfunction prevention circuit of the present invention has a small number of elements and is compact, it can be easily disposed in an I / O cell such as a gate array or an internal logic circuit.

  According to the present invention, it is possible to reliably prevent malfunctions caused by power supply noise in a semiconductor integrated circuit device and an electronic device, and the reliability is improved.

  The present invention is effective in improving the ESD INITI (electrostatic discharge resistance) of an integrated circuit device, which tends to be particularly emphasized in recent years.

  In addition, although this embodiment was explained in full detail, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the present invention. For example, the present invention can be applied even when the power supply voltage greatly fluctuates due to a rush current or the like when the power is turned on, and noise is generated due to this.

  In the integrated circuit device, when noise is generated due to ESD or the like in the power supply, it is possible to reliably prevent transmission of an erroneous signal (noise) generated due to the power supply noise to the inside. Therefore, it is useful as an ESD immunity improvement method for malfunction prevention circuits, semiconductor integrated circuit devices, electronic devices, and semiconductor integrated circuits.

It is a block diagram which shows an example of the malfunction prevention circuit of this invention. It is a circuit diagram which shows the concrete circuit structural example of the malfunction prevention circuit of this invention. FIG. 3 is a circuit diagram showing a more specific circuit configuration example of the malfunction prevention circuit shown in FIG. 2. (A)-(c) is a figure for demonstrating the specific structure and characteristic operation | movement of a switching transistor as a noise detection means. (A)-(c) is a figure for demonstrating the specific circuit structure and operation | movement of the holding circuit 302 which functions as the noise canceller 300. FIG. (A)-(c) is a circuit diagram for demonstrating operation | movement of the timing circuit shown by FIG. 3, and its effect. It is a block diagram which shows an example (example which prevents the noise transmission from an input interface circuit to an internal circuit) of the mounting form of the malfunction prevention circuit of this invention. It is a block diagram which shows the other example (example which prevents the noise transmission from internal logic to internal logic) of the mounting form of the malfunction prevention circuit of this invention. It is a block diagram which shows the other example (example which provides a noise canceller in both an input interface and internal logic) of the mounting form of the malfunction prevention circuit of this invention. (A)-(c) is a figure which shows the external appearance of the example of the electronic device which mounts the malfunction prevention circuit of this invention, respectively. It is a figure for demonstrating an example of an ESD immunity test. FIG. 6 is a circuit diagram for explaining a malfunction of a circuit caused by power supply noise in two circuit blocks operating with different power supplies. FIG. 13 is a timing diagram illustrating how malfunction occurs due to power supply noise in the circuit system illustrated in FIG. 12.

Explanation of symbols

100 first circuit (circuit block A), 110 second circuit (circuit block B),
200 power supply noise detection circuit, 202 step-down circuit,
204 Positive power supply noise detection means, 206 pull-down resistor,
208 Inverter for detecting power supply noise, 212 gate circuit,
250 timing circuit, 252 timing circuit,
300 noise canceller, 302 holding circuit

Claims (11)

A power supply noise detection circuit that detects power supply noise superimposed on the power supply voltage of the first circuit and outputs a power supply noise detection signal;
The first circuit is provided between the first circuit and a second circuit that operates with a power supply different from the first circuit, and an erroneous signal is output from the first circuit during a period in which the power supply noise detection signal is active. A noise canceling circuit for preventing transmission from the second circuit to the second circuit;
A malfunction prevention circuit comprising: The malfunction prevention circuit according to claim 1,
The first circuit operates between a first high-level power supply voltage and a first low-level power supply voltage, and the second circuit includes a second high-level power supply voltage and a first low-level power supply voltage. Operating between two low-level power supply voltages,
The malfunction prevention circuit according to claim 1, wherein the power supply noise detection circuit can detect both positive power supply noise and negative power supply noise applied to the first high-level power supply voltage. A malfunction prevention circuit according to claim 2,
In addition to detecting both positive power supply noise and negative power supply noise applied to the first high level side power supply voltage, the power supply noise detection circuit further includes the first low level side power supply voltage. A malfunction prevention circuit characterized in that it can also detect positive power supply noise applied to the. A malfunction prevention circuit according to claim 2 or claim 3, wherein
The first power supply noise detection circuit includes:
Detecting input of positive power supply noise applied to the first high-level power supply voltage, negative power supply noise, or positive power-supply noise applied to the first low-level power supply voltage And a malfunction prevention circuit comprising a gate circuit for generating a detection pulse. A malfunction prevention circuit according to any one of claims 2 to 4,
The power supply noise detection circuit has a timing adjustment circuit for adjusting the timing of the power supply noise detection signal,
The timing adjustment circuit activates the power supply noise detection signal corresponding to the timing at which the power supply noise is detected, and then is delayed by a predetermined time from the timing at which the power supply noise is not detected, A malfunction prevention circuit, wherein the power supply noise detection signal in an active state is shifted to an inactive state. The malfunction prevention circuit according to claim 5,
A delay of a predetermined time is given to the output signal of the first circuit, and the delay time is the delay time given by the timing adjustment circuit when the power supply noise detection signal in the active state is shifted to the inactive state. A malfunction prevention circuit characterized in that the malfunction prevention circuit is set shorter. The malfunction prevention circuit according to claim 1,
The noise cancellation circuit outputs a signal from the first circuit as it is during a period in which the power supply noise detection signal is in an inactive state, and in a period in which the power supply noise detection signal is in an active state. A malfunction prevention circuit comprising: a holding circuit that outputs a signal immediately before being held in place of a signal from the circuit. The malfunction prevention circuit according to claim 1,
The first circuit operates between a first high-level power supply voltage and a first low-level power supply voltage, and the second circuit includes a second high-level power supply voltage and a first low-level power supply voltage. Operating between two low-level power supply voltages,
The power supply noise detection circuit is
In order to detect positive power supply noise applied to the first high-level power supply voltage,
A gate is connected to the second high-level power supply voltage, and a voltage obtained by stepping down the first high-level power supply voltage is input to one end. A switching transistor that turns on when the input voltage rises and outputs the input voltage on which the power supply noise is superimposed, from the other end;
A pull-down element having one end connected to the other end of the switching transistor and the other end grounded;
A logic gate that is operated by the second high-level power supply voltage and has one end connected to a common connection point between the other end of the switching transistor and the pull-down element;
A malfunction prevention circuit comprising: A malfunction prevention circuit according to claim 8, wherein
The switching transistor is a floating potential type MOS transistor in which the potential of the semiconductor substrate immediately below the gate is not fixed, and both when the switching transistor is in an on state and in an off state, A potential adjustment circuit for adjusting the potential of the semiconductor substrate directly under the gate to a predetermined potential;
The potential adjustment circuit adjusts the semiconductor substrate immediately below the gate to be maintained at a predetermined potential when the switching transistor is in an off state, and adjusts the switching transistor when the switching transistor is in an on state. The one end and the semiconductor substrate immediately below the gate have the same potential,
The malfunction prevention circuit characterized by the above-mentioned. The first circuit;
The second circuit operated by a power source different from the first circuit;
The false signal generated due to the power supply noise of the first circuit is prevented from being transmitted from the first circuit to the second circuit. Malfunction prevention circuit;
A semiconductor integrated circuit device comprising:   An electronic device on which the semiconductor integrated circuit device according to claim 10 is mounted.

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