JP2008102219A - Video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display device that can improve the display quality of moving picture display while suppressing blur in a moving picture and generation of flicker. <P>SOLUTION: The video display device includes: an LCD panel 11 composed of a plurality of horizontal lines comprising a plurality of picture elements or pixels; gate driving circuits (first gate driver 13a, second gate driver 13b) repeatedly processing in a predetermined cycle to display input video information in a video information display period and to display a non-video signal in a non-video display period in a grayscale number different from that of the video information, to each horizontal line of the LCD panel 11; and a control circuit 15 controlling the frequency of pulse signals continuously oscillated so as to regulate a sampling period assigned to each picture element or each pixel from the input video information according to the time ratio of the non-video display period to the predetermined cycle time. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a video display device provided with a period for inserting a non-image signal in one frame period in order to suppress moving image blur.

  In an impulse-type display device such as a CRT (Cathode Ray Tube), focusing on individual pixels, a lighting period in which an image is displayed and a light-off period in which no image is displayed are alternately repeated. For example, even when a moving image is displayed, since an extinguishing period is inserted when an image for one screen is rewritten, an afterimage of an object moving in human vision does not occur. For this reason, the background and the object are clearly distinguished, and the moving image is visually recognized without a sense of incongruity.

  On the other hand, in a hold-type display device such as a liquid crystal display device using TFT (Thin Film Transistor), the luminance of each pixel is determined by the voltage held in each pixel capacitor, and the holding voltage in the pixel capacitor is Is maintained for one frame period once rewritten. In this way, in the hold-type display device, the voltage to be held in the pixel capacitance as pixel data is held until it is rewritten once, so that the image of each frame is the same as the image of the previous frame and the time. Will be close to each other. As a result, when a moving image is displayed, an afterimage of a moving object occurs in human vision.

  As a method for reducing such an afterimage, in a hold-type display device such as a liquid crystal display device, a period for performing black display (non-image display) is inserted in one frame period (hereinafter referred to as black insertion). Thus, there is known a method in which the display on the liquid crystal display device is (pseudo-) impulsed (for example, Patent Document 1).

  However, in the case of the pseudo impulse driving as described above, an image display period and a non-image display (black display) period are mixed in one frame period, and an image display period and a non-image display period in one frame period are mixed. Depending on the ratio (display time ratio), when moving images are displayed, there is a possibility that moving image blur caused by an afterimage may occur.

Therefore, for example, in Patent Document 2, the display time ratio between the image display period and the non-image display period in one frame period is adjusted in accordance with the amount of movement of the image in the moving image, thereby displaying the moving image. A technique for reducing moving image blur caused by an afterimage is disclosed.
JP 2003-066918 A (published on March 05, 2003) JP 2002-323876 A (published November 08, 2002)

  By the way, in Patent Document 2, if the amount of motion of an image in a moving image increases, that is, the motion becomes faster, the afterimage is reduced by improving the time ratio of the non-image display period to improve the motion blur.

  However, in moving image display, when the time ratio of the non-image display period is increased, afterimages can be reduced to improve moving image blur for fast moving images, but flicker phenomenon occurs and display quality in moving image display is improved. This causes a problem of lowering.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a video display device capable of improving the display quality of moving image display by suppressing the occurrence of flicker while suppressing moving image blur. Is to realize.

  In order to solve the above problems, the video display device of the present invention is input to a display unit composed of a plurality of horizontal lines composed of a plurality of picture elements or pixels, and to each horizontal line of the display unit. Display processing means for repeatedly performing display processing for displaying the video information within a video information display period and display processing for displaying with different gradation numbers from the video information within a non-video display period, and the predetermined processing Display control for controlling the frequency of a pulse signal that oscillates continuously in order to define a sampling period assigned to each picture element or pixel from input video information in accordance with the time ratio of the non-video display period to the period of And a means.

  According to the above configuration, for each horizontal line of the display means, display processing for displaying the input video information within the video information display period, and display with a different number of gradations from the video information during the non-video display period When the display processing to be performed is repeated at a predetermined cycle, a sampling period assigned to each picture element or one pixel from the input video information is defined according to the time ratio of the non-video display period to the predetermined cycle. Therefore, by controlling the frequency of the pulse signal that oscillates continuously, the length of one frame period can be adjusted.

  This makes it possible to adjust the value of the AC component, which is the numerator of the equation for obtaining the flicker rate, which is affected by the length of one frame period.

  Therefore, when the non-video display period in which flicker phenomenon is likely to occur is long, the AC component can be reduced and the flicker rate can be reduced by increasing the frequency of the pulse signal and shortening the length of one frame period. As a result, the occurrence of flicker can be suppressed. That is, it is possible to provide a video display device capable of suppressing flicker while suppressing moving image blur even when the non-video display period in which flicker phenomenon is likely to occur is long, that is, when the moving image speed is high. it can.

  The display processing means includes a first scanning means for selecting any one of the horizontal lines each time a horizontal synchronization signal is input in order to display the input video information within a video information display period; First holding means for holding video information for one horizontal line in order to perform a first display process on a horizontal line selected by the first scanning means; and non-video information within the non-video display period. And a second scanning means for selecting a horizontal line different from the horizontal line selected by the first scanning means when the horizontal synchronization signal is input, in order to display with different gradation numbers, The display control means preferably controls the frequency of the pulse signal according to the number of lines between the horizontal lines selected within the same horizontal period by the first scanning means and the second scanning means.

  Here, the number of horizontal lines selected by the second scanning unit increases because the number of lines between the horizontal lines selected within the same horizontal period by the first scanning unit and the second scanning unit decreases. It shows that. That is, the smaller the number of lines between the horizontal lines selected within the same horizontal period in the first scanning means and the second scanning means, the greater the ratio of inserting non-video information within the horizontal period. Indicates.

  Therefore, as in the above configuration, the frequency of the pulse signal is controlled according to the number of lines between each horizontal line selected within the same horizontal period by the first scanning unit and the second scanning unit. Thus, it is possible to set the frequency of the pulse signal according to the ratio of inserting non-video information within one horizontal period.

  For example, if the amount of motion of the video information is large, the number of lines is reduced, and the rate at which non-video information is inserted within the horizontal period increases. Thus, the occurrence of flicker can be suppressed.

  When the number of lines is less than a predetermined value, the display control means preferably controls the frequency of the pulse signal to be twice the frequency of the pulse signal when the number of lines is equal to or greater than the predetermined value.

  Thus, the frequency of the pulse signal when the insertion rate of the non-video information with the number of lines less than the predetermined value is high is 2 of the frequency of the pulse signal when the insertion rate of the non-video information with the number of lines equal to or more than the predetermined value is low. By doubling, the occurrence of flicker when the insertion rate of non-video information is high can be reliably suppressed.

  As described above, the video display device according to the present invention includes a display unit composed of a plurality of horizontal lines composed of a plurality of picture elements or pixels, and video information input to each horizontal line of the display unit. Display processing means for repeatedly displaying a display process within a video information display period and a display process with a different number of gradations from the video information within a non-video display period, with a predetermined period, and for the predetermined period Display control means for controlling the frequency of a pulse signal that continuously oscillates in order to define a sampling period assigned to each picture element or pixel from input video information in accordance with the time ratio of the non-video display period. As a result, it is possible to provide an image display device capable of suppressing flickering while suppressing moving image blur even when the moving image speed of the image is high. .

  An embodiment of the present invention will be described as follows. Note that in this embodiment, a liquid crystal display device is described as an example of a video display device.

  As shown in FIG. 1, the liquid crystal display device according to the present embodiment includes an LCD (Liquid Crystal Display) panel (display means) 11, a first source driver 12a and a second source driver 12b as source drive circuits, and gate drive. The circuit includes a first gate driver (first scanning means) 13a and a second gate driver (second scanning means) 13b as circuits, and further external to the first source driver 12a and the second source driver 12b. A video processing circuit 14 for supplying a video signal and a non-video signal input from a frame unit and supplying a horizontal synchronization signal and a vertical synchronization signal to the first gate driver 13a and the second gate driver 13b; A control circuit 15 for supplying a control signal such as a start pulse signal to each of the drivers, and one frame period A microcomputer 16 for setting the ratio of inserting a non-video signal therein and the number of gradations of the non-video signal, and a memory 17 for storing data used by the microcomputer 16 are provided.

  The LCD panel 11 is composed of a plurality of horizontal lines made up of a plurality of picture elements or pixels, and displays a video signal sent from the video processing circuit 14.

  Further, the source driving circuit and the gate driving circuit display a display process for displaying the video information input from the video processing circuit 14 for each horizontal line of the LCD panel 11 within a video information display period, and a non-video signal. It functions as a display processing means for repeatedly performing display processing for displaying with different gradation numbers from the video information within a non-video display period at a predetermined cycle.

  The video processing circuit 14 includes a frame memory 141 that stores video signals sequentially input frame by frame from a tuner (not shown) in units of frames, and a synchronization that separates a horizontal synchronizing signal and a vertical synchronizing signal from the video signal. The signal separation circuit 142 includes a motion amount determination circuit 143 that determines the motion amount of a moving image included in the video signal from the video signals sequentially input for each frame.

  The motion amount determination circuit 143 is a circuit that determines a motion amount by comparing a difference in motion between two or more consecutive frames from a video signal sequentially input for each frame via a tuner or the like. .

  The motion amount determination circuit 143 determines the motion amount by, for example, the following calculation. That is, i is a pixel number arbitrarily selected from pixels existing in each frame among a plurality of frames sent continuously, and Pm i is the number of gradations of the i-th pixel included in the m-th frame. , Where the number of gradations of the i-th pixel included in the (m + 1) th frame is P (m + 1) i, the difference between Pmi and P (m + 1) i is changed from the minimum value of i to the maximum value ( The amount of motion is determined from an integrated value (Σ | Pm i −P (m + 1) i |) obtained by integrating up to 0 to MAX). Specifically, it is determined whether or not the integrated value is within a certain range, and when it is determined that the integrated value is within the range, the amount of motion is determined according to the range. Here, four types of ranges are prepared in order to classify the amount of movement into four levels of minimum, small, medium, and large.

  The motion amount determination circuit 143 sends data of the motion amounts determined in the above-described manner (four levels of minimum, small, medium, and large) to the microcomputer 16.

  The microcomputer 16 instructs the control circuit 15 to set the dot clock magnification corresponding to the motion amount stored in the memory 17 from the motion amount data sent.

  In the memory 17, the memory map 17 a is divided into the number of motion amounts classified into a memory area in which a predetermined non-video signal insertion rate and a dot clock magnification of a predetermined value are set as a set with respect to the motion amount. Save as. In this memory map 17a, setting values are stored so that the non-video signal insertion rate is higher and the dot clock magnification is higher as the amount of motion is larger.

  Here, the non-video signal insertion rate indicates a time ratio for performing non-video display in one frame period. That is, a non-video signal insertion rate of 0 indicates that there is no period for non-video display in one frame period.

  The control circuit 15 supplies a latch strobe LS signal to the first source driver 12a and a count value control signal to the first gate driver 13a and the second gate driver 13b. As a result, a video signal is written from the first source driver 12a to the target pixel of the LCD panel 11 at a predetermined timing during the video display period of one frame period.

  The control circuit 15 supplies a control signal for setting the number of gradations of a signal output as a non-video signal to the second source driver 12b based on an instruction from the microcomputer 16. ing. Thereby, the non-video signal is written from the second source driver 12b to the target pixel of the LCD panel 11 at a predetermined timing during the non-video display period of one frame period.

  Further, the control circuit 15 continuously oscillates in order to define a sampling period assigned to each picture element or one pixel from the input video information according to the time ratio of the non-video display period to the predetermined period. It has a function as display control means for controlling the frequency of the pulse signal. As a specific configuration for this purpose, the control circuit 15 includes a first counter 151 and a dot clock generation unit 152 in order to control the magnification of the dot clock (cycle of one frame).

  The first counter 151 generates a horizontal synchronization signal by counting the number of pixels arranged on one horizontal line (for example, 1080 or more), and allows each gate driver to sequentially select gate lines one line at a time. Circuit.

  The dot clock generation unit 152 is a circuit for generating a pulse signal for defining a sampling period assigned to each pixel or pixel. Here, when the microcomputer 16 selects the magnification of the dot clock frequency assigned on the memory 17 with respect to the non-video signal insertion rate assigned according to the motion amount of the video signal, the dot to be generated in this circuit is selected. It becomes possible to control the clock generation speed. As a result, the generation speed of the horizontal synchronizing signal generated by the first counter 151 is controlled.

  The liquid crystal display device having the above configuration will be described in detail as follows.

  As shown in FIG. 2, the LCD panel 11 includes a plurality of first source bus lines 101a... Connected to the first source driver 12a and a plurality of second sources connected to the second source driver 12b. A plurality of first gate bus lines 102a connected to the first gate driver 13a and a plurality of second gate bus lines 102b connected to the second gate driver 13b. Are arranged so as to be orthogonal to each other, and a first TFT 111a as a switching element is provided at the intersection of the first source bus line 101a and the first gate bus line 102a, and the second source bus line 101b and the second gate A second TFT 111b as a switching element is provided at the intersection with the bus line 102b.

  A common electrode 113 is connected to each drain electrode of the first TFT 111a and the second TFT 111b via a common pixel capacitor 112. Thereby, signals can be separately supplied to the same pixel capacitor 112 from the first source driver 12a and the second source driver 12b.

  As shown in FIG. 2, the first source driver 12 a includes a reference voltage generation circuit 120, a sampling memory 121, a hold memory 122, a DA converter (DAC) 123, and an output circuit 124.

  The reference voltage generation circuit 120 is a circuit that generates a reference voltage for outputting an analog voltage value suitable for an appropriate number of gradations among RGB gradations expressed as a data signal. Is supplied to the DA converter 123. For example, when performing display processing such as dot inversion and line inversion, voltage data is held so that both positive and negative analog gradation voltages can be output for each number of gradations in accordance with an inversion signal generated for each line. For example, in the case of 256 gradations, 256 × 2 pieces of voltage data are held.

  The sampling memory 121 (first holding means) is a memory for reading and storing one line of the video data (RGB) signal sent from the video processing circuit 14 (FIG. 1) before writing it to the LCD panel 11. It is. That is, it is a memory that holds video information for one horizontal line in order to perform a first display process (video display process) on the horizontal line selected by the first gate driver 13a.

  The hold memory 122 is a memory for writing the same data after a data signal for one line is written in the sampling memory 121. The timing of writing data to the DA converter 123 by the hold memory 122 is controlled by a latch strobe LS signal.

  The DA converter 123 is a circuit that converts the data signal for one line stored in the hold memory 122 in a digital format into an analog voltage value according to the voltage value for each gradation output from the reference voltage generation circuit 120.

  The output circuit 124 is a circuit that outputs an analog voltage value signal converted by the DA converter 123 to each source bus line 101a.

  As shown in FIG. 2, the second source driver 12b includes an APL detection circuit 125, a black level control circuit 126, a DA converter (DAC) 127, and an output circuit 128.

  The APL detection circuit 125 is a circuit that detects APL (average luminance level) from video data (RGB) signals.

  The black level control circuit 126 determines the black level, that is, the number of gradations of the non-video signal from the APL detected by the APL detection circuit 125, and outputs a voltage signal corresponding to the determined number of gradations to the DA converter 127. To output.

  The DA converter 127 is a circuit that converts an input voltage signal into an analog voltage value according to the voltage value output from the black level control circuit 126.

  The output circuit 128 is a circuit that outputs an analog voltage value signal converted by the DA converter 127 to each source bus line 101b.

  The first gate driver 13a functions as a first scanning unit that selects any one of the horizontal lines each time a horizontal synchronization signal is input in order to display the input video information within a video information display period. ing. In order to realize this function, the first shift register 131, the level shifter 132, and the output circuit 133 are included as shown in FIG. An example of a specific circuit configuration of the first gate driver 13a is shown in FIG.

  The first shift register 131 connects the plurality of first gate bus lines 102a... Of the LCD panel 11 via the level shifter 132 and the output circuit 133 in the subsequent stage each time a horizontal synchronization signal (Hsync) is input. The first gate voltage is applied line-sequentially by switching and selecting sequentially. As a result, the data signal for one line stored in the first source driver 12a is written to the first source bus line 101a line-sequentially, thereby performing line-sequential scanning.

  The second gate driver 13b displays the non-video information with a gray scale different from that of the video information within the non-video display period by the first gate p driver 13a when the horizontal synchronization signal is input. It has a function of selecting a horizontal line different from the selected horizontal line. In order to realize this function, the second gate driver 13b includes a second counter 134, a second shift register 135, a level shifter 136, and an output circuit 137, as shown in FIG. An example of a specific circuit configuration of the second gate driver 13b is shown in FIG.

  Since the second counter 134 generates a gate pulse for black writing processing with a delay of several tens to several hundred lines with respect to a gate bus line selected once, the second counter 134 has several tens to several hundred lines. This circuit is intended to measure the horizontal synchronization signal.

  Further, the second counter 134 is added with a configuration for comparing the count upper limit data (digital format) included in the count value control signal sent from the microcomputer or the like with the count number measured by the counter. By adjusting the timing of the gate pulse in units of one horizontal period, the display period ratio (black insertion ratio) between the video signal and the black signal output in one vertical period can be controlled.

  The second shift register 135 is a gate bus line that performs black writing processing with a delay of several tens to several hundred lines counted by the second counter 134 with respect to the first shift register 131 of the first gate driver 13a. Is a circuit for selecting.

  Further, in the second shift register 135, by connecting a logic circuit such as an OR circuit to the input terminal of the output of each flip-flop, a plurality of gate lines can be simultaneously selected within one horizontal synchronization period. Yes, if the black gradation (zero gradation ≒ common voltage) cannot be completely reduced by selecting the gate line once, the above OR circuit can select the gate pulse twice or more to reliably write black. It is possible to execute processing.

  In accordance with the scanning of the black writing gate pulse, the second source driver 12b outputs a specific gradation signal expressing a specific gradation number different from the data signal output from the first source driver 12a. The darkness at the time of actual black writing can be adjusted by the tone value.

  That is, the second shift register 135 sequentially switches the plurality of second gate bus lines 102b... Of the LCD panel 11 via the level shifter 136 and the output circuit 137 in the subsequent stage in accordance with the scanning of the gate pulse for black writing. The second gate voltage is applied line-sequentially. As a result, a black write signal is written line-sequentially from the second source driver 12b to the second source bus line 101b.

  The operation of each driver having the above configuration will be described below with reference to FIGS.

  Here, a case where one frame period is composed of a video signal display period and a non-video signal display period will be described.

First, the flow of the data signal scanning process in the normal time, that is, in the video signal display period will be described.
(1): First, a horizontal synchronization signal (Hsync) is input to the first gate driver 13a and the second gate driver 13b.
(2): In the first shift register 131 of the first gate driver 13a, the gate pulse of the Nth line (LineN) rises by the input of Hsync until the next Hsync signal is input, and at the same time, the latch strobe (LS) The signal rises for a period shorter than the gate pulse.
(3): When the LS signal is turned off in (2) above, the start pulse (SP) signal rises.
(4): The rising edge of the SP signal in (3) above turns on the TFT element of each pixel on the Nth line, and the first source driver 12a analogizes the data signal of the desired gradation number with its drain voltage. The converted voltage value is supplied.

Next, the flow of the data signal scanning process in the non-video signal period (black writing period) will be described.
(5): An Hsync signal for selecting a gate line ((N + m) th line) preceding the Nth line by M lines is input.
(6): As a result, the first gate driver 13a selects the (N + m) th line, and at the same time, the second gate driver 13b selects the Nth line with a delay of m lines.

  (7) (8): After that, the data signal for one line stored in the first source driver 12a is output to the (N + m) th line to which the start pulse signal is input, and at the same time the Nth line A predetermined gradation voltage signal corresponding to a predetermined gradation number for one line stored in the second source driver 12b is output to the line. In FIG. 4, a voltage signal of the number of gradations (number of gradations = 0) for black display is output.

  At this time, it is possible to control the number of m lines, which is the difference between the lines selected by the first gate driver 13a and the second gate driver 13b, by an instruction from the microcomputer 16 (FIG. 1). The non-video signal insertion rate is controlled by adjusting this number. Then, the dot clock generation unit 152 can set the dot clock magnification according to the value of the number of lines m. For example, a condition in which the number of lines m is reduced, the non-video signal insertion rate is improved, and flicker is likely to occur. Even in this case, flicker can be prevented by setting the dot clock frequency from 1 to 2 times and doubling the period of one frame by the control circuit 15. In addition, the predetermined number of gradations stored in the second source driver 12b can be rewritten according to the value of the number of lines m. For example, the number of lines m is reduced, the non-video signal insertion rate is improved, and flicker occurs. Even under easy conditions, flicker can be prevented by rewriting the predetermined number of gradations output from the second source driver 12b from zero to a halftone of, for example, around 32 gradations.

  Details of the above effect will be described below.

  FIG. 5A is a diagram illustrating an example of drive control when the time ratio (non-video signal insertion rate) of the non-video display period in one frame period (1 V period) is 10%.

  Thus, when the non-video signal insertion rate is 10%, the dot clock magnification of 1 frame period from the memory 17 shown in FIG. 1 is 1, so the dot clock is 1/60 sec which is a normal frequency. Is set. Thus, the video signal display period is set to 15.0 msec (90%), and the non-video signal display period is set to 1.7 msec (10%).

  FIG. 5A shows an example in which the non-video signal insertion rate is 10%. However, when the amount of motion increases and the non-video signal insertion rate reaches 20%, FIG. As shown in FIG. 5, the dot clock for one frame period is set to 1/120, which is twice that in the case of FIG. Thus, the video signal display period is set to 6.7 msec (80%), and the non-video signal display period is set to 1.7 msec (20%).

  In this way, when the amount of motion of the moving image increases, the flicker rate can be reduced while maintaining the non-video signal insertion rate by increasing the dot clock magnification. High-quality moving images can be displayed.

  In the present embodiment, an example in which two source drivers and two gate drivers are used to supply video signals and non-video signals to the LCD panel 11 by separate drivers has been described. The present invention is not limited to this, and may be realized by one source driver and one gate driver.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention relates to a liquid crystal display device provided with a period for inserting a non-image signal in one frame period in order to suppress moving image blur. If the display device is a hold-type display device, it is within the technical scope of the present invention.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a liquid crystal display device. FIG. FIG. 2 is a block diagram illustrating a main configuration of each driver of the liquid crystal display device illustrated in FIG. 1. FIG. 3 is a circuit diagram illustrating an example of a gate driver illustrated in FIG. 2. It is a wave form diagram of the output signal of each driver of the liquid crystal display shown in FIG. (A) is a waveform diagram of a start pulse signal of black writing processing with a dot clock set when the non-video signal insertion rate is 10%, and (b) is a non-video signal insertion rate of 20%. It is a waveform diagram of a start pulse signal for black writing with a dot clock set in this case.

Explanation of symbols

11 LCD panel (display means)
12a First source driver (display processing means)
12b Second source driver (display processing means)
13a First gate driver (display processing means, first scanning means)
13b Second gate driver (display processing means, second scanning means)
14 Video processing circuit 15 Control circuit (display control means)
16 microcomputer 17 memory 17a memory map 101a first source bus line 101b second source bus line 102a first gate bus line 102b second gate bus line 111a first TFT
111b 2nd TFT
112 pixel capacity 113 common electrode 120 reference voltage generation circuit 121 sampling memory (first holding means)
122 hold memory 123 DA converter 124 output circuit 125 APL detection circuit 126 black level control circuit 127 DA converter 128 output circuit 131 first shift register 132 level shifter 133 output circuit 134 second counter 135 second shift register 136 level shifter 137 output circuit 141 frame Memory 142 Synchronization signal separation circuit 143 Motion amount determination circuit 151 First counter 152 Dot clock generation unit LS Latch strobe signal

Claims (3)

Display means composed of a plurality of horizontal lines composed of a plurality of picture elements or pixels;
Display processing for displaying input video information within a video information display period for each horizontal line of the display means, and display for displaying a non-video signal with a different number of gradations from the video information within a non-video display period Display processing means for repeatedly performing processing at a predetermined cycle;
Controls the frequency of the pulse signal that oscillates continuously in order to define the sampling period assigned to each picture element or pixel from the input video information according to the time ratio of the non-video display period to the predetermined period. An image display device comprising display control means. The display processing means includes
First scanning means for selecting any one of the horizontal lines each time a horizontal synchronization signal is input in order to display input video information within a video information display period;
First holding means for holding video information for the one horizontal line in order to perform a first display process on the horizontal line selected by the first scanning means;
A horizontal line different from the horizontal line selected by the first scanning means when the horizontal synchronization signal is input to display non-video information with a different number of gradations than the video information within a non-video display period. Second scanning means for selecting
The display control means includes
The frequency of the pulse signal is controlled according to the number of lines between horizontal lines selected within the same horizontal period by the first scanning means and the second scanning means. The video display device described. The display control means includes
The frequency of the pulse signal is controlled to be twice the frequency of the pulse signal when the number of lines is equal to or greater than the predetermined value when the number of lines is less than a predetermined value. Video display device.

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