JP2008098805A - Digital camera system and its flicker correction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital camera system shortening time required for completing flicker correction processing after power source supply. <P>SOLUTION: A digital camera 1 includes: a frequency mode storage part 12 for storing a frequency mode which indicates a power source frequency f before turning off the power source of an imaging element 2. A flicker correction part 10 adjusts the shutter value of the imaging element 2 when the power source of the imaging element 2 is turned on, based on the stored frequency mode. For example, the shutter value of the imaging element 2 is set to be the integral multiple of 1/2f. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a digital camera device having a flicker correction function.

  Generally, a digital camera is provided with a flicker correction function. Flicker refers to flickering of the screen, and occurs when the power supply frequency of illumination (fluorescent lamp, etc.) does not correspond to the shutter value of the image sensor (CCD, CMOS, etc.). The commercial power frequency in Japan is 50 Hz in the eastern Japan area and 60 Hz in the western Japan area. In contrast, the digital camera has two frequency modes (50 Hz mode and 60 Hz mode). For example, when the frequency mode of the digital camera is the 50 Hz mode, the image sensor operates with a shutter value corresponding to a power frequency of 50 Hz (commercial power frequency in the East Japan area).

Conventionally, as a technique for performing flicker correction with a digital camera, a technique is known in which the luminance average value of the current frame and the previous frame is compared to determine whether there is no increase / decrease / change, and flicker is detected (for example, Patent Documents). 1). In addition, as a technology related to flicker correction, it is known that for a video that is easy to determine the presence or absence of flicker, processing is performed based on automatic determination, and for a video that is difficult to determine the presence or absence of flicker, the user determines the flicker mode. (See, for example, Patent Document 2).
Japanese Patent Laid-Open No. 2002-152604 (page 2-4, FIG. 1) JP 2003-198882 A (page 2-5, FIG. 2)

  However, in the conventional digital camera, the frequency mode when the digital camera is turned on (when the image sensor is turned on) is fixed to either the 50 Hz mode or the 60 Hz mode. Therefore, for example, when the frequency mode when the digital camera is turned on is the 50 Hz mode, flicker always occurs in the West Japan area, and flicker correction processing such as detection of the power supply frequency and switching of the frequency mode is performed after the power is turned on. It will always be done. In this case, with the conventional digital camera, when the user uses the digital camera in the West Japan area, the flicker correction process is always performed after the power is turned on and the flicker correction process is always performed, so the flicker correction process is completed after the power is turned on. There was a problem that it took time to do. That is, there is a problem that the convergence time for flicker correction is long.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a digital camera device that can shorten the time from when the power is turned on until the flicker correction processing is completed.

  The digital camera device of the present invention includes an imaging unit, a storage unit that stores a frequency mode indicating a power frequency f before the power-off operation of the imaging unit, and the frequency mode stored in the storage unit based on the frequency mode. And a flicker correction unit that adjusts the shutter value of the imaging unit when the imaging unit is powered on.

  With this configuration, the frequency mode before the power-off operation of the imaging unit is stored, and the shutter value of the imaging unit is set using the frequency mode when the power-on operation of the imaging unit is performed. That is, the frequency mode when the digital camera device is turned on (when the imaging unit is turned on) is set to the frequency mode when the digital camera device was used last time. For example, when a digital camera device activated in the 50 Hz mode is used in the West Japan area, the frequency mode is switched from the 50 Hz mode to the 60 Hz mode, and the 60 Hz mode is stored. The next time the digital camera device is turned on in the same 60 Hz West Japan area, the shutter value of the imaging means is set based on the previous frequency mode (60 Hz mode). In this way, by using the frequency mode when the digital camera device was used last time, after the power is turned on, the process of detecting the power frequency and the transition of the frequency mode are substantially canceled. The time until the flicker correction process is completed can be shortened.

  In the digital camera device of the present invention, the flicker correcting unit has a configuration in which the shutter value of the imaging unit is set to an integral multiple of 1 / 2f.

  With this configuration, the shutter value of the imaging unit is set to an integral multiple of 1 / 2f. For example, when the stored frequency f is 50 Hz, the shutter value of the imaging unit is set to an integral multiple of 1/100 second. When the stored frequency f is 60 Hz, the shutter value of the imaging unit is set to an integral multiple of 1/120 seconds. In this way, by associating the power supply frequency of the illumination (fluorescent lamp or the like) with the shutter value of the image pickup means (image sensor such as CCD or CMOS), a high-quality video signal from which flicker is removed can be obtained.

  The flicker correction method for a digital camera device according to the present invention stores a frequency mode indicating a power supply frequency f before a power-off operation of the imaging unit, and based on the stored frequency mode when the power-on operation of the imaging unit is performed. The shutter value of the imaging means is adjusted.

  Also by this, as described above, the frequency mode before the power-off operation of the imaging unit is stored, and the shutter value of the imaging unit is set using the frequency mode when the imaging unit is powered on. That is, the frequency mode when the digital camera device is turned on (when the imaging unit is turned on) is set to the frequency mode when the digital camera device was used last time. In this way, by using the frequency mode when the digital camera device was used last time, after the power is turned on, the process of detecting the power frequency and the transition of the frequency mode are substantially canceled. The time until the flicker correction process is completed can be shortened.

  In the flicker correction method for the digital camera device of the present invention, the shutter value of the image pickup means is set to an integral multiple of 1 / 2f.

  This also sets the shutter value of the image pickup means to an integral multiple of 1 / 2f as described above. In this way, by associating the power supply frequency of the illumination (fluorescent lamp or the like) with the shutter value of the image pickup means (image sensor such as CCD or CMOS), a high-quality video signal from which flicker is removed can be obtained.

  The present invention provides flicker correction processing after power-on by providing storage means for storing the frequency mode before the power-off operation and flicker correction means for adjusting the shutter value at the time of power-on operation based on the stored frequency mode. It is possible to provide a digital camera device having an effect of shortening the time until completion of.

  Hereinafter, a digital camera device according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the case where the digital camera device is an electronic shutter type digital camera or the like is exemplified.

  A configuration of a digital camera according to an embodiment of the present invention is shown in FIGS. FIG. 1 is a block diagram illustrating a configuration of a digital camera. Here, first, a schematic configuration of the digital camera will be described with reference to FIG.

  As shown in FIG. 1, the digital camera 1 automatically includes an imaging device 2, a CDS unit 3 that removes noise by CDS processing (Correlated Double Sampling), and AGC processing (Automatic Gain Control). The AGC unit 4 for adjusting the amplification factor and the AD conversion unit 5 for converting an analog signal into a digital signal are provided. The image pickup device 2 is an image sensor such as a CCD or a CMOS, and corresponds to the image pickup means of the present invention.

  The digital camera 1 also includes a white balance adjustment unit 6 that adjusts white balance, a Y signal processing unit 7 that separates a Y signal from RGB signals, and a C that separates a C signal (U signal and V signal) from RGB signals. A signal processing unit 8 and a control unit 9 that performs operation control of the image sensor 2 and the white balance adjustment unit 6 are provided. The control unit 9 includes a flicker correction unit 10 that performs processing related to flicker correction such as adjustment of the shutter value of the image sensor 2. Here, the flicker correction unit 10 corresponds to the flicker correction means of the present invention.

  The digital camera 1 also includes a coefficient storage unit 11 that stores coefficients used for white balance adjustment, Y signal processing, and the like, and a frequency mode storage unit 12 that stores the frequency mode of the image sensor 2. The coefficient storage unit 11 and the frequency mode storage unit 12 are configured by a memory. Here, the frequency mode storage unit 12 corresponds to a storage unit of the present invention.

  Next, each configuration of the digital camera 1 will be described with reference to the drawings. FIG. 2 is a diagram illustrating an example of the color filter array of the image sensor 2. As shown in FIG. 2, the color filter array of the image sensor 2 is a primary color Bayer array.

  FIG. 3 is a block diagram illustrating an example of the white balance adjustment unit 6. As shown in FIG. 3, the white balance adjustment unit 6 includes an SP conversion unit 61 that performs SP (serial-parallel) conversion processing for converting an input RGB serial signal into a parallel signal, and a parallel-converted RGB signal (R Signal, G signal, and B signal) are provided.

In these gain adjustment units 62, 63, and 64, gain adjustment is performed using the following equations 1 to 3. Here, the R gain K _R , the G gain K _G , and the B gain K _B are predetermined coefficients. These R gain K _R , G gain K _G , and B gain K _B are stored in the coefficient storage unit 11. In this embodiment, the R ′ signal, the G ′ signal, and the B ′ signal are fed back to the control unit 9, and the R gain K _{R is set} so that R ′ = G ′ = B ′ with respect to the achromatic signal. , G gain K _G and B gain K _B are determined.
R ′ = K _R × R (Formula 1)
G ′ = K _G × G (Formula 2)
B ′ = K _B × B (Formula 3)

  FIG. 4 is a block diagram illustrating an example of the Y signal processing unit 7. As shown in FIG. 4, the Y signal processing unit 7 includes an RGB-Y conversion unit 71 that performs RGB-Y conversion processing for converting input R ′, G ′, and B ′ signals into Y1 signals, and Y1. A gain adjusting unit 72 that adjusts the gain of the signal and outputs the Y2 signal, and an offset adjusting unit 73 that adjusts the offset of the Y2 signal and outputs the Y signal are provided.

In this case, the RGB-Y conversion unit 71 performs RGB-Y conversion processing using the following Equation 4. Further, the gain adjustment unit 72 performs gain adjustment using the following Expression 5. Further, the offset adjustment unit 73 adjusts the offset using the following Expression 6. In the present embodiment, these arithmetic processes are performed based on a control signal from the control unit 9. The coefficient a ₁₁ , coefficient a ₁₂ , coefficient a ₁₃ , Y gain K _Y , and Y offset value Y _off are stored in the coefficient storage unit 11.
_{Y1 = a 11 × R + a} 12 × G + a 13 × B ( Equation 4)
Y2 = K _Y × Y1 (Formula 5)
Y = Y2 + Y _off (Formula 6)

  FIG. 5 is a block diagram illustrating an example of the C signal processing unit 8. As shown in FIG. 5, the C signal processing unit 8 is an RGB-UV conversion unit 81 that performs RGB-UV conversion processing for converting input R ′ signal, G ′ signal, and B ′ signal into U1 signal and V1 signal. A gain adjusting unit 82 that adjusts the gain of the U1 signal and the V1 signal and outputs the U2 signal and the U2 signal; and an offset adjusting unit 83 that adjusts the offset of the U2 signal and the V2 signal and outputs the U signal and the V signal. It has.

In this case, the RGB-C conversion unit 81 performs RGB-UV conversion processing using the following Expression 7 and Expression 8. Further, the gain adjustment unit 82 performs gain adjustment using the following Expression 9 and Expression 10. Further, the offset adjustment unit 83 performs offset adjustment using the following equations 11 and 12. In the present embodiment, these arithmetic processes are performed based on a control signal from the control unit 9. The coefficient a ₂₁ , coefficient a ₂₂ , coefficient a ₂₃ , coefficient a ₃₁ , coefficient a ₃₂ , coefficient a ₃₃ , U gain K _U , V gain K _V , U offset value U _off , and V offset value V _off are Are stored in the coefficient storage unit 11.
_{U1 = a 21 × R + a} 22 × G + a 23 × B ( Formula 7)
_{V1 = a 31 × R + a} 32 × G + a 33 × B ( Formula 8)
U2 = K _U × U1 (Formula 9)
V2 = K _V × V1 (Formula 10)
U = U2 + U _off (Formula 11)
V = V2 + V _off (Formula 12)

  FIG. 6 is a block diagram illustrating an example of the flicker correction unit 10. As shown in FIG. 6, the flicker correction unit 10 has a frequency mode detection unit 101 that detects the current frequency mode, and writes the detected frequency mode in the frequency mode storage unit 12 or is stored in the frequency mode storage unit 12. A frequency mode read / write unit 102 that reads the frequency mode, a frequency mode determination unit 103 that performs a determination process whether the detected current frequency mode matches the frequency mode read and set from the frequency mode storage unit 12, and a frequency A shutter value adjustment unit 104 that adjusts the shutter value of the image sensor 2 based on the mode is provided.

  In the digital camera 1 of the present embodiment, two frequency modes (50 Hz mode and 60 Hz mode) are prepared. The frequency mode detection unit 101 detects whether the power supply frequency is 50 Hz or 60 Hz, that is, whether the frequency mode is the 50 Hz mode or the 60 Hz mode. Further, the shutter value adjustment unit 104 refers to this frequency mode and adjusts the shutter value of the electronic shutter of the image sensor 2 according to the power supply frequency.

  For example, when a fluorescent lamp is used as the light source and the frequency of the commercial power supply is 50 Hz, the shutter value of the electronic shutter is set to an integral multiple of 1/100 second. Further, when the frequency of the commercial power supply is 60 Hz, the shutter value of the electronic shutter is set to an integral multiple of 1/120 seconds. Thereby, when the frequency mode of the digital camera 1 is the 50 Hz mode, the image sensor 2 operates at a shutter value (an integral multiple of 1/100 seconds) corresponding to a power frequency of 50 Hz (commercial power frequency in the East Japan area). . On the other hand, when the frequency mode of the digital camera 1 is the 60 Hz mode, the image sensor 2 operates at a shutter value (an integral multiple of 1/120 seconds) corresponding to a power frequency of 60 Hz (commercial power frequency in the West Japan area). The above frequency mode is also called flicker mode.

  The operation of the digital camera 1 configured as described above will be described with reference to FIG. Here, an example of a power-on / off sequence related to flicker correction will be described.

  FIG. 7 is a flowchart for explaining the operation of the digital camera 1. As shown in FIG. 7, when using the digital camera 1 of the present embodiment, first, the digital camera 1 is turned on (S1). In the present embodiment, when the power of the digital camera 1 is turned on, the power of the image sensor 2 is also turned on. Therefore, it can be said that the power-on operation of the digital camera 1 is a power-on operation of the image sensor 2. When the power source of the digital camera 1 is turned on (when the power source of the image sensor 2 is turned on), the signal photoelectrically converted by the image sensor 2 is converted into a CDS unit 3, an AGC unit 4, an AD converter unit 5, and a white balance adjustment unit 6. Are input to the Y signal processing unit 7, the C signal processing unit 8, and the control unit 9.

  When the power-on operation is performed, the frequency mode read / write unit 102 of the flicker correction unit 10 performs a process of reading the frequency mode written in the frequency mode storage unit 12 (S2). Then, the shutter value adjustment unit 104 of the flicker correction unit 10 sets the frequency mode of the image sensor 2 to the frequency mode read from the frequency mode storage unit 12 (S3). Specifically, referring to the read frequency mode, the shutter value of the electronic shutter of the image sensor 2 is set to the shutter value corresponding to the frequency mode. For example, when the read frequency mode is the 50 Hz mode, the shutter value of the electronic shutter of the image sensor 2 is set to an integral multiple of 1/100 seconds. When the read frequency mode is the 60 Hz mode, the shutter value of the electronic shutter of the image sensor 2 is set to an integral multiple of 1/120 seconds. In this way, the shutter value of the electronic shutter of the image sensor 2 is set with reference to the frequency mode when the digital camera 1 was used last time.

  Next, the frequency mode detection unit 101 of the flicker correction unit 10 detects the current power supply frequency (S4). Specifically, it is detected whether the current power supply frequency is 50 Hz or 60 Hz. Then, the frequency mode determination unit 103 of the flicker correction unit 10 performs frequency mode determination processing (S5). Specifically, a process for determining whether or not the detected current frequency mode matches the frequency mode read and set from the frequency mode storage unit 12 is performed.

  As a result of such frequency mode determination processing, if it is determined that the detected current frequency mode does not match the frequency mode read and set from the frequency mode storage unit 12, the frequency mode is reset. (S6). Specifically, the shutter value of the electronic shutter of the image sensor 2 is set to a shutter value corresponding to the detected frequency mode. For example, when the detected frequency mode is the 50 Hz mode, the shutter value of the electronic shutter of the image sensor 2 is set to an integer multiple of 1/100 seconds. When the detected frequency mode is the 60 Hz mode, the shutter value of the electronic shutter of the image sensor 2 is set to an integral multiple of 1/120 seconds. Thereafter, the process proceeds to a steady state operation of the image sensor 2 (for example, camera image capturing) (S7).

  On the other hand, if it is determined that the detected current frequency mode matches the frequency mode read and set from the frequency mode storage unit 12 as a result of the frequency mode determination process as described above, the frequency mode is reset. Without performing the above, the operation proceeds to the steady state operation of the image sensor 2 (S7). In this way, the power supply for flicker correction is performed.

  When the shooting of the camera image is completed, the frequency mode writing process is performed before the digital camera 1 is turned off (S8). Specifically, the frequency mode read / write unit 102 of the flicker correction unit 10 performs a process of writing the current power supply frequency mode in the frequency mode storage unit 12. At this time, the frequency mode written in the frequency mode storage unit 12 is referred to when the digital camera 1 is activated next time.

  Then, after the frequency mode writing process is completed, the digital camera 1 is turned off (S9). In the present embodiment, when the digital camera 1 is turned off, the image pickup device 2 is also turned off. Therefore, it can be said that the power-off operation of the digital camera 1 is a power-off operation of the image sensor 2. In this way, the power supply for flicker correction is turned off.

  According to the digital camera 1 of the embodiment of the present invention, the frequency mode storage unit 12 that stores the frequency mode before the power-off operation, and the shutter value is adjusted during the power-on operation based on the stored frequency mode. By providing the flicker correction unit 10, it is possible to shorten the time from when the power is turned on until the flicker correction process is completed without complicating the circuit configuration and control.

  That is, in this embodiment, the frequency mode before the power-off operation of the image sensor 2 is stored, and the shutter value of the image sensor 2 is set using the frequency mode when the image sensor 2 is turned on. That is, the frequency mode when the digital camera 1 is turned on (when the image sensor 2 is turned on) is set to the frequency mode when the digital camera 1 was used last time. As described above, by using the frequency mode when the digital camera 1 was used last time, flicker correction (shutter value adjustment) can be performed in a short time after the power is turned on. Can be shortened.

  In the conventional digital camera, the frequency mode at the time of starting the digital camera is fixed to a predetermined preset value (50 Hz mode or 60 Hz mode). Therefore, even if the power supply frequency at the time of power-off operation and at the time of restart is the same, if the power supply frequency at the time of start-up (at the time of restart) is different from the preset value, frequency mode detection processing is always required There is a problem that it takes a long time (convergence time) from when the power is turned on to when the camera shifts to a steady state.

  On the other hand, in the digital camera 1 of the present embodiment, the frequency mode at the start of the digital camera 1 is not fixed to a predetermined preset value (50 Hz mode or 60 Hz mode). That is, in the present embodiment, before the power-off operation of the digital camera 1, the currently used frequency mode is written in the frequency mode storage unit 12, and then the operation of the digital camera 1 is terminated. When the digital camera 1 is restarted, the digital camera 1 is started with reference to the frequency mode written when the power is turned off. Therefore, when the frequency of the commercial power supply at the time of power-off operation and at the time of restarting is the same, the frequency mode detection process becomes unnecessary, and the convergence time for flicker correction can be shortened. This makes it possible to obtain a moving image in which flicker is canceled immediately after the power is turned on.

  For example, even if the preset value of the frequency mode when the digital camera 1 is turned on last time is the 50 Hz mode, when the digital camera 1 is used in the West Japan area, the current frequency mode (60 Hz mode) is stored. The Then, when the digital camera 1 is turned on next time, the shutter value of the image sensor 2 is set with reference to the frequency mode (60 Hz mode). In such a case, by referring to the frequency mode (60 Hz mode) when the digital camera 1 was used last time, the flicker correction is performed after the power is turned on and before the frequency mode detection (flicker detection) is performed. (Shutter value adjustment) can be performed, and the time from when the power is turned on until the flicker correction processing is completed can be shortened.

  In the present embodiment, the shutter value of the image sensor 2 is set to an integral multiple of 1 / 2f. For example, when the stored frequency f is 50 Hz, the shutter value of the image sensor 2 is set to an integer multiple of 1/100 second. When the stored frequency f is 60 Hz, the shutter value of the image sensor 2 is set to an integral multiple of 1/120 seconds. Thus, by associating the power supply frequency of the illumination (fluorescent lamp or the like) with the shutter value of the image sensor 2 (image sensor such as CCD or CMOS), a high-quality video signal from which flicker is removed can be obtained.

  The embodiments of the present invention have been described above by way of example, but the scope of the present invention is not limited to these embodiments, and can be changed or modified according to the purpose within the scope of the claims. is there.

  As described above, the digital camera device according to the present invention has an effect of shortening the time from when the power is turned on until the flicker correction processing is completed, and is useful as an electronic shutter digital camera or the like. .

1 is a block diagram of a digital camera according to an embodiment of the present invention. Explanatory drawing of the color filter arrangement | sequence of the image pick-up element in embodiment of this invention The block diagram of the white balance adjustment part in embodiment of this invention Block diagram of the Y signal processing unit in the embodiment of the present invention The block diagram of the C signal processing part in an embodiment of the invention The block diagram of the flicker correction | amendment part in embodiment of this invention FIG. 3 is a flowchart for explaining the operation of the digital camera in the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Digital camera 2 Image pick-up element 10 Flicker correction | amendment part 12 Frequency mode memory | storage part 101 Frequency mode detection part 102 Frequency mode read / write part 103 Frequency mode determination part 104 Shutter value adjustment part

Claims (4)

Imaging means;
Storage means for storing a frequency mode indicating a power supply frequency f before a power-off operation of the imaging means;
A flicker correction unit that adjusts a shutter value of the imaging unit when a power-on operation of the imaging unit is performed based on the frequency mode stored in the storage unit;
A digital camera device comprising: The flicker correction means includes
2. The digital camera device according to claim 1, wherein a shutter value of the image pickup unit is set to an integral multiple of 1 / 2f. Before the power-off operation of the imaging means, the frequency mode indicating the power frequency f is stored,
A flicker correction method for a digital camera apparatus, comprising: adjusting a shutter value of the imaging unit based on the stored frequency mode when the imaging unit is powered on.   4. The flicker correction method for a digital camera device according to claim 3, wherein a shutter value of the image pickup unit is set to an integral multiple of 1 / 2f.

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