JP2008098469A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a transistor using element isolation technique such as STI, current characteristics of the transistor being superior and characteristic variance depending upon its layout being suppressed. <P>SOLUTION: A semiconductor device has an active region 2 of the transistor formed on a surface portion of a semiconductor substrate 1 and an element isolation region 3 in a periphery of the active region 2, a gate electrode 6 formed on the active region 2, a recess region 4 formed by digging from a surface of the active region 2 on the boundary with the element isolation region 3, and an insulating film buried in the recess region 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and relates to a technique for improving the capability of a transistor.

  In recent years, it has been found that as the semiconductor process becomes finer, the layout pattern and arrangement method of circuit elements greatly affect the performance of the circuit. In particular, in a transistor using an element isolation technique such as STI (Shallow Trench Isolation), the carrier mobility and threshold voltage in the channel change due to mechanical stress applied from the STI to the active region of the transistor, and the transistor characteristics are changed. It is known that it fluctuates greatly (for example, see Non-Patent Document 1).

  FIG. 15 is a schematic view of a cross-sectional view and a plan view schematically showing the structure of a transistor using a conventional STI. An element isolation region 22 is formed on the surface of the semiconductor substrate 21. That is, a groove for element isolation is formed from the surface of the semiconductor substrate 21, and an element isolation insulating film such as an oxide film is embedded in the groove. At that time, heat treatment at about 1000 ° C. is performed for several tens of minutes in order to bury the insulating film and suppress defects. Thereafter, the semiconductor surface is planarized by CMP (chemical mechanical polishing), and the element isolation region 22 is formed. By desired ion implantation in the active region 23 surrounded by the element isolation region 22, a p-type well region is formed in the n-channel transistor region, and an n-type well region is formed in the p-channel transistor region. Next, a gate insulating film is formed by thermally oxidizing the surface of the active region 23. After the formation of the gate insulating film, the gate electrode 24 is formed by depositing a polysilicon film and resist patterning. Thereafter, the extension region 25 is formed by performing desired ion implantation. Next, an oxide film or a nitride film is deposited so as to cover the gate electrode 24, and a sidewall spacer 26 is formed on the side wall of the gate electrode 24 by anisotropic etching. After the formation of the sidewall spacers 26, source / drain regions 27 are formed by heat treatment for desired ion implantation and impurity activation. Next, desired regions on the gate electrode 24 and the source / drain regions 27 are silicided to form silicide regions. Thereafter, a nitride film is deposited as a contact etching stopper film so as to cover the entire transistor.

  In this case, mechanical stress is generated in the interface region between the element isolation region 22 and the active region 23 in the process of forming the element isolation region 22. This stress causes strain to the channel region 28 of the transistor, and changes the mobility and threshold voltage of electrons and holes. Further, the strain generated in the channel region 28 strongly depends on the distance in the channel direction from the end of the gate electrode 24 to the element isolation region 22, and the characteristics of the transistor greatly vary depending on the layout of the active region 23.

  In recent years, methods for improving the performance of transistors using mechanical stress have been reported. Conventionally, miniaturization has been mainly promoted to improve current characteristics of transistors. However, improvement in current characteristics due to miniaturization is approaching the limit due to a decrease in carrier mobility due to an increase in parasitic resistance and an increase in substrate concentration.

Therefore, as an alternative to miniaturization, there is a method for improving carrier mobility by applying a tensile stress to the channel of an n-channel transistor by depositing a stress control film such as a nitride film having a tensile stress on the transistor. It is known (see, for example, Patent Document 1).
JP 2003-60076 (page 5-6, FIG. 1-6) G. Scott, et.al., IEDM digest, pp.91, 1999.

  In a transistor using an element isolation technique such as STI, mechanical stress is generated in an active region of the transistor by a process step. Factors that cause mechanical stress are as follows.

  One is due to the difference in thermal expansion coefficient between the buried oxide film in the element isolation region and the silicon substrate in the heat treatment in the process of forming the element isolation region. In the heat-cooling process of the heat treatment, mechanical stress is generated at the interface between the element isolation region and the active region due to the difference in the thermal expansion / contraction rate of the material.

  The other is due to volume expansion at the silicon / oxide interface due to thermal oxidation of silicon in a gate oxidation process or the like. The oxidized species diffused by the thermal oxidation react at the silicon / oxide film interface, and an oxide film is formed while the volume expands about 2.3 times. The formed oxide film also applies compressive stress to silicon while pushing up the already existing oxide film. This becomes a compressive strain of the channel and becomes a factor of STI stress dependency.

  Since these characteristic changes such as STI stress vary depending on the shape and size of the active region, not only the transistor characteristics are greatly deteriorated by the layout, but also the SPICE simulation accuracy may be deteriorated.

  In recent years, methods using stress have been reported as methods for improving transistor performance other than miniaturization. For example, in an n-channel transistor, there is a method in which a nitride film having tensile stress is formed so as to cover the transistor, and tensile strain is generated in the channel to improve electron mobility.

  However, in these methods, even if the performance of the transistor is improved as a whole, characteristic variations due to layout such as STI stress dependency are still not solved.

  The present invention was created in view of such circumstances, and in a transistor using an element isolation technique such as STI, a semiconductor device having excellent transistor current characteristics and suppressing variation in characteristics due to layout, and a semiconductor device thereof The object is to provide a manufacturing method.

A semiconductor device according to the present invention includes:
An active region of a transistor formed on a surface portion of a semiconductor substrate and an element isolation region around the active region;
A gate electrode formed on the active region;
A recess region formed by digging the active region from the surface at the boundary with the element isolation region;
And an insulating film embedded in the recess region.

  In this configuration, a recess is a recess. In a transistor having an active region surrounded by an element isolation region, a recess region is formed by digging the active region from the surface at the boundary with the element isolation region, and an insulating film is embedded in the recess region. By removing the active region at the boundary with the element isolation region, mechanical stress applied to the active region from the element isolation region is released, and distortion applied to the channel of the transistor can be reduced. The release of the mechanical stress from the element isolation region means that the mechanical stress does not vary greatly even if the distance between the channel region and the element isolation region changes depending on the transistor layout. For this reason, variation in transistor characteristics due to layout is also suppressed.

  In the semiconductor device having the above structure, when the transistor is an n-channel transistor, compressive strain is generated in the active region when the thermal expansion coefficient of the insulating film embedded in the element isolation region is smaller than that of the semiconductor substrate. . In an n-channel transistor, it is possible to reduce the compressive strain applied to the channel of the transistor by removing the active region at the boundary with the element isolation region to form a recess region. That is, in the n-channel transistor, the electron mobility can be improved by reducing the compressive strain applied to the channel.

  In the semiconductor device configured as the n-channel transistor, there is a mode in which the insulating film embedded in the recess region is a nitride film having tensile stress. In an n-channel transistor, a nitride film having a tensile stress is embedded in a recess region formed by digging an active region at the boundary with an element isolation region, and the channel of the n-channel transistor is caused by the tensile stress of the nitride film. Further, since tensile strain occurs, further improvement in electron mobility is expected.

  In the semiconductor device having the above structure, when the transistor is a p-channel transistor, the tensile strain applied to the channel of the transistor is reduced by removing the active region at the boundary with the element isolation region to form a recess region. Is possible. That is, in a p-channel transistor, hole mobility can be improved by reducing tensile strain applied to the channel.

  In the semiconductor device configured as the p-channel transistor, there is an aspect in which the insulating film embedded in the recess region is a nitride film having a compressive stress. In the p-channel transistor, the compressive stress in the channel of the p-channel transistor is increased by the compressive stress of the nitride film embedded in the recess region, so that the hole mobility can be further improved.

  In the above configuration, the recess region may be formed by removing an overlapping region between the active region and the gate electrode. The outer periphery of the active region is surrounded by the element isolation region. In forming the recess region in the active region at the boundary with the element isolation region, in addition to the aspect of forming the recess region continuous over the entire periphery of the active region, In order to secure a larger effective channel width, the recess region may not be formed in a part of the entire circumference of the active region. In other words, if the recess region is formed by removing the region where the active region overlaps with the gate electrode, a larger effective channel width of the transistor is secured, and improvement of the current characteristics of the transistor is expected.

  In the above structure, the transistor in which the recess region is not formed may be partially included.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a transistor formed on a semiconductor substrate,
Forming a trench in an element isolation region by etching in the semiconductor substrate;
Embedding an insulating film in the groove;
Forming the element isolation region by performing a high-temperature heat treatment after embedding the insulating film;
Forming a recess region by selectively etching at least a part of the active region at a boundary with the element isolation region;
Forming a gate electrode on the active region;
Embedding an insulating film in the recess region;
Forming a source region and a drain region in the active region.

  In this semiconductor device manufacturing method, mechanical stress is generated from the element isolation region to the active region in the step of forming the element isolation region by embedding the insulating film in the trench and subjecting the embedded insulating film to a high temperature heat treatment. However, it is possible to release the stress by forming a recess region. Therefore, a semiconductor device in which fluctuations in transistor characteristics due to layout are suppressed can be manufactured as expected.

  In the method of manufacturing a semiconductor device described above, in the step of embedding an insulating film in the recess region, in the n-channel transistor, a nitride film having a tensile stress is embedded as the insulating film.

  In the method for manufacturing a semiconductor device, in the step of embedding an insulating film in the recess region, in the p-channel transistor, a nitride film having a compressive stress is embedded as the insulating film.

  According to the present invention, in a transistor using an element isolation technique such as STI, the recess region is formed by digging the active region at the boundary with the element isolation region from the surface, thereby controlling the distortion applied to the channel and the transistor current. A semiconductor device in which characteristics are improved and variation in characteristics of transistors due to layout is suppressed can be realized.

(Embodiment 1)
FIG. 1 is a cross-sectional view and a schematic plan view of a semiconductor device according to Embodiment 1 of the present invention.

  As shown in FIG. 1, an active region 2 and an element isolation region 3 for forming a transistor are formed in a surface region of a semiconductor substrate 1, and an element isolation insulating film is embedded in the element isolation region 3. In addition, a recess region 4 is formed in a state where it is dug down from the surface of the active region 2 in the boundary region with the element isolation region 3. An insulating film is embedded in the recess region 4. The insulating film is embedded in a gate oxidation process or a side wall spacer formation process. As shown in the schematic plan view, the active region 2 is surrounded by the element isolation region 3, and the recess region 4 is formed in the boundary region with the element isolation region 3 over the entire periphery of the active region 2. The recess area 4 has a rectangular annular shape.

  When the recess region 4 is formed as described above, a change occurs in the mechanical stress applied to the active region 2, and this was analyzed by process simulation. The state of the simulation analysis is shown in FIGS.

  FIG. 2A shows a conventional configuration in which no recess region is formed. FIG. 2B shows a case where the recess region 4 is formed by digging a region up to a distance of 5 nm in the direction from the boundary with the element isolation region 3 toward the active region 2. FIG. 2C shows a form in which the recess region 4 is wider than FIG. 2B and the region is dug down to a distance of 50 nm from the boundary. The depth of the recess region 4 is the same, and the simulation was performed assuming a case of 50 nm.

  FIG. 3 shows a simulation result of the mechanical stress applied to the active region 2 with respect to the width of the recess region 4. The horizontal axis indicates the distance from the center of the active region 2, and the vertical axis indicates the stress on the surface of the active region 2. Further, the minus sign on the vertical axis indicates compressive stress, and the plus sign indicates tensile stress.

  FIG. 3 shows that the compressive stress is reduced by 50 MPa in the result of the form (b) in which the recess width is set to 5 nm, compared to the conventional form (a) in which the recess region 4 is not formed. Further, in the embodiment (c) in which the recess width was set to 50 nm, a reduction in compressive stress of 70 MPa was observed. From this simulation result, by forming the recess region 4 in the active region 2 in the boundary region with the element isolation region 3, the compressive stress applied to the active region 2 is released, and the width of the recess region 4 is increased. It was confirmed that the compressive stress decreased. For this reason, particularly in an n-channel transistor, the current characteristics are expected to be improved by forming the recess region 4.

  FIG. 4 shows a simulation result of mechanical stress applied to the active region 2 with respect to the depth of the recess region 4. The horizontal axis indicates the distance from the center of the active region 2, and the vertical axis indicates the stress on the surface of the active region 2. The simulation results at the depth of each recess region 4 are shown in FIGS. (A) to (d), (a) is the result of a conventional configuration in which the recess region 4 is not formed, and (b) to (d) are It is a simulation result in the case where the depth of the recess region 4 is 10 nm, 30 nm, and 100 nm, respectively.

  As shown in FIG. 4, the compressive stress at the center of the active region 2 at each recess depth (b), (c), (d) is 10 MPa, 40 MPa, and 130 MPa as compared to the conventional configuration (a). A decrease was seen. From this simulation result, it was confirmed that the compressive stress applied to the active region 2 was reduced according to the depth of the recess region 4 dug from the surface of the active region 2. Further, when the depth of the recess region 4 is about 10 nm, the effect of reducing the compressive stress is small, and the depth of the recess region 4 is desirably about 30 nm or more for improving the transistor performance.

  Next, the effect of the first embodiment was analyzed by simulation when the layout of the active region was changed.

  FIGS. 5A and 5B are schematic views showing the form of a semiconductor device subjected to simulation analysis. FIG. 5A shows a conventional configuration in which the recess region 4 is not formed, and FIG. 5B shows the recess region 4 in the first embodiment. The recess region 4 has a width of 50 nm and a depth of 50 nm. It is a form in the case of. In the form shown in FIGS. 5A and 5B, the mechanical stress applied to the active region 2 was analyzed by simulation with respect to the length of the active region 2 sandwiched between the element isolation regions 3.

  FIG. 6 shows a stress simulation result with respect to the length of the active region. The horizontal axis indicates the length of the active region 2, and the vertical axis indicates the stress at the center of the active region 2. (A) of the figure is the simulation result in the conventional form, (b) is the simulation result in the form having the recess region 4 which is the first embodiment, and the forms of FIGS. 5 (a) and 5 (b), respectively. It corresponds.

  As shown in FIG. 6, the compressive stress at the center of the active region 2 increases as the active region length decreases in both forms. Moreover, the change of the compressive stress of the first embodiment is about half of the change of the compressive stress of the conventional form, and it has been confirmed that the layout dependence of the active region is greatly suppressed.

  Next, a method for manufacturing the semiconductor device in the first embodiment of the present invention will be described. 7A to 7D are cross-sectional views showing the steps for manufacturing the semiconductor device of the first embodiment.

  In the step shown in FIG. 7A, an element isolation groove is formed from the surface of the semiconductor substrate 1, and an element isolation insulating film such as an oxide film is embedded in the element isolation groove. At that time, heat treatment at about 1000 ° C. is performed for several tens of minutes in order to embed the insulating film and suppress defects. Thereafter, the semiconductor surface is planarized by CMP (Chemical Mechanical Polishing), and the element isolation region 3 is formed.

  Next, in the step shown in FIG. 7B, a resist film 5 is formed on the semiconductor substrate 1, and patterning by lithography is performed using the resist film 5 as a mask to determine an arbitrary recess region 4.

Next, in the step shown in FIG. 7C, the active region 2 in the recess region 4 is selectively removed by anisotropic etching. The recess region 4 is inside the active region 2 at the boundary region with the element isolation region 3. At this time, the recess region 4 preferably has a width of 5 nm or more from the boundary with the element isolation region 3 to the active region 2 side. The etching depth is preferably set to 30 nm or more. Thereafter, by performing desired ion implantation with an implantation energy of about 1 to 10 KeV and an implantation amount of about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² in the active region 2, a p-type well region is formed in the n-channel transistor region. And an n-type well region is formed in the p-channel transistor region.

Next, in the step shown in FIG. 7D, a gate insulating film is formed by thermally oxidizing the surface of the active region 2. After the formation of the gate insulating film, the gate electrode 6 is formed by depositing a polysilicon film and resist patterning. Thereafter, using the gate electrode 6 as a mask, an n-type impurity such as arsenic is used for the n-channel transistor formation region, and a p-type impurity such as boron is used for the implantation energy of about 1 to 10 KeV for the p-channel transistor formation region. The extension region 7 is formed by ion implantation with an implantation amount of about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . Next, an oxide film or a nitride film is deposited so as to cover the gate electrode 6. At this time, an oxide film or a nitride film is also embedded in the recess region 4. Sidewall spacers 8 are formed on the side walls of the gate electrode 6 by performing anisotropic etching on the oxide film or nitride film achieved on the gate electrode 6. Thereafter, using the gate electrode 6 and the sidewall spacer 8 as a mask, an n-type impurity such as arsenic is used for the n-channel transistor formation region, and a p-type impurity such as boron is used for the p-channel transistor formation region. The source / drain regions 9 are formed by performing ion implantation at an implantation energy of about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² and performing heat treatment for impurity activation. Next, a silicide layer such as NiSi ₂ or CoSi ₂ is formed on the surfaces of the gate electrode 6 and the active region 2. Next, a nitride film 10 is deposited as a contact etching stopper film covering the entire transistor.

  As shown in the schematic plan view of FIG. 7D, when the recess region 4 is formed over the entire periphery of the active region 2, the gate electrode 6 may be formed across the recess region 4. In this case, the reduction of the compressive stress due to the formation of the recess region 4 is effective not only for the compressive stress in the channel direction but also for the compressive stress in the direction of the channel width W.

(Embodiment 2)
FIG. 8 is a sectional view of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment has active regions 2n and 2p and an element isolation region 3 on a semiconductor substrate 1, and an n-channel transistor region 13 and a p-channel transistor region 14. Recess regions 4n and 4p formed by digging down from the surfaces of the active regions 2n and 2p in the boundary region with the element isolation region 3 are provided.

  The difference from the first embodiment is that a nitride film 11 having a tensile stress is buried in a recess region 4n where the active region 2n of the n-channel transistor is dug down, and the active region 2p of the p-channel transistor is dug down. This is that a nitride film 12 having a compressive stress is embedded in the recess region 4p.

  A change in mechanical stress generated by embedding the nitride film 11 having tensile stress in the recess region 4n was analyzed by process simulation.

  9A and 9B, the conventional embodiment (a) in which the recess region 4n is not formed, the embodiment 1 (b) in which the recess region 4n is formed, and the nitride film 11 having the tensile stress is formed by forming the recess region 4n. The simulation result of the mechanical stress concerning the active region 2n in three forms of Embodiment 2 (c) is shown. The horizontal axis indicates the distance from the center of the active region 2n, and the vertical axis indicates the stress on the surface of the active region 2n. Further, the minus sign on the vertical axis indicates compressive stress, and the plus sign indicates tensile stress.

  As shown in FIG. 9, the stress applied to the active region 2n is a compressive stress in the conventional embodiment (a) and the embodiment 1 (b), whereas the nitride film 11 having a tensile stress in the recess region 4n. In the embodiment 2 (c) in which is embedded, the result is reversed to the tensile stress. From this, in the n-channel transistor, a significant improvement in transistor current characteristics can be expected by embedding the nitride film 11 having tensile stress in the recess region 4n. The same effect can be obtained in a p-channel transistor. In a p-channel transistor, the hole mobility increases when compressive stress is applied to the channel region. Therefore, the transistor current characteristics can be improved by embedding the nitride film 12 having compressive stress in the recess region 4p. Become.

  From the above, the nitride film 11 having tensile stress is embedded in the recess region 4n of the n-channel transistor region, and the nitride film 12 having compressive stress is embedded in the recess region 4p of the p-channel transistor region. Improvement in current characteristics of both channel-type and p-channel type transistors can be expected, and the performance of the entire circuit characteristics can be improved. In particular, a large performance improvement can be obtained in an n-channel transistor.

  FIG. 10 is a cross-sectional view showing a modification of the semiconductor device according to the second embodiment. As shown in FIG. 10, the nitride films 11 and 12 embedded in the recess regions 4 n and 4 p may be formed across the element isolation region 3. An increase in the area of the formed nitride film can be expected to increase the effects of tensile stress and compressive stress.

  FIG. 11 is a cross-sectional view showing a modification of the semiconductor device according to the second embodiment. As shown in FIG. 11, the recess region 4n and the nitride film 11 having tensile stress are formed only in the n-channel transistor region 13, and no recess region is formed in the p-channel transistor region.

  In this embodiment, the step of removing the nitride film having tensile stress on the p-channel transistor region and the step of newly depositing the nitride film having compressive stress can be omitted. Thus, in this modification, the process manufacturing process can be simplified, and a semiconductor device that can improve the current characteristics of the n-channel transistor can be provided.

  12A to 12D are cross-sectional views illustrating the steps for manufacturing the semiconductor device of the second embodiment.

  In FIG. 12A, the steps up to the formation of the element isolation region 3, the step of determining the recess regions 4n and 4p by lithography, and the step of removing the active region of the recess regions 4n and 4p by anisotropic etching are performed. This is the same as the method for manufacturing the semiconductor device.

  In the step shown in FIG. 12B, a nitride film 11 having a tensile stress is deposited in the n-channel transistor region 13 and buried in the recess region 4n. Next, the nitride film 11 having tensile stress deposited on the p-channel transistor region 14 is removed by lithography, and a nitride film 12 having compressive stress is deposited on the p-channel transistor region 14 and buried in the recess region 4p.

  The nitride film 11 having a tensile stress is an insulating film such as a silicon nitride film having a tensile stress of about 0.1 to several GPa, and is formed by a plasma CVD method under a low frequency power condition of about 400 W, for example. The nitride film 12 having compressive stress can be obtained by increasing the amount of hydrogen introduced by plasma CVD or the like. The deposited film thickness of the nitride films 11 and 12 is preferably about 30 nm to several hundreds of nm so as to sufficiently fill the recess regions 4n and 4p.

  Next, a resist film 15 is formed on the deposited nitride films 11 and 12, and patterning by lithography is performed using the resist film 15 as a mask, and the nitride film 11 on the active regions 2n and 2p excluding the recess regions 4n and 4p. , 12 are removed by etching.

In the step shown in FIG. 12C, after the nitride films 11 and 12 are etched, an implantation energy of about 1 to 10 KeV is applied to the active regions 2n and 2p to a desired level of about 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . By performing ion implantation, a p-type well region is formed in the n-channel transistor region 13 and an n-type well region is formed in the p-channel transistor region 14. Next, the gate insulating film 16 is formed by thermally oxidizing the surfaces of the active regions 2n and 2p.

  In FIG. 12D, the formation of the gate electrode 6, the sidewall spacer 8, and the source / drain region 9 after the formation of the gate insulating film is the same as in the method for manufacturing the semiconductor device of the first embodiment.

(Embodiment 3)
FIG. 13 is a sectional view and a schematic plan view of a semiconductor device according to the third embodiment of the present invention.

  In the present embodiment, the recess region 4 is formed in the active region 2, but the recess region 4 is not formed in a region where the active region 2 overlaps the gate electrode 6. In the case of the first embodiment, as shown in FIG. 1, since a part of the channel region of the transistor overlaps with the recess region 4, the effective channel width W of the transistor is reduced by the width of the recess region 4. For this reason, the channel width W of the finished dimension is reduced with respect to the mask dimension, and the current characteristics of the transistor are deteriorated. In contrast, in the present embodiment, the recess region 4 is set by removing the overlap region between the active region 2 and the gate electrode 6, so that the current characteristics due to the effective decrease in the channel width W do not deteriorate. Further, the current characteristics of the transistor can be improved by utilizing mechanical stress.

  14A and 14B are a cross-sectional view and a plan view schematically illustrating a modification of the semiconductor device in the third embodiment. As shown in FIG. 14, the recess region 4 is formed in a boundary region with the element isolation region 3 in the channel direction of the transistor. In this semiconductor device, when the recess region 4 is set by patterning by lithography, patterning is performed with a simple shape, so that process manufacturing can be facilitated. Therefore, the process manufacturing is simple, and the current characteristics of the transistor using mechanical stress can be improved.

  The semiconductor device manufacturing method in the third embodiment is the same as the semiconductor manufacturing method in the first embodiment, except that the layout in which the recess region 4 is set is different.

  The technology of the present invention is effective for realizing a semiconductor device having a transistor using an element isolation technique such as STI, which has excellent current characteristics of the transistor and suppresses characteristic variation due to layout.

Sectional drawing and plane schematic diagram of the semiconductor device in Embodiment 1 of this invention Sectional drawing which shows the structure which performed stress simulation analysis of the recess area width dependence for verifying the effect of this invention The graph which shows the stress simulation analysis result of the recess area width dependence for verifying the effect of this invention The graph which shows the stress simulation analysis result of the depth dependence of a recess area | region for verifying the effect of this invention Sectional drawing which shows the structure which performed the stress simulation analysis of the active region length dependence for verifying the effect of this invention The graph which shows the stress simulation analysis result of the active region length dependence for verifying the effect of this invention Sectional drawing which shows the process of manufacturing the semiconductor device of Embodiment 1 of this invention. Sectional drawing of the semiconductor device in Embodiment 2 of this invention The graph which shows the stress simulation analysis result for verifying the effect of Embodiment 2 of this invention Sectional drawing which shows the modification of the semiconductor device in Embodiment 2 of this invention Sectional drawing which shows the modification of the semiconductor device in Embodiment 2 of this invention Sectional drawing which shows the process of manufacturing the semiconductor device of Embodiment 2 of this invention. Sectional drawing and plane schematic diagram of the semiconductor device in Embodiment 3 of this invention Sectional drawing and plane schematic diagram which show the modification of the semiconductor device in Embodiment 3 of this invention Sectional drawing and plane schematic diagram explaining the semiconductor device by a prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2,2n, 2p Active region 3 Element isolation region 4,4n, 4p Recess region 5 Resist film 6 Gate electrode 7 Extension region 8 Side wall spacer 9 Source / drain region 10 Nitride film 11 Nitride film with tensile stress 12 Nitride film having compressive stress 13 n-channel transistor region 14 p-channel transistor region 15 resist film 16 gate oxide film

Claims (10)

An active region of a transistor formed on a surface portion of a semiconductor substrate and an element isolation region around the active region;
A gate electrode formed on the active region;
A recess region formed by digging the active region from the surface at the boundary with the element isolation region;
A semiconductor device comprising an insulating film embedded in the recess region.   The semiconductor device according to claim 1, wherein the transistor is an n-channel transistor.   The semiconductor device according to claim 2, wherein the insulating film embedded in the recess region is a nitride film having tensile stress.   The semiconductor device according to claim 1, wherein the transistor is a p-channel transistor.   The semiconductor device according to claim 4, wherein the insulating film embedded in the recess region is a nitride film having compressive stress.   The semiconductor device according to claim 1, wherein the recess region is formed by removing an overlapping region between the active region and the gate electrode.   The semiconductor device according to claim 1, further comprising a part of the transistor in which the recess region is not formed. A method of manufacturing a semiconductor device having a transistor formed on a semiconductor substrate,
Forming a trench in an element isolation region by etching in the semiconductor substrate;
Embedding an insulating film in the groove;
Forming the element isolation region by performing a high-temperature heat treatment after embedding the insulating film;
Forming a recess region by selectively etching at least a part of the active region at a boundary with the element isolation region;
Forming a gate electrode on the active region;
Embedding an insulating film in the recess region;
Forming a source region and a drain region in the active region.   9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of embedding an insulating film in the recess region, a nitride film having a tensile stress is embedded as the insulating film in the n-channel transistor.   9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of embedding an insulating film in the recess region, a nitride film having a compressive stress is embedded as the insulating film in the p-channel transistor.

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