JP2008096469A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To satisfactorily conduct an alignment treatment in a liquid crystal display device. <P>SOLUTION: Since slits are installed on a transparent electrode which is an upper electrode layer, they produce shadow areas for rubbing treatment on level difference sections in the alignment treatment, and sometimes bring about deterioration of display quality, in an FFS mode liquid crystal display device. The relation between a reciprocal 1/θ<SB>1</SB>of a tilt angle θ<SB>1</SB>and film thickness t of the transparent electrode is satisfactorily approximated with a quadratic curve when data of excellent display quality are connected to one another. When the film thickness t of the transparent electrode is thick, a taper length x gets longer, and consequently by reducing the tilt angle θ<SB>1</SB>and a tilt angle θ<SB>2</SB>of a level difference of an alignment layer 64 so as to sufficiently rub a region tending to be the shadow area for rubbing, the excellent display quality is obtained. When the film thickness t of the transparent electrode is thin, the taper length x gets shorter, and consequently even if the tilt angle θ<SB>2</SB>of the level difference of the alignment layer 64 is increased to a certain extent, the display quality is scarcely affected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and in particular, drives a liquid crystal molecule through an alignment film by applying a voltage between a common electrode layer and a pixel electrode layer formed on the same substrate via an insulating layer. The present invention relates to a liquid crystal display device.

  Conventionally, a TN (Twisted Nematic) method has been widely used as a display method for liquid crystal display devices, but this method has a limited viewing angle in terms of display principle. As a method for solving this, a pixel electrode and a common electrode are formed on the same substrate, a voltage is applied between the pixel electrode and the common electrode, an electric field substantially parallel to the substrate is generated, and liquid crystal molecules are placed on the substrate. A lateral electric field system that drives in a plane that is mainly parallel to the plane is known.

  As the lateral electric field method, there are known an IPS (In Plane Switching) method and an FFS (Fringe Field Switch) method. In the IPS method, a comb-like pixel electrode and a comb-like common electrode are combined. In the FFS method, one of the upper electrode layer and the lower electrode layer formed through the insulating layer is assigned to the common electrode layer, the other is assigned to the pixel electrode layer, and a slit is formed in the upper electrode layer. It is formed.

  The alignment film layer for aligning the liquid crystal is disposed on the electrode layer in which the comb-shaped pixel electrode and the comb-shaped common electrode are formed in the IPS method, and the upper portion where the slit is formed in the FFS method. It is disposed on the electrode layer. In any case, since the alignment film layer is disposed on the electrode layer having unevenness, the alignment film layer also becomes uneven due to the influence of the unevenness of the underlayer. Since the alignment treatment is performed by rubbing the uneven surface of the alignment film layer, depending on the rubbing direction, the alignment treatment for the shadow portion of the unevenness may be insufficient.

  For example, Patent Document 1 points out that in a horizontal electric field type liquid crystal display device, a large step structure is formed because a large number of comb-teeth electrodes are arranged, and alignment processing is difficult. Here, several liquid crystal display devices having different steps and taper inclination angles are produced, and the uniformity of liquid crystal alignment due to rubbing in the vicinity of the step is evaluated as a contrast ratio. Even if the size of the step is changed from 0.1 μm to 0.5 μm, the taper inclination angle of the step end portion is 10 degrees or less and the aspect (vertical / horizontal) ratio is 0.176 or less, and a good contrast. It is disclosed that the contrast ratio can be improved, and in particular, when the taper inclination angle is 8.5 degrees or less and the aspect ratio is 0.14 or less, the contrast ratio is further improved.

  In Patent Document 2, since the pixel electrode and the common electrode are arranged in a comb shape in an IPS liquid crystal display panel, when the liquid crystal is aligned by rubbing, an area near the step such as the electrode is rubbed. It is difficult to point out that the uniaxial orientation in this region is incomplete. Here, it is disclosed that a lower alignment film is formed with a film having a high leveling flattening ability and is formed with a film that does not easily cause a seizure phenomenon when a fixed pattern is displayed thereon to form an alignment film having a two-layer structure. Has been.

JP 2000-131700 A JP 2000-47212 A

  In a liquid crystal display device, for example, in the step portion near the slit end of the electrode in the FFS method, or in the step portion near the comb electrode end in the IPS method, alignment processing by rubbing is difficult, and display such as a decrease in contrast and burn-in is displayed. There was a problem of degrading quality. Further, as the pixels become finer, for example, in the FFS method, the opening of the slit of the electrode becomes smaller, and in the IPS method, the interval between the comb-teeth electrodes becomes narrower, and the influence on the display quality of the stepped portion is increasing. . Here, the disclosure of Patent Document 1 is about a case where the level difference is a certain size. The method of Patent Document 2 discloses that the alignment film has a two-layer structure, but the process is complicated.

  The objective of this invention is providing the liquid crystal display device which can perform an orientation process favorably.

  The liquid crystal display device according to the present invention is a liquid crystal display device that drives a liquid crystal molecule through an alignment film layer by applying a voltage between a pixel electrode and a common electrode formed on the same substrate, the alignment film The layer has a film thickness of 50 nm or more and 100 nm or less, and is rubbed at an angle of 0 ° or more and 10 ° or less with respect to the pattern of the electrode layer that is the lower layer film of the alignment film layer. The film has a thickness of 100 nm or less and a tilt angle of 20 ° to 60 ° in the cross section.

  Further, in the liquid crystal display device according to the present invention, one of the upper electrode layer and the lower electrode layer formed on the same substrate via the insulating layer is assigned to the common electrode layer, and the other is assigned to the pixel electrode layer. In the liquid crystal display device, a slit is formed in the upper electrode layer, a voltage is applied between the lower electrode layer, and liquid crystal molecules are driven through the alignment film layer, and the alignment film layer has a thickness of 50 nm to 100 nm. The rubbing treatment is performed at an angle of 0 ° to 10 ° with respect to the long side of the slit, and the upper electrode layer has a thickness of 50 nm to 100 nm and a thickness of 20 to the insulating layer. It has an inclination angle of not less than 60 ° and not more than 60 °.

Further, in the liquid crystal display device according to the present invention, one of the upper electrode layer and the lower electrode layer formed on the same substrate via the insulating layer is assigned to the common electrode layer, and the other is assigned to the pixel electrode layer. In the liquid crystal display device, a slit is formed in the upper electrode layer, a voltage is applied between the lower electrode layer, and liquid crystal molecules are driven through the alignment film layer. The alignment film layer has a thickness of 50 nm to 100 nm. The upper electrode layer is subjected to a rubbing process at an angle of 0 ° to 10 ° with respect to the long side of the slit, and the upper electrode layer has a thickness t (nm) of 50 nm to 100 nm. The inclination angle θ (°) with respect to the insulating layer is θ ≦ (−5.71 × 10 ⁻⁶ t ² + 1.48 × 10 ⁻³ t−4.06 × 10 ⁻² ) ^−1. And

  With the above configuration, the alignment film layer has a thickness of 50 nm to 100 nm, the rubbing process is performed at an angle of 0 ° to 10 ° with respect to the pattern of the electrode layer, and the electrode layer has a thickness of 50 nm to 100 nm. Thus, the electrode layer has an inclination angle of 20 ° or more and 60 ° or less in the cross section. Under this condition, the experiment confirmed that the display quality was good. Therefore, the alignment process can be performed satisfactorily by keeping the range of the inclination angle.

  Embodiments according to the present invention will be described below in detail with reference to the drawings. In the following, an FFS type liquid crystal display device that performs display composed of four colors of red (R), green (G), blue (B), and cyan (C) will be described. A three-color configuration of G and B may be used, and monochrome display may be performed. Further, a liquid crystal display device using an IPS method as a lateral electric field method may be used. In that case, the results of the following embodiments can be applied to the inclination angle of the electrode layer which is a lower layer film immediately below the alignment film layer and the unevenness affects the alignment film layer. In the following description, the lower electrode layer is assumed to be a pixel electrode layer and the upper electrode layer is assumed to be a common electrode layer as a configuration of the FFS system, but this is reversed, that is, the lower electrode layer is a common electrode layer and the upper electrode. The layer may be a pixel electrode layer. In the following FFS method, the common electrode layer is arranged separately for each pixel. However, the common electrode layer may not be divided for each pixel.

  1 to 4 are diagrams showing a planar configuration for four pixels in the display area when displaying in a four-color configuration of R, G, B, and C in the FFS mode liquid crystal display device 30. FIG. Is a cross-sectional view thereof. Here, FIG. 1 shows a planar configuration immediately before pixel electrode formation, and FIG. 2 shows a pixel electrode further formed in FIG. 1, and FIG. 3 shows a common electrode further formed in FIG. It is. Here, the pixel electrode 52 is illustrated by a thick dashed line, and the common electrode 60 is illustrated by a thick solid line. An alignment film layer is formed thereon to complete the array substrate. FIG. 4 shows the arrangement of the black matrix provided on the counter substrate facing the array substrate, superimposed on FIG. FIG. 5 is a cross-sectional view exaggerating the thickness direction along the line AA shown in FIG.

  First, the planar configuration of the liquid crystal display device 30 will be described with reference to FIGS. 1 to 3, and the structure will be described with reference to the cross-sectional view of FIG.

  As shown in FIG. 1, in the liquid crystal display device 30, each of the plurality of drain wirings 46 extends linearly (in the example of FIG. 1, extends in the vertical direction), and intersects the extending direction. A plurality of gate wirings 40 are arranged in each direction (here, the directions are orthogonal to each other and the horizontal direction in the example of FIG. 1). Each region partitioned by the plurality of drain wirings 46 and the plurality of gate wirings 40 is a pixel arrangement region 46B. In FIG. 1, four regions corresponding to the four-color configuration of R, G, B, and C are provided. A pixel arrangement region 46B is shown. In addition, when counting as 1 pixel for every color expression unit, the pixel arrangement | positioning area | region 46B said here corresponds to a sub pixel. Further, the common electrode wiring 54 is also arranged in a direction intersecting with the direction in which the drain wiring 46 extends (in the horizontal direction in the example of FIG. 1). The arrangement is placed on the opposite side of the gate wiring 40 with each pixel arrangement region 46B interposed therebetween.

  Here, the case where the arrangement pitch of each drain wiring 46 is the same in the whole several drain wiring 46 is illustrated. The width of each drain wiring 46 (the dimension in the arrangement direction of the drain wiring 46) is also assumed to be the same. Moreover, although the case where the drain wiring 46 is linear is illustrated in the drawing, for example, it may have a meandering portion locally and extend in the extending direction as a whole. As the pixel array, a stripe array, a delta array, a mosaic array, or the like may be formed.

  The pixel TFTs 70 are respectively arranged in the pixel arrangement region 46B partitioned by the drain wiring 46, the gate wiring 40, and the common electrode wiring 54. In the example of FIG. 1, for each pixel TFT 70, the semiconductor layer 36 extends in a substantially U shape (in the drawing, the substantially U shape is shown upside down). A gate wiring 40 extends in the arrangement direction of the drain wirings 46 across the arms of the book. In this configuration, the source electrode 48 of the pixel TFT 70 is located on the same side with respect to the gate wiring 40 together with the drain electrode connected to the drain wiring 46. Thereby, in the pixel TFT 70, the gate wiring 40 is configured to intersect the semiconductor layer 36 twice between the source and the drain, in other words, two gate electrodes are provided between the source and the drain of the semiconductor layer 36. It has a configuration.

  Thus, the drain of the pixel TFT 70 is connected to the nearest drain wiring 46, and the source is connected to the pixel electrode 52 via the source electrode 48 as shown in FIG. Further, the common electrode wiring 54 is provided with a common electrode relay electrode 56, which is connected to the common electrode 60 as shown in FIG.

  FIG. 2 is a diagram illustrating a state of the pixel electrode 52. The pixel electrode 52 is a flat electrode that is provided for each pixel and is connected to the source of the pixel TFT 70 of the pixel.

  FIG. 3 is a diagram illustrating a state of the common electrode 60. In the example of FIG. 3, the common electrode 60 is provided for each pixel. However, in some cases, the common electrode 60 may be disposed across the pixels. The common electrode 60 is a transparent electrode film layer provided with slits 61 that are openings. The slit 61 has a function of generating a transverse electric field that is mainly parallel to the substrate surface through the lines of electric force when a voltage is applied between the pixel electrode 52 and the common electrode.

  An alignment film is disposed on the common electrode 60, and a rubbing process is performed as an alignment process. The rubbing direction can be performed in a direction parallel to the gate wiring 40 in FIG. 3, for example. The slit 61 of the common electrode 60 is formed such that the direction in which the long side extends is slightly inclined with respect to the rubbing direction. For example, it can be formed so as to be inclined at an angle of about 5 ° with respect to the rubbing direction. By forming an alignment film on the common electrode 60 and performing a rubbing process, an array substrate is completed.

  Note that the black matrix 62 shown in FIG. 4 is formed of a laminated film of chromium and chromium oxide, for example, and is provided on the counter substrate. The black matrix 62 is provided between the adjacent pixel electrodes 52 with respect to the pixel electrode 52 described in FIG. 2, and is provided with an opening P corresponding to each pixel arrangement region 46B described in FIG. Yes. The opening P is formed so as to partially overlap the edge portion of the slit 61, that is, the short side. That is, the black matrix 62 is provided so as to overlap with and extend along the width of each drain wiring 46 described in FIG. 1 (note that each drain wiring is not shown hidden in FIG. 4). Here, the opening P defines the outline of the pixel. Note that the drain wiring 46, the gate wiring 40, the source electrode 48, the common electrode wiring 54, and the common electrode relay electrode 56 are light-shielding as well as the black matrix, and can also define the pixel openings together with the black matrix. .

  Next, the structure of the array substrate 32 in the FFS mode liquid crystal display device will be described with reference to the cross-sectional view of FIG. FIG. 5 is a cross-sectional view taken along the line AA of FIG. 3 as described above, and each element for one pixel is shown.

  The array substrate 32 includes a translucent substrate 34, a semiconductor layer 36, a gate insulating film 38, a gate wiring 40, an interlayer insulating film 44, a drain wiring 46, a source electrode 48, a planarizing film 50, The pixel electrode 52, the common electrode wiring 54, the common electrode relay electrode 56, the FFS insulating film 58, and the common electrode 60 are configured.

  The translucent substrate 34 is made of glass, for example. The semiconductor layer 36 is made of, for example, polysilicon and is disposed on the translucent substrate 34. The gate insulating film 38 is made of, for example, silicon oxide or silicon nitride, and is disposed on the translucent substrate 34 so as to cover the semiconductor layer 36. The gate wiring 40 is made of, for example, a metal such as Mo or Al, is disposed on the gate insulating film 38 so as to face the semiconductor layer 36, and constitutes a pixel TFT 70 together with the gate insulating film 38 and the semiconductor layer 36. The gate wiring 40 is also called a scanning line.

  The interlayer insulating film 44 is made of, for example, silicon oxide, silicon nitride, or the like, and is disposed on the gate insulating film 38 so as to cover the gate wiring 40. A contact hole is provided through the interlayer insulating film 44 and the gate insulating film 38, and the contact hole is provided at a position corresponding to the source and drain of the pixel TFT 70 in the semiconductor layer 36. The drain wiring 46 is made of, for example, a metal such as Mo, Al, or Ti, and is disposed on the interlayer insulating film 44 and connected to the semiconductor layer 36 through one of the contact holes. The drain wiring is also called a signal line. The source electrode 48 is made of, for example, the same material as the drain wiring 46, is disposed on the interlayer insulating film 44, and is connected to the semiconductor layer 36 through the other contact hole.

  Here, in the semiconductor layer 36, a portion where the drain wiring 46 is connected is the drain of the pixel TFT 70, and a portion where the pixel electrode 52 is connected via the source electrode 48 is the source of the pixel TFT 70. Conversely, it can also be called.

  The planarizing film 50 is made of, for example, an insulating transparent resin such as acrylic, and is disposed on the interlayer insulating film 44 so as to cover the drain wiring 46 and the source electrode 48. A contact hole is provided on the source electrode 48 through the planarizing film 50.

  The pixel electrode 52 is made of a transparent conductive material such as ITO (Indium Tin Oxide), for example, is disposed on the planarization film 50 and is in contact with the source electrode 48 through the contact hole.

  The common electrode wiring 54 is made of, for example, the same conductive material as that of the gate wiring 40 and is disposed on the gate insulating film 38 and covered with the interlayer insulating film 44. A contact hole reaching the common electrode wiring 54 is provided in the interlayer insulating film 44. The common electrode relay electrode 56 is made of, for example, the same material as the drain wiring 46, is disposed on the interlayer insulating film 44, and is in contact with the common electrode wiring 54 through the contact hole.

  The FFS insulating film 58 is made of, for example, nitrogen silicon formed at a low temperature, and is disposed on the planarizing film 50 so as to cover the pixel electrode 52. A contact hole reaching the common electrode relay electrode 56 is provided in the planarizing film 50, and an FFS insulating film 58 is also provided on the side wall of the contact hole.

  The common electrode 60 is made of, for example, a transparent conductive material such as ITO, is disposed on the FFS insulating film 58, and is in contact with the common electrode relay electrode 56 through the contact hole. The common electrode 60 is provided to face the pixel electrode 52 with the FFS insulating film 58 interposed therebetween, and has a plurality of slits 61 in a portion facing the pixel electrode 52.

  Although not shown in the drawing, an alignment film layer is disposed on the common electrode 60. The alignment film layer is a film having a function of initially aligning liquid crystal molecules, and is used, for example, by subjecting an organic film such as polyimide to a rubbing treatment.

  Thus, the common electrode 60 as the upper electrode layer and the pixel electrode 52 as the lower electrode layer are formed on the translucent substrate 34 as the same substrate via the FFS insulating film 58 as the insulating layer. A slit 61 is formed in the common electrode 60 that is an electrode layer, and a voltage is applied between the pixel electrode 52 that is a lower electrode layer, and a lateral electric field that is mainly parallel to the substrate surface is generated to pass through the alignment film layer. Liquid crystal molecules can be driven.

  As described above, in the array substrate of the FFS mode liquid crystal display device, since the alignment film layer is disposed on the upper electrode layer in which the slit is formed and the cross section is uneven, there is a problem in the alignment processing by rubbing. May occur. This will be described with reference to FIGS.

  FIG. 6 is a plan view showing the portion B in FIG. A slit 61 as an opening is formed in the common electrode 60 as the upper electrode layer, and an alignment film layer 64 is disposed on the entire surface of the common electrode 60 including the slit 61 portion. Here, the alignment film layer 64 is subjected to a rubbing process as an alignment process. The rubbing treatment can be performed by rubbing the alignment film layer 64 in one direction using a rubbing material such as cloth. In FIG. 6, the rubbing direction is indicated by an arrow. Generally, the rubbing direction is slightly inclined with respect to the long side direction of the slit 61 in order to give the liquid crystal molecules initial alignment. For example, in the example of FIG. 6, it is convenient to set the rubbing direction parallel to the axis of the pixel plane arrangement, that is, the direction parallel to the gate wiring described in FIG. Are previously inclined slightly with respect to the direction of the gate wiring.

  Therefore, when the rubbing material used for the rubbing process rubs the alignment film layer 64 along the rubbing direction indicated by an arrow in FIG. 6, the slope facing the rubbing material among the slopes along the long side of the slit 61 is rubbed as intended. In FIG. 6, the other slope indicating the region with a diagonal line is a position that becomes a shadow against rubbing of the rubbing material. It may be insufficient.

  FIG. 7 is a cross-sectional view taken along line CD in FIG. A region indicated by hatching in FIG. 7 is indicated as a here. A portion indicated as b other than a is a region where the alignment treatment is sufficiently performed. As described above, the common electrode 60 having the slits 61 on both sides is sufficiently subjected to the alignment treatment because one of the inclined surfaces shown as a in FIG. 7 becomes a shadow in the rubbing process. There is no fear. If there is a region where the alignment treatment is insufficient, the display quality may be deteriorated as a result. Therefore, it is considered that if the taper length, which is the projected length of the inclined surface of the slit 61 on the substrate, is shortened to reduce the shadow area a of the alignment treatment, the deterioration of display quality can be suppressed. .

  In addition, although the inclined surface about the long side of the slit 61 was demonstrated here, it is the same also about the short side of the slit 61, ie, the edge part of the slit 61. FIG. However, as described with reference to FIG. 4, since the edge portion of the slit 61 is usually hidden by the black matrix of the counter substrate, even if the alignment process is slightly insufficient, it does not become a big problem.

Then, the following knowledge was acquired when the slope of this slit was observed using SEM (Scanning Electron Microscope). FIG. 8 is a model of a cross-sectional structure of the pixel electrode 52, the FFS insulating film 58, the common electrode 60, and the alignment film layer 64 in the vicinity of the slit 61. Here, the thickness of the common electrode 60 is t, the inclination angle of the slope forming the slit 61 in the cross section is θ ₁ , the taper length that is the projection length of this slope on the substrate is x, and the inclination angle of the common electrode 60 The inclination angle of the alignment film layer 64 corresponding to θ ₁ is θ _2. Of the thicknesses of the alignment film layer 64, the thickness just above the common electrode 60 is E, and the thickness just above the FFS insulating film 58 is F. As shown. Therefore, the step of the alignment film layer 64 in the slit 61 is shown as t-D.

Here, if the alignment film layer 64 is too thick, display unevenness occurs, and if it is too thin, the alignment regulating force is lost. When the opening width, which is the interval between the long sides in the slit 61, is set to several μm, the thickness of the alignment film layer is appropriately 50 nm to 100 nm. In accordance with this, the thickness t of the common electrode 60 may be thicker than that, but it is preferable that the difference is not so large, and it is preferably about 100 nm. Therefore, the SEM observation was performed on samples in which the inclination angle θ ₁ of the inclined surface of the common electrode 60 was variously formed within such a film thickness range.

As a result, the thickness F of the alignment film layer 64 is greater in the thickness F directly above the FFS insulating film 58 than in the thickness E directly above the common electrode 60. It has been found that θ ₂ is smaller than the inclination angle θ ₁ of the common electrode 60. Then, it was found that the step tD of the alignment film layer 64 does not depend on the inclination angle θ ₁ of the common electrode 60 and is about 25% of the thickness t of the common electrode 60. That is, according to SEM observation, it is found that the step t-D of the alignment film layer 64 in the slit 61 is 0.75 t for samples having various thicknesses t of the common electrode 60 and various inclination angles θ _1. It was.

Using this knowledge, from FIG. 8, the taper length x is t / tan θ ₁ , and therefore, tan θ ₂ = tan [(t−D) / x] = tan (with respect to the inclination angle θ ₂ of the alignment film layer 64. 0.75θ ₁ ). FIG. 9 shows the result of determining the relationship between the inclination angle θ ₁ and the inclination angle θ ₂ based on this calculation. From this, it can be seen that if the inclination angle θ ₁ of the common electrode 60 is reduced, the inclination angle θ _{2 at} the step of the alignment film layer 64 is relaxed.

FIG. 10 is a diagram showing the relationship between the film thickness t of the common electrode 60 that is a transparent electrode and the taper length x obtained as described above, using the inclination angle θ ₁ of the common electrode 60 as a parameter. As can be seen from FIG. 10, the taper length x increases as the tilt angle θ ₁ decreases, and the taper length x increases as the film thickness t of the transparent electrode increases.

Next, a liquid crystal display device in which the thickness t of the transparent electrode and the inclination angle θ ₁ thereof were changed was actually produced, and the display quality was evaluated. The result is shown in FIG. The horizontal axis, vertical axis, and parameters of each curve in FIG. 11 are the same as those in FIG. In FIG. 11, white circles indicate the conditions of the liquid crystal display device having good display quality, and black circles indicate the conditions of the liquid crystal display device in which the display quality is deteriorated. The deterioration in display quality includes an afterimage of a checker flag indicating burn-in. From this result, it is considered that the optimum combination of the film thickness t of the transparent electrode and the inclination angle θ ₁ thereof is in the range surrounded by the frame as the optimum region in FIG. 11 from the viewpoint of display quality.

This will be described in detail. Since the taper length x becomes longer when the film thickness t of the transparent electrode is thicker, the tilt angle θ ₁ is reduced so that the region that is likely to be a shadow of rubbing can be sufficiently rubbed, and the alignment film layer Good display quality can be obtained by reducing the inclination angle θ ₂ of 64 steps. On the other hand, when the film thickness t of the transparent electrode is thin, the taper length x becomes small. Therefore, even if the inclination angle θ ₂ of the step of the alignment film layer 64 is increased to some extent, the display quality is not greatly affected. Thus, in order to obtain good display quality, the inclination angle θ ₁ may be set according to the thickness t of the transparent electrode.

FIG. 12 shows the conditions for improving the display quality in FIG. 11 as the relationship between the film thickness t of the transparent electrode and its inclination angle θ ₁ . Here, the film thickness t of the transparent electrode is taken on the horizontal axis, and the inclination angle θ ₁ and the reciprocal 1 / θ ₁ are taken on the vertical axis. As shown in FIG. 12, the relationship between the reciprocal 1 / θ ₁ of the tilt angle and the film thickness t of the transparent electrode can be approximated by a quadratic curve. The relational expression is that 1 / θ ₁ = (− 5.71 × 10 ⁻⁶ t ² + 1.48 × 10 ⁻ ) where the inclination angle θ ₁ is the degree of angle (°) and the film thickness t of the transparent electrode is nm. ³ t−4.06 × 10 ⁻² ).

Therefore, as a condition for improving the display quality of the liquid crystal display device, the alignment film layer has a film thickness of 50 nm or more and 100 nm or less with respect to the long side of the slit of the common electrode which is the upper electrode layer. The rubbing process is performed at an angle of 0 ° to 10 °, and the common electrode as the upper electrode layer has an inclination angle θ (°) with respect to the FFS insulating layer under the condition that the film thickness t (nm) is 50 nm to 100 nm. , Θ ≦ (−5.71 × 10 ⁻⁶ t ² + 1.48 × 10 ⁻³ t−4.06 × 10 ⁻² ) ⁻¹ is observed.

  More specifically, the alignment film layer has a film thickness of 50 nm to 100 nm, and is rubbed at an angle of 0 ° to 10 ° with respect to the long side of the slit, and the upper electrode layer has a thickness of 50 nm to 100 nm. It is preferable to have the following film thickness and an inclination angle of 20 ° to 60 ° with respect to the FFS insulating layer.

In the FFS mode liquid crystal display device according to the embodiment of the present invention, it is a diagram showing a planar configuration immediately before pixel electrode formation. It is a figure which shows a mode that the pixel electrode was formed in FIG. It is a figure which shows a mode that the common electrode was formed in FIG. It is a figure which shows a mode that the black matrix was arrange | positioned in FIG. It is sectional drawing of the FFS system liquid crystal display device of embodiment which concerns on this invention. It is a schematic diagram explaining the mode of the orientation process by rubbing. It is sectional drawing explaining the mode of the orientation process by rubbing. It is a model figure of the cross-sectional structure in the vicinity of a slit. In the embodiment of the present invention, it is a diagram showing the relationship between the inclination angle θ ₁ and the inclination angle θ ₂ . In the embodiment of the present invention, it is a diagram showing the relationship between the taper length x and the film thickness t of the common electrode, which is a transparent electrode, using the inclination angle θ ₁ of the common electrode as a parameter. In embodiment of this invention, it is a figure which shows the result of having produced the liquid crystal display device which changed thickness t of the transparent electrode, and its inclination | tilt angle (theta) _1, and evaluated the display quality. In the embodiment of the present invention, it is a diagram showing the condition that the display quality is good as the relationship between the film thickness t of the transparent electrode, its inclination angle θ ₁ , and its inverse 1 / θ ₁ .

Explanation of symbols

  30 liquid crystal display device, 32 array substrate, 34 translucent substrate, 36 semiconductor layer, 38 gate insulating film, 40 gate wiring, 42 storage capacitor wiring, 44 interlayer insulating film, 46 drain wiring, 46B pixel arrangement region, 48 source electrode , 50 planarization film, 52 pixel electrode, 54 common electrode wiring, 56 common electrode relay electrode, 58 FFS insulating film, 60 common electrode, 61 slit, 62 black matrix, 64 alignment film layer, 70 pixel TFT.

Claims (3)

A liquid crystal display device that drives a liquid crystal molecule through an alignment film layer by applying a voltage between a pixel electrode and a common electrode formed on the same substrate,
The alignment film layer has a film thickness of 50 nm or more and 100 nm or less, and is subjected to a rubbing treatment at an angle of 0 ° or more and 10 ° or less with respect to a pattern of an electrode layer that is a lower layer film of the alignment film layer
The liquid crystal display device, wherein the electrode layer has a film thickness of 50 nm to 100 nm and an inclination angle of 20 ° to 60 ° in the cross section. One of the upper electrode layer and the lower electrode layer formed on the same substrate via an insulating layer is assigned to the common electrode layer, the other is assigned to the pixel electrode layer, and a slit is formed in the upper electrode layer A liquid crystal display device that drives a liquid crystal molecule through an alignment film layer by applying a voltage between the lower electrode layer,
The alignment film layer has a film thickness of 50 nm or more and 100 nm or less, and is rubbed at an angle of 0 ° or more and 10 ° or less with respect to the long side of the slit,
The liquid crystal display device, wherein the upper electrode layer has a film thickness of 50 nm to 100 nm and an inclination angle of 20 ° to 60 ° with respect to the insulating layer. One of the upper electrode layer and the lower electrode layer formed on the same substrate via an insulating layer is assigned to the common electrode layer, the other is assigned to the pixel electrode layer, and a slit is formed in the upper electrode layer A liquid crystal display device that drives a liquid crystal molecule through an alignment film layer by applying a voltage between the lower electrode layer,
The alignment film layer has a film thickness of 50 nm or more and 100 nm or less, and is rubbed at an angle of 0 ° or more and 10 ° or less with respect to the long side of the slit,
The upper electrode layer has an inclination angle θ (°) with respect to the insulating layer of θ ≦ (−5.71 × 10 ⁻⁶ t ² +1.48 under the condition that the film thickness t (nm) is 50 nm or more and 100 nm. × 10 ⁻³ t−4.06 × 10 ⁻² ) ⁻¹ .

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