JP2008091947A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of reducing the size of a semiconductor chip. <P>SOLUTION: On an insulation film 9, a pad 10 and interconnections 11a and 11b other than the pad are provided. On the insulation film 9 including the pad 10 and interconnections 11a and 11b, a surface protection film 12 is formed and an opening 13 is disposed thereon. The opening 13 is formed on the pad 10 and exposes the surface thereof. A bump electrode 8 is formed on the surface protection film 12 including the opening 13. Here, it is constituted that the size of the pad 10 becomes sufficiently small compared with that of the bump electrode 8. Thus, the interconnections 11a and 11b are arranged in the same layer as the pad 10 just under the bump electrode 8. That is, the interconnections 11a and 11b are arranged at a space under the bump electrode 8 formed by reducing the size of the pad 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor device used for a driver for an LCD (Liquid Crystal Display).

  In Japanese Patent Laid-Open No. 10-233507 (Patent Document 1), in a semiconductor integrated circuit such as a driver IC provided with a large number of output pads and an electronic circuit device such as an electronic timepiece, the chip area is reduced and the production efficiency is improved. Techniques for improving and reducing costs are disclosed.

  Specifically, the output pad is provided on the driving transistor or the logic circuit connected to the output pad in a planar manner. Further, not only aluminum wiring but also bump electrodes or barrier metal are used for the wiring of the semiconductor device. In addition, when the semiconductor integrated circuit is electrically bonded on the printed circuit board by the face-down method, the solder bump provided on the semiconductor integrated circuit and the wiring of the printed circuit board are directly connected. It is formed by. At this time, the bump electrode, which is an external connection terminal of the semiconductor integrated circuit, is provided by being laminated on the transistor.

For example, in FIG. 18 of Patent Document 1, an output pad having a bump structure is arranged so as to overlap with a driving transistor. Accordingly, since the driving transistor and the output pad can be arranged to overlap in a plane, the chip area can be reduced. Further, FIG. 26 of Patent Document 1 discloses a structure in the case where a diffusion region and another diffusion region are electrically connected by bump wiring. By adopting such a structure, it is said that the wiring layer can be increased by one layer as compared with the prior art.
Japanese Patent Laid-Open No. 10-233507

  In recent years, LCDs using liquid crystals as display elements are rapidly spreading. This LCD is controlled by a driver for driving the LCD. The LCD driver is composed of a semiconductor chip and is mounted on a glass substrate, for example. A semiconductor chip constituting an LCD driver has a structure in which a plurality of transistors and multilayer wiring are formed on a semiconductor substrate, and bump electrodes are formed on the surface. And it is mounted in the glass substrate through the bump electrode formed in the surface. At this time, the semiconductor chip and the glass substrate are connected by the bump electrode. From the viewpoint of improving the adhesive force, the area of the bump electrode is increased to increase the bonding area of the semiconductor chip and the glass substrate. . That is, the bump electrode of the semiconductor chip constituting the LCD driver has a feature that the size is much larger than the bump electrode of the semiconductor chip used for general purposes.

  In the LCD driver, an insulating film serving as a passivation film is formed under the bump electrode, and is connected to a pad formed in the uppermost layer of the multilayer wiring through an opening provided in the insulating film. . Usually, the opening and the pad are formed to have the same area according to the size of the bump electrode.

  As described above, pads corresponding to large bump electrodes are formed on the uppermost layer of the multilayer wiring formed on the semiconductor chip. That is, a pad having the same area as the size of the bump electrode is formed in the uppermost layer. Therefore, there is a problem that the size of the semiconductor chip has to be increased in order to secure a space for forming wirings other than the pads in the uppermost layer of the multilayer wiring.

  Further, in the normal structure in which the bump electrode is formed immediately above the bonding pad, the layout configuration of the wiring such as the pad is limited because the position of the bump electrode to be mounted is determined. Therefore, there is a problem that it is difficult to adopt a layout configuration that can efficiently reduce the size of the semiconductor chip.

  An object of the present invention is to provide a technique capable of reducing the size of a semiconductor chip.

  Another object of the present invention is to provide a technique capable of improving the degree of freedom of the layout configuration of wirings formed on a semiconductor chip.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention is formed on (a) a pad formed on a semiconductor substrate, (b) an insulating film having an opening on the pad, and (c) an insulating film having the opening. A semiconductor chip having a bump electrode. The size of the bump electrode is larger than the size of the pad, and a wiring different from the pad is formed below the bump electrode through the insulating film. is there.

  According to another aspect of the present invention, there is provided a semiconductor device comprising: (a) a pad formed on a semiconductor substrate; (b) an insulating film having an opening on the pad; and (c) an insulating film having the opening. A semiconductor chip having a formed bump electrode is provided. The size of the bump electrode is larger than the size of the pad, and the bump electrode has a narrow first portion and a second portion wider than the first portion. It is characterized by.

  The method of manufacturing a semiconductor device according to the present invention includes: (a) a step of forming a pad and a wiring different from the pad on the same layer on a semiconductor substrate; and (b) an insulating film on the wiring different from the pad and the pad. Forming a step. And (c) forming an opening exposing the surface of the pad in the insulating film; and (d) forming a bump electrode on the insulating film including the opening. The pad and the wiring different from the pad are formed below the bump electrode through the insulating film.

  The method for manufacturing a semiconductor device according to the present invention includes (a) a step of forming a pad on a semiconductor substrate, and (b) a step of forming an insulating film on the pad. And (c) forming an opening exposing the surface of the pad on the insulating film, and (d) forming a bump electrode on the insulating film including the opening. A first portion having a narrow width and a second portion having a width wider than that of the first portion are formed on the bump electrode.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The area under the bump electrode can be effectively used, and the size of the semiconductor chip can be reduced. Since the pads can be arranged without being influenced by the position of the bump electrode, the degree of freedom in the layout configuration of the wiring such as the pads can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view showing a configuration of a semiconductor chip 1 (semiconductor device) in the first embodiment. The semiconductor chip 1 in the first embodiment is an LCD driver. In FIG. 1, a semiconductor chip 1 has a semiconductor substrate 2 formed in, for example, an elongated rectangular shape, and an LCD driver for driving a liquid crystal display device is formed on the main surface thereof. This driver has a function of controlling the direction of liquid crystal molecules by supplying a voltage to each pixel of the cell array constituting the LCD, and includes a gate drive circuit 3, a source drive circuit 4, a liquid crystal drive circuit 5, a graphic RAM ( Random Access Memory) 6 and a peripheral circuit 7.

  In the vicinity of the outer periphery of the semiconductor chip 1, a plurality of bump electrodes 8 are arranged along the outer periphery of the semiconductor chip 1 at predetermined intervals. The plurality of bump electrodes 8 are disposed on an active region where the elements and wirings of the semiconductor chip 1 are disposed. Among the plurality of bump electrodes 8, there are a bump electrode for an integrated circuit necessary for the configuration of the integrated circuit and a dummy bump electrode which is not required for the configuration of the integrated circuit. Bump electrodes 8 are arranged in a staggered manner near one long side and two short sides of the semiconductor chip 1. The plurality of bump electrodes 8 arranged in a staggered pattern are mainly bump electrodes for gate output signals or source output signals. Bump electrodes 8 arranged in a staggered manner at the center of the long side of the semiconductor chip 1 are bump electrodes for source output signals, and bump electrodes arranged in a staggered manner near both corners of the long side of the semiconductor chip 1 and on both short sides of the semiconductor chip 1. Reference numeral 8 denotes a bump electrode for a gate output signal. By adopting such a staggered arrangement, it is possible to arrange a bump electrode for a gate output signal and a bump electrode for a source output signal that require a large number while suppressing an increase in the size of the semiconductor chip 1. it can. That is, the number of bump electrodes can be increased while reducing the chip size.

  Further, in the vicinity of the other long side of the semiconductor chip 1, bump electrodes 8 are arranged so as to be arranged in a straight line instead of a staggered arrangement. The bump electrodes 8 arranged in a straight line are bump electrodes for digital input signals or analog input signals. Furthermore, dummy bump electrodes are formed in the vicinity of the four corners of the semiconductor chip 1. In FIG. 1, the example in which the bump electrodes 8 for gate output signals or source output signals are arranged in a staggered manner and the bump electrodes 8 for digital input signals or analog input signals are arranged in a straight line has been described. However, it is also possible to arrange the bump electrodes 8 for gate output signals or source output signals in a straight line and to arrange the bump electrodes 8 for digital input signals or analog input signals in a staggered arrangement.

  FIG. 2 shows a cross section taken along line A-A ′ of FIG. 1. In FIG. 2, the structure below the uppermost layer wiring is omitted. Although not shown in FIG. 2, a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on a semiconductor substrate, and a multilayer wiring is formed on the semiconductor element. FIG. 2 shows the structure above the uppermost layer of the multilayer wiring.

  As shown in FIG. 2, the uppermost layer wiring is formed on the insulating film 9 made of, for example, a silicon oxide film. As the uppermost layer wiring, for example, a pad 10 and wirings 11a and 11b other than the pad 10 are formed. The wirings 11a and 11b are formed, for example, from signal wiring for signals, power wiring for power supply, or dummy wiring. These pads 10 and wirings 11a and 11b are made of, for example, an aluminum film.

  A surface protective film (passivation film) 12 is formed on the pad 10 and the wirings 11a and 11b so as to cover the pad 10 and the wirings 11a and 11b. The surface protective film 12 is formed of an insulating film such as a silicon nitride film. The surface protective film 12 has an opening 13 that exposes the surface of the pad 10. On the surface protective film 12 including the inside of the opening 13, a UBM film 14 that is a base metal film is formed. A bump electrode 8 is formed therethrough.

  In addition to the pad 10 and the wiring layers such as the wirings 11a and 11b, a plurality of wiring layers are formed below the wiring layer such as the pads 10 and the wirings 11a and 11b. (Not shown). Similarly, a semiconductor element such as the aforementioned MISFET is also formed below the bump electrode 8 (not shown). As described above, in this embodiment, the chip area of the semiconductor chip 1 can be reduced by effectively utilizing the region under the bump electrode 8.

  Here, one of the features of the present invention is that the opening 13 and the pad 10 are formed to be smaller than the size of the bump electrode 8. Usually, an opening 13 having the same size as the bump electrode 8 is formed below the bump electrode 8, and a pad 10 larger than the bump electrode 8 is formed below the opening 13. That is, a pad 10 is formed below the bump electrode 8, and the size of the pad 10 is approximately the same as the size of the bump electrode 8. However, the semiconductor chip 1 constituting the LCD driver has a large area because the bump electrode 8 is bonded to the glass substrate. Therefore, the size of the pad 10 formed under the bump electrode 8 is also increased. At this time, if the size of the pad 10 is large, it is difficult to secure a space even if wiring other than the pad 10 is arranged in the uppermost layer of the multilayer wiring layer, and the size of the semiconductor chip 1 is increased. . On the other hand, in the first embodiment, the size of the opening 13 and the pad 10 is made smaller than the size of the bump electrode 8 as shown in FIG. In other words, the size of the bump electrode 8 is larger than the size of the pad 10. Thus, by reducing the size of the pad 10 compared to the size of the bump electrode 8, it is possible to secure a space for forming the wirings 11 a and 11 b other than the pad 10 below the bump electrode 8. That is, since the normal pad 10 is formed immediately below the bump electrode 8 and in the uppermost layer of the same layer as the pad 10, another wiring cannot be formed. However, in the first embodiment, since the size of the pad 10 is made smaller than the size of the bump electrode 8, the pad 10 is located directly below the bump electrode 8 and in the same layer as the pad 10. Space for forming the other wirings 11a and 11b can be secured. Therefore, since the wirings 11a and 11b other than the pad 10 can be formed immediately below the bump electrode 8, the space immediately below the bump electrode 8 can be effectively used, and the size of the semiconductor chip 1 can be reduced.

  In the first embodiment, the size of the pad 10 is made smaller than the size of the bump electrode 8 without changing the size of the bump electrode 8, thereby providing a space for forming wiring other than the pad 10 on the bump electrode 8. It is characterized by providing. That is, while ensuring the area of the bump electrode 8 bonded to the glass substrate, wiring other than the pad 10 is secured under the bump electrode 8 to reduce the size of the semiconductor chip 1. Such a technical idea is neither described nor suggested in Patent Document 1 described in the background art, and is unique to the first embodiment. For example, by increasing the size of the bump electrode without changing the size of the pad, the size of the bump electrode can be made larger than the size of the pad. The space itself is not reduced, and a space formed by reducing the size of the pad cannot be secured. Accordingly, the size of the semiconductor chip cannot be reduced. Furthermore, if the bump electrode is increased, the size of the semiconductor chip also increases, so that the semiconductor chip cannot be reduced. As described above, as a method of reducing the size of the pad electrode relative to the size of the bump electrode, there are means for increasing the size of the bump electrode itself and means for reducing the pad itself. These two means are common in that the size of the pad electrode is smaller than the size of the bump electrode. However, in the means for reducing the pad itself, a layer other than the pad is formed on the same layer as the pad under the bump electrode. There is a significant difference in that a space for forming the wiring can be secured. Furthermore, by reducing the size of the pad itself, the width of the pad may be smaller than that of a relatively wide power supply wiring other than the pad.

  FIG. 3 shows a cross-sectional view taken along the line B-B ′ of FIG. 1. As shown in FIG. 3, a pad 10 is formed on the insulating film 9 in a cross section taken along the line B-B ′, and a surface protective film 12 is formed so as to cover the pad 10. The surface protective film 12 is provided with an opening 13, and the surface of the pad 10 is exposed at the bottom of the opening 13. A bump electrode 8 is formed on the surface protective film 12 including the inside of the opening 13 via a UBM film 14. In the cross-sectional direction cut along the line B-B ′, the width of the pad 10 is approximately the same as or larger than the width of the bump electrode 8. That is, the bump electrode 8 is smaller in width than the bump electrode 8 in the cross-sectional direction cut along the line AA ′ shown in FIG. Pads 10 and signal wirings and power supply wirings other than the pads 10 are formed. On the other hand, as shown in FIG. 3, the width of the pad 10 formed immediately below the bump electrode 8 is about the same as the width of the bump electrode 8 in the cross-sectional direction cut along the line BB ′. It has become.

  FIG. 4 is an enlarged plan view of the area C of FIG. 1, and is a plan view showing a state in which wiring is formed immediately below the bump electrodes 8 arranged in a straight line. As shown in FIG. 4, the rectangular bump electrodes 8 are arranged side by side in the short side direction (direction intersecting the long side direction). A surface protective film 12 is formed below the bump electrode 8, and an opening 13 is formed in the surface protective film 12. A pad 10 is formed below the opening 13 provided in the surface protective film 12. The pad 10 is electrically connected to the bump electrode 8 formed so as to fill the opening 13. The pad 10 has a square shape, and the length of one side thereof is slightly larger than the length of the short side of the bump electrode 8. Therefore, as shown in FIG. 4, the length of the pad 10 is slightly larger than the length of the bump electrode 8 in the short side direction of the bump electrode 8. On the other hand, in the long side direction of the bump electrode 8, the length of the pad 10 is much smaller than the length of the bump electrode 8. That is, the pad 10 is smaller than the bump electrode 8, and the pad 10 is formed only under one end of the bump electrode 8. For this reason, a space is secured in the wiring layer in the long side direction of the bump electrode 8 and the same layer as the pad 10. In this space, wirings 11 a to 11 c different from the pad 10 are formed. As described above, according to the first embodiment, since the size of the pad 10 formed immediately below the bump electrode 8 is reduced, the wirings 11 a to 11 c are formed immediately below the bump electrode 8 in the same layer as the pad 10. be able to. Therefore, the area directly below the rectangular bump electrode 8 can be used effectively, and the semiconductor chip can be reduced.

  The wirings 11a to 11c are made of, for example, signal wirings, power supply wirings, or dummy wirings, and wirings with various widths can be routed. In FIG. 4, the wiring 11c has a larger width than the wirings 11a and 11b. Usually, the pad is formed to be approximately the same as the size of the bump electrode 8, and therefore the width of the pad is larger than the width of the wiring. However, in the first embodiment, the size of the pad 10 is made smaller than the size of the bump electrode 8 so as to secure a space in which wiring can be formed immediately below the bump electrode 8. For this reason, the width of the pad 10 may be smaller than, for example, a power supply wiring formed in a secured space. As described above, according to the configuration of the first embodiment, the width of the pad 10 may be smaller than the width of some other wirings.

  The wirings 11 a to 11 c are formed so as to extend in a direction intersecting the long side direction of the bump electrode 8. Although it is desirable to arrange the wirings 11 a to 11 c so as to be orthogonal to the long side direction of the bump electrode 8 from the viewpoint of effectively using the space, it is not necessarily formed so as to be orthogonal to the long side direction of the bump electrode 8. It does not have to be. For example, depending on the layout of the wiring, the wiring may be formed so as to cross diagonally. Also in this case, since the space immediately below the bump electrode 8 can be utilized, the semiconductor chip can be reduced in size.

  FIG. 5 is an enlarged plan view of the area D in FIG. 1, and is a plan view showing a state in which wiring is formed immediately below the bump electrodes 8 arranged in a staggered manner. 5, as in FIG. 4, the width of the bump electrode 8 in the long side direction is much larger than the width of the pad 10, and is in the long side direction of the bump electrode 8 and the same layer as the pad 10. Space is secured in the layer. Then, wirings 11d to 11k are formed in this space. When the bump electrodes 8 are formed in a zigzag pattern, the bump electrodes 8 are formed in two stages as shown in FIG. For this reason, compared with the case where the bump electrodes 8 are formed in a row, the space formed immediately below the bump electrodes 8 is increased. That is, if a pad is formed in accordance with the size of the bump electrode 8, wiring other than the pad cannot be formed immediately below the bump electrode 8. At this time, when the bump electrodes 8 are formed in a zigzag pattern as compared with the case where the bump electrodes 8 are formed in a single row, the space for forming the wiring is narrowed because the bump electrodes 8 are formed in two rows. However, as shown in FIG. 5, in the first embodiment, the wirings 11d to 11g are formed in the space immediately below the bump electrode 8 formed in the first row, and are formed in the second row. Wirings 11h to 11k are formed in a space immediately below the bump electrode 8 that is provided. For this reason, even when the bump electrodes 8 are arranged in a staggered pattern, the space formed immediately below the bump electrodes 8 can be effectively utilized to the same extent as when the bump electrodes 8 are arranged in a row. Thus, in the bump electrodes 8 formed on the semiconductor chip, wirings can be formed not only under the bump electrodes 8 arranged in a row but also under the bump electrodes 8 arranged in a staggered pattern. Therefore, downsizing of the semiconductor chip can be promoted.

  In addition, the D region (FIG. 5) in FIG. 1 has a larger number of bump electrodes 8 than the C region (FIG. 4) in FIG. 1, but this is the case of the LCD shown in FIG. This is because in order to drive the elements constituting the display unit 20, it is necessary to arrange more bump electrodes 8 on the D region side in FIG. These bump electrodes 8 on the D region side in FIG. 1 are mainly used for gates and sources of elements constituting the display unit 20 of the LCD.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. First, although not shown, for example, a semiconductor element such as a MISFET is formed on a semiconductor substrate made of a silicon single crystal, and a multilayer wiring is formed on the semiconductor element. FIG. 6 shows the wiring formed in the uppermost layer, and the structure below the wiring formed in the uppermost layer is omitted.

  As shown in FIG. 6, an insulating film 9 made of, for example, a silicon oxide film is formed. The insulating film 9 can be formed using, for example, a CVD (Chemical Vapor Deposition) method. Then, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are stacked on the insulating film 9. Thereafter, the laminated film is patterned using a photolithography technique and an etching technique. By this patterning, the pad 10 and the wirings 11a and 11b are formed. The pad 10 formed at this time is smaller than the bump electrode formed in the process described later. The wirings 11a and 11b are formed immediately below the bump electrodes.

  Subsequently, as shown in FIG. 7, a surface protective film 12 is formed on the insulating film 9 on which the pad 10 and the wirings 11a and 11b are formed. The surface protective film 12 is made of, for example, a silicon nitride film, and can be formed by, for example, a CVD method. Next, an opening 13 is formed in the surface protective film 12 using a photolithography technique and an etching technique. The opening 13 is formed on the pad 10 and exposes the surface of the pad 10. The size of the opening 13 is formed so as to be smaller than the size of the pad 10.

  Next, as shown in FIG. 8, a UBM (Under Bump Metal) film 14 is formed on the surface protective film 12 including the inside of the opening 13. The UBM film 14 can be formed by using, for example, a sputtering method, and is formed by a single layer film or a laminated film such as a titanium film, a nickel film, a palladium film, a titanium / tungsten alloy film, a titanium nitride film, or a gold film. ing. Here, the UBM film 14 has a function of improving the adhesion between the bump electrode 8 and the pad 10 or the surface protective film 12, and the metal element of the conductor film 16 formed in the subsequent process is a wiring 11 a, 11 b or the like. It is a film having a barrier function that suppresses or prevents metal elements such as the wirings 11a and 11b from moving to the conductor film 16 side. The planar dimension of the UBM film 14 is larger than that of the opening 13 and is substantially the same as that of the conductor film 16.

  Subsequently, as shown in FIG. 9, after a resist film 15 is applied on the UBM film 14, the resist film 15 is subjected to exposure / development processing for patterning. The patterning is performed so that the resist film 15 does not remain in the bump electrode formation region. Then, as shown in FIG. 10, a gold film is formed as the conductor film 16 by using, for example, a plating method. After that, as shown in FIG. 11, the patterned resist film 15 and the UBM film 14 covered with the resist film 15 are removed, thereby forming the bump electrode 8 composed of the conductor film 16 and the UBM film 14. Next, the semiconductor substrate separated into pieces can be obtained by dicing the semiconductor substrate.

  According to the first embodiment, since the size of the pad 10 formed immediately below the bump electrode 8 is reduced, the wirings 11 a and 11 b can be formed immediately below the bump electrode 8. That is, since the pads 10 and the wirings 11a and 11b formed in the same layer as the pad 10 can be formed immediately below the bump electrode 8, the space formed immediately below the bump electrode 8 can be effectively utilized, and the semiconductor chip Can be miniaturized.

  In the method of manufacturing the semiconductor device according to the first embodiment, the pad 10 and the wirings 11a and 11b formed in the same layer as the pad 10 are formed except that they are patterned so as to be formed immediately below the bump electrode 8. It is the same as the manufacturing process. Therefore, the semiconductor device according to the first embodiment can be manufactured without complicating the manufacturing process. That is, it is possible to obtain an effect that does not require a significant change in the manufacturing process.

  Next, the semiconductor chip formed as described above is mounted on the mounting substrate. FIG. 12 shows a case where the semiconductor chip 1 is mounted on the glass substrate 17a (COG: Chip On Glass). As shown in FIG. 12, a glass substrate 17b is mounted on the glass substrate 17a, thereby forming an LCD display. A semiconductor chip 1 as a driver for the LCD is mounted on the glass substrate 17a in the vicinity of the display unit of the LCD. A bump electrode 8 is formed on the semiconductor chip 1, and the bump electrode 8 and a terminal formed on the glass substrate 17 a are connected via an anisotropic conductive film 19. A glass substrate 17 a and a flexible printed circuit 18 are also connected by an anisotropic conductive film 19. In the semiconductor chip 1 thus mounted on the glass substrate 17a, the output bump electrode 8 is electrically connected to the display portion of the LCD, and the input bump electrode 8 is connected to the flexible printed circuit board 18. .

  FIG. 13 is an enlarged view of a portion where the semiconductor chip 1 is mounted on the glass substrate 17a. In FIG. 13, a terminal 20a is formed on a glass substrate 17a, and a bump electrode 8 formed on the semiconductor chip 1 is electrically connected to the terminal 20a. At this time, the bump electrode 8 and the terminal 20 a are not in direct contact with each other, but are connected through the anisotropic conductive film 19.

  FIG. 14 is a diagram showing the overall configuration of the LCD. As shown in FIG. 14, an LCD display unit 20 is formed on a glass substrate, and an image is displayed on the display unit 20. A semiconductor chip 1 as a driver for LCD is mounted on a glass substrate in the vicinity of the display unit. A flexible printed circuit board 18 is mounted in the vicinity of the semiconductor chip 1, and the semiconductor chip 1 as a driver is mounted between the flexible printed circuit board 18 and the display unit 20 of the LCD. In this way, the semiconductor chip 1 can be mounted on the glass substrate 17a.

  The COG in which the semiconductor chip 1 is mounted on the glass substrate 17a has been described as an example of a mode in which the LCD driver is mounted on the mounting substrate. Next, another mode in which the semiconductor chip 1 is mounted will be described.

  FIG. 15 shows a state where the semiconductor chip 1 is mounted in a mounting form other than the COG form, and shows a TCP (Tape Carrier Package) form 21 and a COF (Chip On Film) form 22. FIG. 16 is a diagram illustrating a state in which the semiconductor chip 1 is mounted on the mounting substrate in the TCP form. In FIG. 16, the mounting substrate is a tape-like film substrate (tape substrate) 23, and leads 24 made of, for example, copper are formed on the film substrate 23. The semiconductor chip 1 is mounted on the film substrate 23 so that the bump electrode 8 is bonded to the lead 24. The semiconductor chip 1 is sealed with a resin 25. FIG. 17 is a diagram showing an example in which the semiconductor chip 1 mounted in the TCP form is disposed between the glass substrate 17a and the printed board 28. As shown in FIG. As shown in FIG. 17, the glass substrate 17a and the lead 24 formed on the film substrate 23 are connected by an anisotropic conductive film 26. Similarly, the lead 24 formed on the film substrate 23 and the printed circuit board 28 are connected to each other. Are connected by an anisotropic conductive film 27.

  FIG. 18 is a diagram illustrating a state in which the semiconductor chip 1 is mounted on the mounting substrate in the COF form. In FIG. 18, the mounting substrate is a tape-shaped film substrate 29. The lead 30 made of copper is formed on the film substrate 29 in the same manner as in the TCP form. However, unlike the TCP form, the lead 30 is fixed to the film substrate 29 even at a portion connected to the bump electrode 8. The semiconductor chip 1 is mounted on the film substrate 29 so that the bump electrodes 8 are bonded to the leads 30. An underfill 31 is formed in the gap between the semiconductor chip 1 and the film substrate 29. FIG. 19 is a diagram illustrating an example in which the semiconductor chip 1 mounted in the COF form is disposed between the glass substrate 17a and the printed circuit board 28. As shown in FIG. 19, the glass substrate 17a and the lead 30 formed on the film substrate 29 are connected by an anisotropic conductive film 26. Similarly, the lead 30 formed on the film substrate 29 and the printed circuit board 28 are connected to each other. Are connected by an anisotropic conductive film 27.

  As described above, the semiconductor chip 1 which is a driver for the LCD can be mounted in various forms.

(Embodiment 2)
In the second embodiment, a semiconductor device having a high degree of freedom in layout that can determine a pad formation position as an optimum position regardless of the position of a bump electrode will be described.

  FIG. 20 is a plan view showing a part of the semiconductor chip in the second embodiment. In FIG. 20, the pad 10 is connected to a pad connection portion 8 a constituting a part of the bump electrode 8 through an opening 13 formed in the surface protective film 12. The bump electrode 8 includes a pad connection portion 8a connected to the pad 10, a terminal connection portion 8c connected to a terminal of the mounting substrate, and a wiring portion 8b connecting the pad connection portion 8a and the terminal connection portion 8c. . Usually, the bump electrode is composed only of a terminal connection portion, and this terminal connection portion is connected to the pad. That is, in the normal bump electrode, the terminal connection portion also serves as the pad connection portion, and the pad connection portion and the terminal connection portion overlap in a plane. On the other hand, in the bump electrode 8 of the second embodiment, the pad connection portion 8a and the terminal connection portion 8c are formed at different positions on a plane, and the pad connection portion 8a formed at a different position on the plane. And the terminal connection portion 8c are connected by the wiring portion 8b. Further, the pad connection portion 8a and the terminal connection portion 8c are formed so that the wiring width of the planar shape is larger than that of the wiring portion 8b. This is because the pad connecting portion 8a and the terminal connecting portion 8c need to be connected to the pads 10 and the leads provided on the glass substrate (or film substrate), respectively, so that it is necessary to secure the plane area to some extent. . In the wiring part 8b, by reducing the wiring width, the possibility of contact with the other wiring part 8b can be prevented, and the degree of freedom of wiring can be increased.

  By configuring the bump electrodes 8 in this way, the pads 10 can be arranged in a row in the x direction without arranging the pads 10 in a zigzag pattern while arranging the terminal connection portions 8c of the bump electrodes 8 in a zigzag pattern. Become. That is, the position of the pad can be determined without being influenced by the arrangement position of the bump electrode. Usually, the bump electrode and the pad are arranged so as to overlap in a plane. Therefore, when the bump electrodes are arranged in a zigzag pattern in the y direction, the pads are also arranged in a zigzag pattern in the y direction. At this time, the pads are arranged in two rows, but wirings other than the pads cannot be routed to the places where the pads are arranged. For this reason, as described in the first embodiment, by reducing the size of the pad compared to the size of the bump electrode, even when a wiring other than the pad is formed immediately below the bump electrode, Since the pads are formed in two rows in the y direction, the space for forming the wiring other than the pads cannot be expanded accordingly. On the other hand, according to the second embodiment, even if the bump electrodes 8 are arranged in a zigzag pattern, the pads 10 do not need to be arranged in a zigzag pattern, and are arranged in a line in the x direction as shown in FIG. Is possible. Therefore, the space occupied by the pads 10 is reduced compared to the case where the pads 10 are arranged in two rows. As described above, since the space occupied by the pad 10 can be reduced, a sufficient space for forming the wirings 11 a to 11 k other than the pad 10 can be secured under the bump electrode 8 in the same layer as the pad 10. Thereby, the miniaturization of the semiconductor chip can be further promoted. Note that the shape of the wirings 11a to 11k formed immediately below the bump electrode 8 is not limited to a linear shape, and may be a bent shape or a curved shape.

  As described above, one of the features of the present invention is that the bump electrode 8 includes the pad connection portion 8a, the wiring portion 8b, and the terminal connection portion 8c, and the pad connection portion 8a and the terminal connection portion 8c are planarly formed. It is arranged so that it does not overlap. Here, the pad connection portion 8a, the wiring portion 8b, and the terminal connection portion 8c are formed in the same layer. With this configuration, the bump electrodes 8 are formed so as to extend in the y direction and arranged in a staggered manner, while the pads 10 can be arranged in a line in the x direction. Here, since the terminal connection part 8c which comprises the bump electrode 8 adhere | attaches with mounting substrates, such as a glass substrate, the width | variety becomes large compared with the width | variety of the wiring part 8b or the pad connection part 8a from a viewpoint of ensuring adhesive force. ing. In the present embodiment, the bump electrode 8 is composed of a pad connection portion 8a, a wiring portion 8b, and a terminal connection portion 8c. In other words, the bump electrode 8 has a narrow width wiring portion (first portion) 8b. It can also be said that the terminal connection portion (second portion) 8c is wider than the wiring portion 8b. With this configuration, the bump electrodes 8 can be arranged in a staggered manner at a narrow pitch while ensuring a contact area of the mounting substrate. That is, since the terminal connection portion 8c of the bump electrode 8 is a part that adheres to the mounting substrate, the area is relatively wide, while the wiring portion 8b only connects the pad connection portion and the terminal connection portion. By reducing the width, the bump electrodes 8 can be arranged in a staggered manner at a narrow pitch.

  According to the second embodiment, the position of the pad can be arranged at a position where the size of the semiconductor chip can be efficiently reduced without being influenced by the position of the bump electrode. That is, since the degree of freedom of the pad layout configuration can be improved, the size of the semiconductor chip can be efficiently reduced. Moreover, since the area of the terminal connection part 8c of the bump electrode 8 can be increased regardless of the pad 10, the adhesion area with the mounting substrate can be flexibly changed.

  The manufacturing method of the semiconductor device in the second embodiment is almost the same as that in the first embodiment. The difference is that when the bump electrode 8 is formed, the bump electrode 8 has a pad connection portion 8a, a wiring portion 8b, and a terminal connection portion 8c, and the pad connection portion 8a and the terminal connection portion 8c are planar. It is a point to form so as not to overlap. Then, the width of the terminal connection portion 8c is made wider than the width of the wiring portion 8b. In this way, the semiconductor device according to the second embodiment can be manufactured.

  Next, a modification of the second embodiment will be described. FIG. 21 is a plan view showing a modification of the second embodiment. FIG. 21 shows a case where the pads 10 are arranged in a line in the x direction and the terminal connection portions 8c of the bump electrodes 8 are arranged in a line in the y direction. Such a case can also be realized by configuring the bump electrode 8 from the pad connection portion 8a, the wiring portion 8b, and the terminal connection portion 8c. For example, even when the bump electrodes 8c are arranged in a line in the y direction as requested by the customer, the pads 10 can be arranged in a line in the x direction different from the y direction. That is, the pad 10 can be disposed regardless of the position where the terminal connection portion 8c is formed. Although not shown, in FIG. 21 as well, a wiring different from the pad 10 is formed in the same layer as the pad 10 immediately below the bump electrode 8. For this reason, the space which can be directly under the bump electrode 8 can be effectively utilized, and the semiconductor chip can be miniaturized. Furthermore, since the degree of freedom of the layout configuration of the pad 10 is improved, the semiconductor chip can be reduced in size by optimizing the arrangement position of the pad 10. In FIG. 21, the wiring portion 8b of the bump electrode 8 is formed from a shape bent at a right angle. However, the present invention is not limited to this. For example, the wiring portion 8b may be formed from a curved shape.

  FIG. 22 is a plan view showing a modification of the second embodiment. FIG. 22 shows a case where the pads 10 are arranged in a row in the x direction and the terminal connection portions 8c of the bump electrodes 8 are arranged in a staggered manner in the y direction. Such a case can also be realized by configuring the bump electrode 8 from the pad connection portion 8a, the wiring portion 8b, and the terminal connection portion 8c. For example, even when the bump electrodes 8c are arranged in a staggered manner in the y direction as requested by the customer, the pads 10 can be arranged in a row in the x direction different from the y direction. That is, the pad 10 can be disposed regardless of the position where the terminal connection portion 8c is formed. Although not shown, also in FIG. 22, wiring different from the pad 10 is formed in the same layer as the pad 10 immediately below the bump electrode 8. For this reason, the space which can be directly under the bump electrode 8 can be effectively utilized, and the semiconductor chip can be miniaturized. Furthermore, since the degree of freedom of the layout configuration of the pad 10 is improved, the semiconductor chip can be reduced in size by optimizing the arrangement position of the pad 10.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the example in which the positions of the bump electrode 8 and the pad 10 are arranged on the four sides of the semiconductor chip has been described, but the present invention is not limited to this. For example, it is possible to dispose the pads 10 near the four sides of the semiconductor chip 1 and extend the bump electrodes 8 to the center of the semiconductor chip 1. It is also possible to arrange the pads 10 in the center of the semiconductor chip 1 and extend the bump electrodes 8 to the vicinity of the four sides of the semiconductor chip 1.

  In the above-described embodiments, the LCD driver has been described as an example. However, the present invention is not limited to this, and the present invention can be widely applied to semiconductor devices having bump electrodes.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is the top view which showed the structure of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which showed the cross section cut | disconnected by the A-A 'line | wire of FIG. It is sectional drawing which showed the cross section cut | disconnected by the B-B 'line | wire of FIG. FIG. 2 is an enlarged view of a region indicated by a C line in FIG. 1, and is a plan view showing a state in which a wiring is formed immediately below a bump electrode arranged linearly. It is the enlarged view of the area | region shown by the D line of FIG. 1, Comprising: It is the top view which showed a mode that wiring was formed directly under the bump electrode arrange | positioned in zigzag form. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; It is the figure which showed the case where a semiconductor chip is mounted in a glass substrate. It is the figure which expanded the part which mounted the semiconductor chip on the glass substrate. It is the figure which showed the whole structure of LCD. It is the figure which showed the other structure of LCD. It is the figure which showed a mode that the semiconductor chip was mounted in the mounting board | substrate by the TCP form. It is a figure which shows the example which has arrange | positioned the semiconductor chip mounted with the TCP form between the glass substrate and the printed circuit board. It is the figure which showed a mode that the semiconductor chip was mounted in the mounting board | substrate by the COF form. It is a figure which shows the example which has arrange | positioned the semiconductor chip mounted with the COF form between the glass substrate and the printed circuit board. FIG. 6 is a plan view showing a part of a semiconductor chip in a second embodiment. FIG. 10 is a plan view showing a modification of the second embodiment. FIG. 10 is a plan view showing a modification of the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Semiconductor substrate 3 Gate drive circuit 4 Source drive circuit 5 Liquid crystal drive circuit 6 Graphic RAM
DESCRIPTION OF SYMBOLS 7 Peripheral circuit 8 Bump electrode 8a Pad connection part 8b Wiring part 8c Terminal connection part 9 Insulating film 10 Pad 11a-11k Wiring 12 Surface protective film 13 Opening part 14 UBM film 15 Resist film 16 Conductive film 17a Glass substrate 17b Glass substrate 18 Flexible Printed circuit board 19 Anisotropic conductive film 20 Display unit 20a Terminal 21 TCP form 22 COF form 23 Film board 24 Lead 25 Resin 26 Anisotropic conductive film 27 Anisotropic conductive film 28 Printed board 29 Film board 30 Lead 31 Underfill

Claims (10)

A semiconductor substrate formed in a rectangular shape;
A semiconductor element formed on the semiconductor substrate;
A first insulating film formed on the semiconductor substrate and covering the semiconductor element;
A pad electrode formed on the first insulating film;
A second insulating film formed to cover the pad electrode and having an opening above the pad electrode;
A bump electrode formed on the second insulating film and electrically connected to the pad electrode through the opening, and a part of the bump electrode is arranged to overlap the pad electrode in a plane A bump electrode,
The size of the pad electrode is formed smaller than the size of the bump electrode,
A plurality of the bump electrodes are arranged at predetermined intervals in a first direction along the long side of the semiconductor substrate,
Each of the bump electrodes is arranged such that the long side of the bump electrode is along the second direction along the short side of the semiconductor substrate,
The semiconductor device according to claim 1, wherein a width of the bump electrode in the first direction is smaller than a width of the pad electrode in the first direction. The semiconductor device according to claim 1,
A semiconductor device, wherein a plurality of wiring layers extending in the first direction are formed in a space immediately below the bump electrode. The semiconductor device according to claim 2,
The plurality of wiring layers are formed so as to overlap with the bump electrodes in a planar manner, and extend so as to intersect with the long sides of the bump electrodes. The semiconductor device according to claim 1,
A metal film serving as a base of the bump electrode is formed between the second insulating film and the bump electrode, and the bump electrode is electrically connected to the pad electrode through the metal film. A featured semiconductor device. The semiconductor device according to claim 4.
The semiconductor device, wherein the second insulating film is a silicon nitride film. The semiconductor device according to claim 5.
The semiconductor device, wherein the first insulating film is a silicon oxide film. The semiconductor device according to claim 4.
The bump device is composed of a gold film. The semiconductor device according to claim 3.
The semiconductor device, wherein the pad electrode and the plurality of wiring layers are conductor films formed in the same process. The semiconductor device according to claim 8.
The pad electrode and the wiring layer include an aluminum film and a titanium film and a titanium nitride film stacked on and under the aluminum film. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the pad electrode has a square shape.

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