JP2008091801A - Semiconductor device, and its manufacturing method - Google Patents

Semiconductor device, and its manufacturing method Download PDF

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JP2008091801A
JP2008091801A JP2006273527A JP2006273527A JP2008091801A JP 2008091801 A JP2008091801 A JP 2008091801A JP 2006273527 A JP2006273527 A JP 2006273527A JP 2006273527 A JP2006273527 A JP 2006273527A JP 2008091801 A JP2008091801 A JP 2008091801A
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conductor
electrode
solder material
semiconductor device
powder
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JP4973109B2 (en
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Mitsuo Yamashita
満男 山下
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/77—Apparatus for connecting with strap connectors
    • H01L2224/7725—Means for applying energy, e.g. heating means
    • H01L2224/77272—Oven
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
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    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a jointing part excellent in thermal resistance and thermal fatigue, and face-jointing a wiring conductor to a surface electrode of a semiconductor device and jointing the semiconductor device to a conductor substrate with high positional precision, using a soldering material free from lead. <P>SOLUTION: A solder paste of a Sn3.5Ag0.5Cu particle (melting temperature: 220°C) is applied on the surface of a conductor substrate 12; and a semiconductor device 14 is placed thereon. A cream solder of mixed particles (solidus temperature: 220°C, liquidus temperature: 345°C) of a Sn20Ag20Cu0.4Ni powder and a Sn3.5Ag0.5Cu0.07Ni0.01Ge powder in the weight ratio of 62:35, is applied on a surface electrode of the semiconductor device 14; and a wiring conductor 16 is placed thereon. The resultant is heated at 250°C in this state to melt the solder paste of the Sn3.5Ag0.5Cu particle and to make the cream solder of a Sn14.2Ag13.2Cu0.28Ni0.035Ge in total composition into a solid-liquid coexistence state. Then, the resultant is cooled to joint the conductor substrate 12, the semiconductor device 14 and the wiring conductor 16 through the Sn3.5Ag0.5Cu jointing material 17 and the Sn14.2Ag13.2Cu0.28Ni0.035Ge jointing material 15. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、半導体装置およびその製造方法に関し、特に半導体素子の表面電極および裏面電極にそれぞれ配線用導体および導体基板が面接合した構成の半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a configuration in which a wiring conductor and a conductor substrate are surface-bonded to a front electrode and a back electrode of a semiconductor element, respectively, and a manufacturing method thereof.

パワー半導体装置では、半導体素子で発生する熱をその裏面から放熱する構成となっている。図５は、従来のパワー半導体装置の要部を示す正面図である。図５において、符号１は絶縁基板であり、その表面に電気回路を兼ねる導体基板２が接合され、かつその裏面に図示しない冷却導体への熱伝導を担う熱伝導体３が接合されている。
さらに、導体基板２の表面に半導体素子４の裏面電極（図示省略）がはんだ材料５を用いて接合されている。半導体素子４の表面電極（図示省略）は、ボンディングワイヤ６を介して導体基板２に電気的に接続されている。熱伝導体３は、半導体パッケージの図示しない冷却導体である金属基板にはんだ材料を用いて接合されている。この金属基板は、図示しない外部冷却体とコンパウンドなどで密着されている。 The power semiconductor device is configured to dissipate heat generated in the semiconductor element from its back surface. FIG. 5 is a front view showing a main part of a conventional power semiconductor device. In FIG. 5, reference numeral 1 denotes an insulating substrate, a conductor substrate 2 also serving as an electric circuit is bonded to the front surface, and a heat conductor 3 responsible for heat conduction to a cooling conductor (not shown) is bonded to the back surface.
Further, a back electrode (not shown) of the semiconductor element 4 is bonded to the surface of the conductor substrate 2 using a solder material 5. A surface electrode (not shown) of the semiconductor element 4 is electrically connected to the conductor substrate 2 via a bonding wire 6. The heat conductor 3 is joined to a metal substrate which is a cooling conductor (not shown) of the semiconductor package using a solder material. This metal substrate is in close contact with an external cooling body (not shown) by a compound or the like.

半導体素子４は、通電時に熱を発生する。そして、半導体素子４と導体基板２の接合部が面接合であるため、その接合部には大きな熱ひずみが発生する。それによって、その接合部を構成するはんだ材料５は、過酷な使用環境下に置かれることになるので、そのはんだ材料には、高熱伝導性と熱疲労強度に優れた特性が要求される。そのような特性を備えたはんだ材料５として、従来、鉛入りの高温はんだ材料（溶融点２９０℃）が使用されていた。   The semiconductor element 4 generates heat when energized. And since the junction part of the semiconductor element 4 and the conductor substrate 2 is surface junction, a big thermal strain generate | occur | produces in the junction part. As a result, the solder material 5 constituting the joint portion is placed under a severe use environment, and therefore, the solder material is required to have characteristics excellent in high thermal conductivity and thermal fatigue strength. Conventionally, a high-temperature solder material containing lead (melting point 290 ° C.) has been used as the solder material 5 having such characteristics.

しかし、近時、環境上の配慮から、鉛を含まない（鉛フリー）はんだ材料を用いることが要求されている。この温度に対応可能な鉛フリーはんだ材料としてＡｕ−Ｓｎ合金があるが、高価であるため、実用的ではない。実用性の点から、鉛フリーはんだ材料としてＳｎＡｇはんだ材料（溶融点２２０℃）が適当である。
また、鉛フリーはんだ材料として、ＳｎまたはＳｎ合金からなる第１金属粉と、この第１金属粉よりも高い融点を持ち、ＣｕまたはＣｕ合金からなる第２金属粉とを含み、第１金属粉の含有割合が６０質量％より大きく８５質量％以下であり、第２金属粉の含有割合が１５質量％以上で４０質量％より小さい構成のものが公知である（例えば、特許文献１参照）。この特許文献１には、第１金属粉の平均粒径が３〜３０μｍであり、第２金属粉の平均粒径が５〜４０μｍであることと、はんだペーストにＡｇを多量に用いることが開示されている。
特開２００３−２４５７９３号公報 However, recently, due to environmental considerations, it is required to use a lead-free (lead-free) solder material. There is an Au-Sn alloy as a lead-free solder material that can cope with this temperature, but it is not practical because it is expensive. From the viewpoint of practicality, a SnAg solder material (melting point 220 ° C.) is suitable as a lead-free solder material.
Further, the lead-free solder material includes a first metal powder made of Sn or Sn alloy and a second metal powder made of Cu or Cu alloy having a higher melting point than the first metal powder. The content ratio is larger than 60 mass% and 85 mass% or less, and the content ratio of the second metal powder is 15 mass% or more and smaller than 40 mass% (for example, see Patent Document 1). This Patent Document 1 discloses that the average particle diameter of the first metal powder is 3 to 30 μm, the average particle diameter of the second metal powder is 5 to 40 μm, and that a large amount of Ag is used in the solder paste. Has been.
JP 2003-245793 A

近時、半導体パッケージの小型化、半導体素子の面積低減化に伴い、電流密度の増加が望まれている。また、半導体基板と導体基板の接合部の熱疲労信頼性および熱伝導性の一層の向上が望まれている。一方、従来のワイヤボンディング技術では、負荷電流レベルの限界にきており、パワーサイクル寿命の点でも、ボンディングワイヤと半導体素子の接合部の信頼性の要求が一層、厳しいものとなっている。   In recent years, an increase in current density has been desired along with miniaturization of semiconductor packages and reduction in area of semiconductor elements. In addition, it is desired to further improve the thermal fatigue reliability and thermal conductivity of the joint between the semiconductor substrate and the conductor substrate. On the other hand, the conventional wire bonding technology has reached the limit of the load current level, and the reliability of the bonding portion between the bonding wire and the semiconductor element is more severe in terms of power cycle life.

これらの対策として、半導体素子の表面の電流密度を均一化して温度分布の均一化を図るとともに、半導体素子の裏面側に加えて表面側からも熱を逃がす構造として、半導体素子の表面電極に配線用導体を面接合させてその接合面積を大きくすることが考えられる。この場合、配線用導体が銅材でできていると、半導体素子と配線用導体の間の熱膨張係数差が大きくなるため、その接合部の熱疲労に対する信頼性が厳しくなってしまう。   As measures against these problems, the current density on the surface of the semiconductor element is made uniform to make the temperature distribution uniform, and the heat is released from the front surface side in addition to the back surface side of the semiconductor element. It is conceivable to increase the bonding area by surface bonding of the conductor. In this case, if the wiring conductor is made of a copper material, the difference in thermal expansion coefficient between the semiconductor element and the wiring conductor becomes large, so that the reliability of the bonded portion against thermal fatigue becomes severe.

また、半導体素子の表面電極と配線用導体の接合、および半導体素子の裏面電極と導体基板の接合に、同じような接合温度を有するはんだ材料を用いて同時に接合する場合、その接合温度に加熱したときに半導体素子の上下ではんだ材料が溶融した状態となる。そのため、はんだの表面張力によって半導体素子や配線用導体が動きやすくなってしまい、半導体素子や配線用導体の接合位置の精度が低くなるという問題点がある。   In addition, when simultaneously bonding using a solder material having a similar bonding temperature to the bonding of the front electrode of the semiconductor element and the conductor for wiring, and the bonding of the back electrode of the semiconductor element to the conductor substrate, the heating was performed to the bonding temperature. Sometimes the solder material melts above and below the semiconductor element. Therefore, the semiconductor element and the wiring conductor are easily moved by the surface tension of the solder, and there is a problem that the accuracy of the joining position of the semiconductor element and the wiring conductor is lowered.

また、ＳｎＡｇはんだ材料（溶融点２２０℃）は、鉛入りの高温はんだ９５Ｐｂ５Ｓｎ（溶融点２９０℃）よりも耐熱性が低いという問題点がある。一方、金属の接合材料としてＡｇろうが公知である。しかし、Ａｇろうの接合温度が８００〜９００℃と高く、半導体素子の耐熱性、接合後の熱応力および剛性が高いことによる、ヒートサイクル・パワーサイクル時に半導体素子に及ぼす熱応力の影響などから望ましくない。   Further, the SnAg solder material (melting point 220 ° C.) has a problem that its heat resistance is lower than that of high-temperature solder 95Pb5Sn (melting point 290 ° C.) containing lead. On the other hand, Ag brazing is known as a metal bonding material. However, the bonding temperature of Ag brazing is as high as 800 to 900 ° C., which is desirable due to the effects of thermal stress on the semiconductor element during heat cycle and power cycle due to high heat resistance of the semiconductor element and high thermal stress and rigidity after bonding. Absent.

この発明は、上述した従来技術による問題点を解消するため、鉛フリーはんだ材料を用いて、耐熱性や熱疲労性に優れた接合部を実現することができる半導体装置およびその製造方法を提供することを目的とする。また、この発明は、鉛フリーはんだ材料を用いて、半導体素子の表面電極に配線用導体を面接合させるとともに、半導体素子を高い位置精度で導体基板に接合させることができる半導体装置およびその製造方法を提供することを目的とする。   The present invention provides a semiconductor device capable of realizing a joint having excellent heat resistance and thermal fatigue using a lead-free solder material, and a method for manufacturing the same, in order to eliminate the above-described problems caused by the prior art. For the purpose. In addition, the present invention provides a semiconductor device and a method for manufacturing the same, in which a conductor for wiring is surface bonded to a surface electrode of a semiconductor element using a lead-free solder material, and the semiconductor element is bonded to a conductor substrate with high positional accuracy. The purpose is to provide.

上述した問題を解決し、目的を達成するため、請求項１の発明にかかる半導体装置は、半導体素子と、該半導体素子の電極に接合された導体とを備えた半導体装置において、前記電極と前記導体との間に、Ag10〜20重量%, Cu2〜20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒をフラックスによりクリーム状としたはんだ材料の接合により形成される接合層を備えることを特徴とする。   In order to solve the above-described problem and achieve the object, a semiconductor device according to claim 1 is a semiconductor device including a semiconductor element and a conductor bonded to an electrode of the semiconductor element. A first powder containing 10 to 20% by weight of Ag and 2 to 20% by weight of Cu between the conductor and the balance consisting of Sn and unavoidable impurities, Ag 4% by weight or less (excluding 0), Cu 2 weight Characterized in that it comprises a joining layer formed by joining solder material containing a mixture of second powder consisting of Sn and unavoidable impurities and containing cream in the form of a cream with a content of not more than% (not including 0) And

また、請求項２の発明にかかる半導体装置は、半導体素子と、該半導体素子の第１の面および第２の面にそれぞれ設けられた第１の電極および第２の電極にそれぞれ接合された第１の導体および第２の導体とを備えた半導体装置において、前記第１の電極と前記第１の導体との間、および前記第２の電極と第２の導体との間に、Ag10〜20重量%, Cu2〜20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒をフラックスによりクリーム状としたはんだ材料の接合により形成される接合層を備えることを特徴とする。   According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor element; and a first electrode and a second electrode that are respectively provided on the first surface and the second surface of the semiconductor element. In a semiconductor device including one conductor and a second conductor, Ag10 to Ag20 are provided between the first electrode and the first conductor and between the second electrode and the second conductor. 1% powder containing Sn and unavoidable impurities, and 4% by weight or less of Ag (not including 0) and 2% by weight or less of Cu (not including 0) It is characterized by comprising a joining layer formed by joining solder materials in which a mixed powder of the second powder consisting of Sn and inevitable impurities is contained in a cream form with a flux.

また、請求項３の発明にかかる半導体装置は、半導体素子と、該半導体素子の第１の面および第２の面にそれぞれ設けられた第１の電極および第２の電極にそれぞれ接合された第１の導体および第２の導体とを備えた半導体装置において、前記第１の電極と第１の導体との間に、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状としたはんだ材料からなる第１の接合層、前記第２の電極と前記第２の導体との間に、鉛を含まない第２のはんだ材料からなる第２の接合層を備えることを特徴とする。   According to a third aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor element; and first and second electrodes respectively provided on the first surface and the second surface of the semiconductor element. In a semiconductor device comprising one conductor and a second conductor, Ag 10-20 wt%, Cu 2-20 wt% are contained between the first electrode and the first conductor, with the balance being Sn and First powder composed of inevitable impurities, Ag 4% by weight or less (not including 0), Cu 2% by weight or less (not including 0), the balance being Sn and inevitable impurities second A first bonding layer made of a solder material creamed with a powder mixture and flux, and a second solder material made of a second solder material that does not contain lead between the second electrode and the second conductor. It is characterized by comprising a bonding layer.

また、請求項４の発明にかかる半導体装置は、請求項３に記載の発明において、前記第２のはんだ材料の溶融温度が、前記第１のはんだ材料の液相線の温度よりも低いことを特徴とする。
また、請求項５の発明にかかる半導体装置は、請求項１ないし４に記載の発明において、前記第１の粉末はNi、Co、Fe、Geのうち、少なくとも一種類の添加元素を含有し、請求項６の発明にかかる半導体装置は、請求項1ないし５に記載の発明において、第２の粉末は、Ni、Co、Fe、Ge、Sb、Bi及びInのうち、少なくとも１種類の添加元素を含むことを特徴とする。 According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the melting temperature of the second solder material is lower than the liquidus temperature of the first solder material. Features.
The semiconductor device according to claim 5 is the semiconductor device according to any one of claims 1 to 4, wherein the first powder contains at least one additive element of Ni, Co, Fe, and Ge, A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the second powder is at least one additive element of Ni, Co, Fe, Ge, Sb, Bi, and In. It is characterized by including.

また、請求項７の発明にかかる半導体装置の製造方法は、半導体素子の電極に導体を接合するにあたって、前記電極と前記導体を、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状としたはんだ材料よりなる接合材料を介して貼り合わせる工程と、前記はんだ材料の固相線の温度以上で、かつ液相線の温度よりも低い温度で加熱して半溶融、固液共存状態とし、その後冷却して、接合固化させる工程と、を含むことを特徴とする。   According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: joining a conductor to an electrode of a semiconductor element, the electrode and the conductor containing Ag 10-20 wt%, Cu 2-20 wt%; Contains Sn and unavoidable impurities, Ag 4 wt% or less (not including 0), Cu 2 wt% or less (not including 0), with the balance consisting of Sn and unavoidable impurities A step of bonding through a joint material made of a solder material creamed with a mixture of the second powder and flux, and a temperature that is not lower than the temperature of the solidus of the solder material and lower than the temperature of the liquidus And a step of semi-melting and solid-liquid coexistence heating followed by cooling and solidifying the joint.

また、請求項８の発明にかかる半導体装置の製造方法は、半導体素子の第１の面および第２の面にそれぞれ第１の電極および第２の電極が設けられ、該第１の電極および第２の電極にそれぞれ第１の導体および第２の導体を接合するにあたって、前記第１の電極と前記第１の導体、および前記第２の電極と前記第２の導体を、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状としたはんだ材料からなる接合材料を介してそれぞれ貼り合わせる工程と、前記第１のはんだ材料の固相線の温度以上で、かつ液相線の温度よりも低い温度で加熱して半溶融、固液共存状態とし、その後冷却して、接合固化させる工程と、を含むことを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a first electrode and a second electrode are provided on a first surface and a second surface of a semiconductor element, respectively. In joining the first conductor and the second conductor to the two electrodes, respectively, the first electrode and the first conductor, and the second electrode and the second conductor are made of Ag10-20% by weight. , Cu2-20% by weight, the balance of the first powder consisting of Sn and unavoidable impurities, Ag 4% by weight (not including 0), Cu 2% by weight (not including 0) And bonding the mixture of the second powder composed of Sn and inevitable impurities with a bonding material composed of a solder material creamed with a flux, and the solid phase line of the first solder material. Heat at a temperature above or below the liquidus temperature and semi-dissolve Melting and solid-liquid coexistence state, and then cooling and joining and solidifying.

また、請求項９の発明にかかる半導体装置の製造方法は、半導体素子の第１の面および第２の面にそれぞれ第１の電極および第２の電極が設けられ、該第１の電極および第２の電極にそれぞれ第１の導体および第２の導体を接合するにあたって、前記第１の電極と第１の導体を、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状とした第１のはんだ材料よりなる第１の接合材料を介して貼り合わせるとともに、前記第２の電極と第２の導体を、鉛を含まない第２のはんだ材料よりなる第２の接合材料を介して貼り合わせる工程と、前記第１のはんだ材料の固相線の温度以上で、かつ前記第１のはんだ材料の液相線の温度よりも低く、さらに前記第２のはんだ材料の溶融温度以上の温度で加熱することにより、第１のはんだ材料が半溶融、固液共存状態とするとともに、前記第２のはんだ材料を溶かす工程と、その後冷却して、前記第１および第２のはんだ材料を固化させる工程と、を含むことを特徴とする。   According to a ninth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a first electrode and a second electrode are provided on a first surface and a second surface of a semiconductor element, respectively. In joining the first conductor and the second conductor to the two electrodes, respectively, the first electrode and the first conductor contain 10-20% by weight of Ag and 20% by weight of Cu, with the balance being Sn and First powder composed of inevitable impurities, Ag 4% by weight or less (not including 0), Cu 2% by weight or less (not including 0), the balance being Sn and inevitable impurities second A second solder not containing lead is bonded to the second electrode and the second conductor through a first bonding material made of a first solder material creamed with a mixed powder and flux. A step of bonding through a second bonding material made of a material, and the first solder By heating at a temperature equal to or higher than the solidus temperature of the material and lower than the liquidus temperature of the first solder material and further equal to or higher than the melting temperature of the second solder material, The solder material is in a semi-molten and solid-liquid coexistence state, and includes a step of melting the second solder material and a step of cooling to solidify the first and second solder materials. And

また、請求項１０の発明にかかる半導体装置の製造方法は、請求項７ないし９に記載の発明において、前記第１の粉末は、Ni、Co、Fe、Geのうち,少なくとも1種類の添加元素を含有することを特徴とし、請求項１１の発明にかかる半導体装置の製造方法は、請求項７ないし１０に記載の発明において、前記第２の粉末は、Cu、Ni、Co、Fe、Ge、Sb、BiおよびInのうち、少なくとも１種類の添加元素を含むことを特徴とする。   According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the seventh to ninth aspects, wherein the first powder is at least one additive element of Ni, Co, Fe, and Ge. The method of manufacturing a semiconductor device according to the invention of claim 11 is characterized in that, in the invention of claims 7 to 10, the second powder is Cu, Ni, Co, Fe, Ge, It contains at least one kind of additive element among Sb, Bi and In.

ＳｎＡｇ系のはんだ材料は、被接合材がＣｕである場合、はんだ材料中にＣｕが添加されていれば、被接合材からのＣｕの溶出を抑制することができるとともに、はんだ接合部の強度を向上させる効果があり、ＳｎＣｕ系やＳｎＳｂ系のはんだ材料と比較して、接合性や信頼性の点で優れている。ＳｎＡｇ系はんだ材料では、Ａｇの含有割合が７０質量％に至るまで、共晶反応を有し、固相線の温度は２２１℃である。また、完全に液化する液相線の温度は、Ａｇの含有量が増加するとともに上昇する。   When the material to be joined is Cu, the SnAg-based solder material can suppress elution of Cu from the material to be joined and can increase the strength of the solder joint portion if Cu is added to the solder material. It has the effect of improving and is superior in terms of bondability and reliability compared to SnCu-based and SnSb-based solder materials. The SnAg solder material has a eutectic reaction until the Ag content reaches 70% by mass, and the solidus temperature is 221 ° C. Further, the temperature of the liquidus that completely liquefies increases as the Ag content increases.

はんだ材料は固相線にて液化が開始するが、ＳｎＡｇ系はんだ材料の固体状態のミクロ組織が粗い場合には、金属組織の濃度分布により、液化している部分と固体部分が不均一に存在しやすくなり、固相線以上の広い温度範囲において、固液共存状態が粗い状態で存在しやすくなる。そのため、はんだ材料と被接合材との界面における接合反応を生じさせるには、接合温度として高温側までの加熱が必要となる。   The solder material starts to be liquefied by solid phase lines, but when the solid state microstructure of the SnAg solder material is rough, the liquefied part and the solid part are unevenly distributed due to the concentration distribution of the metal structure. In a wide temperature range above the solidus, the solid-liquid coexistence state tends to exist in a rough state. Therefore, in order to cause a bonding reaction at the interface between the solder material and the material to be bonded, heating up to a high temperature side is required as the bonding temperature.

Ag10〜20重量%, Cu 2〜20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒から成るはんだ材料とすることにより、Ｓｎ−Ａｇ−Ｃｕ３元共晶組成付近の組成のもの（代表的には、Ｓｎ３．５Ａｇ０．５Ｃｕ）よりも耐熱性が向上する。はんだ材料が微細な粒子で構成されていれば、その粒子内の成分濃度分布が少なく、また、成分拡散が生じやすいので、固相線以上の温度において均一に液化が生じやすくなり、比較的低温側で接合することができる。   A first powder containing 10 to 20% by weight of Ag, 2 to 20% by weight of Cu, and the balance consisting of Sn and inevitable impurities, Ag 4% by weight or less (excluding 0), Cu 2% by weight or less (0 Of the composition near Sn-Ag-Cu ternary eutectic composition (typically) by using a solder material comprising a mixture of second powder consisting of Sn and unavoidable impurities. Is more heat resistant than Sn3.5Ag0.5Cu). If the solder material is composed of fine particles, the component concentration distribution in the particles is small, and component diffusion is likely to occur, so that liquefaction tends to occur uniformly at temperatures above the solidus and relatively low temperatures. Can be joined on the side.

この発明では、ＳｎＡｇ系はんだ材料のＡｇの含有割合の下限は、３．５質量％Ａｇに共晶組成を有し、必要な固液共存温度範囲を有する液相線の温度である３００℃に相当する１０質量％である。Ａｇの含有割合が２０質量％以上であっても接合可能であるが、接合作業性として望ましい２５０〜３００℃付近での液化程度から、Ａｇの含有割合の上限は２０質量％であるのが適当である。さらに、Cu単独の量としては、接合部内におけるCuSn化合物の生成を容易とするため、下限２％とし、Cuが多過ぎると、CuSnの持つ強度が高く脆い性質が支配的となるため、Cu20%を上限とする。   In this invention, the lower limit of the Ag content ratio of the SnAg solder material is 300 ° C., which is the temperature of the liquidus having the eutectic composition at 3.5 mass% Ag and the necessary solid-liquid coexistence temperature range. The corresponding 10% by mass. Bonding is possible even when the Ag content is 20% by mass or more, but it is appropriate that the upper limit of the Ag content is 20% by mass because of the degree of liquefaction around 250 to 300 ° C., which is desirable for workability. It is. Furthermore, as the amount of Cu alone, the lower limit is set to 2% in order to facilitate the formation of a CuSn compound in the joint, and if there is too much Cu, the strength and brittleness of CuSn dominate, so Cu20% Is the upper limit.

また、固相線と液相線の温度範囲が広い場合、接合温度において固液共存状態となるので、はんだ材料の粘性が高い。それによって、接合作業中に半導体素子や配線用導体の動きが生じにくくなり、半導体素子や配線用導体を精度よく接合することができる。
はんだ材料の粒子の大きさは、通常のクリームはんだと同様、５〜５０μｍで十分であるが、さらに微粒子化すれば、粒子相互の拡散およびはんだ材料の溶融が促進されるので、有効である。また、粒子径を５〜２０μｍにすることにより、フラックス内に粒子を均一に分散させることができる。 Further, when the temperature range of the solidus line and the liquidus line is wide, the solder material has a high viscosity because it is in a solid-liquid coexistence state at the joining temperature. Thereby, the movement of the semiconductor element and the wiring conductor is less likely to occur during the bonding operation, and the semiconductor element and the wiring conductor can be bonded with high accuracy.
As for the size of the solder material particles, 5 to 50 μm is sufficient as in the case of ordinary cream solder. However, if the particle size is further reduced, diffusion between the particles and melting of the solder material are promoted, which is effective. Further, by setting the particle diameter to 5 to 20 μm, the particles can be uniformly dispersed in the flux.

本発明にかかる半導体装置およびその製造方法によれば、鉛フリーはんだ材料を用いて、階層はんだが可能となり、また、耐熱性を有するはんだ材料の接合と代表的鉛フリーはんだであるSnAg系はんだ材料の接合との同時接合が可能であり、温度耐熱性や熱疲労性に優れた接合部を実現することができるという効果を奏する。また、鉛フリーはんだ材料を用いて、半導体素子の表面電極に配線用導体を面接合させるとともに、半導体素子を高い位置精度で導体基板に接合させることができるという効果を奏する。   According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to perform hierarchical soldering using a lead-free solder material, and the joining of a heat-resistant solder material and a SnAg solder material that is a typical lead-free solder Simultaneous bonding with these can be performed, and an effect is achieved that it is possible to realize a bonded portion excellent in temperature heat resistance and thermal fatigue. Further, the lead-free solder material is used to bring the wiring conductor to the surface electrode of the semiconductor element, and the semiconductor element can be bonded to the conductor substrate with high positional accuracy.

以下に添付図面を参照して、この発明にかかる半導体装置およびその製造方法の好適な実施の形態を詳細に説明する。以下の実施の形態の説明および図面において、同様の構成には同一の符号を付し、重複する説明を省略する。
実施の形態１．
図１は、本発明の実施の形態１にかかる製造方法により製造された半導体装置の一例の要部を示す正面図である。図１に示すように、半導体素子１４の裏面電極（図示省略）は、導体基板１２の表面にＳｎ３．５Ａｇ０．５Ｃｕ接合部材１７を介して接合されている。その半導体素子１４の表面電極（図示省略）には、配線用導体１６がSn20Ag20Cu0.4NiとSn3.5Ag0.5Cu0.07Ni0.01Geの各粉末を重量比65:35の混合粒によるクリームはんだ接合材料（第１はんだ材料）による接合層（接合部総合組成Sn14.2Ag13.2Cu0.28Ni 0.0035Ge）１５を介して接合されている。ここで、配線用導体１６と半導体素子１４の表面電極（図示省略）は面接合しており、その接合面積は、従来のワイヤボンディング法によるワイヤの接着面積よりも大きい。本実施例におけるはんだ材料のNiの添加は、耐熱性向上、Geは接合性の改善をはかるためである。 Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description of the embodiments and drawings, the same components are denoted by the same reference numerals, and redundant description is omitted.
Embodiment 1 FIG.
FIG. 1 is a front view showing a main part of an example of a semiconductor device manufactured by the manufacturing method according to the first embodiment of the present invention. As shown in FIG. 1, the back electrode (not shown) of the semiconductor element 14 is bonded to the surface of the conductor substrate 12 via a Sn3.5Ag0.5Cu bonding member 17. On the surface electrode (not shown) of the semiconductor element 14, a cream solder bonding material (mixed grains with a weight ratio of 65:35) consisting of Sn20Ag20Cu0.4Ni and Sn3.5Ag0.5Cu0.07Ni0.01Ge is used as the wiring conductor 16. The first solder material is joined via a joining layer (joining portion total composition Sn14.2Ag13.2Cu0.28Ni 0.0035Ge) 15. Here, the wiring conductor 16 and the surface electrode (not shown) of the semiconductor element 14 are surface-bonded, and the bonding area is larger than the bonding area of the wire by the conventional wire bonding method. This is because the addition of Ni as the solder material in the present example improves heat resistance, and Ge improves bondability.

Sn20Ag20Cu0.4Niの粉末には、Niの代わりにCo、Fe、Geのうち少なくとも一種類の添加元素を含有させることができ、Sn3.5Ag0.5Cu0.07Ni0.01Geの粉末には、Ni、Geの代わりにCo、Fe、Sb、Bi及びInのうち、少なくとも１種類の添加元素を含有させることができる。
前者の場合には、Ni，Fe，Coは1.0重量%以下、Geは0.1重量%以下、後者の場合には、Ni、Co、Sb、Fe、Ge、BiおよびInのうち、少なくとも１種類の添加元素を合計で2重量％以下の割合で含むことが好ましい。 Sn20Ag20Cu0.4Ni powder can contain at least one additive element of Co, Fe, Ge instead of Ni, and Sn3.5Ag0.5Cu0.07Ni0.01Ge powder can contain Ni, Ge Instead, at least one additive element of Co, Fe, Sb, Bi, and In can be contained.
In the former case, Ni, Fe and Co are 1.0% by weight or less, and Ge is 0.1% by weight or less. In the latter case, at least one of Ni, Co, Sb, Fe, Ge, Bi and In is used. It is preferable to contain the additive elements in a proportion of 2% by weight or less in total.

次に、本発明の実施の形態１にかかる半導体装置の製造方法について説明する。まず、導体基板１２の表面に、Ｓｎ３．５Ａｇ０．５Ｃｕ粒子（粒子径：２０〜５０μｍ、溶融温度：２２０℃）を用いたはんだペーストを、例えば１００μｍの厚さに塗布する。そして、そのはんだペーストに接触するように、導体基板１２の上に半導体素子１４を置く。
続いて、半導体素子１４の表面電極の表面に、粒径が５〜２０μｍである第１はんだ材料（混合粒）（固相線の温度：２２０℃、液相線の温度：３４５℃）とフラックスを混合したクリームはんだを塗布する。半導体素子１４の表面電極の表面には、はんだ接合を可能とするために、Ｎｉめっきが施されている。その後、塗布したクリームはんだに配線用導体１６の被接合面が接触するように、半導体素子１４の上に配線用導体１６を置く。 Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described. First, a solder paste using Sn3.5Ag0.5Cu particles (particle diameter: 20 to 50 μm, melting temperature: 220 ° C.) is applied to the surface of the conductor substrate 12 to a thickness of 100 μm, for example. Then, the semiconductor element 14 is placed on the conductor substrate 12 so as to contact the solder paste.
Subsequently, a first solder material (mixed grain) having a particle size of 5 to 20 μm (solidus temperature: 220 ° C., liquidus temperature: 345 ° C.) and flux on the surface electrode surface of the semiconductor element 14. Apply the mixed cream solder. The surface of the surface electrode of the semiconductor element 14 is plated with Ni in order to enable solder bonding. Thereafter, the wiring conductor 16 is placed on the semiconductor element 14 so that the bonded surface of the wiring conductor 16 contacts the applied cream solder.

その状態で、導体基板１２、半導体素子１４および配線用導体１６を電気炉に入れ、第１はんだ材料（混合粒）の固相線の温度（２２０℃）以上、かつ液相線の温度（３４５℃）以下で、さらにＳｎ３．５Ａｇ０．５Ｃｕのクリームはんだの溶融温度（２２０℃）以上の温度、例えば２５０℃に加熱する。その際、Ｓｎ３．５Ａｇ０．５Ｃｕ粒子を用いたはんだペーストは溶融する。一方、第１はんだ材料（混合粒）とフラックスを混合したクリームはんだは、固液共存の状態となる。その後、冷却して、溶けたはんだを凝固させる。それによって、導体基板１２に半導体素子１４がＳｎ３．５Ａｇ０．５Ｃｕ接合部材１７を介して接合されるとともに、半導体素子１４に配線用導体１６が第１はんだ材料（混合粒）による接合部１５を介して接合され、図１に示す構成の半導体装置が得られる。   In this state, the conductor substrate 12, the semiconductor element 14 and the wiring conductor 16 are put in an electric furnace, and the temperature of the solidus line of the first solder material (mixed grains) (220 ° C.) or higher and the temperature of the liquidus line (345 ° C) or lower and further heated to a temperature equal to or higher than the melting temperature (220 ° C) of the Sn3.5Ag0.5Cu cream solder, for example, 250 ° C. At that time, the solder paste using Sn3.5Ag0.5Cu particles melts. On the other hand, the cream solder obtained by mixing the first solder material (mixed grain) and the flux is in a solid-liquid coexistence state. Then, it cools and solidifies the melted solder. Thereby, the semiconductor element 14 is bonded to the conductor substrate 12 via the Sn3.5Ag0.5Cu bonding member 17, and the wiring conductor 16 is bonded to the semiconductor element 14 via the bonding portion 15 made of the first solder material (mixed grain). Thus, the semiconductor device having the structure shown in FIG. 1 is obtained.

ここで、Ｓｎ３．５Ａｇ０．５Ｃｕ粒子を用いたはんだペーストは一旦溶融した後に固化するため、溶融前の形態は粒子を用いたペーストに限らない。例えばＳｎ３．５Ａｇ０．５Ｃｕのシート状のはんだを用いてもよい。
なお、図２に示すように、導体基板１２と半導体素子１４の裏面電極を第１はんだ材料（混合粒、総合組成Sn14.2Ag13.2Cu0.28Ni 0.0035Ge）からなる接合部材１５により接合し、半導体素子１４の表面電極と配線用導体１６をＳｎ３．５Ａｇ０．５Ｃｕ接合部材１７により接合してもよい。この場合には、導体基板１２の表面に、第１はんだ材料（混合粒）とフラックスを混合したクリームはんだを塗布し、その上に半導体素子１４を置く。そして、半導体素子１４の表面電極の表面に、第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕ粒子を用いたはんだペーストを塗布し、その上に配線用導体１６を置く。その状態で、電気炉で第１はんだ材料（混合粒）の固相線の温度（２２０℃）以上、かつ液相線の温度（３４５℃）以下で、さらに第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕのクリームはんだの溶融温度（２２０℃）以上の温度、例えば２５０℃に加熱した後、冷却すればよい。 Here, since the solder paste using Sn3.5Ag0.5Cu particles is once melted and then solidified, the form before melting is not limited to the paste using particles. For example, Sn3.5Ag0.5Cu sheet-like solder may be used.
As shown in FIG. 2, the conductor substrate 12 and the back electrode of the semiconductor element 14 are joined by a joining member 15 made of a first solder material (mixed grain, total composition Sn14.2Ag13.2Cu0.28Ni 0.0035Ge). The surface electrode of the element 14 and the wiring conductor 16 may be joined by the Sn3.5Ag0.5Cu joining member 17. In this case, a cream solder in which a first solder material (mixed grain) and a flux are mixed is applied to the surface of the conductor substrate 12, and the semiconductor element 14 is placed thereon. Then, a solder paste using the second solder material Sn3.5Ag0.5Cu particles is applied to the surface of the surface electrode of the semiconductor element 14, and the wiring conductor 16 is placed thereon. In this state, the temperature of the solidus line of the first solder material (mixed grains) is not less than 220 ° C. and not more than the temperature of the liquidus line (345 ° C.) in the electric furnace, and further the second solder material Sn3.5Ag0.5Cu What is necessary is just to cool, after heating to the temperature more than the melting temperature (220 degreeC) of the cream solder of this, for example, 250 degreeC.

また、図３に示すように、導体基板１２と半導体素子１４の裏面電極、および半導体素子１４の表面電極と配線用導体１６の両方を第１はんだ材料（混合粒）接合部材１５により接合してもよい。この場合には、導体基板１２の表面に、第１はんだ材料（混合粒）とフラックスを混合したクリームはんだを塗布し、その上に半導体素子１４を置く。そして、半導体素子１４の表面電極の表面に、同じクリームはんだを塗布し、その上に配線用導体１６を置く。その状態で、電気炉で第１はんだ材料（混合粒）の固相線の温度（２２０℃）以上、かつ液相線の温度（３４５℃）以下、例えば２５０℃に加熱した後、冷却すればよい。   Further, as shown in FIG. 3, both the conductor substrate 12 and the back electrode of the semiconductor element 14, and both the front electrode of the semiconductor element 14 and the wiring conductor 16 are joined by the first solder material (mixed grain) joining member 15. Also good. In this case, a cream solder in which a first solder material (mixed grain) and a flux are mixed is applied to the surface of the conductor substrate 12, and the semiconductor element 14 is placed thereon. And the same cream solder is apply | coated to the surface of the surface electrode of the semiconductor element 14, and the conductor 16 for wiring is put on it. In that state, if the electric furnace is heated to a temperature of the solidus line (220 ° C.) of the first solder material (mixed grains) or higher and a temperature of the liquidus line (345 ° C.) or lower, for example, 250 ° C., then cooled. Good.

実施の形態１によれば、第１はんだ材料（混合粒）の固相線と液相線の間の温度で、第１はんだ材料（混合粒）の液化が均一に生じやすいので、比較的低温側ではんだ接合を行うことができる。従って、はんだ接合部の耐熱性が向上し、また、熱疲労強度が向上する。また、加熱したときに、第１はんだ材料（混合粒）を含むクリームはんだが固液共存の状態となり、高い粘性を有するので、半導体素子１４と配線用導体１６の相互の動きが抑制される。従って、半導体素子１４および配線用導体１６を高い位置精度で接合することができる。   According to the first embodiment, liquefaction of the first solder material (mixed grain) is likely to occur uniformly at a temperature between the solidus line and the liquidus line of the first solder material (mixed grain), so that the temperature is relatively low. Can be soldered on the side. Therefore, the heat resistance of the solder joint is improved and the thermal fatigue strength is improved. Further, when heated, the cream solder containing the first solder material (mixed grains) is in a solid-liquid coexistence state and has a high viscosity, so that the movement of the semiconductor element 14 and the wiring conductor 16 is suppressed. Therefore, the semiconductor element 14 and the wiring conductor 16 can be joined with high positional accuracy.

実施の形態２．
図４は、本発明の実施の形態２にかかる製造方法により製造された半導体装置の一例の要部を示す正面図である。図４に示すように、実施の形態２では、半導体パッケージの外部冷却体への熱導体となる例えば金属基板よりなる熱伝導部材１８の表面に、アルミナ等からなる絶縁基板１１の裏面に設けられた熱伝導体１３の裏面が第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕによる接合部材１７を介して接合されている。そして、絶縁基板１１の表面に設けられた、電気回路を兼ねる導体基板１２の表面に、半導体素子１４の裏面電極が第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕによる接合部材１７を介して接合されている。半導体素子１４の表面電極には、配線用導体１６が第１はんだ材料（混合粒）１５を介して接合されている。 Embodiment 2. FIG.
FIG. 4 is a front view showing a main part of an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment of the present invention. As shown in FIG. 4, in the second embodiment, the heat conducting member 18 made of, for example, a metal substrate serving as a heat conductor to the external cooling body of the semiconductor package is provided on the back surface of the insulating substrate 11 made of alumina or the like. The back surface of the heat conductor 13 is joined via a joining member 17 made of the second solder material Sn3.5Ag0.5Cu. Then, the back electrode of the semiconductor element 14 is bonded to the surface of the conductor substrate 12 also serving as an electric circuit provided on the surface of the insulating substrate 11 via the bonding member 17 made of the second solder material Sn3.5Ag0.5Cu. . A wiring conductor 16 is bonded to the surface electrode of the semiconductor element 14 via a first solder material (mixed grain) 15.

次に、本発明の実施の形態２にかかる半導体装置の製造方法について説明する。まず、熱伝導部材１８の表面に、第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕ粒子（粒子径：２０〜５０μｍ、溶融温度：２２０℃）を用いたクリームはんだを塗布する。そして、そのクリームはんだに絶縁基板１１の熱伝導体１３が接触するように、熱伝導部材１８の上に絶縁基板１１を置く。   Next, a method for manufacturing the semiconductor device according to the second embodiment of the present invention will be described. First, cream solder using the second solder material Sn3.5Ag0.5Cu particles (particle diameter: 20 to 50 μm, melting temperature: 220 ° C.) is applied to the surface of the heat conducting member 18. Then, the insulating substrate 11 is placed on the heat conducting member 18 so that the heat conductor 13 of the insulating substrate 11 contacts the cream solder.

続いて、絶縁基板１１の導体基板１２の表面に、同じ第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕ粒子を用いたクリームはんだを塗布する。そして、そのクリームはんだに接触するように、導体基板１２の上に半導体素子１４を置く。さらに、半導体素子１４の表面電極の表面に、粒径が５〜２０μｍである第１はんだ材料（混合粒）（固相線の温度：２２０℃、液相線の温度：３４５℃）とフラックスを混合したクリームはんだを塗布する。半導体素子１４の表面電極の表面には、はんだ接合を可能とするために、Ｎｉめっきが施されている。その後、塗布したクリームはんだに配線用導体１６の被接合面が接触するように、半導体素子１４の上に配線用導体１６を置く。   Subsequently, cream solder using the same second solder material Sn3.5Ag0.5Cu particles is applied to the surface of the conductor substrate 12 of the insulating substrate 11. Then, the semiconductor element 14 is placed on the conductor substrate 12 so as to contact the cream solder. Further, a first solder material (mixed grain) having a particle diameter of 5 to 20 μm (solidus temperature: 220 ° C., liquidus temperature: 345 ° C.) and flux are applied to the surface electrode surface of the semiconductor element 14. Apply mixed cream solder. The surface of the surface electrode of the semiconductor element 14 is plated with Ni in order to enable solder bonding. Thereafter, the wiring conductor 16 is placed on the semiconductor element 14 so that the bonded surface of the wiring conductor 16 contacts the applied cream solder.

その状態で、熱伝導部材１８、絶縁基板１１、半導体素子１４および配線用導体１６を電気炉に入れ、例えば２５０℃に加熱する。その際、Ｓｎ３．５Ａｇ０．５Ｃｕ粒子を用いたクリームはんだは溶融する。一方、第１はんだ材料（混合粒）とフラックスを混合したクリームはんだは、固液共存の状態となる。その後、冷却して、溶けたはんだを凝固させる。それによって、熱伝導部材１８に絶縁基板１１が第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕ接合部材１７を介して接合され、かつ導体基板１２に半導体素子１４がＳｎ３．５Ａｇ０．５Ｃｕ接合部材１７を介して接合され、さらに半導体素子１４に配線用導体１６が第１はんだ材料（混合粒）による接合部材１５を介して接合され、図４に示す構成の半導体装置が得られる。   In this state, the heat conducting member 18, the insulating substrate 11, the semiconductor element 14, and the wiring conductor 16 are placed in an electric furnace and heated to, for example, 250 ° C. At that time, the cream solder using Sn3.5Ag0.5Cu particles melts. On the other hand, the cream solder obtained by mixing the first solder material (mixed grain) and the flux is in a solid-liquid coexistence state. Then, it cools and solidifies the melted solder. Thereby, the insulating substrate 11 is bonded to the heat conducting member 18 via the second solder material Sn3.5Ag0.5Cu bonding member 17, and the semiconductor element 14 is bonded to the conductor substrate 12 via the Sn3.5Ag0.5Cu bonding member 17. Further, the wiring conductor 16 is joined to the semiconductor element 14 via the joining member 15 made of the first solder material (mixed grains), and the semiconductor device having the configuration shown in FIG. 4 is obtained.

なお、導体基板１２と半導体素子１４の裏面電極を第１はんだ材料（混合粒）による接合部材１５により接合し、半導体素子１４の表面電極と配線用導体１６を第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕ接合部材１７により接合してもよいし、導体基板１２と半導体素子１４の裏面電極、および半導体素子１４の表面電極と配線用導体１６の両方を第１はんだ材料（混合粒）による接合部材１５により接合してもよい。さらに、熱伝導部材１８と絶縁基板１１を第１はんだ材料（混合粒）１５により接合してもよい。実施の形態２によれば、実施の形態１と同様の効果が得られる。   The conductor substrate 12 and the back electrode of the semiconductor element 14 are joined by the joining member 15 made of the first solder material (mixed grains), and the surface electrode of the semiconductor element 14 and the wiring conductor 16 are joined to the second solder material Sn3.5Ag0.5Cu. The bonding member 17 may bond the conductive substrate 12 and the back electrode of the semiconductor element 14, and both the front electrode of the semiconductor element 14 and the wiring conductor 16 may be bonded by the bonding member 15 made of the first solder material (mixed grains). You may join. Further, the heat conducting member 18 and the insulating substrate 11 may be joined by the first solder material (mixed grain) 15. According to the second embodiment, the same effect as in the first embodiment can be obtained.

以上において本発明は、上述した実施の形態に限らず、種々変更可能である。例えば、はんだ接合温度は、２５０℃に限らず、第１はんだ材料（混合粒）の固相線の温度以上で、かつ第１はんだ材料（混合粒）の液相線の温度よりも低く、さらに第２はんだ材料Ｓｎ３．５Ａｇ０．５Ｃｕ粒子を用いたはんだペーストまたはクリームはんだの溶融温度以上の温度であればよい。   As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the solder bonding temperature is not limited to 250 ° C., and is equal to or higher than the solidus temperature of the first solder material (mixed grain) and lower than the liquidus temperature of the first solder material (mixed grain). What is necessary is just the temperature more than the melting temperature of the solder paste or cream solder using the 2nd solder material Sn3.5Ag0.5Cu particle | grains.

以上のように、本発明にかかる半導体装置の製造方法は、半導体素子の表面電極と配線用導体が面接合された構成を有する半導体装置に有用であり、特に、通電時の発熱量が多いパワー半導体装置に適している。   As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a semiconductor device having a configuration in which a surface electrode of a semiconductor element and a wiring conductor are surface-bonded, and in particular, a power that generates a large amount of heat when energized. Suitable for semiconductor devices.

本発明の実施の形態１にかかる製造方法により製造された半導体装置の一例の要部を示す正面図である。It is a front view which shows the principal part of an example of the semiconductor device manufactured by the manufacturing method concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる製造方法により製造された半導体装置の別の例の要部を示す正面図である。It is a front view which shows the principal part of another example of the semiconductor device manufactured by the manufacturing method concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる製造方法により製造された半導体装置のさらに別の例の要部を示す正面図である。It is a front view which shows the principal part of another example of the semiconductor device manufactured by the manufacturing method concerning Embodiment 1 of this invention. 本発明の実施の形態２にかかる製造方法により製造された半導体装置の一例の要部を示す正面図である。It is a front view which shows the principal part of an example of the semiconductor device manufactured by the manufacturing method concerning Embodiment 2 of this invention. 従来の半導体装置の要部を示す正面図である。It is a front view which shows the principal part of the conventional semiconductor device.

符号の説明Explanation of symbols

１２，１６ 導体
１４ 半導体素子
１５ 第１のはんだ材料の粒子よりなる接合材料
１７ 第２のはんだ材料の粒子よりなる接合材料 12, 16 Conductor 14 Semiconductor element 15 Joining material made of particles of first solder material 17 Joining material made of particles of second solder material

Claims (11)

半導体素子と、該半導体素子の電極に接合された導体とを備えた半導体装置において、前記電極と前記導体との間に、Ag10〜20重量%, Cu2〜20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒をフラックスによりクリーム状としたはんだ材料の接合により形成される接合層を備えることを特徴とする半導体装置。 In a semiconductor device comprising a semiconductor element and a conductor bonded to an electrode of the semiconductor element, Ag is contained between 10 and 20% by weight, Cu is contained between 20 and 20% by weight, and the balance is Sn. And a first powder composed of inevitable impurities, Ag 4 wt% or less (excluding 0), Cu2 wt% or less (not including 0), the balance being Sn and inevitable impurities second A semiconductor device comprising a bonding layer formed by bonding a solder material in which powder mixed particles are creamed with a flux. 半導体素子と、該半導体素子の第１の面および第２の面にそれぞれ設けられた第１の電極および第２の電極にそれぞれ接合された第１の導体および第２の導体とを備えた半導体装置において、前記第１の電極と第１の導体との間、および前記第２の電極と第２の導体との間に、Ag10〜20重量%, Cu2〜20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒をフラックスによりクリーム状としたはんだ材料の接合により形成される接合層を備えることを特徴とする半導体装置。 Semiconductor comprising: a semiconductor element; and a first conductor and a second conductor respectively joined to a first electrode and a second electrode provided on the first surface and the second surface of the semiconductor element, respectively In the apparatus, between the first electrode and the first conductor and between the second electrode and the second conductor, Ag of 10 to 20 wt%, Cu of 2 to 20 wt% are contained, and the balance is First powder composed of Sn and unavoidable impurities, Ag 4% by weight or less (excluding 0), Cu2% by weight or less (not including 0), the remainder comprising Sn and unavoidable impurities A semiconductor device comprising: a bonding layer formed by bonding a solder material in which a mixed powder of powder is creamed with a flux. 半導体素子と、該半導体素子の第１の面および第２の面にそれぞれ設けられた第１の電極および第２の電極にそれぞれ接合された第１の導体および第２の導体とを備えた半導体装置において、前記第１の電極と第１の導体との間に、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状としたはんだ材料からなる第１の接合層、前記第２の電極と前記第２の導体との間に、鉛を含まない第２のはんだ材料からなる第２の接合層を備えることを特徴とする半導体装置。 Semiconductor comprising: a semiconductor element; and a first conductor and a second conductor respectively joined to a first electrode and a second electrode provided on the first surface and the second surface of the semiconductor element, respectively In the apparatus, between the first electrode and the first conductor, Ag 10-20 wt%, Cu 2-20 wt% are contained, and the balance of the first powder consisting of Sn and inevitable impurities, Ag 4 Solder material containing 2% by weight or less (excluding 0), 2% by weight or less of Cu (not including 0), and the balance of the second powder consisting of Sn and inevitable impurities and creamed by flux A semiconductor device comprising: a first bonding layer comprising: a second bonding layer made of a second solder material not containing lead between the second electrode and the second conductor. 前記第２のはんだ材料の溶融温度が、前記第１のはんだ材料の液相線の温度よりも低いことを特徴とする請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein a melting temperature of the second solder material is lower than a temperature of a liquidus of the first solder material. 前記第１の粉末は、Ni、Co、Fe、Geのうち,少なくとも1種類の添加元素を含有することを特徴とする請求項１ないし４のいずれか1項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the first powder contains at least one additive element of Ni, Co, Fe, and Ge. 前記第２の粉末は、Cu、Ni、Co、Fe、Ge、Sb、BiおよびInのうち、少なくとも１種類の添加元素を含むことを特徴とする請求項１ないし５のいずれか１項に記載の半導体装置。 6. The second powder according to claim 1, wherein the second powder contains at least one additive element of Cu, Ni, Co, Fe, Ge, Sb, Bi, and In. Semiconductor device. 半導体素子の電極に導体を接合するにあたって、前記電極と前記導体を、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状としたはんだ材料からなる接合材料を介して貼り合わせる工程と、前記はんだ材料の固相線の温度以上で、かつ液相線の温度よりも低い温度で加熱して半溶融、固液共存状態とし、その後冷却して、接合固化させる工程と、を含むことを特徴とする半導体装置の製造方法。 In joining a conductor to an electrode of a semiconductor element, the electrode and the conductor are each composed of Ag 10-20 wt%, Cu 2-20 wt%, with the balance being a first powder composed of Sn and inevitable impurities, Ag 4 Solder material containing 2% by weight or less (excluding 0), 2% by weight or less of Cu (not including 0), and the balance of the second powder consisting of Sn and inevitable impurities and creamed by flux A step of bonding via a joining material comprising: heating at a temperature equal to or higher than the solidus temperature of the solder material and lower than the temperature of the liquidus temperature to be in a semi-molten, solid-liquid coexisting state, and then cooled. And a step of bonding and solidifying the semiconductor device. 半導体素子の第１の面および第２の面にそれぞれ第１の電極および第２の電極が設けられ、該第１の電極および第２の電極にそれぞれ第１の導体および第２の導体を接合するにあたって、前記第１の電極と第１の導体、および前記第２の電極と第２の導体を、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状としたはんだ材料からなる接合材料を介してそれぞれ貼り合わせる工程と、前記はんだ材料の固相線の温度以上で、かつ液相線の温度よりも低い温度で加熱して半溶融、固液共存状態とし、その後冷却して、接合固化させる工程と、を含むことを特徴とする半導体装置の製造方法。 A first electrode and a second electrode are respectively provided on the first surface and the second surface of the semiconductor element, and the first conductor and the second conductor are joined to the first electrode and the second electrode, respectively. The first electrode and the first conductor, and the second electrode and the second conductor contain 10-20% by weight of Ag and 20% by weight of Cu, and the balance is Sn and inevitable impurities. A mixture of the first powder and the second powder containing 4% by weight or less of Ag (not including 0) and 2% by weight or less of Cu (not including 0), the balance being Sn and inevitable impurities And a step of laminating each of them through a bonding material made of a solder material creamed with flux, and semi-melting by heating at a temperature higher than the solidus temperature of the solder material and lower than the liquidus temperature And solid-liquid coexistence state, and then cooling and joining and solidifying. A method of manufacturing a semiconductor device. 半導体素子の第１の面および第２の面にそれぞれ第１の電極および第２の電極が設けられ、該第１の電極および第２の電極にそれぞれ第１の導体および第２の導体を接合するにあたって、前記第１の電極と第１の導体を、Ag10-20重量%, Cu2-20重量%を含有し、残部がSnおよび不可避的不純物からなる第１の粉末と、Ag 4重量%以下（０を含まず）、Cu 2重量%以下（０を含まず）を含有し、残部がSnおよび不可避的不純物からなる第２の粉末の混粒とフラックスによりクリーム状とした第１のはんだ材料よりなる第１の接合材料を介して貼り合わせるとともに、前記第２の電極と第２の導体を、鉛を含まない第２のはんだ材料よりなる第２の接合材料を介して貼り合わせる工程と、前記第１のはんだ材料の固相線の温度以上で、かつ前記第１のはんだ材料の液相線の温度よりも低く、さらに前記第２のはんだ材料の溶融温度以上の温度で加熱することにより、第１のはんだ材料が半溶融、固液共存状態とするとともに、前記第２のはんだ材料を溶かす工程と、その後冷却して、前記第１および第２のはんだ材料を固化させる工程と、を含むことを特徴とする半導体装置の製造方法。 A first electrode and a second electrode are respectively provided on the first surface and the second surface of the semiconductor element, and the first conductor and the second conductor are joined to the first electrode and the second electrode, respectively. In the first electrode and the first conductor, the first powder containing 10-20% by weight of Ag and 2-20% by weight of Cu, with the balance being Sn and inevitable impurities, and Ag 4% by weight or less First solder material creamed with a mixture of a second powder consisting of Sn and unavoidable impurities and flux containing 2% by weight or less of Cu (excluding 0) (excluding 0) and Cu (not including 0) A step of bonding the second electrode and the second conductor together via a second bonding material made of a second solder material not containing lead; The first solder material is at or above the solidus temperature of the first solder material. The temperature of the liquid phase line is lower than that of the second solder material and is heated at a temperature equal to or higher than the melting temperature of the second solder material. A method of manufacturing a semiconductor device, comprising: a step of melting a solder material; and a step of cooling thereafter to solidify the first and second solder materials. 前記第１の粉末は、Ni、Co、Fe、Geのうち,少なくとも1種類の添加元素を含有することを特徴とする請求項7ないし９のいずれか1項に記載の半導体装置の製造方法。 10. The method for manufacturing a semiconductor device according to claim 7, wherein the first powder contains at least one additive element of Ni, Co, Fe, and Ge. 前記第２の粉末は、Cu、Ni、Co、Fe、Ge、Sb、BiおよびInのうち、少なくとも１種類の添加元素を含むことを特徴とする請求項7ないし１０のいずれか1項に記載の半導体装置の製造方法。 11. The second powder according to claim 7, wherein the second powder contains at least one additive element of Cu, Ni, Co, Fe, Ge, Sb, Bi, and In. Semiconductor device manufacturing method.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102717200A (en) * 2012-06-26 2012-10-10 高新锡业（惠州）有限公司 Lead-free soft braze welding material and preparation method of lead-free soft braze welding material
JP2020204599A (en) * 2019-06-19 2020-12-24 昭和電工マテリアルズ株式会社 Method for evaluating joint material and evaluation testing device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127160A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor device
JPH06269981A (en) * 1993-03-18 1994-09-27 Tokuriki Honten Co Ltd Ag solder
JPH08139243A (en) * 1994-11-07 1996-05-31 Rohm Co Ltd Manufacture of semiconductor device
JPH0929480A (en) * 1995-07-19 1997-02-04 Fujitsu Ltd Solder paste
JPH11186712A (en) * 1997-12-24 1999-07-09 Nissan Motor Co Ltd Solder paste and connecting method
JP2000343273A (en) * 1999-06-01 2000-12-12 Fuji Electric Co Ltd Soldering alloy
JP2003245793A (en) * 2002-02-26 2003-09-02 Tdk Corp Soldering composition, soldering method, and electronic component
JP3627591B2 (en) * 1999-10-07 2005-03-09 富士電機機器制御株式会社 Power semiconductor module manufacturing method
JP2006512212A (en) * 2002-12-31 2006-04-13 モトローラ・インコーポレイテッド Lead-free solder paste made of mixed alloy
JP2006287064A (en) * 2005-04-01 2006-10-19 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52127160A (en) * 1976-04-19 1977-10-25 Toshiba Corp Semiconductor device
JPH06269981A (en) * 1993-03-18 1994-09-27 Tokuriki Honten Co Ltd Ag solder
JPH08139243A (en) * 1994-11-07 1996-05-31 Rohm Co Ltd Manufacture of semiconductor device
JPH0929480A (en) * 1995-07-19 1997-02-04 Fujitsu Ltd Solder paste
JPH11186712A (en) * 1997-12-24 1999-07-09 Nissan Motor Co Ltd Solder paste and connecting method
JP2000343273A (en) * 1999-06-01 2000-12-12 Fuji Electric Co Ltd Soldering alloy
JP3627591B2 (en) * 1999-10-07 2005-03-09 富士電機機器制御株式会社 Power semiconductor module manufacturing method
JP2003245793A (en) * 2002-02-26 2003-09-02 Tdk Corp Soldering composition, soldering method, and electronic component
JP2006512212A (en) * 2002-12-31 2006-04-13 モトローラ・インコーポレイテッド Lead-free solder paste made of mixed alloy
JP2006287064A (en) * 2005-04-01 2006-10-19 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102717200A (en) * 2012-06-26 2012-10-10 高新锡业（惠州）有限公司 Lead-free soft braze welding material and preparation method of lead-free soft braze welding material
JP2020204599A (en) * 2019-06-19 2020-12-24 昭和電工マテリアルズ株式会社 Method for evaluating joint material and evaluation testing device

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