JP2008090921A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which a time required for restoring from a power down mode to an active mode can be shortened while reducing power consumption. <P>SOLUTION: A high voltage generating circuit 113 boosts a high voltage line 112. When a mode is set to an electric power supply mode, a control circuit 109 activates the high voltage generating circuit 113, keeps a switch 108 in an on-state always, and supplies voltage from the high voltage line 112 side to a common electric power line side. Also, when a mode is set to a power down mode, the control circuit 109 makes the high voltage generating circuit 113 non-activation, makes the switch 108 on periodically. Thereby, voltage is supplied from the common electric power line side receiving voltage supply from other semiconductor chip set to the electric supply mode to the high voltage line 112 in a chip, and voltage of the high voltage line 112 is kept. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a plurality of semiconductor chips each including a voltage generation circuit.

In recent years, MCP (Multi Chip Package) in which a plurality of chips are stacked in one package is used in devices for mobile use. In mobile environments, there is a strong demand for standby power reduction, and in devices for mobile applications, among the multiple chips mounted on a semiconductor integrated circuit, the power that consumes less power is available for chips that can enter standby mode. Set to down mode to reduce standby power. As a technique for reducing power consumption in a semiconductor memory device in which a plurality of semiconductor chips are sealed in one package, there is a technique described in Patent Document 1. In Patent Document 1, one of a plurality of chips is activated and operated, and in other chips, power supply to the circuit is stopped and deactivated to reduce power consumption. .
JP 2001-35146 A

  Usually, in a chip set in a power down mode, a power supply circuit with high power consumption is stopped to reduce power consumption. In particular, in a memory device, the power consumption of a high voltage circuit that generates a high voltage necessary for activating a word circuit or a digit circuit for selecting a memory element during a read / write operation is large. To achieve low power consumption. However, when the high voltage generation circuit is stopped, the level of the high voltage line in the chip decreases, and recharging of the high voltage line requires a lot of time in terms of the CPU time. It takes time to return to the active mode for operation. For this reason, the conventional semiconductor integrated circuit has a problem that the power down mode cannot be easily set.

  An object of the present invention is to provide a semiconductor integrated circuit capable of solving the above-described problems of the prior art and reducing the time required for returning from the power-down mode to the active mode while reducing power consumption.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a plurality of semiconductor chips each including a voltage generation circuit and performing an operation according to an operation mode set for each of the plurality of semiconductor chips. The semiconductor chip set in the power supply mode activates the voltage generation circuit, and outputs the voltage generated by the voltage generation circuit to a common power line commonly connected to the plurality of semiconductor chips, Among the plurality of semiconductor chips, the semiconductor chip set in the power down mode deactivates the voltage generation circuit and enters a standby state, and the power line connected to the output of the voltage generation circuit is periodically connected from the common power line. Is supplied with a voltage.

  In the semiconductor integrated circuit of the present invention, among the plurality of semiconductor chips, the semiconductor chip whose operation mode is set to the power supply mode activates the voltage generation circuit and outputs a voltage to the common power line, and the operation mode is power down. The semiconductor chip set in the mode deactivates the voltage generation circuit to enter a standby state, and is periodically supplied with a voltage from the common power line to the power supply line connected to the output of the voltage generation circuit. In this way, in the semiconductor chip set in the power-down mode, the voltage generation circuit is deactivated, thereby reducing the power consumption. The time required for the voltage to return to the voltage during normal operation can be reduced, and the return time from the power down mode to the normal operation state can be reduced.

  In the semiconductor integrated circuit of the present invention, the semiconductor chip includes a switch that connects / disconnects between the common power line and the power supply line, and a control circuit that controls the switch, and the control circuit is included in the semiconductor chip. If the set operation mode is the power supply mode, the voltage generated by the voltage generation circuit by connecting the switch is output to the common power line via the power line, and if the operation mode is the power down mode, A configuration in which the switch is periodically connected to supply a voltage from the common power line to the power supply line can be employed. In this case, each semiconductor chip can be operated in a desired operation mode in accordance with the operating status of the semiconductor chip.

  In the semiconductor integrated circuit of the present invention, the control circuit can be configured to include a register for holding an operation mode. In this case, the control circuit may perform an operation corresponding to the set operation mode with reference to the register.

  In the semiconductor integrated circuit of the present invention, when the operation mode is the power supply mode, the control circuit outputs a trigger signal having a predetermined cycle to a common trigger line commonly connected to the plurality of semiconductor chips. In the power down mode, a configuration can be adopted in which the switch is connected and a voltage is supplied from the common power line to the power supply line for a predetermined period from a timing based on a trigger signal input via the common trigger line. . In this case, the semiconductor chip set in the power down mode takes in the voltage from the common power line to the power supply line at a timing based on the trigger signal output from the semiconductor chip set in the power supply mode.

  In the semiconductor integrated circuit of the present invention, the control circuit includes a delay circuit that delays a signal by a predetermined delay time and determines a time from a signal edge of the trigger signal to connection of the switch. it can. In this case, the delay time of the delay circuit is preferably different for each semiconductor chip. By setting the delay time of the delay circuit in each semiconductor chip to a different time for each semiconductor chip, the timing for starting the voltage capture from the common power line to the power supply line in each semiconductor chip can be set to a different timing. . When a plurality of semiconductor chips are set to the power-down mode, the voltage at the semiconductor chip set to the power supply mode is prevented by preventing the plurality of semiconductor chips from simultaneously taking in the voltage from the common power line to the power supply line. The burden on the generation circuit can be reduced, and the chip cost can be reduced by designing the high-voltage generation circuit with reduced capacity.

  In the semiconductor integrated circuit of the present invention, the control circuit has a comparison circuit that compares the voltage of the common power line and the voltage of the power supply line in the power-down mode, and as a result of comparison by the comparison circuit, When it is determined that the voltage of the power line is lower than the voltage of the common power line, the switch is connected for a predetermined period from the timing based on the trigger signal, and the voltage is supplied from the common power line to the power line. it can. In this case, voltage can be taken from the common power line to the power line only when the voltage of the power line is lower than the voltage of the common power line.

  In the semiconductor integrated circuit of the present invention, the voltage generation circuit may be a high voltage generation circuit that boosts the power supply line so that the voltage of the power supply line becomes a predetermined level. In this case, in the activated state, the voltage generation circuit sets the power supply line to the predetermined level based on a comparison result between a voltage obtained by dividing the voltage of the power supply line by a predetermined voltage dividing ratio and a predetermined reference voltage. It is possible to employ a configuration in which the voltage is boosted so as to be maintained at a high level. For example, a memory device requires a high voltage generation circuit that generates a high voltage in order to activate a word circuit or a digit circuit that selects a memory element at the time of reading / writing. If the high voltage generation circuit is stopped to reduce power consumption in the power down mode, the voltage of the power supply line will drop, and it will take time to boost the power supply line when the power down mode is canceled and the normal operation state is entered. This delays the transition to normal operation. In power-down mode, the voltage of the power supply line is maintained by the voltage from other semiconductor chips set in the power supply mode, reducing the time required for boosting the power supply line when shifting to the normal operation state Thus, the time until the semiconductor chip performs a normal operation can be shortened.

  In the semiconductor integrated circuit of the present invention, a semiconductor chip whose operation mode is set to the power supply mode among the plurality of semiconductor chips activates the voltage generation circuit and outputs a voltage to the common power line. The semiconductor chip set in the power down mode deactivates the power generation circuit to enter a standby state, and periodically receives a voltage supply from the common power line to the power supply line connected to the output of the voltage generation circuit. This makes it possible to reduce the time required for the power supply line voltage to return to the normal operation voltage when shifting from the power-down mode to the normal operation while suppressing power consumption. The time required for migration can be shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a connection relationship between chips in an MCP package in a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit 10 is configured as an MCP / SIP product in which a plurality of chips are stacked, and includes a plurality of chips (three chips 100, 200, and 300 in FIG. 1), a common power line 11 connected to each chip, and a common And a trigger line 12. The semiconductor integrated circuit 10 is used, for example, for a mobile use, a device having a low power consumption function and a strong demand for power saving.

  Each chip has bonding pads 101, 201, and 301 for common power lines, and bonding pads 102, 202, and 302 for common trigger lines. The common power line bonding pads 101, 201, 301 are connected to the package substrate side bonding pads 105, 205, 305 of the common power line 11 via bonding wires 103, 203, 303, respectively. The common trigger line bonding pads 102, 202, 302 are connected to the package substrate side bonding pads 106, 206, 306 of the common trigger line 12 through bonding wires 104, 204, 304, respectively.

  FIG. 2 is a circuit block diagram showing the internal configuration of the chip 100 of FIG. Hereinafter, the configuration of the chip 100 will be described as a representative, but the other chips (200, 300) in the semiconductor integrated circuit 10 have the same configuration as the chip 100. The chip 100 is typically configured as a memory chip, and includes a word system circuit / column system circuit 111, a high voltage generation circuit 113, a reference potential circuit 114, a voltage dividing circuit 115, a comparison circuit 116, a command circuit 117, a switch 108, And a control circuit 109.

  The output of the high voltage generation circuit 113 is connected to the high voltage line 112 in the chip. The word system circuit / column system circuit 111 operates using a high voltage supplied to the high voltage line 112, and selects a memory element when reading / writing the memory device. The voltage dividing circuit 115 divides the voltage of the high voltage line 112 at a predetermined voltage dividing ratio. The comparison circuit 116 compares the voltage divided by the voltage dividing circuit 115 with a predetermined reference voltage output from the reference potential circuit 114, and outputs a comparison result. The high voltage generation circuit 113 boosts the high voltage line 112 with reference to the comparison result so that the voltage of the high voltage line 112 is maintained at a predetermined high voltage.

  The command circuit 117 determines the operation mode of the chip 100. A command is input to the command circuit 117 from the outside using a general combination of an address and a control signal. The operation mode set by the command circuit 117 includes an active mode that operates in a normal operation state, a power-down mode that waits in a low-power consumption state, a chip that operates in a normal operation state and is set in a power-down mode. On the other hand, there is a power supply mode in which voltage is supplied.

  Of the plurality of chips in the semiconductor integrated circuit 10, chips that do not generate access are set in the power down mode to reduce the power consumption of the semiconductor integrated circuit 10. The chip set to the power down mode deactivates the high voltage generation circuit 113 having the largest power consumption in the chip and shifts to a standby state. For the chip where access occurs, the active mode is set, and the high voltage generation circuit 113 is normally operated to read / write the memory element. In addition, any of the normally operating chips, for example, a chip that is constantly accessed is set in the power supply mode, and voltage supply is executed to the chip set in the power down mode.

  The switch 108 controls the connection between the common power line bonding pad 101 and the high voltage line 112. Connection / disconnection of the switch 108 is controlled by the control circuit 109. The control circuit 109 performs an operation according to the operation mode set by the command circuit 117. When the operation mode is the power supply mode, the control circuit 109 connects between the common power line bonding pad 101 and the high voltage line 112, and applies a voltage to the common power line 11 (FIG. 1) from the high voltage line 112 side. Supply. If the operation mode is the active mode, the switch 108 is disconnected and the common power line 11 and the high voltage line 112 are disconnected.

  If the set operation mode is the power supply mode, the control circuit 109 outputs a trigger signal having a predetermined cycle to the common trigger line 12 via the common trigger line bonding pad 102. This trigger signal is used to determine the timing of voltage supply from the common power line 11 side to the high voltage line 112 in the chip set in the power down mode. The control circuit 109 of the chip set in the power-down mode places the switch 108 in the connected state for a predetermined time at a timing based on the trigger signal input via the common trigger line bonding pad 102, and sets the common power line bonding pad 101 to the connected state. Thus, a voltage is periodically supplied from the common power line 11 side to the high voltage line 112.

  FIG. 3 shows the configuration of the control circuit 109. The control circuit 109 includes a delay circuit 121, an oscillator circuit 122, a register 123, a comparison circuit 124, and control logic 125. The register 123 holds the operation mode set by the command circuit 117 (FIG. 2). The comparison circuit 124 compares the voltage of the common power line bonding pad 101 with the voltage of the high voltage line 112. The oscillator circuit 122 outputs a signal having a predetermined cycle as a trigger signal to the common trigger line 12 (FIG. 1) in the power supply mode.

  The delay circuit 121 delays the signal by a predetermined delay time that is set in advance, and determines the time from when the trigger signal is turned on to when the switch 108 is turned on to start power capture with reference to the trigger signal. The delay time of the delay circuit 121 is set to a different value for each chip. The control logic 125 has control logic for controlling the switch 108. The control logic 125 turns on the switch 108 at a timing delayed by the delay time of the delay circuit 121 from the timing based on the trigger signal, and supplies a voltage to the high voltage line 112 from the common power line 11 side.

  Hereinafter, the operation of the semiconductor integrated circuit 10 will be described using a specific example. Of the three chips 100, 200, and 300 (FIG. 1), it is assumed that the chip 100 is always accessed, and this chip 100 is used in the power supply mode. When the power supply mode is set, a command for setting the power supply mode is input to the command circuit 117 (FIG. 2) in the same manner as a general memory command. The command circuit 117 interprets the command and stores a value indicating the power supply mode in the register 123 (FIG. 3).

  In the chip 100, when the operation mode is set to the power supply mode, the switch 108 is turned on, and the level (voltage) of the high voltage line 112 maintained at a high voltage by the high voltage generation circuit 113 is the same as that of the switch 108. The power is output to the common power line 11 through the power line bonding pad 101, the bonding wire 103, and the package substrate side bonding pad 105. The control circuit 109 outputs the trigger signal generated by the oscillator circuit 122 to the common trigger line bonding pad 102. This trigger signal is output to the common trigger line 12 via the bonding wire 104 and the package substrate side bonding pad 106.

  Since the chip 200 is not accessed, it is set to the power down mode and the high voltage generation circuit 113 is stopped. A value indicating the power down mode is stored in the register 123 of the chip 200 by the command circuit 117. The chip 300 is set to an active mode in which normal operation is performed. A value indicating the active mode is stored in the register 123 of the chip 300 by the command circuit 117. In addition, the control circuit 109 of the chip 300 turns off the switch 108 and disconnects the high voltage line 112 and the common power line 11.

  FIG. 4 shows operation waveforms of each part of the semiconductor integrated circuit 10. The period of the trigger signal output from the chip 100 set to the power supply mode is 1 μs. The delay time of the delay circuit 121 in the chip 200 is 200 ns, and the delay time of the delay circuit 121 in the chip 300 is 300 ns. When the control circuit 109 of the chip 200 set in the power down mode detects the rising edge of the trigger signal, the control circuit 109 activates the comparison circuit 116 (FIG. 2) and the comparison circuit 124 (FIG. 3), and the reference voltage and high voltage line 112 are activated. And the voltage of the common power line 11 and the voltage of the high voltage line 112 are compared.

  The control circuit 109 detects that the voltage of the high voltage line 112 is equal to or lower than the reference voltage in the comparison by the comparison circuit 116, and the voltage of the common power line 11 is higher than the voltage of the high voltage line 112 in the comparison by the comparison circuit 124. If it is detected that it is high, it is determined to take in power. The control circuit 109 turns on the switch 108 for a predetermined capture time, for example, 80 ns from the timing delayed by the delay time of the delay circuit 121 from the rising edge of the trigger signal. In the chip 200, the switch 108 is turned on only during the capture period, whereby a voltage is supplied from the common power line 11 to the high voltage line 112, and the voltage of the high voltage line 112 increases. Such an operation is performed for each rising edge of the trigger signal. Since the cycle of the trigger signal is 1 μs, the voltage of the high voltage line 112 of the chip 200 is monitored every 1 μs, and power supply is repeatedly performed so that the voltage is maintained at a predetermined voltage or higher.

  Next, consider a case where access to the chip 300 is lost and the chip 300 is set to the power down mode in addition to the chip 200. With the above operation, the chip 200 turns on the switch 108 for the capture time of 80 ns after the elapse of 200 ns from the rising edge of the trigger signal, and executes voltage supply from the common power line 11 to the high voltage line 112. The chip 300 is the same as the operation in the chip 200, and after the lapse of 300 ns, which is the delay time of the delay circuit 121, from the rising edge of the trigger signal, the switch 108 is turned on for the capture time of 80 ns. The voltage supply to the line 112 is executed. When viewed in time series, the voltage supply to the high voltage line 112 is executed by the chip 200 in the period from the rising edge of the trigger signal to 280 ns within one cycle (1 μs) of the trigger signal, and after 300 ns has elapsed. In the period up to 380 ns, voltage supply to the high voltage line 112 is executed by the chip 300.

  In the present embodiment, in the chip set to the power supply mode, the switch 108 is turned on, the high voltage line 112 boosted by the high voltage generation circuit 113 and the common power line 11 are connected, and the common power line 11 is connected to the high power line 11. The voltage of the voltage line 112 is supplied. In the chip set in the power down mode, the switch 108 is turned on periodically (intermittently), and the voltage is supplied to the high voltage line 112 from the common power line 11 side. In this way, in the chip set in the power down mode, the voltage of the high voltage line 112 can be kept at a constant level while the high voltage generation circuit 113 is stopped to reduce power consumption. The time for boosting the high voltage line 112 when returning from the power-down mode to the normal active mode can be shortened.

  In the chip, when the power consumption of the high voltage generation circuit 113 is large and no access occurs, the chip is set in the power down mode and the high voltage generation circuit 113 is stopped to reduce power consumption (standby power). it can. However, once the voltage of the high voltage line 112 drops, it takes time to boost the high voltage line 112, and as a result, it takes time to return from the power down mode to the active mode. In the present embodiment, attention is paid to the fact that the delay in returning to the active mode is the time required for boosting the level of the stepped-down high voltage line 112. In the power down mode, another delay is made via the common power line 11. By receiving a voltage supply from the high voltage line 112 of the chip, the level of the high voltage line 112 is maintained. By doing so, the recharge time of the high voltage line 112 when returning to the active mode can be greatly shortened, and the return time from the power down mode can be shortened. Thereby, it becomes easy to set the chip in the power down mode, and the power consumption of the semiconductor integrated circuit 10 can be reduced by actively utilizing the power down mode.

  In the present embodiment, the trigger signal is output from the chip in the power supply mode, and each chip in the power down mode has a voltage from the common power line 11 to the high voltage line 112 for a predetermined capture time from the timing based on the trigger signal. Capture. At that time, the delay time of the delay circuit 121 that determines the voltage capture timing in each chip is set to a different value for each chip so that the timing of voltage capture in each chip does not overlap. When a plurality of chips simultaneously capture voltage, the burden on the high voltage generation circuit 113 in the chip in the power supply mode increases, so the capability of the high voltage generation circuit 113 needs to be designed to be high. In this embodiment, even when a plurality of chips are set in the power down mode, the timing of voltage capture is shifted and each chip captures voltage in a time-sharing manner, thereby reducing the burden on the high voltage generation circuit 113. Therefore, it is possible to design with the capability of the high voltage generation circuit 113 suppressed, and the chip cost can be suppressed.

  Although FIG. 1 shows an example in which the semiconductor integrated circuit 10 includes three semiconductor chips, the number of chips is not limited to three. For example, the number of semiconductor chips may be four or more. In that case, the delay time of the delay circuit 121 of each chip is set so that the voltage capture timings of each chip do not overlap in consideration of the cycle of the trigger signal and the voltage capture time of each chip. Good. In the above-described embodiment, any one of the plurality of chips is set to the power supply mode. However, a plurality of chips can be set to the power supply mode. In that case, a trigger signal may be output from any of the chips set in a plurality of power supply modes to determine the timing of voltage capture.

  In the above-described embodiment, the example in which the voltage is supplied from the chip set in the power supply mode to the chip set in the power down mode in the same package using the common power line 11 and the common trigger line 12 has been described. This is not a limitation. For example, the common power line 11 and the common trigger line 12 may be taken out of the package from the terminals, connected to another semiconductor integrated circuit, and supplied with a voltage to a power-down mode chip in the other semiconductor integrated circuit. Good. In this case, it is possible to receive power supply between the semiconductor integrated circuits.

  Although the present invention has been described based on the preferred embodiments, the semiconductor integrated circuit of the present invention is not limited to the above embodiments, and various modifications and changes are made to the configuration of the above embodiments. What has been done is also included in the scope of the present invention.

1 is a circuit block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The circuit block diagram which shows the structure inside a semiconductor chip. The circuit block diagram which shows the structure of a control circuit. The wave form diagram which shows the operation | movement waveform of each part of a semiconductor integrated circuit.

Explanation of symbols

10: Semiconductor integrated circuit 11: Common power line 12: Common trigger line 100, 200, 300: Semiconductor chips 101, 201, 301: Common power line bonding pads 102, 202, 302: Common trigger line bonding pads 103, 104, 203 204, 303, 304: Bonding wires 105, 106, 205, 206, 305, 306: Substrate side bonding pad 108: Switch 109: Control circuit 111: Word system circuit / column system circuit 112: High voltage line 113: High voltage Generation circuit 114: reference potential circuit 115: voltage dividing circuit 116: comparison circuit 117: command circuit 121: delay circuit 122: oscillator circuit 123: register 124: comparison circuit 125: control logic

Claims (9)

Each includes a voltage generation circuit, and has a plurality of semiconductor chips that operate according to the operation mode set for each.
The semiconductor chip set in the power supply mode among the plurality of semiconductor chips activates the voltage generation circuit, and the voltage generated by the voltage generation circuit on a common power line commonly connected to the plurality of semiconductor chips. Output
Among the plurality of semiconductor chips, the semiconductor chip set in the power down mode deactivates the voltage generation circuit and enters a standby state. From the common power line to the power supply line connected to the output of the voltage generation circuit, A semiconductor integrated circuit characterized by receiving a voltage supply. The semiconductor chip includes a switch that connects / disconnects between the common power line and the power line, and a control circuit that controls the switch,
If the operation mode set in the semiconductor chip is the power supply mode, the control circuit connects the switch and outputs the voltage generated by the voltage generation circuit to the common power line via the power line, and the operation mode 2. The semiconductor integrated circuit according to claim 1, wherein when the power is in a power-down mode, the switches are periodically connected to supply a voltage from the common power line to the power supply line.   The semiconductor integrated circuit according to claim 2, wherein the control circuit includes a register that holds an operation mode.   When the operation mode is the power supply mode, the control circuit outputs a trigger signal having a predetermined cycle to a common trigger line commonly connected to the plurality of semiconductor chips, and when the operation mode is the power-down mode, 4. The semiconductor integrated circuit according to claim 3, wherein the switch is connected to supply a voltage from the common power line to the power supply line for a predetermined period from a timing based on a trigger signal input via the common trigger line.   The semiconductor integrated circuit according to claim 4, wherein the control circuit includes a delay circuit that delays a signal by a predetermined delay time and determines a time from a signal edge of the trigger signal to connection of the switch.   The semiconductor integrated circuit according to claim 5, wherein a delay time of the delay circuit is different for each semiconductor chip.   The control circuit has a comparison circuit that compares the voltage of the common power line and the voltage of the power supply line in a power down mode, and the voltage of the power supply line is the same as a result of comparison by the comparison circuit. When it is determined that the voltage is lower than the voltage of the power line, the switch is connected only for a predetermined period from the timing based on the trigger signal, and the voltage is supplied from the common power line to the power supply line. The semiconductor integrated circuit as described.   The semiconductor integrated circuit according to claim 1, wherein the voltage generation circuit is a high voltage generation circuit that boosts the power supply line so that a voltage of the power supply line becomes a predetermined level.   In an activated state, the voltage generation circuit maintains the power supply line at the predetermined level based on a comparison result between a voltage obtained by dividing the voltage of the power supply line by a predetermined voltage dividing ratio and a predetermined reference voltage. The semiconductor integrated circuit according to claim 8, wherein the voltage is boosted to a low level.

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