JP2008084997A - Semiconductor device design support system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the occurrence of iteration upon chip design and efficiently manufacture a semiconductor device with high yield. <P>SOLUTION: The predicted yields before and after the DFM measures are computed using the chip specification in the design start stage (steps S20-S22); the predicted manufacturing costs before and after the DFM measures are computed using them (step S23); the difference between the predicted manufacturing costs before and after the DFM measures is compared with the DFM measure cost required for the DFM measures, and the magnitude thereof is judged (step S24). As implementation judgement on the DFM measures can be carried out using the chip specification in the design start stage, the occurrence of the iteration of the design can be suppressed. Further, the predicted manufacturing cost after the DFM measures, and the relation between the predicted manufacturing cost and the DFM measure cost are made clear at the design start stage, so that implementation judgement on the DFM measures can suitably be carried out. Thereby, the semiconductor device can efficiently be manufactured with high yield. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device design support system, and more particularly to a semiconductor device design support system used for designing in consideration of yield.

  Usually, in the development of a chip such as an LSI (Large Scale Integration), a design is first performed based on the chip size, required performance, and the like, and the manufacture is performed based on the design. In recent years, high-performance chips can be obtained at a relatively high yield by improving manufacturing techniques such as lithography techniques. However, with the miniaturization of chips, it has become difficult to obtain chips with a yield exceeding a certain value only by improving manufacturing technology. Therefore, there is an increasing need to take design measures that can contribute to yield improvement not only in the manufacturing stage but also in the design stage.

FIG. 30 is a diagram for explaining the flow of implementation of a conventional design measure.
In general, chip development is designed based on a plan (steps S100 and S110), manufactured based on the design (step S120), and tested for the performance of the obtained chip (step S130). Implemented in a stream. At that time, at the stage where the planning and design of steps S100 and S110 are performed, the yield is predicted in order to determine whether or not a design measure is necessary.

  Therefore, first, after the design of step S110, chip information of the designed chip (referred to as chip information such as chip area, line width, and number of vias) is acquired. Further, analysis / verification is performed using the yield record obtained in the previous chip development (step S111), and a predicted yield calculation formula is created. A predicted yield is calculated using this predicted yield calculation formula and the chip information obtained after the design in step S110 (step S112). Further, a predicted manufacturing cost is calculated using the predicted yield (step S113). If the predicted yield is predicted to be greater than or equal to a certain value while considering the calculated predicted manufacturing cost (step S114), the process proceeds to step 120 as it is. On the other hand, when the predicted yield is predicted to fall below a certain value (step S114), after implementing redesign by implementing design measures such as changing the wiring arrangement or contact structure (step S115), step 120 is performed. Proceed to manufacturing.

Conventionally, at the chip design stage, for each combination of a plurality of functional blocks prepared in advance, the yield is predicted using a known defect occurrence rate for the production line to be used, and the manufacturing cost per chip is estimated. A method of selecting an optimal combination of functional blocks based on the above has been proposed (for example, see Patent Document 1).
JP 2004-31891 A

  However, as shown in FIG. 30 above, in the method of predicting the yield using the chip information obtained after completing the design of the chip, if it is predicted that the yield will be lowered, the redesign must be performed. As a result, there is a problem that an iteration occurs and the chip development speed decreases.

  Furthermore, since the design measures to be implemented vary depending on the type of chip, the design measures (design rules) that must be taken regardless of the type of chip are considered in the initial design stage, but the subsequent redesign stage. Then, the implementation decision of each design measure is performed for each chip. However, the effect of individual design measures for individual chips cannot be easily calculated at the redesign stage and is difficult to clarify.

In recent years, LSI chips and the like are often designed and manufactured in accordance with their uses and the above problems are more likely to occur.
The present invention has been made in view of these points, and provides a semiconductor device design support system for efficiently developing semiconductor devices by implementing appropriate design measures that contribute to yield improvement. Objective.

  In the present invention, in order to solve the above problems, in a semiconductor device design support system used for designing a semiconductor device, specification storage means for storing specifications at the design start stage of the semiconductor device, and design measures that can be implemented in the semiconductor device Design measure cost storage means for storing the design measure cost required for the process, and the predicted yield when the design measure is not implemented and the predicted yield when the design measure is implemented using the specifications stored in the specification store means A predictive yield calculating means for calculating the predictive yield, a predictive yield when the design measure calculated by the predictive yield calculating means is not implemented, and a predictive yield when the design measure is implemented, and not implementing the design measure Predicted manufacturing cost and a predicted manufacturing cost calculating means for calculating the predicted manufacturing cost when the design measures are implemented, The difference between the predicted manufacturing cost when not implementing the design measure calculated by the predicted manufacturing cost calculating means and the predicted manufacturing cost when executing the design measure, and the design stored in the design measure cost storage means There is provided a semiconductor device design support system characterized by comprising comparison / determination means for comparing / determining countermeasure costs.

  According to such a semiconductor device design support system, the specification storage means stores the specifications at the design start stage of the semiconductor device, and the predicted yield calculation means does not implement a design measure using the stored specifications. The predicted yield in the case of carrying out the design is calculated, and the predicted manufacturing cost calculating means calculates the predicted manufacturing cost in the case where the design measure is not carried out and in the case where the design measure is carried out, using the calculated predicted yield. Then, the comparison / determination means compares the difference between the predicted manufacturing cost when the design countermeasure is not implemented and the case where it is implemented with the design countermeasure cost required for the design countermeasure stored in the design countermeasure cost storage means, judge. Since it is possible to make a design measure implementation decision using the specifications at the design start stage, the occurrence of design iteration can be suppressed. Further, at the design start stage, the predicted manufacturing cost when the design countermeasure is implemented and the relationship between the predicted manufacturing cost and the design countermeasure cost required for the design countermeasure are clarified.

  In the present invention, it is made possible to determine whether to implement a design measure using the specifications at the design start stage of the semiconductor device. Thereby, it is possible to suppress the occurrence of iteration when designing the semiconductor device. In addition, at the design start stage, the predicted manufacturing cost when implementing the design countermeasure and the relationship between the predicted manufacturing cost and the design countermeasure cost are clarified, so that the design can be performed appropriately. Therefore, it becomes possible to manufacture a semiconductor device at a high yield early.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example the case of application to the development of an LSI chip.
FIG. 1 is a diagram for explaining the flow of implementation of design measures in LSI chip development.

  The LSI chip is developed based on a plan (steps S10 and S20), manufactured based on the design (step S30), and tested for the performance of the obtained chip (step S40). Implemented in a stream. At that time, the necessity of a design measure (DFM (Design For Manufacturing) measure) that contributes to improving the yield of the chip at the design start stage of step S20, for example, at the start of design or immediately after the start of design, and if necessary, In order to determine the type, the yield and manufacturing cost are predicted.

  Therefore, first, a chip specification is acquired after planning in step S10 or at the design start stage in step S20. The chip specification includes various chip characteristics obtained at the design start stage, such as a chip name, the number of gates, a chip area, a memory area, and a wiring layer structure.

  Then, from analysis / verification of past development results (step S21), a calculation formula (predicted yield calculation formula) used for yield prediction and a coefficient used for this predicted yield calculation formula for each type of DFM measure The set coefficient (countermeasure coefficient) is derived.

  A predicted yield is calculated for each DFM measure by using the predicted yield calculation formula, its countermeasure coefficient, and the previously acquired chip specification (step S22). Furthermore, in this step S22, the predicted yield when the DFM countermeasure is not implemented is also calculated.

  Next, using the calculated predicted yield, for each DFM measure, a predicted manufacturing cost when each DFM measure is implemented is calculated (step S23). In calculating the predicted manufacturing cost when implementing this DFM countermeasure, in addition to the predicted yield previously calculated, the factory cost such as fixed cost and variable cost and the mass production number of chips to be designed / manufactured are also used. Furthermore, in this step S23, the estimated manufacturing cost when not implementing the DFM countermeasure is also calculated. The above-mentioned factory cost and the number of mass production are used for calculation of the predicted manufacturing cost when this DFM countermeasure is not implemented.

  First, for each DFM countermeasure, the estimated manufacturing costs when the DFM countermeasure is implemented and when the DFM countermeasure is not implemented are compared, and the improvement effect of the manufacturing cost (the reduction effect of the manufacturing cost) when each DFM countermeasure is implemented is estimated. Subsequently, it is compared with labor costs, infrastructure costs, etc. (DFM countermeasure costs) required to implement each DFM countermeasure, and any of the DFM countermeasures among the various types of DFM countermeasures can improve the manufacturing cost. Is determined to exceed the DFM countermeasure cost (step S24). Details of the comparison / determination in step S24 will be described later.

  After the comparison / determination in step S24, a DFM countermeasure whose manufacturing cost improvement effect exceeds the DFM countermeasure cost is selected, the DFM countermeasure is implemented, and the design in step S20 is advanced. At this time, the record of DFM countermeasures used in the design of the chip, for example, the chip specifications at the end of the chip design, the improvement rate of the predicted yield when the DFM countermeasure is implemented on the chip, and the cost required for the DFM countermeasure Are acquired and stored as past design measure results.

  After completion of the design in step S20, the manufacturing and testing of steps S30 and S40 are performed as described above. After the test, the actual yield obtained for this chip is acquired and stored as a past yield record.

  Using the past design measure results obtained in the chip design stage and the past yield results obtained in the chip manufacturing stage, that is, the past development results, the analysis / verification of step S21 is performed, The predicted yield calculation formula and the countermeasure coefficient can be obtained. The predicted yield calculation formula and the countermeasure coefficient obtained here can be used as needed when developing another chip. The information stored as past design countermeasure results can be reflected in the contents of the DFM countermeasure cost used in the comparison / determination in step S24, and can be used as necessary when developing another chip. .

Here, the comparison / determination in step S24 will be described in more detail.
FIG. 2 is a diagram showing the relationship between the number of mass production and the cost when the DFM countermeasure is implemented and not implemented.

  The total cost required for chip development is approximately the sum of the cost required for design (design cost) and the cost required for manufacturing (manufacturing cost). The total cost increases as the number of mass production increases, regardless of whether or not DFM countermeasures are implemented.

  When the DFM countermeasure is implemented, the design cost increases regardless of the number of chips produced as compared with the case where the DFM countermeasure is not implemented. In addition, when the DFM countermeasure is implemented, the yield can be improved as compared with the case where the DFM countermeasure is not implemented, and thus the increase rate of the manufacturing cost associated with the increase in the number of chips produced is reduced.

  Therefore, as shown in FIG. 2, when the number of chips produced is small, the total cost when implementing DFM countermeasures (with DFM countermeasures) is increased due to the increase in design cost associated with the implementation of DFM countermeasures. It exceeds the total cost when no countermeasures are taken (without DFM countermeasures). However, when the mass production number of chips exceeds a certain value c, as shown in FIG. 2, depending on the type of DFM countermeasures, when the DFM countermeasures are implemented by improving the manufacturing cost by improving the yield (with DFM countermeasures) The total cost may be lower than the total cost when the DFM countermeasure is not implemented (without the DFM countermeasure).

FIG. 3 is a diagram showing the relationship between the number of mass production and the cost when different DFM measures are implemented.
As shown in FIG. 3, when the DFM countermeasure a is selected from the different DFM countermeasures a and b, as described with reference to FIG. 2, the mass production number exceeds a certain value d. The total cost when the DFM countermeasure a is implemented becomes lower than the total cost when the DFM countermeasure a is not implemented. On the other hand, when DFM countermeasure b is selected, even if the number of mass production increases, the total cost when implementing DFM countermeasure b does not fall below the total cost when not implementing DFM countermeasure b.

Thus, different types of DFM countermeasures have different effects on the total cost.
Therefore, at the time of the comparison / determination shown in step S24 of FIG. 1, the DFM countermeasure is implemented as an effect of improving the manufacturing cost when the DFM countermeasure indicating a certain predicted yield is performed for a predetermined mass production. It is determined whether or not the manufacturing cost improvement effect exceeds the DFM countermeasure cost as compared with the increase in design cost due to this, that is, the DFM countermeasure cost.

  As a result, when a certain DFM measure is implemented at a predetermined mass production, if a relationship of manufacturing cost improvement effect> DFM measure cost is obtained, it can be said that the DFM measure is effective for yield improvement and total cost reduction. . Conversely, if the relationship of manufacturing cost improvement effect> DFM countermeasure cost cannot be obtained, it can be said that the DFM countermeasure is not effective for yield improvement and total cost reduction.

By performing such comparison / determination, a DFM countermeasure that satisfies the relationship of manufacturing cost improvement effect> DFM countermeasure cost is selected, and a design for implementing the DFM countermeasure is performed.
Next, an LSI chip design support system used for designing LSI chips as described above will be described.

FIG. 4 is a diagram showing a principle configuration of the LSI chip design support system.
The LSI chip design support system 1 shown in FIG. 4 includes a predicted yield calculation unit 2, a predicted manufacturing cost calculation unit 3, a comparison / determination unit 4, and a display unit 5.

  The predicted yield calculation unit 2 included in the LSI chip design support system 1 uses the data stored in the calculation formula table 6, the countermeasure coefficient table 7 and the chip specification table 8 that are also included in the LSI chip design support system 1 to design chips. Calculate the predicted yield of.

Here, FIG. 5 is a content explanatory diagram of the calculation formula table, FIG. 6 is a content explanatory diagram of the countermeasure coefficient table, and FIG. 7 is a content explanatory diagram of the chip specification table.
In the calculation formula table 6, as shown in FIG. 5, the calculation formula application conditions when the DFM countermeasure is implemented and when the DFM countermeasure is implemented, the predicted yield and the predicted manufacturing cost when the DFM countermeasure is implemented and not implemented are calculated. In addition to coefficient names and chip characteristic names described later, a calculation formula that includes factory cost and mass production as parameters, and a calculation result name that is an identification name given to an object calculated from the calculation formula are stored.

  As shown in FIG. 1 (step S21), the contents of the calculation formula table 6 analyze the past design measure results obtained by the design that implements the DFM measure and the past yield results obtained after the test. • Created (or added or updated) by verification.

  As shown in FIG. 6, the countermeasure coefficient table 7 stores DFM countermeasure names that are identification names assigned to different types of DFM countermeasures, coefficient names used in calculation formulas, and coefficient values corresponding to the coefficient names. Is done. There are a plurality of coefficient names and coefficient values for each DFM measure.

  The contents of the countermeasure coefficient table 7 are created together with the contents of the calculation formula table 6 by analyzing and verifying the past design countermeasure results and the past yield results as shown in FIG. 1 (step S21) ( Or added or updated).

  As shown in FIG. 7, the chip specification table 8 includes a chip name, which is an identification name assigned to different types of LSI chips, a chip characteristic name used in a calculation formula, and a chip characteristic value corresponding to the chip characteristic name. Is stored. A plurality of chip characteristic names and chip characteristic values exist for each chip.

As shown in FIG. 1 (step S20), the contents of the chip specification table 8 are acquired at an early stage of design such as the design start time or immediately after the design start.
The predicted yield calculation unit 2 extracts the calculation formula for the predicted yield when the DFM countermeasure is not implemented from the calculation formula table 6, extracts the chip characteristic value of the chip to be designed from the chip specification table 8, and does not implement the DFM countermeasure. Calculate the predicted yield for the case. At this time, the chip characteristic value is extracted from the chip specification table 8 using the chip characteristic name included in the extracted calculation formula as a key.

  Further, the predicted yield calculation unit 2 extracts, for each DFM measure that can be applied to the chip to be designed, a predicted yield calculation formula when implementing the DFM measure from the calculation formula table 6, and calculates the calculated formula from the measure coefficient table 7. The coefficient value of the countermeasure coefficient used in the above is extracted, the chip characteristic value of the chip to be designed is extracted from the chip specification table 8, and the predicted yield when each DFM countermeasure is implemented is calculated. At this time, the coefficient value is extracted from the countermeasure coefficient table 7 using the coefficient name included in the extracted calculation formula as a key. The chip characteristic value is extracted from the chip specification table 8 using the chip characteristic name included in the extracted calculation formula as a key.

  Here, Ni (i = 1,..., N) is the chip characteristic value before the DFM countermeasure is implemented, and Ni ′ (i ′ = 1,..., N) is the chip characteristic value after the DFM countermeasure is implemented. n) When the coefficient value of the countermeasure coefficient is Xk (k = 1,..., n), as shown in the following equation (1), the chip characteristic value Ni ′ after the DFM countermeasure is the chip before the DFM countermeasure. It can be expressed by a function g of the characteristic value Ni and the coefficient value Xk.

Ni ′ = g (Xk, Ni) (1)
In the analysis / verification shown in step S21 of FIG. 1, the function g and the coefficient value Xk are obtained from the past development results using the function g, and these data are stored in the calculation formula table 6 And stored in the countermeasure coefficient table 7.

  Further, assuming that the predicted yield of a certain chip when the DFM countermeasure is not implemented is Y, and the predicted yield when the DFM countermeasure is implemented is Y ′, each predicted yield Y and Y ′ is expressed by the following equations (2) and (2), respectively. As shown in 3a), it can be expressed by the function f of the chip characteristic values Ni and Ni ′ before and after the DFM countermeasure.

Y = f (Ni) (2)
Y ′ = f (Ni ′) (3a)
Further, the expression (3a) can be rewritten as the following expression (3b) using the expression (1).

Y ′ = f (Ni ′) = f (g (Xk, Ni)) (3b)
Therefore, the predicted yield Y ′ when the DFM countermeasure is implemented can be obtained using the chip characteristic value Ni and the coefficient value Xk before the DFM countermeasure.

  In the analysis / verification shown in step S21 in FIG. 1, such a function f is obtained from past development results. The calculation formula table 6 stores formulas (2) and (3b), and the predicted yield calculation unit 2 calculates a predicted yield Y when the DFM countermeasure is not implemented using the formula (2). Using formula (3b), the predicted yield Y ′ when the DFM countermeasure is implemented is calculated.

  Returning to FIG. 4, the predicted yield calculated by the predicted yield calculation unit 2 when the DFM countermeasure is implemented and when it is not implemented is stored in the predicted yield table 9 provided in the LSI chip design support system 1 for each DFM countermeasure. It is like that.

FIG. 8 is a diagram for explaining the contents of the predicted yield table.
In the predicted yield table 9, as shown in FIG. 8, the DFM countermeasure name (including the case where no DFM countermeasure is implemented), which is an identification name assigned to each type of DFM countermeasure, and the predicted yield calculation unit 2. The predicted yield when the calculated DFM countermeasure is implemented and when it is not implemented is stored.

  4 is stored in a factory cost table 10, a mass production number table 11, and a DFM countermeasure cost table 12 that are also provided in the LSI chip design support system 1. The predicted manufacturing cost of the chip to be designed is calculated using the stored data and the data stored in the predicted yield table 9.

Here, FIG. 9 is a content explanatory diagram of the factory cost table, FIG. 10 is a content explanatory diagram of the mass production number table, and FIG. 11 is a content explanatory diagram of the DFM countermeasure cost table.
As shown in FIG. 9, the factory cost table 10 includes a chip name, which is an identification name assigned to each of different types of LSI chips, and a fixed cost and a variable cost that are predicted to be necessary for manufacturing each LSI chip. The factory cost including etc. is stored.

  As shown in FIG. 10, the mass production number table 11 stores a chip name, which is an identification name assigned to each of different types of LSI chips, and a planned mass production number for each LSI chip.

The contents of the factory cost table 10 and the mass production number table 11 can be configured as a single table (for example, refer to an example described later).
As shown in FIG. 11, the DFM countermeasure cost table 12 includes a DFM countermeasure name, which is an identification name assigned to different types of DFM countermeasures, and a labor cost expected to be required for each DFM countermeasure. Stores DFM countermeasure costs including infrastructure costs.

The data of the DFM countermeasure cost table 12 is created (or added or updated) using the past design countermeasure results obtained by the design that implements the DFM countermeasure.
The predicted manufacturing cost calculation unit 3 extracts a formula for calculating the predicted manufacturing cost when the DFM countermeasure is not implemented from the calculation formula table 6, and calculates the factory cost of the chip to be designed from the factory cost table 10 and the mass production number table 11. Then, the mass production numbers of the chips to be designed are respectively extracted, and the predicted manufacturing cost when the DFM countermeasure is not implemented is calculated.

  Further, the predicted manufacturing cost calculation unit 3 extracts, for each DFM countermeasure that can be applied to the chip to be designed, a calculation formula for the predicted manufacturing cost when the DFM countermeasure is implemented from the calculation formula table 6, and the factory cost table 10 and the mass production When the factory cost and the mass production number of the chip to be designed are extracted from the number table 11, respectively, and the predicted yield when the DFM countermeasure is implemented and not implemented are extracted from the predicted yield table 9, and each DFM countermeasure is implemented. Calculate the estimated manufacturing cost.

  Here, Y, Y ′ are the predicted yields of a certain chip when the DFM countermeasure is not implemented and when it is implemented, the mass production number is R, and the factory cost is C. Assuming that the estimated manufacturing cost when the DFM countermeasure is not implemented is CM, the predicted manufacturing cost CM can be expressed by a function h of the predicted yield Y, the mass production number R, and the factory cost C as shown in the following equation (4). . Further, assuming that the predicted manufacturing cost when implementing DFM countermeasures is CM ′, the predicted manufacturing cost CM ′ is calculated from the predicted yield Y, Y ′, the number of mass production R, and the factory cost C as shown in the following equation (5). It can be represented by function h.

CM = h (R, Y, C) (4)
CM ′ = h (R, Y, Y ′, C) (5)
If the manufacturing cost improvement effect by implementing the DFM countermeasure is Z, the manufacturing cost improvement effect Z can be obtained by the following equation (6) using equations (4) and (5).

Z = CM−CM ′ (6)
The calculation formula table 6 stores formulas (4), (5), and (6), and the predicted yield calculation unit 2 uses formula (4) to calculate the predicted manufacturing cost CM when the DFM countermeasure is not implemented. The predicted manufacturing cost CM ′ for implementing the DFM countermeasure is calculated using the equation (5), and the manufacturing cost improvement effect Z is calculated using the equation (6).

  Returning to FIG. 4, the predicted manufacturing cost calculated when the predicted manufacturing cost calculation unit 3 implements the DFM countermeasure and the predicted manufacturing cost when the countermeasure is not implemented, and the manufacturing cost improvement effect are as follows. It is stored in the cost comparison table 13 provided.

FIG. 12 is an explanatory diagram of the contents of the cost comparison table.
As shown in FIG. 12, the cost comparison table 13 includes a DFM countermeasure name, which is an identification name assigned to different types of DFM countermeasures, and labor costs and infrastructure expenses that are predicted to be necessary for implementing each DFM countermeasure. And the like (same data stored in the DFM countermeasure cost table 12) and manufacturing cost improvement effect (= (predicted manufacturing cost when the DFM countermeasure is not implemented) − (predicted manufacturing when the DFM countermeasure is implemented) Cost)) is stored. The cost comparison table 13 stores data such as the chip name of the LSI chip to be designed, the predicted yield used in the process of obtaining the manufacturing cost improvement effect, and the number of mass production in association with the manufacturing cost improvement effect. May be.

  Further, the comparison / determination unit 4 included in the LSI chip design support system 1 shown in FIG. 4 compares and determines the data stored in the cost comparison table 13, and the display unit 5 displays the result on a display or the like. Display on the display device. The displayed data includes, for example, chip name, mass production number, DFM countermeasure name, predicted yield when implementing the DFM countermeasure, manufacturing cost improvement effect, DFM countermeasure cost, net cost effect (= (manufacturing cost improvement effect)) -(DFM countermeasure cost)). The display unit 5 displays such data, and when displaying data on a plurality of types of DFM countermeasures, displays them as a list.

  Further, as described above, in the LSI chip design support system 1, the contents of the calculation formula table 6 and the countermeasure coefficient table 7 are added based on the analysis / verification of the past design countermeasure results and the past yield results. Updated. In the LSI chip design support system 1, when such addition or update is performed, the calculation formula (predicted yield calculation formula) or countermeasure coefficient data to be added or updated is obtained from the past design measure results or the past yield results. It also has a mechanism (addition / update data check mechanism) for checking whether or not it is appropriate.

FIG. 13 is a diagram showing the configuration of the addition / update data check mechanism.
As shown in FIG. 13, the add / update data check mechanism 20 included in the LSI chip design support system 1 includes an input unit 21 to which a predicted yield calculation formula or countermeasure coefficient data to be added or updated is input, and an addition or update An evaluation unit 22 that evaluates the quality of predicted yield calculation formulas and countermeasure coefficient data to be updated is provided.

The input unit 21 temporarily stores the predicted yield calculation formula and countermeasure coefficient data to be added or updated in the calculation formula table 6 and the countermeasure coefficient table 7, respectively.
Then, as described above, the predicted yield calculation unit 2 uses the calculation formula table 6, the countermeasure coefficient table 7 and the chip specification table 8 in which such data is stored, and a chip developed in the past (past development chip). Of these, the predicted yield of the DFM countermeasure of the same type as that to be added or updated is calculated again and stored in the predicted yield table 23 for data check.

FIG. 14 is an explanatory diagram of the contents of the predicted yield table for data check.
As shown in FIG. 14, the data check prediction yield table 23 includes a chip name that is an identification name assigned to each type of LSI chip, and a DFM countermeasure that is an identification name assigned to each type of DFM countermeasure. The name (including the case where DFM countermeasures are not implemented) and the predicted yield of the past development chip calculated by the predicted yield calculation unit 2 are stored.

  Further, the evaluation unit 22 uses the data check prediction yield table 23 and the past development chip yield record table 24 storing the past development chip yield record as shown in FIG. The calculated predicted yield and the past yield performance are compared, and further compared with a specified value stored in a specified value table 25 as shown in FIG. 16, thereby evaluating the quality of the input data.

FIG. 15 is an explanatory diagram of the contents of the past development chip yield record table.
As shown in FIG. 15, the past development chip yield record table 24 includes a chip name that is an identification name assigned to different types of LSI chips and a DFM measure that is an identification name assigned to different types of DFM measures. A name (including a case where DFM countermeasures are not implemented) and a past development chip yield record are stored.

FIG. 16 is an explanatory diagram of the contents of the specified value table.
In the specified value table 25, as shown in FIG. 16, specified values (ranges) used as criteria for pass / fail evaluation, such as the standard deviation of the predicted yield and the actual yield of past developed chips and the average value of the differences, are set in advance. Stored.

The quality evaluation process in the evaluation unit 22 is performed as follows, for example. That is, the evaluation unit 22 firstly calculates the predicted yield Y ”of the past development chip calculated using the predicted yield calculation formula to be added or updated and the input data of the countermeasure coefficient, and the yield actual Y ^* of the past development chip. Difference Y ^* −Y ″. This is performed for a past development chip in which the DFM countermeasure of the same type as that to be added or updated is performed, and thereafter, for example, the standard deviation is obtained, compared with a specified value, and further displayed on a display or the like. When the calculated standard deviation is within the specified value, the calculation formula table 6 and the countermeasure coefficient table 7 are added or updated with the input data. When the calculated standard deviation is outside the specified value, the input data is input to the calculation formula table 6. Alternatively, the countermeasure coefficient table 7 may be deleted.

Next, the flow of processing in the LSI chip design support system 1 will be described.
First, an overall flow of processing for supporting the determination of implementation of DFM countermeasures will be described with reference to FIG. 17 and FIGS. 4 to 12 described above.

FIG. 17 is a flowchart of DFM countermeasure implementation decision support processing.
When the chip name of the LSI chip to be designed is input (step S50), the LSI chip design support system 1 first calculates the predicted yield calculation formula when the DFM countermeasure is not implemented from the calculation formula table 6 by the predicted yield calculation unit 2. Further, the corresponding chip characteristic value is extracted from the chip specification table 8 using the input chip name and the chip characteristic name included in the extracted predicted yield calculation formula as a key (step S51).

  Then, the predicted yield calculation unit 2 calculates the predicted yield when the DFM countermeasure is not implemented using the extracted predicted yield calculation formula and the chip characteristic value (step S52), and uses the calculated predicted yield as the DFM countermeasure. The name is stored in the predicted yield table 9 in association with the name (in this case, there is no DFM countermeasure) (step S53).

The subsequent steps S54 to S61 are performed for each DFM measure for all possible DFM measures.
That is, the predicted yield calculation unit 2 extracts a predicted yield calculation formula when implementing DFM countermeasures from the calculation formula table 6, and includes the chip name input in step S50 and the chip included in the extracted predicted yield calculation formula. The corresponding chip characteristic value is extracted from the chip specification table 8 using the characteristic name as a key, and further, the countermeasure coefficient table 7 using the DFM countermeasure name of the target DFM countermeasure and the coefficient name included in the predicted yield calculation formula as a key. The corresponding coefficient value is extracted from (Step S54).

  Then, the predicted yield calculation unit 2 uses the extracted predicted yield calculation formula, chip characteristic value, and coefficient value to calculate the predicted yield when the target DFM countermeasure is implemented (step S55), and the calculated prediction The yield is stored in the predicted yield table 9 in association with the DFM measure name of the target DFM measure (step S56).

  Next, the LSI chip design support system 1 extracts a predicted manufacturing cost calculation formula from the calculation formula table 6 by the predicted manufacturing cost calculation unit 3 (step S57). Subsequently, using the chip name input in step S50 as a key, the corresponding factory cost and mass production number are extracted from the factory cost table 10 and mass production number table 11, respectively, and the DFM countermeasure DFM of the target DFM countermeasure is extracted from the DFM countermeasure cost table 12. The countermeasure cost is extracted, and further, each predicted yield when the target DFM countermeasure is implemented and when not implemented is extracted from the predicted yield table 9 (step S58).

  Then, the predicted manufacturing cost calculation unit 3 uses the extracted predicted manufacturing cost calculation formula, factory cost, mass production number, and each predicted yield to calculate each predicted manufacturing cost when the target DFM countermeasure is implemented and when not implemented. Calculate (step S59). Further, the predicted manufacturing cost calculation unit 3 calculates a manufacturing cost improvement effect from the difference between the calculated predicted manufacturing costs (step S60), and the predicted manufacturing cost and the manufacturing cost improvement effect are extracted from the DFM countermeasure name and the extracted DFM. The cost is stored in the cost comparison table 13 in association with the countermeasure cost (step S61).

  In step S58, the DFM countermeasure cost is not extracted from the DFM countermeasure cost table 12. Instead, the DFM countermeasure cost is extracted in the step S61, and the cost comparison table together with the DFM countermeasure name and the manufacturing cost improvement effect is extracted. 13 may be stored.

The processing from step S54 to step S61 is performed for each DFM countermeasure.
Next, the LSI chip design support system 1 first extracts the manufacturing cost improvement effect and the DFM countermeasure cost from the cost comparison table 13 by the comparison / determination unit 4 (step S62). Subsequently, the comparison / determination unit 4 targets all the DFM measures for which the manufacturing cost improvement effect has been calculated, between the extracted manufacturing cost improvement effect and the corresponding DFM countermeasure cost, and the manufacturing cost improvement effect> the DFM countermeasure cost. Are determined (step S63).

  Then, the display unit 5 displays the DFM countermeasures determined by the comparison / determination unit 4 as satisfying the relationship of manufacturing cost improvement effect> DFM countermeasure costs, if necessary, the chip name and mass production number of the corresponding LSI chip. Then, it is displayed on the display together with the predicted yield (step S64).

  The LSI chip design support system 1 stores the actual design measures taken and their costs as past design measure results, for example, in a form that can be distinguished from the chip specifications acquired at the design start stage in the chip specification table 8. (Step S65).

  If the comparison / determination unit 4 determines that there is no DFM countermeasure satisfying the relationship of manufacturing cost improvement effect> DFM countermeasure cost (step S63), the fact is displayed on a display or the like as necessary. Then, the DFM countermeasure implementation decision support process is terminated.

  It should be noted that the chip designer is mainly responsible for managing the processing of steps S50 to S65 in the LSI chip design support system 1. The chip designer can determine which DFM countermeasure to implement based on the display in step S64.

  Next, the flow of data addition / update processing for the calculation formula table 6 and the countermeasure coefficient table 7 will be described with reference to FIG. 18 and FIGS. 5 to 7 and FIGS. Here, the case where both the predicted yield calculation formula stored in the calculation formula table 6 and the coefficient value of the countermeasure coefficient stored in the countermeasure coefficient table 7 are added or changed will be described as an example.

FIG. 18 is a flowchart of the data addition / update process.
When adding or updating calculation formulas and countermeasure coefficients to the calculation formula table 6 and countermeasure coefficient table 7, the LSI chip design support system 1 uses the input unit 21 to add a new predicted yield calculation formula and countermeasure coefficients to be added or updated. Is input (step S70), the input data is temporarily stored in the calculation formula table 6 and the countermeasure coefficient table 7 respectively (step S71).

The subsequent steps S72 to S74 are performed by the number of past development chips that have implemented the same type of DFM countermeasures as the target of addition or update.
That is, the LSI chip design support system 1 extracts the predicted yield calculation formula input in step S70 from the calculation formula table 6 by the predicted yield calculation unit 2, and the countermeasure coefficient input in step S70 from the countermeasure coefficient table 7. The coefficient value is extracted, and the chip characteristic value of the target past developed chip is extracted from the chip specification table 8 (step S72).

  Then, the predicted yield calculation unit 2 uses the extracted predicted yield calculation formula, coefficient value, and chip characteristic value to calculate a predicted yield when these are applied to the target past development chip (step S73). The predicted yield thus obtained is stored in the data check predicted yield table 23 in association with the chip name of the past development chip and the DFM countermeasure name of the DFM countermeasure implemented on the past development chip (step S74).

The processes from step S72 to step S74 are performed by the number of past development chips that have implemented the same type of DFM countermeasures as the addition or update target.
Next, in the LSI chip design support system 1, first, the evaluation unit 22 calculates the predicted yield and the yield of the past development chip calculated for the past development chip from the data check prediction yield table 23 and the past development chip yield result table 24, respectively. The results are extracted together with the chip name and DFM countermeasure name stored in association with them (step S75). Further, the evaluation unit 22 extracts a predetermined specified value from the specified value table 25 (step S76).

  Then, the evaluation unit 22 compares the difference between the predicted yield and the actual yield (for example, standard deviation) and the extracted specified value in consideration of the chip name of the past developed chip and the DFM countermeasure name (step Further, they are displayed on a display or the like (step S78).

  After that, for example, when the difference between the predicted yield of the past developed chip and the actual yield is within a specified value (step S79), the LSI chip design support system 1 sets the calculation formula table 6 and the countermeasure coefficient table 7 to step S70. The data is added or updated according to the data input in (Step S80), and the process is terminated. If the difference between the predicted yield and the actual yield of the past developed chip is outside the specified value (step S79), the data input in step S70 is deleted from the calculation formula table 6 and the countermeasure coefficient table 7 (step S81). ), The process is terminated.

  The management of the processing of steps S70 to S81 in the LSI chip design support system 1 is mainly handled by a chip design engineer. Further, the processing in steps S79 to S81 may be manually performed by such a chip design engineer based on the display in step S78.

  In addition, FIG. 18 illustrates a process in the case where both the predicted yield calculation formula and the countermeasure coefficient are added or changed. However, the same process is applied to the addition or change of only the predicted yield calculation formula and the countermeasure coefficient. It can be carried out.

  That is, when only the predicted yield calculation formula is added or changed, in the process up to step S73, the new predicted yield calculation formula and the countermeasure coefficient used so far are used as they are to predict the previously developed chip. What is necessary is just to calculate a yield. When only the countermeasure coefficient is added or changed, in the processing up to step S73, the predicted yield of the past development chip is calculated by using the new countermeasure coefficient and the predicted yield calculation formula used so far. What is necessary is just to calculate.

Next, an embodiment of LSI chip development using the LSI chip design support system 1 will be described.
19 is a diagram illustrating an example of a calculation formula table, FIG. 20 is a diagram illustrating an example of a countermeasure coefficient table, FIG. 21 is a diagram illustrating an example of a chip specification table, FIG. 22 is a diagram illustrating an example of a predicted yield table, and FIG. FIG. 24 is a diagram illustrating an example of a factory cost / mass production number table, FIG. 24 is a diagram illustrating an example of a DFM countermeasure cost table, and FIG. 25 is a diagram illustrating an example of a cost comparison table.

Here, it is assumed that the data of each table excluding the predicted yield table 9a in FIG. 22 and the cost comparison table 13a in FIG. 25 has already been acquired.
In addition, here, as DFM countermeasures, two types of relaxation wiring and double VIA are illustrated. The relaxed wiring is a measure for arranging the wiring so as not to concentrate on a small area, and is implemented mainly for the purpose of suppressing the occurrence of wiring defects. The double VIA is a measure for forming two VIAs for connecting a pair of upper and lower layer wirings. When a formation defect occurs mainly in one of the VIAs, the other VIA is used for conduction. It is implemented for the purpose of ensuring. These wiring defects and VIA formation defects are more likely to occur with the miniaturization of chips.

After planning, a chip specification is acquired at the design start stage, and when, for example, “MB123” is input as a chip name to the LSI chip design support system 1, first, the calculation formula shown in FIG. A calculation formula “(1+ (chip area + sensing area × 2) × 5 × 10 ⁻⁴ ) ⁻³ ” for obtaining a calculation result name “predicted yield without countermeasure” is extracted from the table 6a. Further, from the chip specification table 8a shown in FIG. 21, the predicted yield calculator 2 uses the input chip name “MB123” and the chip characteristic names “chip area” and “sensed area” included in the extracted calculation formula as keys. Corresponding chip characteristic values “60.8” and “50.2” are extracted. Then, using this calculation formula and the chip characteristic value, the “predicted yield without countermeasure” is calculated. That is,
“Predicted yield without countermeasures” = (1+ (chip area + sensing area × 2) × 5 × 10 ⁻⁴ ) ⁻³ = (1+ (60.8 + 50.2 × 2) × 5 × 10 ⁻⁴ ) ⁻³ = 0 .79
It becomes.

The calculation result of the calculated “predicted yield without countermeasure” is stored in the predicted yield table 9a shown in FIG.
Subsequently, a calculation formula “(1+ (X1 × chip area + X2 × sensing area × 2)” for calculating the calculation result name “predicted yield with countermeasure” from the calculation formula table 6a shown in FIG. × 5 × 10 ⁻⁴ ) ⁻³ ”is extracted. Further, from the chip specification table 8a shown in FIG. 21, the predicted yield calculator 2 uses the input chip name “MB123” and the chip characteristic names “chip area” and “sensed area” included in the extracted calculation formula as keys. Corresponding chip characteristic values “60.8” and “50.2” are extracted. Further, the predicted yield calculation unit 2 first calculates coefficient values “1.1” and “0” corresponding to the coefficient names “X1” and “X2” of the DFM countermeasure name “relaxed wiring” from the countermeasure coefficient table 7a shown in FIG. .5 "is extracted. Then, the “predicted yield with countermeasure” (relaxed wiring) is calculated using the calculation formula, the chip characteristic value, and the coefficient value. That is,
“Predicted yield with countermeasures” (relaxed wiring) = (1+ (X1 × chip area + X2 × sensing area × 2) × 5 × 10 ⁻⁴ ) ⁻³ = (1+ (1.1 × 60.8 + 0.5 × 50. 2 × 2) × 5 × 10 ⁻⁴ ) ⁻³ = 0.84
It becomes. The calculation result of “predicted yield with countermeasure” (relax wiring) is stored in the predicted yield table 9a shown in FIG. 22 in association with the DFM countermeasure name.

Next, the calculation formula “fixed cost + (variable cost × number of mass production)” for obtaining the calculation result name “predicted manufacturing cost without countermeasure” is extracted from the calculation formula table 6a shown in FIG. Is done. Further, the estimated manufacturing cost calculation unit 3 uses the input chip name “MB123” and the “fixed cost”, “variable cost”, and “mass production” included in the extracted calculation formula as keys, and the factory cost shown in FIG. The corresponding values “1000000”, “300”, and “1000000” are extracted from the mass production number table 10a. Then, the “predicted manufacturing cost without countermeasure” is calculated using the calculation formula, the factory cost, and the number of mass production. That is,
“Prevented manufacturing cost without countermeasures” = fixed cost + (variable cost × number of mass production) = 1000000 + (300 × 1000000) = 301 million (yen)
It becomes.

Subsequently, the calculation formula “fixed cost + (variable cost × number of mass production) × () for calculating the calculation result name“ predicted manufacturing cost with countermeasures ”from the calculation formula table 6a shown in FIG. Predicted yield without countermeasure / predicted yield with countermeasure)) is extracted. Further, the estimated manufacturing cost calculation unit 3 uses the chip name “MB123” and “fixed cost”, “variable cost”, and “mass production number” included in the calculation formula as a key to the factory cost / mass production table 10a shown in FIG. Are extracted from the corresponding values “1000000”, “300”, and “1000000”, respectively. Further, the predicted manufacturing cost calculation unit 3 extracts “predicted yield without countermeasure” and “predicted yield with countermeasure” (relaxed wiring) from the predicted yield table 9a. Then, using these, a “predicted manufacturing cost with countermeasures” (relax wiring) is calculated. That is,
“Predicted manufacturing cost with measures” (relaxed wiring) = fixed cost + (variable costs × number of mass production) × (predicted yield without measures / predicted yield with measures) = 1000000 + (300 × 1000000) × (0.79 / 0.84) ) ≒ 283 million (yen)
It becomes.

Further, the predicted manufacturing cost calculation unit 3 extracts a calculation formula for calculating the calculation result name “manufacturing cost improvement effect” from the calculation formula table 6a, and calculates its value. That is,
“Manufacturing cost improvement effect” (relaxed wiring) = “predicted manufacturing cost without countermeasures” − “predicted manufacturing cost with countermeasures” (relaxed wiring) = 301000000-283000000 = 18000000 (yen)
It becomes.

  The calculated “manufacturing cost improvement effect” (relaxation wiring) and the DFM countermeasure cost (the total value of “personnel cost”, “infrastructure cost” and other expenses) in the DFM countermeasure cost table 12a shown in FIG. 24 are shown in FIG. The cost comparison table 13a shown is stored in association with the DFM countermeasure name.

The same processing is performed for another DFM countermeasure, and in the case of dual VIA,
“Predicted yield with countermeasures” (double VIA) = (1+ (X1 × chip area + X2 × sensing area × 2) × 5 × 10 ⁻⁴ ) ⁻³ = (1+ (1.1 × 60.8 + 0.7 × 50.2 × 2) × 5 × 10 ⁻⁴ ) ⁻³ = 0.82
“Predicted manufacturing cost with countermeasures” (double VIA conversion) = fixed cost + (variable cost × number of mass production) × (predicted yield without countermeasure / predicted yield with countermeasure) = 1000000 + (300 × 1000000) × (0.79 × 0 .82) ≒ 290000000 (yen)
“Production cost improvement effect” (double VIA conversion) = “predicted manufacturing cost without countermeasure” − “predicted manufacturing cost with countermeasure” (double VIA conversion) = 301000000-290000000 = 11,000,000 (yen)
It becomes. The “predicted manufacturing cost without countermeasures” can be calculated at the time of the process for the previous relaxed wiring, but may be calculated again at the time of the process for the double VIA.

  The calculation result of “predicted yield with countermeasure” (double VIA conversion) is stored in the predicted yield table 9a shown in FIG. 22 in association with the DFM countermeasure name. Further, the “manufacturing cost improvement effect” (double VIA conversion) is stored in association with the DFM countermeasure name in the cost comparison table 13a shown in FIG. 25 together with the DFM countermeasure cost of the DFM countermeasure cost table 12a shown in FIG.

  Subsequently, the comparison / determination unit 4 extracts “manufacturing cost improvement effect” and “DFM countermeasure cost” from the cost comparison table 13a, and whether or not the relationship “manufacturing cost improvement effect”> “DFM countermeasure cost” is satisfied. Are compared and determined, and the display unit 5 displays the DFM countermeasure names satisfying the relationship on the display.

FIG. 26 is a display example of the result.
On the display screen 30 of the display, for example, as shown in FIG. 26, a chip name, a DFM countermeasure name, a mass production number, a yield improvement (degree), a manufacturing cost improvement effect, a DFM countermeasure cost, and a net cost effect are displayed. be able to.

  Note that the chip name is acquired from the input data. The DFM countermeasure name, the manufacturing cost improvement effect, and the DFM countermeasure cost can be extracted from the cost comparison table 13a. The mass production number can be extracted from the factory cost / mass production number table 10a. Yield improvement can be extracted from the predicted yield table 9a. The net cost effect can be obtained using the manufacturing cost improvement effect and the DFM countermeasure cost. Further, the data to be displayed on the display screen 30 may be stored in the cost comparison table 13a in advance before being displayed in association with the DFM countermeasure cost and the manufacturing cost improvement effect.

  Thereafter, based on such indications, an appropriate DFM countermeasure, for example, a DFM countermeasure with high yield and cost effectiveness is selected, and the design is advanced using the DFM countermeasure, and the manufacturing is performed based on the design and the test is performed. What should I do?

Moreover, addition and update of the contents of the calculation formula table 6a and the countermeasure coefficient table 7a are performed as follows, for example.
When adding or updating the contents of the calculation formula table 6a and the countermeasure coefficient table 7a, first, the predicted yield calculation formula and countermeasure coefficient data to be added or updated are input. For example, the user inputs predetermined data to the LSI chip design support system 1 while watching the screen displayed on the display or the like.

FIG. 27 shows a display example of the input screen.
The input screen 40 includes a column 41 for inputting a calculation formula for a predicted yield, a column 42 for inputting or selecting a DFM countermeasure name, a plurality of columns 43 for inputting coefficient names of countermeasure coefficients included in the calculation formula, and coefficient values. A plurality of fields 44 are provided for inputting.

  When the contents as shown in FIG. 27 are input to such an input screen 40, in the LSI chip design support system 1, the input unit 21 inputs the input data to the calculation formula table 6a and the countermeasure coefficient table 7a. Each is stored temporarily.

  Next, the predicted yield calculation unit 2 extracts the calculation formula from the calculation formula table 6a, extracts the coefficient value from the countermeasure coefficient table 7a using the coefficient name as a key, and inputs the chip characteristic name included in the calculation formula and the input Alternatively, the chip characteristic value of the previously developed chip is extracted from the chip specification table 8a using the selected DFM countermeasure name as a key. Then, using these data, the predicted yield for the past development chip is calculated, and the calculation result is stored in the data check predicted yield table 23a.

FIG. 28 is a diagram showing an example of a data check prediction yield table. FIG. 29 is a diagram showing an example of a past development chip yield record table.
As shown in FIG. 28, in the predicted yield table for data check 23a, the “predicted yield” newly calculated for the past development chip indicates the chip name of the past development chip and the “DFM countermeasure name” implemented on the past development chip. Stored in association with.

  Similarly, as shown in FIG. 29, the past development chip yield record is stored in the past development chip yield record table 24a in association with the chip name of the past development chip and the “DFM countermeasure name” implemented for the past development chip. Is done.

  The past development chip in which the “predicted yield” calculation processing for the past development chip and the storage processing of the calculation result in the data check prediction yield table 23a implement the same type of DFM countermeasures as the target of addition or update To be done. FIG. 28 shows a case where “predicted yield” calculation processing and calculation result storage processing are performed for both relaxation wiring and double VIA conversion, which are DFM countermeasures.

  Next, the evaluation unit 22 uses the chip name and “DFM countermeasure name” as keys, and the “predicted yield” and the past calculated for the past developed chip from the predicted yield table for data check 23a and the past developed chip yield record table 24a, respectively. The “yield record” of the developed chip is extracted. In addition, a predetermined specified value is extracted from the standard value table.

Then, the standard deviation of the “predicted yield” and the “yield record” is calculated by the evaluation unit 22 for the previously developed chip that has implemented the same type of DFM countermeasure, and is compared with the specified value. The standard deviation σ can be obtained by σ = Σ (A−M) ² / (number−1) where A = “actual yield” − “predicted yield” and M = Σ | A | / number. . The specified value and the obtained standard deviation σ are displayed on the display.

  In addition, when the standard deviation σ of the “predicted yield” and “yield result” of the past development chip is within the specified value, the calculation formula table 6a and the countermeasure coefficient table 7a are added by the data input to the input screen 40 or Updated. Further, when the standard deviation σ of “predicted yield” and “yield result” of the past developed chip is outside the specified value, the input data is deleted from the calculation formula table 6a and the countermeasure coefficient table 7a.

  Here, the case where the user inputs the predicted yield calculation formula and countermeasure coefficient data to be added or updated while looking at the input screen 40 has been described. However, these data are automatically generated based on past development results. If it can be generated, the process following such an input step may be performed using the automatically generated data.

  As described above, according to the LSI chip design support system 1, the yield when the DFM countermeasure is implemented using the chip specifications acquired at the early stage of the chip design such as the design start time or immediately after the design start, and the yield Since it is possible to predict the manufacturing cost, it is possible to improve chip development speed without design iteration.

  Further, since the yield and the manufacturing cost are predicted at the chip design stage for each DFM countermeasure that can be implemented on the chip, it is possible to determine whether to implement the DFM countermeasure suitable for the chip. In addition, since the yield improvement of each DFM measure and the contribution to the manufacturing cost are clarified, it is possible to judge the implementation of the DFM measure suitable for the chip, and the knowledge can be used for the subsequent chip design to quickly use the chip. It becomes possible to manufacture at a high yield.

  Furthermore, such LSI chip design support system 1 is shared by various users involved in chip development, such as chip designers in charge of chip design and chip design engineers in charge of technology development related to chip design. By using this, the chip can be manufactured more quickly and with a high yield.

The processing functions of the LSI chip design support system 1 can be realized using a computer.
The computer includes a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), HDD (Hard Disk Drive), graphic processing unit, input I / F (Interface), communication I / F, etc. These are connected via a bus. The CPU executes processing by using a program stored in the HDD and data stored (stored) in each of the above tables. The ROM stores basic programs and data executed by the CPU. The RAM stores programs and data being executed by the CPU. The HDD stores (stores) data such as an OS (Operation System) executed by the CPU, application programs, and the above tables. A display device such as a display is connected to the graphic processing unit, and the graphic processing unit displays an image on the screen of the display device in accordance with a drawing command from the CPU. A mouse and a keyboard are connected to the input I / F, and information input by the user is received by these and transmitted to the CPU via the bus. The communication I / F is an interface for LAN connection between computers.

Each processing function of the LSI chip design support system 1 can be realized by a computer having such a hardware configuration.
In addition, a program (LSI chip design support program) describing the processing contents of the functions that the LSI chip design support system 1 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer.

  The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Magnetic recording devices include HDDs, flexible disks (FD), magnetic tapes, and the like. Examples of the optical disc include a DVD (Digital Versatile Disk), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. Further, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

  In the above description, the development of LSI has been described as an example. Of course, the design support system, the design support method, and the design support program as described above may be such a semiconductor integrated circuit (IC). It is applicable to the development of various semiconductor devices including

Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
(Supplementary Note 1) In a semiconductor device design support system used for designing a semiconductor device,
Specification storage means for storing specifications at the design start stage of the semiconductor device;
Design measure cost storage means for storing a design measure cost required for a design measure that can be implemented in the semiconductor device;
Using the specifications stored in the specification storage means, predicted yield calculation means for calculating a predicted yield when the design countermeasure is not implemented and a predicted yield when the design countermeasure is implemented;
Using the predicted yield when not implementing the design measure calculated by the predicted yield calculation means and the predicted yield when executing the design measure, the predicted manufacturing cost when not implementing the design measure and the design measure A predicted manufacturing cost calculating means for calculating a predicted manufacturing cost in the case of carrying out;
The difference between the predicted manufacturing cost when not implementing the design measure calculated by the predicted manufacturing cost calculating unit and the predicted manufacturing cost when executing the design measure, and the design stored in the design measure cost storing unit Comparison / determination means for comparing / determining countermeasure costs,
A semiconductor device design support system comprising:

(Supplementary Note 2) The design measure cost storage means stores a plurality of design measure costs required for a plurality of the design measures,
The predicted yield calculation means calculates, for each design measure, a predicted yield when the design measure is not implemented and a predicted yield when the design measure is implemented,
The predicted manufacturing cost calculation means calculates, for each design measure, a predicted manufacturing cost when the design measure is not implemented and a predicted manufacturing cost when the design measure is implemented,
The comparison determination unit stores, for each of the design measures, a difference between a predicted manufacturing cost when the design measure is not implemented and a predicted manufacturing cost when the design measure is implemented, and is stored in the design measure cost storage unit. Compare and judge the target design measures cost,
The semiconductor device design support system according to appendix 1, wherein

(Additional remark 3) The calculation formula which stores the 1st calculation formula used for calculation of the prediction yield when not implementing the said design measure, and the 2nd calculation formula used for calculation of the prediction yield when implementing the said design measure Storage means;
Coefficient storage means for storing coefficients used in the second calculation formula;
Have
The predicted yield calculation means includes:
Using the specification stored in the specification storage unit and the first calculation formula stored in the calculation formula storage unit, calculate a predicted yield when the design measure is not implemented,
When the design measure is implemented using the specifications stored in the specification storage unit, the second calculation formula stored in the calculation formula storage unit, and the coefficient stored in the coefficient storage unit Calculate the predicted yield of
The semiconductor device design support system according to appendix 1, wherein

(Supplementary Note 4) When a new calculation formula is stored in the calculation formula storage means, the validity of the new calculation formula stored is the specifications of the semiconductor device developed in the past and the semiconductor developed in the past. It has an evaluation means for evaluating using the device yield record,
The predicted yield calculation means calculates the predicted yield of the semiconductor device developed in the past using the specifications of the semiconductor device developed in the past and the new calculation formula stored in the calculation formula storage means. ,
The evaluation means compares and evaluates the calculated yield of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past.
The semiconductor device design support system according to supplementary note 3, wherein

(Supplementary Note 5) When a new coefficient is stored in the coefficient storage means, the validity of the new coefficient stored is determined based on the specifications of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past. Having an evaluation means to evaluate using actual results,
The predicted yield calculation means uses specifications of the semiconductor device developed in the past, the second calculation formula stored in the calculation formula storage means, and the new coefficient stored in the coefficient storage means. Calculating the predicted yield of the semiconductor device developed in the past,
The evaluation means compares and evaluates the calculated yield of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past.
The semiconductor device design support system according to supplementary note 3, wherein

(Additional remark 6) The said estimated manufacturing cost calculating means is
Using the predicted yield when not implementing the design measure calculated by the predicted yield calculation means, calculating the predicted manufacturing cost when not implementing the design measure,
Using the predicted yield when not implementing the design measure calculated by the predicted yield calculation means and the predicted yield when implementing the design measure, calculating the predicted manufacturing cost when implementing the design measure;
The semiconductor device design support system according to appendix 1, wherein

(Appendix 7) Factory cost storage means for storing factory costs required for manufacturing the semiconductor device;
A mass production number storage means for storing the mass production number of the semiconductor device;
Have
The predicted manufacturing cost calculation means includes
Using the factory cost stored in the factory cost storage means and the mass production number stored in the mass production number storage means, calculate a predicted manufacturing cost when the design measure is not implemented,
The factory cost stored in the factory cost storage means, the mass production number stored in the mass production number storage means, the predicted yield and the design when the design measure calculated by the predicted yield calculation means is not implemented Using the predicted yield when implementing the measure, calculate the predicted manufacturing cost when implementing the design measure,
The semiconductor device design support system according to appendix 1, wherein

  (Supplementary Note 8) The comparison / determination unit compares the reduction amount of the predicted manufacturing cost when the design countermeasure is performed with respect to the predicted manufacturing cost when the design countermeasure is not performed and the design countermeasure cost, and reduces the decrease. The semiconductor device design support system according to appendix 1, wherein it is determined whether or not an amount exceeds the design countermeasure cost.

  (Additional remark 9) It has a display means which displays the difference of the estimated manufacturing cost when not implementing the said design countermeasure, and the estimated manufacturing cost when implementing the said design countermeasure, and the comparison and determination result with the said design countermeasure cost. The semiconductor device design support system according to supplementary note 1, characterized by:

(Supplementary Note 10) In a semiconductor device design support method used for designing a semiconductor device,
A specification storage means stores a specification at the design start stage of the semiconductor device,
The design measure cost storage means stores the design measure cost required for the design measure that can be implemented in the semiconductor device,
Predictive yield calculation means uses the specifications stored in the specification storage means to calculate a predicted yield when the design countermeasure is not implemented and a predicted yield when the design countermeasure is implemented,
Prediction when the predicted manufacturing cost calculation means does not implement the design measure using the predicted yield when the design measure calculated by the predicted yield calculation means is not executed and the predicted yield when the design measure is executed Calculate the manufacturing cost and the predicted manufacturing cost when implementing the design measures,
The difference between the predicted manufacturing cost when the comparison / determination means does not implement the design measure calculated by the predicted manufacturing cost calculation means and the predicted manufacturing cost when the design measure is executed, and the design measure cost storage means Compare and judge the design countermeasure cost stored in
A semiconductor device design support method.

(Supplementary Note 11) In a semiconductor device design support program used for designing a semiconductor device,
Computer
Specification storage means for storing specifications at the design start stage of the semiconductor device,
Design measure cost storage means for storing a design measure cost required for a design measure that can be implemented in the semiconductor device;
Using the specifications stored in the specification storage means, predicted yield calculation means for calculating a predicted yield when the design countermeasure is not implemented and a predicted yield when the design countermeasure is implemented;
Using the predicted yield when not implementing the design measure calculated by the predicted yield calculation means and the predicted yield when executing the design measure, the predicted manufacturing cost when not implementing the design measure and the design measure A predicted manufacturing cost calculating means for calculating a predicted manufacturing cost in the case of carrying out;
The difference between the predicted manufacturing cost when not implementing the design measure calculated by the predicted manufacturing cost calculating unit and the predicted manufacturing cost when executing the design measure, and the design stored in the design measure cost storing unit Comparison / determination means for comparing / determining countermeasure costs,
A semiconductor device design support program characterized by functioning as

It is a figure explaining the flow of implementation of the design measure in LSI chip development. It is a figure which shows the relationship between the number of mass production and the cost when not implementing DFW countermeasures. It is a figure which shows the relationship between the number of mass production and cost in the case of implementing different DFM countermeasures. It is a figure which shows the principle structure of a LSI chip design support system. It is content explanatory drawing of a calculation formula table. It is content explanatory drawing of a countermeasure coefficient table. It is content explanatory drawing of a chip specification table. It is a content explanatory view of a prediction yield table. It is content explanatory drawing of a factory cost table. It is content explanatory drawing of a mass production number table. It is content explanatory drawing of a DFM countermeasure cost table. It is content explanatory drawing of a cost comparison table. It is a figure which shows the structure of an addition / update data check mechanism. It is content explanatory drawing of the prediction yield table for a data check. It is content explanatory drawing of the past development chip yield results table. It is a content explanatory view of a regulation value table. It is a flowchart of the implementation decision support process of a DFM countermeasure. It is a flowchart of a data addition / update process. It is a figure which shows an example of a calculation formula table. It is a figure which shows an example of a countermeasure coefficient table. It is a figure which shows an example of a chip specification table. It is a figure which shows an example of a prediction yield table. It is a figure which shows an example of a factory cost and mass production number table. It is a figure which shows an example of a DFM countermeasure cost table. It is a figure which shows an example of a cost comparison table. It is a display example of a result. It is a display example of an input screen. It is a figure which shows an example of the prediction yield table for data checks. It is a figure which shows an example of the past development chip yield results table. It is a figure explaining the flow of implementation of the conventional design measure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 LSI chip design support system 2 Predicted yield calculating part 3 Predicted production cost calculating part 4 Comparison / determination part 5 Display part 6, 6a Calculation formula table 7, 7a Countermeasure coefficient table 8, 8a Chip specification table 9, 9a Predictive yield table 10 Factory cost table 10a Factory cost / mass production number table 11 Mass production number table 12, 12a DFM countermeasure cost table 13, 13a Cost comparison table 20 Add / update data check mechanism 21 Input unit 22 Evaluation unit 23, 23a Predictive yield table for data check 24 24a Past development chip yield results table 25 Specified value table 30 Display screen 40 Input screen 41, 42, 43, 44

Claims (5)

In a semiconductor device design support system used for designing a semiconductor device,
Specification storage means for storing specifications at the design start stage of the semiconductor device;
Design measure cost storage means for storing a design measure cost required for a design measure that can be implemented in the semiconductor device;
Using the specifications stored in the specification storage means, predicted yield calculation means for calculating a predicted yield when the design countermeasure is not implemented and a predicted yield when the design countermeasure is implemented;
Using the predicted yield when not implementing the design measure calculated by the predicted yield calculation means and the predicted yield when executing the design measure, the predicted manufacturing cost when not implementing the design measure and the design measure A predicted manufacturing cost calculating means for calculating a predicted manufacturing cost in the case of carrying out;
The difference between the predicted manufacturing cost when not implementing the design measure calculated by the predicted manufacturing cost calculating unit and the predicted manufacturing cost when executing the design measure, and the design stored in the design measure cost storing unit Comparison / determination means for comparing / determining countermeasure costs,
A semiconductor device design support system comprising: A calculation formula storage means for storing a first calculation formula used for calculating a predicted yield when the design measure is not implemented and a second calculation formula used for calculating a predicted yield when the design measure is implemented;
Coefficient storage means for storing coefficients used in the second calculation formula;
Have
The predicted yield calculation means includes:
Using the specification stored in the specification storage unit and the first calculation formula stored in the calculation formula storage unit, calculate a predicted yield when the design measure is not implemented,
When the design measure is implemented using the specifications stored in the specification storage unit, the second calculation formula stored in the calculation formula storage unit, and the coefficient stored in the coefficient storage unit Calculate the predicted yield of
The semiconductor device design support system according to claim 1. When a new calculation formula is stored in the calculation formula storage means, the validity of the stored new calculation formula is determined based on the specifications of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past. And an evaluation means for evaluating using
The predicted yield calculation means calculates the predicted yield of the semiconductor device developed in the past using the specifications of the semiconductor device developed in the past and the new calculation formula stored in the calculation formula storage means. ,
The evaluation means compares and evaluates the calculated yield of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past.
The semiconductor device design support system according to claim 2. When a new coefficient is stored in the coefficient storage means, the validity of the stored new coefficient is determined using the specifications of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past. Evaluation means to evaluate
The predicted yield calculation means uses specifications of the semiconductor device developed in the past, the second calculation formula stored in the calculation formula storage means, and the new coefficient stored in the coefficient storage means. Calculating the predicted yield of the semiconductor device developed in the past,
The evaluation means compares and evaluates the calculated yield of the semiconductor device developed in the past and the yield of the semiconductor device developed in the past.
The semiconductor device design support system according to claim 2.   The comparison / determination unit compares a reduction amount of the predicted manufacturing cost when the design measure is implemented with respect to the predicted manufacturing cost when the design measure is not implemented, and the design measure cost, and the reduction amount is the design measure 2. The semiconductor device design support system according to claim 1, wherein it is determined whether or not the countermeasure cost is exceeded.

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