JP2008084455A - Error correcting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an error correcting method improving encoding efficiency in a hologram memory recording and reproducing device of two dimensional code. <P>SOLUTION: Bits in the same positions of respective code words are extracted as one bit string respectively with respect to the prescribe number of two dimensional code words (step 101), error correction encoding is applied to each bit string other than one bit string in the two dimensional code word block and a plurality of parity bits are generated (step 102), the two dimensional code word corresponding to the parity bit is two-dimensionally demodulated and the plurality of parity bits are generated, error correction is applied to the bit string being error-correction-encoded in the two dimensional code word block using the plurality of parity bits, and error correction is performed using a two dimensional encoding rule for bit strings to which the error correction encoding is not applied in the error correction encoding step on the basis of the result (step 203). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a correction method for a hologram memory recording / reproducing apparatus using a hologram as a recording medium.

  The hologram memory recording / reproducing apparatus records and reproduces digital data by creating interference fringes on a hologram memory medium. In a conventional hologram memory recording / reproducing apparatus, during modulation, a two-dimensional encoding method is performed in which 2-bit recording data is converted into a two-dimensional array (two-dimensional codeword) of 2 × 2 cells as shown in FIG. Is disclosed. In FIG. 14, 1101 is a cell that transmits light (High), and 1102 to 1104 are cells that shield light (Low) (for example, refer to Patent Document 1).

  In recent years, a signal processing method has been disclosed in which error correction coding (RS: Reed-Solomon) is performed after modulation to reduce the influence of error increase due to demodulation (see, for example, Non-Patent Document 1). .

  FIG. 15 is a block diagram of a recording / reproducing apparatus that performs RS encoding after performing conventional modulation. FIG. 16 is a flowchart showing processing performed from the RS encoding circuit 2 to the RS decoding circuit 7 in FIG.

In the encoding step, first, the RS encoding circuit 2 adds a parity bit to the data (modulation codeword) encoded by the first modulation circuit 1 (step 501). Next, the added parity bit is modulated by the second modulation circuit 3 (step 502).
Thereafter, the RS encoded data is recorded on the medium as recording data in the recording / reproducing circuit 4.
In the decoding step, first, the data reproduced from the medium in the recording / reproducing circuit 4 is binarized by the binarizing circuit 5 (step 601). Next, only the parity bit part is demodulated in the second demodulation circuit 6 (step 602). Then, the RS decoding circuit 7 corrects an error for each RS codeword restored by demodulating the parity bit part (step 603).
Japanese Patent Laid-Open No. 9-197947 IEICE Transactions A Vol. J82-A No. 2 p. 267

  However, in a hologram memory recording / reproducing apparatus that performs two-dimensional encoding, the encoded data has a data amount twice that of the data before encoding. Therefore, when the conventional RS encoding is applied, the encoding efficiency is increased. Has a problem that it is greatly deteriorated.

  The present invention solves the conventional problems and provides an error correction method for improving coding efficiency by applying the characteristic that the number of High bits of a two-dimensional code is determined to RS coding. For the purpose.

  In order to solve the above-described conventional problem, the error correction method of the present invention extracts a bit existing at the same position of each codeword as a bit string for a predetermined number of two-dimensional codewords. A first sequence conversion step for generating a codeword block; and error correction encoding for each remaining bit string excluding one bit string for the two-dimensional codeword block to generate a plurality of parity bits, An error correction encoding step of generating a coding unit block by placing a two-dimensional codeword generated by performing two-dimensional code modulation on a plurality of parity bits at the end of the two-dimensional codeword block; A first sequence reverse conversion step for performing a process reverse to the one sequence conversion step to rearrange the coding unit blocks so as to become a two-dimensional codeword; and the first sequence reverse conversion step. A binarization step of binarizing luminance data obtained by recording and reproducing a plurality of two-dimensional codewords generated by the recording on a hologram memory recording medium to reproduce a two-dimensional codeword, and the binarization step A second sequence conversion step of collecting the binarized two-dimensional codewords for each encoding unit block and performing the same processing as the first sequence conversion step to generate the encoding unit block; A two-dimensional codeword corresponding to the parity bit is two-dimensionally code demodulated from a coding unit block to generate the plurality of parity bits, and the error correction code of the two-dimensional codeword block using the plurality of parity bits Error correction is performed on the converted bit string, and a two-dimensional coding rule is applied to the bit string that is not subjected to the error correction coding in the error correction coding step based on the result. An error correction step for performing error correction using the second correction code, and a second process for reproducing a two-dimensional codeword by performing the same processing as the first sequence inverse transform step on the two-dimensional codeword block subjected to error correction. It is characterized by comprising the sequence inverse transformation step.

  Further, in the error correction method, the error correction encoding step divides the data obtained by the first sequence conversion step into check unit blocks for each predetermined number of two-dimensional code words, and each check unit block has an arbitrary An error correction codeword that generates a parity bit by performing error correction coding for each row on the remaining rows excluding one bit string and outputs the error correction codeword with the parity bit added to each row A generation step, and a parity bit modulation step that performs a two-dimensional code modulation on the parity bit to form a parity bit portion, and generates a coding unit block that combines the check unit block and the parity bit portion. It is characterized by that.

  Further, in the error correction method, the error correction step detects and corrects an error for each error correction code word for the data obtained by the second sequence conversion step, and the error correction result and the two-dimensional code Error correction is performed on a bit string that has not been subjected to error correction coding using the property that if the values of all the remaining bits except one bit in the word are determined, the value of the remaining one bit is also determined. It is characterized by this.

  Further, in the error correction method, the error correction step is a parity bit for dividing the data obtained by the second sequence conversion step for each coding unit block and performing two-dimensional code demodulation only on the parity bit portion. A demodulation step, an error detection step for calculating an error syndrome for one error correction codeword in one check unit block, and detecting the presence or absence of an error, and an error in the error correction codeword in the error detection step Is detected, the first error correction step for correcting the error using the syndrome for the error correction codeword, and errors for all error correction codewords in the target check unit block An error detection end determination step for determining whether or not detection has been performed, and the first check unit in the target test unit block. If there is no error correction codeword determined to be uncorrectable in the error correction step, the remaining one bit is determined if the values of all the remaining bits except for one bit in the two-dimensional codeword are determined. A second error correction step for correcting an error for a row that has not been error-correction-encoded using the characteristic that the value of the error is also determined, and error detection and correction for all check unit blocks It is characterized by comprising an error detection / correction end determination step for determining whether or not it has been performed, and a parity bit removal step for removing a parity bit in each error correction codeword.

  Further, in the error correction method, for a predetermined number of two-dimensional codewords, a first sequence conversion step of extracting a bit existing at the same position of each codeword as one bit string and generating a two-dimensional codeword block An error-correcting codeword generation step of dividing the two-dimensional codeword block as a check unit block and outputting each bit string with the parity bit added as an error-correcting codeword; and a two-dimensional code for the parity bit Performing a modulation to form a parity bit part, generating a coding unit block obtained by combining the check unit block and the parity bit part, and performing a process reverse to the first sequence conversion step, A first sequence inverse transforming step of rearranging the coding unit blocks so as to become a two-dimensional codeword; A binarization step of binarizing luminance data obtained by recording and reproducing a plurality of two-dimensional codewords generated in the column reverse conversion step on a hologram memory recording medium to reproduce a two-dimensional codeword; A second sequence conversion step of collecting the two-dimensional codeword binarized in the encoding step for each encoding unit block and performing the same processing as the first sequence conversion step to generate the encoding unit block A two-dimensional codeword corresponding to the parity bit from the coding unit block is two-dimensionally code demodulated to generate the plurality of parity bits, and error correction of each bit string using the plurality of parity bits and two-dimensional An error correction step that alternately and repeatedly performs error correction using a coding rule of the code, and the first sequence inverse change with respect to the two-dimensional codeword block that has been subjected to error correction Second series inverse conversion step of reproducing the two-dimensional code words by performing the same processing as step and is characterized in that it consists of.

  Furthermore, in the error correction method, the error correction codeword generation step is characterized in that parity bits are generated by performing error correction encoding for each bit string in each check unit block.

  Further, in the error correction method, the error correction step detects and corrects errors for each bit string, and uses the result of error correction and the fact that the number of High bits included in the two-dimensional codeword is constant. Error detection, correction, and generation of erasure position information are performed in units of dimension codewords.

  Further, in the error correction method, the error correction step is a parity bit demodulation in which the data obtained by the second sequence conversion step is divided for each coding unit block and two-dimensional code demodulation is performed only on the parity bit part. Step and checking the bit value for each two-dimensional codeword for one test unit block, if there is a two-dimensional codeword indicating a pattern that cannot exist as a codeword pattern of the two-dimensional codeword, An erasure position information generation step of generating bits of erasure position information based on the information by setting a bit in the two-dimensional code word as an erasure position and an error correction code word in one error correction code word An error detection step for calculating a syndrome and detecting the presence or absence of an error, and an error is detected in an error correction codeword in the error detection step. A first error correction step for correcting an error for the error correction codeword using the syndrome and the erasure position information, and for all error correction codewords in the target check unit block An error detection end determination step for determining whether or not an error has been detected, and an error correction codeword determined to have no error in the error detection step, or an error correction in the first error correction step If the error correction code word is present, the value of each bit in the error correction code word is checked. If there is a bit indicating a high value, the bit in the two-dimensional code word including the bit is included. The number of high bits whose reliability is confirmed matches the number of high bits that should be included in the two-dimensional codeword, and further reliability is confirmed. A second error correction step for inverting the value of the high bit whose reliability has not been confirmed, and an error correction code determined to have no error in the error detection step When there is a word or when there is an error correction codeword whose error has been corrected in the first error correction step, the bit value is checked for each two-dimensional codeword, and the codeword pattern of the two-dimensional codeword If there is a two-dimensional codeword indicating a pattern that cannot exist as a bit, an unreliable bit in the two-dimensional codeword is determined as an erasure position, and the erasure position information is determined based on the information. Erasure position information update step to be updated, and it is determined that all error correction codewords in the target check unit block do not contain an error, or Iterative decoding step that repeats the operations from the error detection step to the erasure position information update step until it is determined that the error is not likely to be corrected or until a predetermined number of repetition decoding is reached, and all inspections An error detection / correction end determination step for determining whether or not an error has been detected and corrected for a unit block, and a parity bit removal step for removing a parity bit in each error correction codeword It is characterized by.

  According to the error correction method of the present invention, even if error correction encoding is performed after two-dimensional encoding in order to improve error correction capability in a hologram memory recording / reproducing apparatus, it is possible to improve encoding efficiency. it can.

  Embodiments of an error correction method according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a flowchart showing processing steps of an error correction method according to Embodiment 1 of the present invention.

  Hereinafter, each step will be described with reference to FIG. In the encoding step, it is assumed that a two-dimensional encoding step for modulating input 2 bits into four bits (hereinafter referred to as cells) has already been performed. Next, RS (Reed-Solomon) encoding (step 101, step 102, and step 103) is performed on the encoded cell. Cells subjected to RS encoding are arranged on a two-dimensional plane, recorded in a hologram memory recording / reproducing apparatus, and read out. Next, in the decoding step, the signal output from the hologram memory recording / reproducing apparatus is binarized, and errors are detected and corrected using parity bits (step 201, step 202, and step 203). Then, the process proceeds to the two-dimensional decoding step.

  The modulation / demodulation used here is obtained by encoding 2-bit recording data into 4 bits (cells) by the conventional two-dimensional encoding shown in FIG. 14, and the output bit “1” is a high cell (light signal). Transmitting cell), bit “0” corresponds to a Low cell (cell that blocks light), and one set of these four cells is one code word.

Hereinafter, each step will be described in detail.
Since the two-dimensional encoding is the same as that described in the prior art, description thereof is omitted.
Next, step 101 will be described. FIG. 2 is a diagram for explaining the series conversion in step 101. In step 101, series conversion is performed so that the two-dimensionally encoded data has cells arranged in the vertical (column) direction for each codeword. Various orders can be considered for arranging the cells in the column direction. Here, as shown in FIG. 2, the four bits 1001 to 1004 constituting the two-dimensional code word 1000 are arranged in order from top to bottom. The cells are arranged in a row. Similarly, the next codeword is also subjected to series conversion in the column direction, and arranged in order so as to be adjacent to the previous codeword.

  Next, step 102 will be described. FIG. 3 is a flowchart showing the processing steps in step 102. In FIG. 3, in step 121, the data obtained in step 101 is divided into blocks for each predetermined number of code words (for each number of column units in FIG. 2), and each block is arranged in step 101. RS coding is performed for each codeword in the horizontal direction (row), and a parity bit (cell) is added. In step 122, two-dimensional encoding is performed on the added parity bit (cell). Hereinafter, each step will be described in detail.

  First, step 121 will be described. FIG. 4 is a diagram for explaining the RS encoding in step 121. In step 121, in order to perform RS encoding on the data subjected to the series conversion in step 101, first, the data is divided for each predetermined number of code words. Hereinafter, the divided blocks are referred to as inspection unit blocks.

  The number of codewords constituting one inspection unit block is set to the number of codewords that can correct all errors for each block according to the frequency of error occurrence in the transmission path (hologram memory recording / reproducing apparatus). Here, taking as an example a case where an error of one event occurs every 12 codewords in the transmission line, 12 codewords are defined as one inspection unit block. Then, RS coding is performed for each row for each check unit block, and a parity bit is added. At this time, the line including the parity bit is an RS code word. However, at this time, as shown in FIG. 4, only one of the four rows (the bottom row) is not subjected to RS encoding. Thereby, compared with the case where RS encoding is performed on all four rows, the encoding efficiency is improved.

Here, it is assumed that a 1-symbol error correcting RS code on GF (2 ³ ) is used. That is, one symbol is formed for every 3 bits, and a remainder operation using a generator polynomial is performed on a polynomial expressed using these symbols, so that data of 12 bits (4 symbols) is obtained as shown in FIG. On the other hand, a parity bit (cell) of 6 bits (2 symbols) is added. Since the encoding algorithm of the RS code uses a method well known in this field, the description is omitted here.

  Next, step 122 will be described. FIG. 5 is a diagram for explaining the parity bit encoding in step 122. In step 121, 18-bit parity bits are generated for each check unit block, but these parity bits do not satisfy the constraints of the two-dimensional code. Therefore, in step 122, the 18-bit parity bits added as shown in FIG. 5B are divided every two bits, and two-dimensional encoding is performed on each of the divided two bits. Then, the two-dimensionally encoded parity bits are subjected to the same series conversion as that performed in step 101, and then added to the end of each check unit block as shown in FIG. Hereinafter, the check unit block to which the two-dimensionally encoded parity bits are added is referred to as a coding unit block.

  Next, step 103 will be described. In step 103, a series conversion operation opposite to the series conversion operation performed in step 101 is performed on the data obtained in step 122. That is, the data of the coding unit block is divided for each column, and each column is rearranged in the form of a two-dimensional plane as one two-dimensional code word.

  Next, the hologram memory recording / reproducing apparatus rearranges the data output in step 103 into a form conforming to the recording format of the hologram memory recording / reproducing apparatus, and then records the data on the hologram memory medium. FIG. 6 is a diagram for explaining recording data generation. In hologram memory recording, two-dimensional code words are arranged on a two-dimensional matrix as shown in FIG. 6 and recorded as page data. There are various methods for arranging the data. Here, it is assumed that page data is generated by arranging the data in the row direction as shown in FIG. Then, the generated page data is recorded on the hologram memory medium as an aggregate of cells having a unit area.

  The hologram memory recording / reproducing apparatus reads page data by irradiating the hologram memory medium with reference light. An image obtained by irradiating the hologram memory medium with reference light is taken using a CCD (Charge-Coupled Devices) camera or the like. The photographed image is obtained by photoelectrically converting the level of the electric signal (luminance value) according to the brightness of received light. The luminance value is represented by digital data of 10 (dark) to 100 (bright). At this time, when the resolution of the data recorded on the hologram memory medium is one pixel of the CCD element per cell, the luminance value of each pixel is set to the luminance value of one cell (bit). Alternatively, when the resolution of a plurality of pixels per cell is set, the cumulative addition value or the average value of the luminance values of the plurality of pixels is set as the luminance value of one cell (bit). Further, the hologram memory recording / reproducing apparatus sequentially outputs the luminance value information of the page data in units of codewords in the reverse order of the recording.

  Next, in the binarization in step 201, the luminance value output from the hologram memory recording apparatus is compared with a threshold value, and the bit whose luminance value is lower than the threshold value is set to the Low bit, and the luminance value is higher than the threshold value. A bit having a high value is realized as a high bit.

  Next, step 202 will be described. In step 202, series conversion is performed on the binarized data so that bits are arranged in the column direction for each two-dimensional codeword in the same manner as in step 101.

  Next, step 203 will be described. FIG. 7 is a flowchart showing the processing steps in step 203. In FIG. 7, in step 231, the data obtained in step 202 is divided for each coding unit block, and the two-dimensional code is decoded only for the parity bit part. Next, in step 232, an error syndrome is calculated for one RS codeword in one check unit block, and the presence or absence of an error is detected. In step 233, if an error is detected in the RS code word in step 232, the error is corrected for the RS code word using the syndrome.

  Next, in step 234, it is determined whether or not an error has been detected for all the RS codewords in the examination unit block currently focused on. In step 235, if there is no RS codeword determined to be error-correctable in step 233, the remaining 1 bit is obtained if the 3-bit value in the two-dimensional codeword is determined. Using the characteristic that the value of inevitably is determined, error correction is performed on a line that is not RS-coded.

  In step 236, it is determined whether or not errors have been detected and corrected for all check unit blocks. In step 237, parity bits in each RS codeword are removed.

Hereinafter, each step will be further described in detail.
First, step 231 will be described. In step 231, first, the data subjected to the series conversion in step 202 is divided for each coding unit block. That is, the configuration of one coding unit block is as shown in FIG. 5C, and includes 21 two-dimensional codewords (9 of which are two-dimensionally encoded parity bits). Become. Then, only the parity bit portion is decoded for each coding unit block. Thereby, the parity bits are restored to the original form, and the RS code word is restored for each row in each block. As a result, the configuration of each block is as shown in FIG. 5A, which is converted into a form including 12 two-dimensional codewords and 18 parity bits.

  Next, step 232 will be described. In step 232, a remainder calculation is performed on a single RS codeword in one check unit block using a generator polynomial, and an error syndrome is calculated. At this time, if the calculated syndrome value is zero, it can be considered that no error has occurred. If the syndrome is non-zero, an error has occurred in the RS codeword. If it is detected that there is no error in the RS codeword, the process proceeds to step 234, and if an error is detected, the process proceeds to step 233.

  Next, step 233 will be described. In step 233, when an error is detected in the RS code word in step 232, the error is corrected using the syndrome for the RS code word. In the first embodiment, since a 1-symbol error correcting RS code is used, errors up to 1 symbol out of 6 symbols can be corrected. If an error of 2 symbols has occurred in 6 symbols, the error cannot be corrected but can be detected, so that it is determined that correction is impossible. Since an error correction method for an RS codeword is well known in this field, a description thereof is omitted here.

  Next, step 234 will be described. In step 234, it is determined whether or not errors have been detected for all RS codewords in the target test unit block. If there are RS codewords for which the presence or absence of an error has not yet been detected, the operations of step 232 and step 233 are repeated for those RS codewords. In the first embodiment, since there are three RS code words included in one inspection unit block, the operations of Step 232 and Step 233 are repeated three times.

  Next, step 235 will be described. In step 235, it is first checked in step 232 whether an error has been detected in the RS codeword. Further, if an error is detected in the RS code word, it is confirmed whether or not the error has been corrected in step 233. If no error is detected in step 232 and if an error is detected in step 232 but the error is corrected in step 233, the error check unit block contains an RS-uncoded row. Correct the error. On the other hand, if an error is detected in the RS codeword in step 232, but the error cannot be corrected in step 233, the error in the line that is not RS-coded cannot be corrected in the block. The process proceeds to step 236 without correcting the above.

  FIG. 8 is a diagram showing a method of correcting an error for a row that has not been RS-encoded in step 235. Since the two-dimensional code word is composed of 1 high bit and 3 low bits, if the value of 3 bits out of these 4 bits is determined, the value of the remaining 1 bit is inevitably determined. Will do. Therefore, if the three RS code words in the check unit block can be correctly decoded, the value of three bits is determined for each two-dimensional code word. Can be detected and corrected.

  That is, in step 235, errors are detected and corrected in the three RS code words in the check unit block in step 232 and step 233, and there is one RS code word that is determined to be uncorrectable. If not, a 1-bit value that is not RS-encoded is estimated and determined from the three-bit values determined for each two-dimensional codeword. In this way, by using the encoding characteristics of the two-dimensional code, error correction is performed even when one of the four rows is not RS-encoded, so RS encoding is performed for all rows. Compared with the case where it carries out, the improvement of encoding efficiency can be aimed at.

  Next, step 236 will be described. In step 236, it is determined whether or not an error has been detected for all the test unit blocks. If there are test unit blocks for which the presence or absence of an error has not yet been detected, the operations from step 232 to step 235 are repeated for those test unit blocks.

  Next, step 237 will be described. In step 237, the parity bits in each RS codeword are removed.

  Next, step 204 will be described. In step 204, the data from which the parity bits have been removed is read for each column in the same manner as in step 103, and each two-dimensional code word is rearranged in a two-dimensional form. By this operation, an estimated sequence of a two-dimensionally encoded sequence is obtained.

  As described above, the first embodiment uses the characteristic of the two-dimensional code that if the value of 3 bits among the 4 bits constituting the code word is fixed, the value of the remaining 1 bit is inevitably fixed. As a result, error correction can be performed without performing RS coding on a part of the data, so that the encoding efficiency is improved in the hologram memory recording / reproducing apparatus that performs RS coding after two-dimensional coding. Can be achieved.

  In addition, in extracting the block of a codeword unit from the page data read from the hologram recording medium at the time of binarization in step 201, explanation about which position of the page data is divided into blocks is omitted. Then, a marker of a pattern that does not exist as a code word is recorded at a predetermined position of the page data, and a block break is determined based on the location. As the marker, for example, if all 4 × 4 cells are set to the High bit, the marker can be easily detected. Marker locations are set at the design time such as at the four corners of the page data.

  Further, the case where a two-dimensional code is used as the modulation code has been described. However, the modulation code is not limited to this, and any modulation code in which the number of High bits included in one code word is determined can be similarly implemented. .

  Moreover, although the case where the RS code is used as the error correction code has been described, any code other than the RS code may be used as long as the number of error symbols that can be corrected is determined, such as a BCH (Bose-Chudhuri-Hocquechem) code or an algebraic geometric code. Even when the error correction code is used, it can be similarly implemented.

  When the error correction capability is more important than the encoding efficiency, all four rows are RS-encoded and decoded using the error correction method described in the first embodiment. Then, even if any one of the four rows is determined to be uncorrectable, correct data can be obtained from the remaining three rows, enabling more efficient error correction. It becomes.

  FIG. 9 is a flowchart showing processing steps of the error correction method according to the second embodiment of the present invention.

  In FIG. 9, in the encoding step, RS encoding is performed on the two-dimensionally encoded data. The transmission path represents a path for recording / reproducing data in / from the hologram memory. In the decoding step, the signal output from the transmission path is binarized so as to be any one of the two-dimensional codewords, and errors are detected and corrected using parity bits.

  Hereinafter, each step will be described in detail. Here, the input code word is obtained by encoding 2-bit recording data into 4 bits (cells) by the conventional 2-dimensional encoding shown in FIG. 14 as in the case of the first embodiment. Assume that bit “1” corresponds to a High cell and bit “0” corresponds to a Low cell.

  First, step 301 will be described. In step 301, as in the case of the first embodiment, series conversion is performed on the two-dimensionally encoded data so that bits are arranged in the column direction for each codeword.

Next, step 302 will be described. In step 302, as in step 121 of the first embodiment, first, the data is divided for each inspection unit block. Here, the number of code words constituting one inspection unit block is determined to be 12 code words as in the first embodiment. Then, RS coding is performed for each row for each check unit block, and a parity bit is added. In this case as well, the 1-symbol error correcting RS code on GF (2 ³ ) is used as in the first embodiment. That is, as shown in FIG. 10, 6 bits (2 symbols) of parity bits are added to 12 bits (4 symbols) of data. As in the first embodiment, each row including parity bits is an RS code word.

  Next, step 303 will be described. FIG. 11 is a diagram for describing parity bit encoding in step 303. In step 302, 24 parity bits are generated for each check unit block, but these parity bits do not satisfy the constraints of the two-dimensional code. Therefore, in step 303, the 24-bit parity bits added as shown in FIG. 11B are divided every two bits, and two-dimensional encoding is performed on each of the divided two bits. The two-dimensionally encoded parity bits are added to the end of each check unit block as shown in FIG. Hereinafter, the check unit block to which the two-dimensionally encoded parity bits are added is referred to as a coding unit block as in the first embodiment.

  Next, step 304 will be described. In step 304, the series conversion operation opposite to the series conversion operation performed in step 301 is performed on the data obtained in step 303 as in the case of the first embodiment.

  Next, the data obtained in step 304 is rearranged into a form conforming to the recording format of the hologram memory in the recording / reproducing circuit in the same manner as in the first embodiment, and then recorded on the hologram memory medium.

  Next, step 401 will be described. In step 401, binarization is performed on the data reproduced in the recording / reproducing circuit. Note that the data reproduced in the recording / reproducing circuit is an electric signal level corresponding to the light and darkness of the light received by each element from the optical signal read from the hologram memory medium using a CCD (Charge-Coupled Devices) camera or the like. The brightness value is represented by digital data of 10 (dark) to 100 (bright). At this time, when the resolution of the data recorded on the hologram memory medium is one pixel of the CCD element per cell, the luminance value of each pixel is set to the luminance value of one cell (bit). Alternatively, when the resolution of a plurality of pixels per cell is set, the cumulative addition value or the average value of the luminance values of the plurality of pixels is set as the luminance value of one cell (bit). The binarization in step 401 can be performed by the same method as in step 201 of the first embodiment.

  Next, step 402 will be described. In step 402, series conversion is performed on the binarized data so that bits are arranged in the column direction for each two-dimensional codeword in the same manner as in step 301.

  Next, step 403 will be described. FIG. 12 is a flowchart showing the processing steps in step 403. In FIG. 12, in step 431, the data obtained in step 402 is divided for each coding unit block, and decoding of the two-dimensional code is performed only on the parity bit portion.

  Next, in step 432, a bit value is checked for each two-dimensional codeword for one check unit block, and a two-dimensional codeword indicating a pattern that cannot exist as a codeword pattern of the two-dimensional codeword Is present, the corresponding two-dimensional codeword is determined as the erasure position, and erasure position information is generated based on the information.

  In step 433, an error syndrome is calculated for one RS codeword in one check unit block, and the presence or absence of an error is detected. Next, in step 434, when an error is detected in the RS code word in step 433, the RS code word is corrected using the syndrome and the erasure position information. In step 435, it is determined whether or not errors have been detected for all RS codewords in the test unit block that is currently subject to error detection.

  Next, in step 436, it is confirmed whether there is an RS codeword determined to have no error in step 433 or an RS codeword in which an error is corrected in step 434. Performs error correction in units of two-dimensional codewords.

  Also, in step 437, if there is an RS codeword determined to have no error in step 433, or if there is an RS codeword in which the error is corrected in step 434, the bit value is set for each two-dimensional codeword. If there is a two-dimensional code word that indicates a pattern that cannot be present in the code word rule of the two-dimensional code word, the two-dimensional code word is determined as an erasure position, and the erasure position is determined based on the information. Update information.

  Then, in step 438, it is determined in step 433 that all the RS codewords in the current examination unit block do not include an error, or it is determined that there is no possibility that the error will be corrected any more, or a determination is made. When the number of repeated decoding is reached, the process goes to step 439. Until the above condition is satisfied, the operations from step 433 to step 437 are repeated. Next, in step 439, it is determined whether or not errors have been detected and corrected for all check unit blocks. In step 440, the parity bits in each RS codeword are removed.

Hereinafter, each step in step 403 will be described in detail.
In step 431, first, the data subjected to the series conversion in step 402 is divided for each coding unit block. That is, the configuration of one coding unit block is as shown in FIG. 11C, and includes 24 two-dimensional code words (of which 12 are two-dimensionally encoded parity bits). Become. Then, the two-dimensional code is decoded only for the parity bit portion for each coding unit block. Thereby, the parity bits are restored to the original form, and the RS code word is restored for each row in each block. As a result, the configuration of each block is as shown in FIG. 11A, which is converted into a form including 12 two-dimensional codewords and 24 parity bits.

  In step 432, erasure position information for use in erasure error correction is generated. Each two-dimensional code word included in the inspection unit block is encoded so as to be composed of one high bit and three low bits, so that the binarized two-dimensional code word is If the law is not satisfied, some kind of error has occurred. Therefore, such a two-dimensional code word is determined as the erasure position, and erasure position information is generated based on the information.

  In step 433, first, a residue calculation is performed on one RS codeword in one check unit block using a generator polynomial to calculate an error syndrome. As a result, when it is detected that there is no error in the RS codeword, the routine proceeds to step 435, and when an error is detected, the routine proceeds to step 434.

  In step 434, when an error is detected in the RS code word in step 433, the error is corrected using the syndrome calculated in step 433 and the erasure position information obtained in step 432 for the RS code word. . In the second embodiment, since a 1-symbol error correcting RS code is used, if normal error correction is performed, errors up to 1 symbol out of 6 symbols can be corrected. Further, when erasure error correction is performed, errors up to 2 symbols out of 6 symbols can be corrected. Since the erasure error correction algorithm is well known in this field, the explanation is omitted here.

  In step 435, it is determined whether or not errors have been detected for all RS codewords in the test unit block that is currently subject to error detection. If there are RS codewords for which the presence or absence of an error has not yet been detected, the operations of step 433 and step 434 are repeated for those RS codewords. In the second embodiment, since there are four RS codewords included in one inspection unit block, the operations in step 433 and step 434 are repeated four times.

  In step 436, it is first checked in step 433 whether an error has been detected in the RS codeword. Further, if an error is detected in the RS code word, it is confirmed whether or not the error has been corrected in step 434. If an error cannot be corrected in spite of detecting an error in the RS codeword, error correction cannot be performed in units of two-dimensional codewords, so that no processing is performed and the process goes to step 438. And migrate. On the other hand, when no error is detected in step 433 and when an error is detected in step 433 but the error is corrected in step 434, the result of error correction in step 434 and the characteristics of the two-dimensional code Is used to check error correction in units of two-dimensional codewords, and if there is a two-dimensional codeword in which an error exists, the error is corrected.

  For example, consider a case where the code word of FIG. 13A is recorded and reproduced as a code word as shown in FIG. In this case, an error has occurred in two bits of bits 2001 and 2002. In step 434, it is assumed that only the error of bit 2001 among these errors is corrected and converted into a pattern as shown in FIG. In this case, normally, the error of the bit 2002 remains, but since the position of the High bit is determined by correcting the bit 2001 from the Low bit to the High bit, it originally showed the High value. It can be seen that an error has occurred in bit 2002 as well. Therefore, all the errors existing in the code word 2000 can be corrected by inverting the bit 2002.

  That is, when there is an RS codeword determined to have no error in step 433, or when there is an RS codeword in which an error is corrected in step 434, first, each bit of the RS codeword excluding the parity bit is excluded. The value is checked, and if there is a bit indicating a high value among them, the value in the two-dimensional codeword including the bit is checked. Then, only when the bit indicating the High value is present in addition to the bit corresponding to the RS codeword, the value of the High bit is inverted. As a result, it is possible to correct errors that could not be corrected by only step 434.

  In step 437, the disappearance position information is updated. Since there is a very high possibility that the contents of each two-dimensional code word have been updated by error correction in step 434 and step 436, the erasure position information is updated accordingly. Specifically, when there is an RS codeword determined to have no error in step 433, or when there is an RS codeword in which an error is corrected in step 434, first, the bit value is set for each two-dimensional codeword. Investigate. When there is a two-dimensional code word that cannot be a code word pattern of a two-dimensional code word, the two-dimensional code word is determined as an erasure position. In addition, when the two-dimensional code word determined as the erasure position in step 432 is corrected in the steps up to step 436 and satisfies the rule of the two-dimensional code, the erasure position set in the two-dimensional code. Is deleted. In this way, the contents of the erasure position information are updated.

  Next, step 438 will be described. By performing the operations of step 436 and step 437, error correction and erasure position information are updated in units of two-dimensional codewords, so that more errors can be corrected by decoding the RS code again. There is. Therefore, in step 438, it is determined in step 433 that all the RS codewords in the current examination unit block do not contain an error, or the erasure position is determined in step 437 even though the erasure position remains. The operations from Step 433 to Step 437 are repeated until the information is not updated or the predetermined number of repeated decoding is reached.

  In step 439, it is determined whether or not errors have been detected and corrected for all inspection unit blocks. If there are test unit blocks for which errors are not yet detected and corrected, the operations from step 432 to step 438 are repeated for those test unit blocks.

In step 440, the parity bits in each RS codeword are removed, and the process proceeds to step 404.
In step 404, the data from which the parity bits have been removed is read for each column in the same manner as in step 304, and each two-dimensional code word is rearranged in a two-dimensional form. By this operation, an estimated sequence of a two-dimensionally encoded sequence is obtained.

  As described above, according to the second embodiment, the erasure position information can be acquired and iteratively decoded by using the characteristic that the two-dimensional code word is composed of one high bit and three low bits. Therefore, the error correction capability can be improved as compared with the conventional method. Therefore, since the same error rate characteristic can be achieved with less redundancy than the conventional method, the encoding efficiency can be improved in the hologram memory recording / reproducing apparatus that performs RS encoding after two-dimensional encoding.

  Although the case where a two-dimensional code is used as the modulation code has been described, the modulation code is not limited to this, and any modulation code in which the number of High bits included in one codeword is determined can be implemented in the same manner. .

  Also, the case where an RS code is used as an error correction code has been described, but an error correction code other than the RS code is used as long as the number of error symbols that can be corrected is determined, such as a BCH code or an algebraic geometric code. Even in the case, it can be similarly implemented.

  In the second embodiment, error correction and erasure position information update in units of two-dimensional codewords are performed in step 436 and step 437. However, it may be performed immediately after step 433 and step 434. In this case, every time RS decoding is performed, error correction and erasure position information are updated in units of two-dimensional codewords, so that the number of repeated decoding may be reduced.

  Further, the error correction method described in the first embodiment and the error correction method described in the second embodiment can be used in combination. In this case, it is possible to further improve the encoding efficiency or the error correction capability as compared with the case where only one is performed.

  The error correction method of the present invention can improve the encoding efficiency in a transmission path in which error correction encoding is performed after encoding is performed using a modulation code in which the number of High bits included in one code word is determined. Therefore, the present invention is useful for a hologram recording / reproducing apparatus or the like employing a two-dimensional code in which the number of High bits included in one code word is determined.

The flowchart which shows the processing step of the error correction method in 1st Example. The figure which shows the method of the series conversion in 1st Example The flowchart which shows the error correction encoding step of 1st Example. The figure which shows the method of RS encoding in 1st Example The figure which shows a mode that the parity bit in 1st Example is encoded in two dimensions, and a coding unit block is comprised. The figure which shows the example of the recording format in hologram recording Flowchart showing error detection / correction steps of the first embodiment The figure which shows the method of correcting an error with respect to the line which is not RS-encoded in the 1st Example The flowchart which shows the processing step of the error correction method in 2nd Example. The figure which shows the method of RS encoding in 2nd Example The figure which shows a mode that the parity bit in a 2nd Example is comprised two-dimensionally and the encoding position block is comprised. Flowchart showing error detection / correction steps of the second embodiment The figure which shows the error correction method of the two-dimensional codeword unit in a 2nd Example The figure which shows the example of two-dimensional encoding Block diagram of recording / reproducing channel in conventional example The flowchart which shows the procedure of the encoding step and decoding step in a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st modulation circuit 2 RS encoding circuit 3 2nd modulation circuit 4 Recording / reproducing circuit 5 Binary circuit 6 2nd demodulation circuit 7 RS decoding circuit 8 1st demodulation circuit 101 1st series conversion step 102 Error correction coding step 103 First sequence inverse conversion step 121 Error correction codeword generation step 122 Parity bit modulation step 201 Binarization step 202 Second sequence conversion step 203 Error correction step 204 Second sequence inverse conversion step 231 Parity bit demodulation step 232 Error detection step 233 First error correction step 234 Error detection end determination step 235 Second error correction step 236 Error detection / correction end determination step 237 Parity bit removal step 301 First sequence conversion step 302 Error correction codeword generation Step 303 Parity bit modulation step 304 First sequence inverse conversion step 401 Binarization step 402 Second sequence conversion step 403 Error correction step 404 Second sequence inverse conversion step 431 Parity bit demodulation step 432 Erasure position information generation step 433 Error detection step 434 First error correction step 435 Error detection end determination step 436 Second error correction step 437 Erasure position information update step 438 Iterative decoding step 439 Error detection / correction end determination step 440 Parity bit removal step 501 Error correction code Conversion step 502 second modulation step 601 binarization step 602 second demodulation step 603 error detection / correction step 1000 two-dimensional codeword 1001 to 1004 two-dimensional code Bits constituting the bit 1101 High cell 1102 to 1104 Low cell 2000 2D codeword 2001-2004 2D code words constituting the

Claims (8)

A first sequence conversion step for extracting a bit existing in the same position of each code word as one bit string for a predetermined number of two-dimensional code words, and generating a two-dimensional code word block;
Error correction coding is performed for each remaining bit string except one bit string for the two-dimensional codeword block to generate a plurality of parity bits, and two-dimensional code modulation is performed on the plurality of parity bits. An error correction coding step of generating a coding unit block by placing the generated two-dimensional codeword at the end of the two-dimensional codeword block;
A first sequence inverse transform step of performing a process reverse to the first sequence transform step to rearrange the coding unit blocks to be a two-dimensional codeword;
A binarization step of binarizing luminance data obtained by recording and reproducing a plurality of two-dimensional codewords generated in the first series inverse transform step on a hologram memory recording medium to reproduce a two-dimensional codeword; ,
The two-dimensional codeword binarized in the binarization step is collected for each coding unit block, and the same processing as in the first sequence conversion step is performed to generate the coding unit block. A series conversion step;
Two-dimensional codeword corresponding to the parity bit is two-dimensionally code demodulated from the coding unit block to generate the plurality of parity bits, and the error correction of the two-dimensional codeword block is performed using the plurality of parity bits Error correction is performed by performing error correction on a coded bit string and performing error correction using a two-dimensional coding rule on a bit string that has not been subjected to the error correction coding in the error correction coding step based on the result. Steps,
A second sequence inverse transform step for reproducing the two-dimensional codeword by performing the same processing as the first sequence inverse transform step on the two-dimensional codeword block subjected to error correction;
An error correction method comprising: The error correction encoding step comprises:
The data obtained in the first sequence conversion step is divided into check unit blocks for each predetermined number of two-dimensional code words, and in each check unit block, the lines for the remaining rows excluding any one bit string are respectively stored. An error correction codeword generation step of generating a parity bit by performing error correction coding every time, and outputting the parity bit added to each row as an error correction codeword;
A parity bit modulation step of performing a two-dimensional code modulation on the parity bit to form a parity bit portion, and generating a coding unit block obtained by combining the check unit block and the parity bit portion;
The error correction method according to claim 1, comprising: The error correction step includes
An error is detected and corrected for each error correction codeword for the data obtained by the second sequence conversion step, and the error correction result and all remaining bits except for one bit in the two-dimensional codeword If the value of is determined, error correction is performed on a bit string that has not been error correction encoded using the characteristic that the value of the remaining 1 bit is also determined.
The error correction method according to claim 1. The error correction step comprises:
A parity bit demodulating step in which the data obtained by the second sequence conversion step is divided for each coding unit block and two-dimensional code demodulation is performed only on the parity bit portion;
An error detection step of calculating an error syndrome for one error correction codeword in one check unit block and detecting the presence or absence of an error;
If an error is detected in the error correction codeword in the error detection step, a first error correction step of correcting the error using the syndrome for the error correction codeword;
An error detection end determination step for determining whether or not errors have been detected for all error correction codewords in the target check unit block;
If there are no error correction codewords determined to be uncorrectable in the first error correction step in the target check unit block, all remaining except one bit in the two-dimensional codeword A second error correction step for correcting an error for a row that has not been error-correction-encoded using the property that if the value of one bit is determined, the value of the remaining one bit is also determined;
An error detection / correction end determination step for determining whether or not errors have been detected and corrected for all inspection unit blocks;
A parity bit removal step of removing the parity bits in each error correction codeword;
The error correction method according to claim 3, comprising: A first sequence conversion step for extracting a bit existing in the same position of each code word as one bit string for a predetermined number of two-dimensional code words, and generating a two-dimensional code word block;
An error correction codeword generation step of dividing the two-dimensional codeword block as a check unit block and outputting the bit string added with the parity bit as an error correction codeword;
A parity bit modulation step of performing a two-dimensional code modulation on the parity bit to form a parity bit portion, and generating a coding unit block obtained by combining the check unit block and the parity bit portion;
A first sequence inverse conversion step of performing an inverse process to the first sequence conversion step and rearranging the coding unit block to be a two-dimensional codeword;
A binarization step of binarizing luminance data obtained by recording and reproducing a plurality of two-dimensional codewords generated in the first series inverse transform step on a hologram memory recording medium to reproduce a two-dimensional codeword; ,
The two-dimensional codeword binarized in the binarization step is collected for each coding unit block, and the same processing as in the first sequence conversion step is performed to generate the coding unit block. A series conversion step;
Two-dimensional codewords corresponding to the parity bits from the coding unit block are two-dimensionally code demodulated to generate the plurality of parity bits, and error correction of each bit string using the plurality of parity bits and two-dimensional code An error correction step in which error correction using coding rules is alternately repeated;
A second sequence inverse transform step for reproducing the two-dimensional codeword by performing the same processing as the first sequence inverse transform step on the two-dimensional codeword block subjected to error correction;
An error correction method comprising: The error correction codeword generation step includes:
In each check unit block, parity correction is generated by performing error correction coding for each bit string,
6. The error correction method according to claim 5, wherein: The error correction step includes
Error detection and correction is performed for each bit string, and error detection, correction, and erasure are performed in units of two-dimensional codewords using the result of error correction and the fact that the number of High bits included in the two-dimensional codeword is constant. Generate location information,
6. The error correction method according to claim 5, wherein: The error correction step comprises:
A parity bit demodulation step of dividing the data obtained by the second sequence conversion step for each coding unit block and performing two-dimensional code demodulation only on the parity bit portion;
The bit value is examined for each two-dimensional code word for one check unit block, and if there is a two-dimensional code word indicating a pattern that cannot exist as a code word pattern of the two-dimensional code word, the two-dimensional code word An erasure position information generating step for setting a bit in a codeword as an erasure position and generating erasure position information based on the information
An error detection step of calculating an error syndrome for one error correction codeword in one check unit block and detecting the presence or absence of an error;
When an error is detected in the error correction codeword in the error detection step, a first error correction step for correcting the error using the syndrome and the erasure position information for the error correction codeword;
An error detection end determination step for determining whether or not errors have been detected for all error correction codewords in the target check unit block;
When there is an error correction codeword determined to have no error in the error detection step, or when there is an error correction codeword in which an error is corrected in the first error correction step, The value of each bit is checked, and if there is a bit indicating the High value, the value of the bit in the two-dimensional codeword including the bit is checked, and the number of High bits whose reliability is confirmed is 2 If the number of High bits that should be included in the dimensional codeword matches the number of High bits that are not confirmed, and the High bits exist, the value of the High bits whose reliability is not confirmed is inverted. A second error correction step of causing
If there is an error correction codeword determined to have no error in the error detection step, or if there is an error correction codeword in which an error has been corrected in the first error correction step, a bit for each two-dimensional codeword If there is a two-dimensional code word indicating a pattern that cannot exist as the code word pattern of the two-dimensional code word, the bits in the two-dimensional code word whose reliability has not been confirmed are lost. Erasure position information update step for determining the position and updating the erasure position information based on the information;
It is determined that all error correction codewords in the target check unit block do not contain an error, it is determined that there is no possibility that the error will be corrected any more, or the predetermined number of repeated decoding An iterative decoding step that repeatedly performs operations from the error detection step to the erasure position information update step until reaching
An error detection / correction end determination step for determining whether or not errors have been detected and corrected for all inspection unit blocks;
A parity bit removal step of removing the parity bits in each error correction codeword;
The error correction method according to claim 7, comprising:

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