JP2008082740A - Pattern flaw inspection method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a pattern flaw inspection method of a semiconductor device capable of efficiently performing review inspection of high precision near to all-points inspection. <P>SOLUTION: An operator can accurately perform review inspection with respect to the place detected by a flaw inspection machine 1 by referring to the image data of a pattern having the flaw produced on the basis of a coordinates file excepting a duplicate pattern. The reference of the pattern is performed by producing a binary pattern and navigating the review place. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to defect inspection in a pre-manufacturing process of a semiconductor device, and more particularly to a method for pattern defect inspection.

  In manufacturing a semiconductor device, it is necessary to form various patterns on a semiconductor wafer. Pattern dimensions and shapes of semiconductor devices vary depending on photolithography conditions and processing conditions. When the shape of the pattern formed on the substrate is not within a predetermined tolerance, a pattern defect occurs. If it is excessive, pattern defects such as pattern opening and pattern shorting occur. In a semiconductor device, there are many places where patterns are repeated in units of circuits, and pattern defects are frequently generated on the same pattern. Therefore, the number of pattern defects detected from the defect inspection machine is an enormous number of thousands to tens of thousands, and the time required for pattern defect inspection is long.

  In general, design pattern defect inspection methods are roughly classified into a light scattering method and a pattern comparison method using a bright field image. In the light scattering method, the entire surface of the wafer is irradiated while scanning with a laser beam, the scattered light is detected by a photomultiplier tube (PMT) detector, and the scattered light images of adjacent dies or cell arrays are compared to detect foreign matter. And detecting pattern defects. Since this method uses scattered light, it has an excellent ability to detect foreign substances such as particles, and has an advantage that a high throughput can be realized. In the pattern comparison method, light is illuminated on a wafer, a pattern image is formed on a detector by an optical system, and an image signal is taken into an image computer. The image signals of the same pattern are compared to remove the influence of the ground pattern, and the defect is detected. As a method for comparing images, in the case of periodic patterns such as memory cells, adjacent cells are compared (Cell to Cell comparison method) to extract defects. On the other hand, a random pattern such as a logic device performs defect detection by comparing images at the same position of adjacent dies (Die to Die comparison method). Although the detection sensitivity is superior to that of the light scattering method, since the pixel size is small, it takes time to perform image capturing and image comparison processing, and the throughput is extremely low compared to the light scattering method. However, since the defect detection rate is superior to the light scattering method, a pattern comparison type inspection apparatus is used in the current wafer production line (see, for example, Patent Document 1).

  Generally, in pattern defect inspection of a semiconductor device, first, in order to detect a defective portion, each inspection area of a wafer on which a semiconductor device is mounted is irradiated with light (UV, visible light, infrared light, etc.) that is different from an adjacent pattern. This is detected by detecting the amount of reflected light and irregular reflection. This inspection is performed by a defect inspection machine. However, at this time, particles having a very small particle diameter, surface scratches, color unevenness, and the like are detected simultaneously with the pattern defect.

  Therefore, in order to distinguish a detected defect from a pattern defect and other defects, for example, a review inspection is performed with a scanning electron microscope (SEM) using defect coordinate information output from a defect inspection machine. Yes. At present, this review inspection is performed by an operator.

Here, an inspection method showing the pattern defect inspection method for the semiconductor device according to the prior art shown in FIG. 2 will be described with reference to a flowchart.

First, the wafer is inspected with a defect inspection machine (step 21). Next, an inspection result is acquired from the defect inspection machine (step 22). Among the defects, the same pattern is duplicated, and the number of detections is enormous. In step 23, a defect coordinate file is created based on the inspection result. Again, there are many overlapping patterns. Next, the coordinate data contained in the created coordinate file is transmitted to the SEM review inspection process for defect analysis (step 24). In the SEM review inspection in step 25, the inspection result is extracted at random and a review inspection is performed. Then, as a step 26, the inspection result of the review inspection is output.

As described above, since SEM review inspection is currently performed by an operator, review inspection of several thousand to several tens of thousands of orders is practically impossible. Actually, several hundred points are randomly extracted and SEM review is performed. Has been implemented. Even if inspection data is sent to a defect inspection machine host computer for analysis, there is a limit to the number of points that can be reviewed due to the limited data capacity.

Thus, in the conventional extraction method, only a few percent is inspected in the SEM review, and the remaining 90 percent or more is overlooked. There is a possibility that a serious defect is included in this oversight, and there has been a problem that sufficient detection accuracy cannot be obtained by the conventional pattern defect inspection.
JP 2000-47369 A

  An object of the present invention is to provide a pattern defect inspection method for a semiconductor device that can perform an efficient and highly accurate review inspection close to an all-point inspection.

  According to one aspect of the present invention, a step of inputting defect coordinate information from a defect inspection machine for a semiconductor wafer, a step of generating a coordinate file from the defect coordinate information, and the generated coordinate file are referred to. Extracting a representative pattern from a database of design data; generating a coordinate file from which pattern duplication is deleted by pattern matching; and drawing a reference pattern by a coordinate file from which duplication of pattern is deleted; There is provided a method for inspecting a pattern defect of a semiconductor device, comprising: a step of inspecting a representative pattern with an image by a scanning electron microscope using a coordinate file from which the duplication of the pattern is deleted with reference to the reference pattern. .

  According to another aspect of the present invention, a step of inputting defect coordinate information from a semiconductor wafer defect inspection machine, a step of generating a coordinate file from the defect coordinate information, and the generated coordinate file Referring to the above, a step of extracting a representative pattern from the design data database, and a step of generating coordinate files from which pattern duplication is deleted by deleting coordinate information of the same shape pattern as the pattern classification by pattern matching And drawing a reference pattern by a coordinate file from which the pattern duplication has been deleted, and inspecting a representative pattern by a scanning electron microscope image by referring to the reference pattern and from the coordinate file from which the pattern duplication has been deleted A pattern defect inspection method for a semiconductor device is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the pattern defect inspection method of the semiconductor device which can perform the highly accurate review test | inspection close | similar to all-points inspection which is efficient is provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, while attaching | subjecting the same code | symbol about the same location, the overlapping description is abbreviate | omitted.

FIG. 1 is an inspection flowchart showing a pattern defect inspection method for a semiconductor device according to this embodiment. First, a semiconductor wafer is inspected for defects by a defect inspection machine (step 11). From the defect inspection machine, for example, information such as defect coordinates, defect size, semiconductor chip index, etc. is output as a text file. Here, the index of the semiconductor chip is coordinate information for identifying a defective semiconductor chip in the semiconductor wafer. Among the defects, the same pattern is duplicated, and the number of detections is enormous.

  In addition, if a defect inspection machine can obtain the above-mentioned information, a well-known thing can be utilized without selecting a special model. Further, in the inspection sensitivity adjustment stage, adjustment is performed so as to eliminate as much as possible the pseudo defects caused by color unevenness, grains (particles) and the like. However, since it is difficult to completely remove the pseudo defect only by adjusting the inspection sensitivity, the operator discriminates between the actual defect and the pseudo defect in the review with the SEM (electron microscope) which is the final inspection.

  Next, when a defect is detected by the defect inspection machine, a defect coordinate file A is created based on the text format information described above (step 12).

  Next, the created coordinate file A is collated with a design file in which design data of each semiconductor device is filed, and a circuit pattern at a location where a defect is generated is extracted from the design data and drawn ( Step 13). That is, since the defect position coordinates are described in the defect coordinate file output from the defect inspection machine, the design data and the actual pattern on the wafer are not directly compared. Then, the circuit pattern of the portion where the defect is generated is cut out as an image. As the design file, for example, a GDS file which is a VLSI automatic design data system manufactured by Karma is suitable.

  When extracting the pattern, the size of the image cut out from the design data needs to be changed depending on the wiring size (product generation). For example, it is preferable to cut out a 10 μm square image from design data with the coordinates of the inspection result as the center.

  After the circuit pattern information is cut out from the design data with a predetermined size by the above operation, the circuit pattern information is converted into image data by a software application that is developed into a bitmap format, for example.

These image data are output as files to a hard disk device, for example.

  Next, as step 14, pattern matching processing is performed on the pattern drawn as described above by the pattern matching tool, and the coordinates of the same pattern are deleted leaving one representative point. For the pattern matching process, well-known tools and methods can be used. For example, as a device for high-speed processing to classify a large number of defects, small area matching and all defects are matched by a tournament method. Is preferred.

  Here, the coordinates of the same pattern are deleted except for one representative point for the following reason. That is, a major factor that causes the number of defects to be enormous is that similar defects have occurred in repeated portions of the circuit pattern. Therefore, by narrowing down such repeated patterns to representative points, it is possible to save work for reviewing similar defects over and over, and to expect to review different types of defects uniformly.

  By this method, it is possible to achieve the same effect as if all the detected defect points are reviewed.

  In this way, a defect coordinate file B without pattern duplication is created (step 15).

  Next, the information of the defect coordinate file B excluding the duplicate pattern is collated with the contents of the design file filed with the design data of the individual semiconductor devices described above, and a detection pattern is created for reference (step 16). ).

  As step 17, by referring to the image data of the pattern in which the defect is generated, the operator can accurately perform the review inspection on the portion detected by the defect inspection machine. The pattern is referred to by, for example, generating a binary pattern as described above and navigating the review location. By referring to such a pattern, the detection defect can be definitely reviewed. The inspection result is output to an output device (not shown) such as a printer (step 18).

  In this way, after the pattern classification process, the entire inspection area of the semiconductor wafer is subjected to a review inspection, whereby an inspection covering all the results of the defect inspection can be performed.

  According to the present embodiment, it is possible to perform a review inspection that is efficient and close to an all-point inspection. The pattern classification is expected not only to increase the efficiency and accuracy of inspection, but also to obtain information on defect tendency (pattern durability, etc.) as the inspection parameter increases. By feeding this information back to the design, it can be used for more appropriate pattern design.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

It is an inspection flowchart which shows the pattern defect inspection method of the semiconductor device which concerns on embodiment of this invention. It is an inspection flowchart which shows the pattern defect inspection method of the semiconductor device by a prior art.

Claims (6)

A process of inputting defect coordinate information from a semiconductor wafer defect inspection machine;
Generating a coordinate file from the defect coordinate information;
A step of extracting a representative pattern from a database of design data with reference to the generated coordinate file;
A step of generating a coordinate file by deleting pattern duplication by pattern matching;
Drawing a reference pattern by a coordinate file from which duplication of the pattern is deleted;
Referring to the reference pattern, inspecting the representative pattern with an image by a scanning electron microscope by a coordinate file from which duplication of the pattern is deleted; and
A pattern defect inspection method for a semiconductor device, comprising: A process of inputting defect coordinate information from a semiconductor wafer defect inspection machine;
Generating a coordinate file from the defect coordinate information;
A step of extracting a representative pattern from a database of design data with reference to the generated coordinate file;
By performing pattern matching, deleting the coordinate information of the same shape pattern as the pattern classification, and generating a coordinate file from which the duplication of the pattern is deleted,
Drawing a reference pattern by a coordinate file from which duplication of the pattern is deleted;
Referring to the reference pattern, inspecting the representative pattern with an image by a scanning electron microscope by a coordinate file from which duplication of the pattern is deleted; and
A pattern defect inspection method for a semiconductor device, comprising:   3. The step of extracting a representative pattern from a design data database with reference to the generated coordinate file further outputs image data in which the representative pattern is drawn. A pattern defect inspection method for a semiconductor device as described.   The coordinate information of the defect includes, in addition to the position information, coordinate information for specifying a defect size and / or a defective semiconductor chip in the semiconductor wafer. Pattern inspection method for semiconductor devices.   4. The pattern defect inspection method for a semiconductor device according to claim 1, wherein the pattern matching is performed by a small area matching and all defects by a tournament method. 5.   4. The pattern defect inspection method for a semiconductor device according to claim 3, wherein the image data is created in a bitmap format.

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