JP2008078839A - Decoder and decoding method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a turbo decoding method by which a correction function of an ACSO (Add-Compare-Select-Offset) operation often used for turbo Log-MAP decoding is easily attained. <P>SOLUTION: A subtractor 11 performs subtraction (x<SB>1</SB>-x<SB>2</SB>) to input x<SB>1</SB>and input x<SB>2</SB>and selects either the input x<SB>1</SB>or the input x<SB>2</SB>for output of a multiplexing circuit 12 according to a result of the subtraction. On the other hand, the subtraction result of the subtractor 11 passes through an absolute value operation circuit 13 to enter a correction processing part via a selection circuit 14. The correction processing part is comprised of units of a plurality of multipliers 15-1 to 15-n and adders 16-1 to 16-n (a<SB>1</SB>and b<SB>1</SB>, a<SB>2</SB>and b<SB>2</SB>, ...), its result is output via a multiplexing circuit 17 and addition between output of a multiplexing circuit 12 and output of the multiplexing circuit 17 is performed by an adder 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a decoder and a decoding method thereof, and more particularly to a method for realizing optimization of decoding operation in a turbo decoder.

  In recent years, C.I. Berrou et al. Presents a so-called turbo code as an error correction code close to the Shannon limit, and is a high-performance, high-reliability code used in a wide range of fields including mobile communication, information recording systems, digital broadcasting, etc. Research and development is underway.

  Here, first, operations of a general turbo encoder and turbo decoder will be described. FIG. 4 is a block diagram showing the configuration of a known turbo encoder, and FIG. 5 is a block diagram showing the configuration of a known turbo decoder. FIG. 4 shows a turbo encoder with a coding rate = 1/3, and includes element encoders 31 and 33 and an interleaver 32.

  An encoded bit sequence (Information Bit to be encoded) 101 is branched and transmitted as a systematic bit sequence 102 and input to the element encoder 31 and the interleaver 32.

  The element encoder 31 encodes the encoded bit sequence 101 using an error correction code, and outputs a redundant bit sequence (Parity Bit) 103. The interleaver 32 generally writes the encoded bit sequence 101 once in a memory (not shown) and reads it out in a different order, thereby sending the data sequence to the element encoder 33 in a mixed order.

  The element encoder 33 encodes the interleaved encoded bit sequence with the element code, and transmits the redundant bit sequence 104. For the element encoders 31 and 33, a recursive systematic convolutional encoder (RSC) is usually used.

  The turbo decoder shown in FIG. 5 includes element decoders (Decoders) 41 and 43, an interleaver 42, a deinterleaver (De-interleaver) 44, and a hard decision unit 45. The element decoder 41 includes a systematic information sequence (Systematic Information) 201 corresponding to the systematic bit sequence 102 in FIG. 4, a redundant information sequence (Parity Information) D02 corresponding to the redundant bit sequence 103 in FIG. 4, and external information (Extrinsic). Information) 209 is input, and external information 203 is output. The output external information 203 is used for the next element decoder 43.

  Furthermore, the external information 203 and the organization information sequence 201 obtained by the element decoder 41 are transmitted via the interleaver 42 (external information 204 and organization information sequence 205) to the redundant information sequence (corresponding to the redundant bit sequence 104 in FIG. Together with (Parity Information) 206, it is input to the element decoder 43. Soft output information (Soft Output Information) 207 and external information 208 obtained by the element decoder 43 are sent to the deinterleaver 44.

  The deinterleaver 44 outputs the data in the reverse order of the data replacement order by the interleaver 42. That is, the interleaved soft output information 207 and the external information 208 are returned to the order before the interleaving, and are output as the soft output information 210 and the external information 209. Further, the hard decision unit 45 makes a hard decision on the soft output information 210 and outputs a final decoding result. The external information 209 is fed back to the element decoder 41 for the next decoding process.

  As described above, in the turbo decoder shown in FIG. 5, the decoding process is repeatedly performed while updating the external information 209 and 204 of the two element decoders, and after a plurality of loops, the soft output information 210 is a hard decision. Is done.

  As a soft output decoding algorithm applied to an element decoder of turbo decoding, a method using Log-MAP (Log Maximum A Posteriori Probability) is said to be the best at present. Since the device scale and the processing amount are remarkably increased, Max-Log that simplifies the processing by determining whether the transmitted data is '1' or '0' based on the maximum likelihood value at the time of mounting. -A method using MAP (Max Logical Maximum A Postoriori) is generally widely used. However, the decoding performance of the Max-Log-MAP method is deteriorated as compared with the Log-MAP method.

  The Log-MAP algorithm is a maximum likelihood decoding algorithm using a trellis diagram (see, for example, Patent Document 1). FIG. 6A shows an example of the configuration of a certain element encoder (the number of registers: 3). As shown in FIG. 6B, the trellis diagram represents a relationship between an output value when a certain value is input to the element encoder and a register state. In FIG. 6A, the element encoder includes adders 51 to 54 and registers (D) 55 to 57.

The MAP algorithm is roughly divided into
(A) Forward processing: calculating the probability (forward path metric) of reaching each state at each time point from the beginning of the trellis diagram (b) Backward processing: reaching each state at each time point from the end of the trellis diagram Calculating the probability (backward path metric) (c) soft output generation processing and external value calculation: using the processing results of (a) and (b) above, calculate the soft output value of the tissue bit at each time point; This soft output value is used to form three types of processing for calculating an external value.

  In the trellis diagram, the forward path metric and the backward path metric calculated by the forward process and the backward process at the time point t and the state s are expressed as Alpha (t, s) and Beta (t, s), respectively. Also, the probability of transition from the state s to the state s ′ at the time t is expressed as Gamma (t, s, s ′) (Gamma is called a branch metric). Gamma (t, s, s') is a probability obtained from a received value (organization information series, redundant information series, external information).

・・・（１）

・・・（２）
という式で表される。 The most basic part of the decoding operation is composed of an ACSO (Add-Compare-Select-Offset) unit,

... (1)

... (2)
It is expressed by the formula.

は、実際、ＬＵＴ（Ｌｏｏｋｕｐ Ｔａｂｌｅ）で実装し、図７に示すように、ＬＵＴは基本的にメモリの構造となる。ＬＵＴを利用しない場合、Ｍａｘ＊＝Ｍａｘとなるため、Ｌｏｇ−ＭＡＰアルゴリズムもＭａｘ−Ｌｏｇ−ＭＡＰとなる。また、ＭＭＡＸ＊はＭＡＸ＊の拡張であり、入力が三つ以上の場合、複数のＭＡＸ＊組み合わせ回路となる。 here,

Is actually implemented by a LUT (Lookup Table), and as shown in FIG. 7, the LUT basically has a memory structure. When LUT is not used, since Max * = Max, the Log-MAP algorithm is also Max-Log-MAP. MMAX * is an extension of MAX *, and when there are three or more inputs, a plurality of MAX * combination circuits are formed.

FIG. 8 shows the configuration of an ACSO circuit used by the conventional Log-MAP decoding. For the two inputs of ACSO, an appropriate value in the LUT is selected based on the difference value, and addition with the maximum value of the two inputs is performed. In FIG. 8, a subtracter (x ₁ −x ₂ ) 61, a multiplexer (MUX) 62, an LUT 63, and an adder 64 are included.

Next, an actual example at the time of decoding will be described. Forward processing, backward processing, soft output generation processing, and external value calculation are executed as follows.
(A) Forward processing
Alpha (t, s)
= Max * {Alpha (t-1, s')
+ Gamma (t, s ′, s)}
It is expressed by the formula. Here, the definition of the Max * function refers to equations (1) and (2). Max * processing means taking for all states s ′.

  As shown in FIG. 9A, Alpha (t, S3) with respect to State (S3) at time t is calculated as follows. The branch metrics Gamma (t, S1, S3) and Gamma (t, S2, S3) are added to the path metrics Alpha (t-1, S1) and Alpha (t-1, S2) of the two previous stages. Compare the added values. The corresponding value stored in the LUT is read according to the difference value, and addition is performed with the larger calculated value to obtain the Alpha value of Alpha (t, S3) (referred to as Alpha ACSO operation). This process is performed on all the states of all time transitions t, and the Alpha values of all the states are held.

(B) Backward processing
Beta (t, s)
= Max * {Beta (t + 1, s')
+ Gamma (t + 1, s, s ′)}
It is expressed by the formula.

  As shown in FIG. 9B, Beta (t, S4) for State (S4) at time t is calculated as follows. The branch metrics Gamma (t + 1, S4, S5) and Gamma (t + 1, S4, S6) are added to the path metrics Beta (t + 1, S5) and Beta (t + 1, S6) of the two subsequent stages State, and the added value Compare The corresponding value stored in the LUT is read according to the difference value, and addition is performed with the larger calculated value to obtain Beta (t, S4) (referred to as Beta ACSO operation). In this state, Beta calculation processing is performed for all States of all time transition t from the opposite direction to Alpha (from the trellis final State side).

(C) Soft output generation processing and external value calculation The value of Alpha (t-1, s ') that has already been calculated is added to Beta (t, s) and Gamma (t, s', s), All path metric values at time t are obtained. At this time, the MMAX * function of the above equation (2) is used. Then, the difference between the “maximum path metric of the path whose decoding result is 0” and the “maximum path metric of the path whose decoding result is 1” is the soft output value at time t.

  In the Log-MAP algorithm, the channel value (value obtained from the received value) and the prior value (external information given from the preceding decoder) are subtracted from the soft output value (post value) obtained in the above processing. The value is external information.

JP 2002-215608 A

  As described above, in the Log-MAP algorithm, Alpha and Beta operations are performed on all data to be decoded at once. The LUT used for the ACSO calculation has a memory configuration, and the more correction values are stored, the more accurate calculation results can be obtained. However, the use of a huge memory increases the circuit scale. A method of mounting a correction function that can be realized with a simple circuit while maintaining the accuracy of ACS calculation at the time of decoding is a problem.

  Accordingly, an object of the present invention is to solve the above-described problems and provide a decoder and a decoding method thereof that can easily realize a correction function of ACSO calculation that is often used in turbo Log-MAP decoding.

A decoder according to the present invention is a decoder that performs a decoding operation in an ACSO (Add-Compare-Select-Offset) unit,
A correction processing circuit is provided that corrects the output of the ACSO unit using an approximate branching linear function.

The decoding method according to the present invention is a decoding method used in a decoder that performs decoding operation in an ACSO (Add-Compare-Select-Offset) unit,
The decoder corrects the output of the ACSO unit using an approximate staged linear function.

  That is, the decoding method of the present invention relates to a method for optimizing a decoding operation in a turbo decoder, and is an ACSO (Add Logarithmic A posteriori probability decoding) ACSO (Additional Logarithmic Probabilistic Decoding Method) decoding device. -Compare-Select-Offset) operation is implemented by an approximate stepwise linear function.

  In this case, the approximate stepwise linear function is implemented by stepwise multiplication and addition, and when an appropriate gradient is selected in the approximate stepwise linear function, the multiplication is implemented by shift operation and addition. Further, in the approximate stepwise linear function, when a certain threshold is exceeded, a constant (horizontal line) is obtained. When an appropriate gradient is determined, the approximate stepwise linear function is determined, and the application range of the stepwise function is determined at the intersection of each straight line.

  As described above, in the decoding method of the present invention, MAX-LOG-MAP (MAX Ideal-Maximum A Postoriori) is used as the basis for MAX-LOG-MAP (MAX Ideal) by optimizing the stepwise linear error compensation function. Compensation for systematic errors due to the difference in decoding operation with). That is, in the turbo decoding method of the present invention, performance close to LOG-MAP can be obtained with a simple circuit addition.

  Thus, in the decoding method of the present invention, it is possible to easily realize the correction function of the ACSO calculation that is often used for turbo Log-MAP decoding by using the approximate stepwise linear function. In such a case, the greater the number of stage stages, the higher the correction accuracy. However, since the circuit implementation becomes somewhat complicated, the trade-off between the number of stage stages and the correction accuracy must be considered in practice.

  The present invention has the above-described configuration and operation, so that it is possible to easily realize the correction function of the ACSO calculation that is often used for turbo log-MAP decoding.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an ACSO (Add-Compare-Select-Offset) circuit according to an embodiment of the present invention. FIG. 1 shows a correction arithmetic circuit of an ACSO unit often used for turbo decoding, which is provided with an optimal approximate staged linear correction function, which is simple and small-scale while maintaining the accuracy of ACSO calculation at the time of decoding. It is implemented by the circuit (addition, multiplication or shift register).

An ACSO circuit according to an embodiment of the present invention includes a subtracter (x ₁ −x ₂ ) 11, multiple circuits (Multiplexers) 12 and 17, and an absolute value calculation [ABS (function for calculating an absolute value of an integer)] circuit. 13, a selection circuit (SEL: Selector) 14, multipliers 15-1 to 15-n, and adders 16-1 to 16-n and 18.

Subtractor 11 performs the subtraction (x ₁ -x ₂₎ with respect to an input x ₁ and the input x _2, resulting by selecting whether the input x ₁ whether the input x ₂ output of the multiplex circuit 12. On the other hand, the subtraction result of the subtractor 11 passes through the absolute value calculation circuit 13 and enters the correction processing portion via the selection circuit 14.

The correction processing section plurality of multipliers 151 to 15-n and the adder 16-1~16-n (a ₁ and b _1, a ₂ and b _2, · · ·) are composed of units of, The result is output via the multiplexing circuit 17 and the adder 18 adds the output of the multiplexing circuit 12 and the output of the multiplexing circuit 17.

になる場合（Ｐ_m の値は０あるいは１、ｍは整数）、乗算は右シフト演算及び加算となる。この変形処理によって、補正部分の回路は更に小さくなる。図１に示す本発明の一実施例によるＡＣＳＯ回路の変形例を図２に示す。この図２に示す変形例では、ａ₁ ＝−１／２，ａ₂ ＝−３／１６＝−（１／８＋１／１６）である。 In the above correction processing part, the multiplication coefficient is

(P _m is 0 or 1, m is an integer), multiplication is a right shift operation and addition. By this deformation process, the circuit of the correction portion is further reduced. FIG. 2 shows a modification of the ACSO circuit according to the embodiment of the present invention shown in FIG. In the modification shown in FIG. 2, a ₁ = −1 / 2 and a ₂ = −3 / 16 = − (1/8 + 1/16).

  In FIG. 2, in the modification of the ACSO circuit, the correction processing part is composed of units of shift registers (SFT) 21 to 25, subtractors 26 and 28, and an adder 27.

In this ACSO circuit, the subtracter 11 performs subtraction (x ₁ -x ₂ ) on the input x ₁ and the input x _2, and the output of the multiplexing circuit 12 is input x ₁ or input x ₂ depending on the result. Select. On the other hand, the subtraction result of the subtractor 11 passes through the absolute value calculation circuit 13 and enters the correction processing portion via the selection circuit 14. The threshold setting of the selection circuit 14 depends on the value of a _i . The definition of the optimum threshold will be described later.

For a ₁ = −1 / 2 and a ₂ = −3 / 16, each multiplication is a right shift operation (in the case of 1/2, a single right shift by the shift register 21) or a right shift operation and addition (3 In the case of / 16, the result of the right shift three times by the shift registers 22 to 24 and the result of the right shift four times by the shift registers 22 to 25 are added by the adder 27). The results obtained by these operations are subtracted from the respective constants b ₁ and b ₂ (since a _i is a negative value). The result of the correction process is output via the multiplexing circuit 17 and the adder 18 adds the output of the multiplexing circuit 12 and the output of the multiplexing circuit 17.

Next, the optimum coefficients (a _i , b _i , threshold values of the stage) of the staged linear correction function of the ACSO operation according to an embodiment of the present invention are obtained. As shown in FIG. 3, since it is difficult to implement the correction function, an approximate stepwise linear function is used as the correction function in this embodiment.

上記で、

・・・（３）
である。 First, the optimal solution of the approximate linear function is estimated by a mathematical method. in this case,
The minimum value of ln (1 + e ^−x ) −ax−b is obtained.
f (x) = ln (1 + e ^−x ) −ax−b
When obtaining the minimum value of f (x), first, an optimum a value is obtained with f ′ (x) = 0.

Above,

... (3)
It is.

If the a value is known, the x value of the corresponding point is also obtained. When this straight line ax + b is a tangent of ln (1 + e ^−x ), the b value is also obtained. According to different a values, a plurality of tangent lines are created as shown in FIG. The intersection is a threshold for the stepwise linear function.

  Looking at the actual curve, as the x value increases (> 3), the change in the y value decreases, and the gradient of the tangent gradually becomes horizontal. For easy implementation, when a certain threshold is exceeded, the approximate linear function is set as a horizontal line.

In this _{embodiment, a 1 = -1 / 2,} a 2 = -1 / 4, a 3 = -1 / 8, and described for the case of a ₄ = 0, (3) the contact of the x _i by the formula But,
x ₁ = 0
x ₂ = 1.10
x ₃ = 1.95
Is required. x ₄ is selected in the experience value. Here, it is assumed that x ₄ = 3.50.

In addition, using ln (1 + e ^−x ), y _i is
y ₁ = 0.693
y ₂ = 0.287
y ₃ = 0.133
y ₄ = 0.030
Is required.

と推定することができる。 Therefore, the four-stage linear function in the above example is

Can be estimated.

と決められる。また、上述したように、直線１、直線２、直線３の乗算はそれぞれ一回、二回、三回の右シフト演算で実装することができる。 The application range of each straight line at the intersection of the above straight lines is

It is decided. As described above, the multiplication of the straight line 1, the straight line 2, and the straight line 3 can be implemented by one, two, and three right shift operations, respectively.

  As described above, in the present embodiment, by using the approximate stepwise linear function, it is possible to easily realize the correction function of the ACSO calculation that is often used for turbo Log-MAP decoding. In this case, the greater the number of stage stages, the higher the correction accuracy. However, the circuit implementation becomes somewhat complicated, and therefore, a trade-off between the number of stage stages and the correction precision must be considered in practice.

  The above-described ACSO mounting method is particularly required when a turbo decoding device is mounted on a device such as a mobile phone that requires a small circuit scale. Although the present invention assumes a turbo Log-MAP decoding algorithm, it can actually be adapted to various decoding algorithms using ACSO arithmetic.

It is a block diagram which shows the structure of the ACSO circuit by one Example of this invention. It is a block diagram which shows the modification of a structure of the ACSO circuit by one Example of this invention. It is a figure which shows the relationship between the correction function of Log-MAP in one Example of this invention, and an approximate step function. It is a block diagram which shows the structural example of the conventional turbo encoder. It is a block diagram which shows the structural example of the conventional turbo decoder. (A) is a block diagram showing a configuration of a conventional element encoder, and (b) is a trellis diagram thereof. It is a figure which shows the structure of LUT of the conventional correction function. It is a block diagram which shows the structure of the conventional ACSO arithmetic circuit. (A), (b) is a figure which shows an example of the ACSO calculation in Log-MAP decoding.

Explanation of symbols

11 Subtractor (x ₁ -x ₂ )
12, 17 Multiplex circuit
13 Absolute value calculation circuit
14 selection circuit 15-1 to 15-n multiplier 16-1 to 16-n,
18, 27 Adder 1
21-25 Shift register
26, 28 subtractor

Claims (12)

A decoder that performs a decoding operation in an ACSO (Add-Compare-Select-Offset) unit,
A decoder comprising: a correction processing circuit that corrects the output of the ACSO unit using an approximate branching linear function.   2. The decoder according to claim 1, wherein the correction processing circuit implements the approximate stepwise linear function by stepwise multiplication and addition.   3. The decoder according to claim 2, wherein the stepwise multiplication is implemented by shift operation and addition by selecting an appropriate gradient in the approximate stepwise linear function.   The decoder according to any one of claims 1 to 3, wherein the approximate stepwise linear function becomes a constant when a certain threshold value is exceeded.   5. The decoder according to claim 1, wherein an application range of the stage function is determined at an intersection of each straight line in the approximate stage linear function.   The decoder according to any one of claims 1 to 5, wherein the decoder is a turbo log-MAP (Log Maximum A Postiori Probability) decoding device. A decoding method used in a decoder that performs a decoding operation in an ACSO (Add-Compare-Select-Offset) unit,
The decoding method, wherein the decoder corrects the output of the ACSO unit using an approximate staged linear function.   8. The decoding method according to claim 7, wherein when the output of the ACSO unit is corrected, the approximate stepwise linear function is implemented by stepwise multiplication and addition.   9. The decoding method according to claim 8, wherein the stepwise multiplication is implemented by shift operation and addition by selecting an appropriate gradient in the approximate stepwise linear function.   The decoding method according to any one of claims 7 to 9, wherein the approximate stepwise linear function becomes a constant when a certain threshold value is exceeded.   The decoding method according to any one of claims 7 to 10, wherein an application range of the stage function is determined at an intersection of each straight line in the approximate stage linear function.   The decoding method according to any one of claims 7 to 11, wherein the decoder is a turbo log-MAP (Log Maximum A Positive Probability) decoder.

Images