JP2008078514A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit device by which a signal delay in long distance wiring can be reduced by providing a most significant wiring layer without any constraint by an LSI process. <P>SOLUTION: A process of providing a semiconductor integrated circuit substrate comprises: a process of forming on a base substrate 11 for a semiconductor integrated circuit the semiconductor integrated circuit and a wiring layer 12 which doesn't contain any most significant wiring layer for the semiconductor integrated circuit; and a process of forming on a wiring layer of the base substrate 11 for the semiconductor integrated circuit a connection pad 13 connected to the wiring layer. A process of providing a wiring substrate comprises: a process of carrying out on a base substrate 1 for the wiring substrate a plating of a thick film wiring layer 3 used as the most significant wiring layer for the semiconductor integrated circuit; and a process of forming on the thick film wiring layer 3 a bonding bump 6 connected to the thick film wiring layer 3. A face on which the connection pad 13 of the semiconductor integrated circuit substrate is formed is faced to a face on which the bonding bump 6 of the wiring substrate is formed, and the connection pad 13 and the bonding bump 6 are aligned and bonded. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device in which an uppermost wiring layer is formed by a thick film wiring.

  In a large-scale integrated circuit device (LSI) with a high degree of integration, there is not enough space to perform complicated wiring on one plane, so a multilayer wiring structure that performs wiring three-dimensionally using a large number of wiring layers Is adopted. In the multilayer wiring structure, the wiring is thinner and denser in the lower layer, but the wiring is thicker and the density is lower in the upper layer. Further, since the upper layer wiring is used to connect transistors that are farther apart, the wiring length is longer. In the system-on-chip (SoC) technology that integrates a high-performance and multifunctional LSI on a single chip, the chip length increases and the wiring length tends to further increase.

  One of the causes that hinders speeding up of LSIs is a problem of signal delay. The conventional signal delay problem has been dominated by the gate delay at the gate of the transistor. However, as miniaturization of semiconductor integrated circuits progresses, the influence of signal delay in long-distance wiring due to the wiring length becoming longer than gate delay has become dominant. Since the signal delay time in the wiring is proportional to the wiring resistance and the inter-wiring capacitance, it is indispensable to reduce the wiring resistance and reduce the inter-wiring capacitance in order to increase the speed of the LSI. For this reason, development of a new multilayer wiring technique for reducing wiring delay has been an issue (Non-Patent Document 1).

Patent Office edition, “2003 Patent Application Technology Trend Survey Report, LSI Multi-layer Wiring Technology”, March 2004

  In order to reduce the wiring delay, it is conceivable to increase the number of wiring layers and shorten the total wiring length to reduce the wiring resistance, but the increase in the number of wiring layers is limited from the viewpoint of manufacturing cost, Not a realistic solution. Further, in the current LSI wiring formation process, the maximum film thickness is about 1 to 2 μm, and there is a limit to reducing the resistance of the wiring. Therefore, it has been desired to reduce the influence of signal delay in long-distance wiring, which will become more apparent in the future.

  In view of such circumstances, the present invention intends to provide a method of manufacturing a semiconductor integrated circuit device capable of reducing signal delay in long-distance wiring by providing an uppermost wiring layer that is not restricted by an LSI process. .

  In order to achieve the above-described object of the present invention, a manufacturing method of a semiconductor integrated circuit device according to the present invention is a process of providing a semiconductor integrated circuit substrate and a wiring substrate, and the process of providing a semiconductor integrated circuit substrate includes: A process of forming a semiconductor integrated circuit and a wiring layer not including the uppermost wiring layer for the semiconductor integrated circuit on the base substrate for the semiconductor integrated circuit, and a wiring layer on the wiring layer of the base substrate for the semiconductor integrated circuit. Forming a connection pad to be connected, and providing the wiring substrate includes plating a thick wiring layer serving as a top wiring layer for a semiconductor integrated circuit on the wiring substrate base substrate. Providing a semiconductor integrated circuit substrate and a wiring substrate, and a step of providing a bonding bump connected to the thick film wiring layer on the thick film wiring layer, and connecting the semiconductor integrated circuit substrate Pad shape Those comprising a process of facing the surface on which the bonding bumps of the surface and the wiring substrate is formed, a step of bonding by aligning the connection pads and the bonding bumps, the.

  Here, the process of plating the thick film wiring layer may be a process of forming the first insulating layer on the wiring board base substrate and plating the thick film wiring layer on the first insulating layer. .

  The first insulating layer may be a low dielectric constant insulating layer.

  Further, the first insulating layer may have a thickness of 10 μm or more.

  Further, the process of forming the bonding bump is a process of forming the second insulating layer on the thick wiring layer, patterning the opening in the second insulating layer, and forming the bonding bump in the opening. May be.

  Furthermore, the semiconductor integrated circuit base substrate and the wiring substrate base substrate may be made of the same material.

  Furthermore, after the process of joining, you may comprise the process of flowing in an underfill.

  Furthermore, a process for forming an inductor element on a wiring board base substrate may be provided.

  In addition, a plurality of thick film wiring layers may be formed on the wiring board by plating.

  The method of manufacturing a semiconductor integrated circuit device according to the present invention has an advantage that signal delay in long-distance wiring can be reduced by providing a thick low-resistance uppermost wiring layer that is not restricted by an LSI process. Further, since the thick film wiring layer is simply formed on a separately prepared substrate, there is an advantage that it can be manufactured at low cost. Further, there is an advantage that a passive element such as an inductor element can be formed on the wiring board side.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a view for explaining a method of manufacturing a wiring board of a semiconductor integrated circuit device according to the present invention. FIGS. 1A to 1F are crossings of the wiring board of the semiconductor integrated circuit device in each process. FIG. Although the manufacturing process of the LSI substrate having the semiconductor device is omitted in FIG. 1, the present invention is not limited to a specific LSI substrate manufacturing method, and a general LSI substrate manufacturing method is applied. Just do it.

  First, as shown in FIG. 1A, in the wiring substrate of the semiconductor integrated circuit device of the present invention, the first insulating layer 2 is formed on the wiring substrate base substrate 1. The wiring board base substrate 1 may be made of Si or the like, but may be made of a compound semiconductor made of GaAs or the like. Further, it may be made of an insulator such as glass or plastic. When the wiring board base substrate 1 is made of an insulator such as glass or plastic, the action of the insulating layer is included in the wiring board base substrate 1, so that the physical first insulating layer 2 is It is not necessary to use it.

  The 1st insulating layer 2 should just consist of polyimide, an epoxy, a silicone resin etc., for example, and the film thickness should just be 10 micrometers-20 micrometers, for example, Preferably it is 10 micrometers. The first insulating layer 2 may be formed by a spin coating method, a printing method, a laminating method, or the like. Furthermore, the first insulating layer 2 is preferably composed of a low dielectric constant insulating layer (Low-k insulating layer).

  Next, as shown in FIG. 1B, a thick film wiring layer 3 serving as the uppermost wiring layer for the semiconductor integrated circuit is formed on the first insulating layer 2 by plating. The thick film wiring layer 3 is made of a low resistance material such as Cu, and has a film thickness of 10 μm to 50 μm, for example. For example, after forming a seed layer made of Ti, Cr or the like on the entire surface of the first insulating layer 2, the thick film wiring layer 3 is opened by etching a pattern corresponding to the thick film wiring by a photolithography technique, and by Cu plating. Etc. may be formed.

  As described above, since the uppermost wiring layer of the semiconductor integrated circuit device according to the present invention is formed on a substrate different from the LSI substrate, the wiring is formed with an arbitrary film thickness without being limited to the LSI process. Is possible. Further, since an existing semiconductor manufacturing process can be used, it can be manufactured at low cost. Here, in the LSI process, a multilayer wiring is formed by a plurality of grid-like wirings. However, according to the present invention, the uppermost wiring can be an arbitrary shape wiring because it does not depend on the LSI process. For this reason, the wiring can be bent at an arbitrary angle or curved.

  Furthermore, the uppermost wiring layer does not have to be a single layer, and a plurality of thick film wiring layers may be formed as necessary. As a result, not only the uppermost wiring layer but also the lower wiring layer can be formed into a thick film wiring, that is, the resistance can be reduced. Moreover, not only thick film wiring but also passive elements such as inductor elements can be formed on the wiring board. For example, it is possible to pattern an inductor element having a meander shape or a spiral shape on a wiring board base substrate using an existing semiconductor process. As a result, a semiconductor integrated circuit device including a high-performance inductor having a high Q value can be manufactured.

  Next, as shown in FIG. 1C, the second insulating layer 4 is formed on the thick film wiring layer 3. Similarly to the first insulating layer, the second insulating layer 4 may be made of, for example, polyimide, epoxy, silicone resin, or the like, and the film thickness thereof may be, for example, 10 μm to 20 μm. Similar to the first wiring layer, the second insulating layer 4 may be formed by a spin coating method, a printing method, a laminating method, or the like.

  Then, as shown in FIG. 1 (d), an opening 5 is formed in the second insulating layer 4. The opening 5 is formed at a position connected to the lower layer wiring of the semiconductor integrated circuit on the LSI substrate side. In the opening 5, a bonding bump described later is formed. The opening 5 may be formed, for example, by patterning the second insulating layer 4 by photolithography.

  Thereafter, as shown in FIG. 1 (e), bonding bumps 6 are formed in the openings 5. The bonding bump 6 is made of Au or the like, for example, a stud bump formed by a bonding method. Further, it may be formed by vapor deposition, plating, printing, or the like. In the illustrated example, the second insulating layer 4 is provided and the bonding bump 6 is formed in the opening 5. However, the present invention is not limited to this, and the bonding bump 6 may be formed directly on the thick wiring layer 3. good.

  On the other hand, as shown in FIG. 1F, the LSI substrate 10 having a semiconductor integrated circuit has a wiring layer that does not include the semiconductor integrated circuit and the uppermost wiring layer for the semiconductor integrated circuit on the base substrate 11 for the semiconductor integrated circuit. 12 (multilayer wiring layer). On the wiring layer 12, connection pads 13 connected to the wiring layer are formed.

  As shown in FIG. 1 (f), the wiring board and the LSI substrate formed as shown in FIGS. 1 (a) to 1 (e) are connected to the surface on which the connection pads 13 of the LSI substrate are formed and the wiring. The surface of the substrate on which the bonding bumps 6 are formed is opposed. Then, the connection pad 13 and the bonding bump 6 are aligned and bonded. For example, the ultrasonic bonding may be performed using a flip chip bonder. Thereby, the wiring layer of the LSI substrate and the thick film wiring layer of the wiring substrate are electrically connected. After bonding, an underfill may flow between the LSI substrate and the wiring substrate. As a result, it is possible to improve connection reliability against thermal stress such as heat cycle and connection reliability against physical stress such as impact and bending.

  Here, the semiconductor integrated circuit base substrate 11 and the wiring substrate base substrate 1 may be made of different materials, but are preferably made of the same material. By using the same material, the thermal expansion coefficient of the base substrate becomes equal, so that cracks at the joint between the joint bump 6 and the connection pad 13 do not easily occur.

  Note that the method of manufacturing the semiconductor integrated circuit device of the present invention is not limited to the illustrated example described above, and it is needless to say that various modifications can be made without departing from the scope of the present invention.

FIG. 1 is a view for explaining a method of manufacturing a wiring board of a semiconductor integrated circuit device according to the present invention. FIGS. 1A to 1F are crossings of the wiring board of the semiconductor integrated circuit device in each process. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base substrate for wiring boards 2 1st insulating layer 3 Thick film wiring layer 4 2nd insulating layer 5 Opening part 6 Junction bump 10 LSI substrate 11 Base substrate for semiconductor integrated circuits 12 Wiring layer 13 Connection pad

Claims (9)

A method of manufacturing a semiconductor integrated circuit device, the method comprising:
A process for providing a semiconductor integrated circuit board and a wiring board,
Providing the semiconductor integrated circuit substrate includes:
Forming a semiconductor integrated circuit and a wiring layer not including the uppermost wiring layer for the semiconductor integrated circuit on a semiconductor integrated circuit base substrate;
Forming a connection pad connected to the wiring layer on the wiring layer of the base substrate for the semiconductor integrated circuit;
Have
The process of providing the wiring board includes:
A process of plating a thick film wiring layer to be the uppermost wiring layer for the semiconductor integrated circuit on the wiring board base substrate;
Forming a bonding bump connected to the thick film wiring layer on the thick film wiring layer;
Having
Providing a semiconductor integrated circuit board and a wiring board;
A process of making the surface of the semiconductor integrated circuit board where the connection pads are formed and the surface of the wiring board where the bonding bumps are formed;
Aligning and bonding the connection pads and bonding bumps;
A method for manufacturing a semiconductor integrated circuit device, comprising:   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step of plating the thick film wiring layer includes forming a first insulating layer on the wiring substrate base substrate, and forming the first insulating layer on the first insulating layer. A method of manufacturing a semiconductor integrated circuit device, which is a process of forming a thick film wiring layer by plating.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first insulating layer is made of a low dielectric constant insulating layer.   4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first insulating layer has a thickness of 10 μm or more. 5.   5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step of forming the bonding bump, a second insulating layer is formed on the thick film wiring layer, and the second insulating layer is formed. A method of manufacturing a semiconductor integrated circuit device, comprising: patterning an opening in a layer and forming a bonding bump in the opening.   6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit base substrate and the wiring substrate base substrate are made of the same material. A method of manufacturing a circuit device.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of flowing an underfill after the bonding step. Device manufacturing method.   8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a step of forming an inductor element on the wiring board base substrate. A method for manufacturing an integrated circuit device.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a plurality of thick film wiring layers are formed on the wiring substrate by plating. Method.