JP2008072392A - Load driving device, image reader, image forming apparatus, program and driving signal generating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable high-speed driving of a target load by allowing variation factors of characteristics of each component such as timing skew to be substantially zero. <P>SOLUTION: A load driving device includes a driving signal generating means 20e for generating driving signals and outputting the signal to loads 10, 23; and a feedback means for feeding the driving signals output from the generating means 20e to the loads back to the generating means 20e. The generating means 20e generates a driving signal having controlled delay on the basis of the fed-back driving signals, and outputs the generated signal. In this way, the apparatus has a configuration in which the driving signals to the loads are fed back to the generating means 20e and delay (phase) to the driving signals is controlled and output, and thus, the variation factors of the characteristics of each component such as a timing skew can be made to be substantially zero and the target loads can be driven at a high speed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a load driving device, an image reading device, an image forming apparatus, a program, and a driving signal generation method.

  In recent years, there is an increasing demand for high image quality and high speed (high productivity) for image reading apparatuses such as MFPs (Multi Function Peripherals) and scanner units provided in copying machines. Particularly in an image reading apparatus, it is important how to drive a CCD image sensor, which is a reading key part, at high speed. Therefore, in addition to the ODD / EVEN separate readout type linear CCD image sensor that reads out the charges accumulated in each pixel of the light receiving pixel row separately into ODD and EVEN, and the ODD / EVEN separated readout, the charge of the light receiving pixel row is fasted. A linear CCD image sensor having a structure in which data is read by being divided into / Last has been proposed (for example, see Patent Document 1).

JP 2002-218186 A

  As described above, the high-speed driving of the CCD image sensor is realized mainly by multi-channel processing such as Even / Odd or Fast / Last, but in this case, there is a problem that costs are high. Therefore, attempts have been made to reduce the drive load (capacity) of the device itself, but the speedup by this has a limit in the structure of the CCD.

  On the other hand, in the high-speed driving of the CCD, it is a big problem that the performance guarantee cannot be performed because the characteristic variation of the CCD and the CCD driver such as the timing skew of the driving signal is large with respect to the satisfactory timing. On the other hand, for example, it may be possible to optimally adjust the timing of each unit while looking at the characteristics of the read image. However, if the number of production is small, it can be handled, but the number of units is large. On the other hand, it is virtually impossible in terms of cost and productivity.

  The present invention has been made in view of the above, and is a load driving device that can substantially eliminate variation factors of each component characteristic such as timing skew, and enables high-speed driving of a target load. An object of the present invention is to provide an image reading apparatus, an image forming apparatus, a program, and a drive signal generation method.

  In order to solve the above-described problems and achieve the object, a load driving device according to a first aspect of the present invention includes a drive signal generating unit that generates and outputs a drive signal to a load, and the drive signal generating unit. Feedback means for feeding back the drive signal output to the load to the drive signal generating means, and the drive signal generating means outputs a drive signal whose delay is controlled based on the drive signal fed back by the feedback means. Generate and output.

  According to a second aspect of the present invention, in the load driving device according to the first aspect, the driving signal generating means includes a delay detecting means for detecting a delay between the two driving signals fed back by the feedback means, and a delay. Delay determining means for determining the target value, and delay control means for controlling the delay detected by the delay detecting means to be the target value determined by the delay determining means.

  According to a third aspect of the present invention, in the load driving device according to the first aspect, the drive signal generating means detects a delay between the drive signal fed back by the feedback means and an arbitrary internal signal. Detecting means; delay determining means for determining a target value of delay; and delay control means for controlling the delay detected by the delay detecting means to be the target value determined by the delay determining means.

  According to a fourth aspect of the present invention, in the load driving device according to the second or third aspect, the delay determining unit determines a target value of the delay by selectively switching and outputting a plurality of divided voltages. .

  According to a fifth aspect of the present invention, there is provided the load driving device according to the second or third aspect, wherein the delay determining means switches and outputs a plurality of divided voltages using a D / A converter. Determine the value.

  According to a sixth aspect of the present invention, in the load driving device according to the second or third aspect, the delay determining means determines a target value of the delay based on any two signals obtained by DLL (Delay-Lock-Loop). To do.

  According to a seventh aspect of the present invention, in the load driving device according to any one of the second to sixth aspects, the target value of the delay determined by the delay determining means can be set in a register.

  According to an eighth aspect of the present invention, in the load driving device according to any one of the second to fifth aspects, the delay control means uses a variable delay element.

  According to a ninth aspect of the present invention, in the load driving device according to the sixth aspect, the delay control means uses a frequency variable element.

  According to a tenth aspect of the present invention, in the load drive device according to any one of the first to ninth aspects, the feedback means divides and inputs a drive signal at an input end of the load.

  The invention according to claim 11 is the load driving device according to any one of claims 1 to 9, wherein the feedback means includes a driver for driving the load. The signal is fed back at the input.

  According to a twelfth aspect of the present invention, in the load driving device according to any one of the first to ninth aspects, the feedback means includes a level conversion element that converts a logic level of a driving signal of the load.

  According to a thirteenth aspect of the present invention, in the load driving device according to the third aspect, a resistor and a capacitor for adjusting the timing of the driving signal are not mounted between the driving signal generating means and the load. .

  According to a fourteenth aspect of the present invention, there is provided an image reading apparatus that generates and outputs a drive signal for a load used for image reading, and a drive that is output from the drive signal generating means to the load. Feedback means for feeding back the signal to the drive signal generating means, and the drive signal generating means generates and outputs a drive signal with a delay controlled based on the drive signal fed back by the feedback means.

  According to a fifteenth aspect of the present invention, in the image reading apparatus according to the fourteenth aspect, the driving signal generating means includes a delay detecting means for detecting a delay between two driving signals fed back by the feedback means, and a delay. Delay determining means for determining the target value, and delay control means for controlling the delay detected by the delay determining means to be the target value determined by the delay detecting means.

  According to a sixteenth aspect of the present invention, in the image reading apparatus according to the fourteenth aspect, the drive signal generating means detects a delay between the drive signal fed back by the feedback means and an arbitrary internal signal. Detecting means; delay determining means for determining a target value of the delay; and delay control means for controlling the delay detected by the delay determining means to be the target value determined by the delay detecting means.

  The invention according to claim 17 is the image reading apparatus according to any one of claims 14 to 16, wherein the load is an image sensor.

  The invention according to claim 18 is the image reading apparatus according to any one of claims 14 to 16, wherein the load is an AFE (Analog Front End) circuit.

  According to a nineteenth aspect of the present invention, there is provided an image forming apparatus according to any one of the fourteenth to eighteenth aspects, and an image printing apparatus that forms and outputs an image according to the image data read by the image reading apparatus. And comprising.

  According to a twentieth aspect of the invention, there is provided a program for detecting a delay between two drive signals fed back by a feedback unit, a delay determining function for determining a target value of the delay, and the delay detecting function. And causing the computer to execute a delay control function for controlling the detected delay to be the target value determined by the delay determination function.

  According to a twenty-first aspect of the present invention, there is provided a program for detecting a delay between a drive signal fed back by a feedback means and an arbitrary internal signal, a delay detecting function for determining a delay target value, And causing a computer to execute a delay control function for controlling the delay detected by the delay detection function to be a target value determined by the delay determination function.

  The drive signal generation method of the invention according to claim 22 feeds back the drive signal output to the load from the drive signal generation means for generating and outputting the drive signal to the load to the drive signal generation means, The drive signal generating means generates and outputs a drive signal whose delay is controlled based on the fed back drive signal.

  According to the first aspect of the present invention, the drive signal to the load is fed back to the drive signal generating means, and the delay (phase) of the drive signal is controlled and output. The variation factor can be substantially zero, and the target load can be driven at high speed.

  Moreover, according to the invention concerning Claim 2, there exists an effect that the delay between arbitrary signals can be adjusted and hold | maintained appropriately.

  Further, according to the invention of claim 3, there is an effect that the delay of an arbitrary signal can be adjusted and held with a simple configuration.

  Moreover, according to the invention concerning Claim 4, there exists an effect that it becomes possible to control delay amount with an easy structure.

  Further, according to the invention of claim 5, there is an effect that it is possible to control a high-resolution delay amount with an easy configuration.

  Moreover, according to the invention concerning Claim 6, there exists an effect that delay amount can be controlled now with high precision.

  Further, according to the invention of claim 7, there is an effect that the user can easily change the delay amount of the signal.

  Moreover, according to the invention concerning Claim 8, there exists an effect that the delay (phase) of a signal can be hold | maintained appropriately.

  Further, according to the ninth aspect of the invention, there is an effect that the delay (phase) of the signal can be appropriately and easily maintained.

  According to the tenth aspect of the invention, there is an effect that even if the input breakdown voltage of the timing generator is not satisfied, it is possible to cope with it.

  According to the eleventh aspect of the present invention, there is an effect that even if the input breakdown voltage of the timing generator is not satisfied, it is possible to cope with it.

  Further, according to the twelfth aspect of the present invention, there is an effect that even if the input breakdown voltage of the timing generator is not satisfied, it is possible to cope with it.

  Further, according to the invention of claim 13, there is an effect that the delay of an arbitrary signal can be appropriately adjusted and held with a simple configuration.

  According to the fourteenth aspect of the present invention, each component such as timing skew is configured by feeding back the drive signal to the load to the drive signal generating means and controlling and outputting the delay (phase) of the drive signal. There is an effect that the characteristic variation factor can be made substantially zero and the target load can be driven at high speed.

  Further, according to the fifteenth aspect of the invention, there is an effect that the delay between arbitrary signals can be appropriately adjusted and maintained.

  Further, according to the sixteenth aspect of the invention, there is an effect that it is possible to adjust and maintain the delay of an arbitrary signal with a simple configuration.

  According to the seventeenth aspect of the invention, there is an effect that the image sensor can be driven at high speed.

  According to the eighteenth aspect of the invention, the AFE circuit can be driven at a high speed.

  According to the nineteenth aspect of the present invention, since the load such as the image sensor or the AFE circuit can be driven at a high speed, the productivity of the image printing apparatus can be improved.

  According to the twentieth aspect of the invention, there is an effect that it is possible to appropriately adjust and maintain a delay between arbitrary signals.

  Further, according to the twenty-first aspect, there is an effect that it is possible to adjust and hold a delay of an arbitrary signal with a simple configuration.

  According to the twenty-second aspect of the present invention, each component such as a timing skew is configured by feeding back the drive signal to the load to the drive signal generating means and controlling and outputting the delay (phase) of the drive signal. There is an effect that the characteristic variation factor can be made substantially zero and the target load can be driven at high speed.

  Exemplary embodiments of a load driving device, an image reading device, an image forming device, a program, and a driving signal generation method according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. This embodiment is an example in which a flat bed type image scanner is applied as an image reading device (load driving device).

  FIG. 1 is a longitudinal front view showing a schematic configuration of an image scanner 1 according to a first embodiment of the present invention. As shown in FIG. 1, the image scanner 1 includes a contact glass 3 on which a document 2 is placed, a first carriage 6 including a halogen lamp 4 for exposing the document 2 and a first reflection mirror 5, and a second carriage. A second carriage 9 comprising a reflection mirror 7 and a third reflection mirror 8, a CCD (Charge Coupled Devices) 10 as an image sensor, a lens unit 11 for forming an image on the CCD 10, and a white reference plate 12 for shading correction. And. The CCD 10 is provided on a sensor substrate 13, and the sensor substrate 13 includes a signal processing board 14 on which a signal processing circuit 20 (see FIG. 2) for performing various signal processing on an image signal output from the CCD 10 is mounted. They are connected by a connection cable 15. That is, the halogen lamp 4, the first, second, and third reflecting mirrors 5, 7, and 8 and the lens unit 11 constitute a scanning optical system. The scanning optical system may be a relative type and may be of a type in which the document side moves while the mirror or the like is fixed.

  The halogen lamp 4 irradiates light at a certain angle with respect to the reading surface of the white reference plate 12 or the contact glass 3, and the light reflected by the white reference plate 12 or the original 2 is the first, second, and third reflecting mirrors. The light enters the CCD 10 via 5, 7, 8 and the lens unit 11. The CCD 10 outputs a voltage corresponding to the amount of incident light as an analog image signal. The first and second carriages 6 and 9 are moved in the sub-scanning direction (arrow A direction) while maintaining a constant distance between the reading surface of the document 2 and the CCD 10 by driving a stepping motor (not shown). Is scanned by exposure.

  Here, FIG. 2 is a block diagram showing a drive control system of the image scanner 1. As shown in FIG. 2, the signal processing board 14 of the image scanner 1 includes a signal processing circuit 20, an image processing unit 21, and a control unit 22 that controls the signal processing circuit 20, the image processing unit 21, and the like. The control unit 22 includes a CPU (Central Processing Unit) (not shown), a memory, and the like, and includes various arithmetic processing functions based on the operation of the CPU according to a program stored in the memory.

  As shown in FIG. 2, the signal processing circuit 20 that processes the read image signal from the CCD 10 performs signal processing by an analog processing circuit for each RGB, and then performs A / D conversion, and outputs the read data to the image processing unit 21. Signal processing of the read image up to is performed. The flow of signal processing in the signal processing circuit 20 will be described. Here, a signal obtained by AC coupling of the output of the CCD 10 is line clamped by a clamp (CLMP) circuit 20a, and then held by a sample hold (SH) circuit 20b. The amplified signal is amplified through a variable gain amplifier (VGA) 20c whose gain can be controlled and input to an A / D converter (ADC) 20d. The converted digital image data is input to the image processing unit 21 as read image data. The clamp (CLMP) circuit 20 a, sample hold (SH) circuit 20 b, variable gain amplifier (VGA) 20 c, and A / D converter (ADC) 20 d constitute an AFE (Analog Front End) circuit 23. The signal processing circuit 20 generates a control signal for executing the above-described signal processing flow. The signal processing circuit 20 includes a timing generator 20e that is a driving signal generation unit that generates a timing signal for the CCD 10 and the AFE circuit 23, and a control unit 22. A CPU IF 20f that directly communicates with the CPU is included as a constituent element. The timing generator 20e includes a driver 20g for driving the CCD 10 and the AFE 23.

  Conventionally, as shown in FIG. 3, the CCD drive control system of an image scanner is composed of a timing generator (TG), a CCD driver (DRV), and a load (LD: CCD and AFE are shown here). The drive signal generated by the timing generator is buffered by the CCD driver to drive the CCD / AFE. Further, resistances or capacitors between the timing generator and the CCD driver and between the CCD driver and the load (CCD, AFE) are inserted to adjust the timing of the drive signal. However, the characteristics of each component (TG, DRV, CCD, AFE, resistance / capacitance) vary among individuals, and there are also parasitic components such as wiring capacitance. As a result, each signal timing is relative to the design value (center value). Will vary greatly. Naturally, this variation must be taken into consideration from the viewpoint of quality assurance, and it is necessary to satisfy the required signal timing including this variation in the design stage. However, in the case of high-speed driving of CCD / AFE, since the influence of characteristic variation becomes large with respect to the required timing, there is a problem that it is difficult to guarantee quality including the variation and high-speed driving cannot be performed.

  Therefore, in order to solve the above-described problem, in the image scanner 1 of the present embodiment, as shown in FIG. 4, the drive signal input to the load (CCD 10, AFE 23) is fed back to the timing generator 20e ( FB), thereby controlling the delay (phase) of an arbitrary signal. In FIG. 4, S1 and S2 indicate drive signals, and S1_FB and S2_FB indicate signals fed back from the load (CCD10, AFE23) input terminal to the timing generator 20e. Here, feedback means is realized.

  Here, the operation of the timing generator 20e will be described in detail. FIG. 5 is a block diagram showing a configuration of the timing generator 20e. As shown in FIG. 5, the timing generator 20e includes a delay detection unit (D-DET) 31, which is a delay detection unit, a delay determination unit (D-TGT) 32, which is a delay determination unit, a subtraction unit (SUB) 33, A band cut filter (FIL) 34 and a delay control unit (D-CNT) 35 as delay control means are provided. The delay detection unit (D-DET) 31 includes a phase detector (PC) 31a and a high-frequency cut filter (FIL) 31b, and detects a delay between the fed back signals (S1, S2). The delay determining unit (D-TGT) 32 is configured to switch and output a divided voltage generated by inserting a plurality of resistors between the power supply and the GND, and outputs a target value of delay. Has function. The delay control unit (D-CNT) 35 uses a delay variable element including a plurality of delay elements (D) 35a.

  The operation of the timing generator 20e configured as described above is as shown in FIG. FIG. 6 is a timing chart showing delay control by feedback in the timing generator 20e. As shown in FIG. 6, the phase detector (PC) 31a of the delay detector (D-DET) 31 detects the phase difference (delay) of the signals (S1_FB, S2_FB) fed back to the timing generator 20e. It is converted into a square wave (Vd0) having a pulse width corresponding to the delay amount. The square wave (Vd0) becomes a DC signal (Vd) from which a high frequency component has been removed by the high-frequency cut filter (FIL) 31b, and is input to the subtractor (SUB) 33. Here, the DC level of the DC signal (Vd) increases or decreases according to the pulse width of the square wave (Vd0) (pulse width → DC level conversion).

  On the other hand, the delay determining unit (D-TGT) 32 selects a target delay amount (Vr) by register setting and inputs it to the subtracter (SUB) 33. The subtractor (SUB) 33 takes the difference between the detected delay amount (Vd, DC level) and the target delay amount (Vr, DC level), and filters this with a high-frequency cut filter (FIL) 34 to obtain a delay control unit. This is input as the adjustment potential (Va) of the delay element (D) 35a of the (D-CNT) 35, that is, the delay correction amount of the S2 signal. The delay control unit (D-CNT) 35 controls and outputs the delay of the signal S2 according to the adjustment potential (Va).

In FIG. 6, the target delay amount of S2 with respect to S1 is to, and the potential at that time is Vo. Also, the delay correction amount Va in one loop of feedback operation
Va = (detection delay amount-target delay amount) * k
(K: correction coefficient, k = 0.5 in FIG. 6)
It is said. Here, the correction coefficient k is an important factor that determines the follow-up speed and stability of the feedback system. The correction coefficient k is determined by the gain of the subtractor 33 and the configuration of the high-frequency cut filter 34. A faster characteristic (shorter correction period) results in a poor stability characteristic. If the coefficient is small, the follow-up speed is slow, but a stable characteristic is steady.

  Since such an operation to keep the delay of S2 with respect to S1 is performed by such a feedback loop, the signal is automatically adjusted so as to always have the optimum timing. For this reason, even if there is a variation in characteristics, the deviation due to the variation is detected and automatically corrected, so that it is not necessary to substantially consider the influence of the variation.

  Thus, by feeding back the signal at the load input end to the timing generator 20e, the timing generator 20e can control the delay (phase) between arbitrary signals to optimize the timing, and perform high-speed driving. Therefore, it is not necessary to substantially consider the adverse variation, so that the CCD 10 / AFE 23 can be easily driven at a high speed.

  The above shows an example in which the delay (phase) of S2 is varied with respect to S1. Further, if the target delay amount can be set by a register or the like, the delay can be easily varied.

  In this embodiment, the divided voltage switching configuration is used as the delay determining unit (D-TGT) 32. However, as shown in FIG. 7, it is easy to use a D / A converter (DAC) 32b. It is also possible to increase the resolution (to make the setting step finer).

Furthermore, when using the output of the voltage divider or the D / A converter (DAC) 32b, the error of the target delay amount may increase due to the output changing depending on the reference potential (power supply, GND). However, by using a DLL (Delay-Lock-Loop) 32c (see FIG. 8), a configuration with less error can be achieved. In FIG. 8, an arbitrary internal signal Sr is used as a reference signal for the DLL 32c, and the phase of the output of the delay element (D, an example of four elements here) 32d is compared by a phase comparator (PC) 32e, and its output Is obtained through a high frequency cut filter (FIL) 32f. The delay of each delay element 32d is controlled by the obtained DC signal, and finally, the phase of the reference signal Sr and the output of the delay element 32d is adjusted to be 360 ° different (one cycle different) (the phase is locked). ) At this time, as shown in FIG. 9, if the delay amount D per delay element is assumed to be the signal period T of Sr and the number N of delay elements,
D = T / N
Thus, the delay amount D is determined only by the period T of the reference signal and the number N of delay elements. For this reason, the outputs of the delay elements 32d have a certain delay amount without being affected by temperature, power supply voltage, etc., and by selecting any two of these signals, a delay amount with a small error ( Can be generated. Note that the correction coefficients in FIG. 9 are the same as those described above, and a description thereof will be omitted. The two signals of the DLL 32c selected by the selector (SEL) 32g in the delay determination unit (D-TGT) 32 are converted into a DC signal through the phase comparator (PC) 32h and the high-frequency cut filter (FIL) 32i. It is converted and input to the subtractor 33. In addition, when the DLL 32c is used, the number N of delay elements may be increased in order to increase the resolution (increase the setting step).

  Further, in the present embodiment, the delay control unit (D-CNT) 35 is configured by using the delay element (D) 35a and varying the delay. At this time, only the delay element (D) 35a is built in the timing generator 20e. However, considering feedback from the load (CCD10, AFE23), the feedback including the load (CCD10, AFE23) is the same as the DLL 32c described above. It can also be regarded as a DLL of a loop. At this time, the delay control unit (D-CNT) 35 only needs to be able to adjust the delay (phase) according to a given signal. Therefore, even if a PLL (Phase Locked Loop) functioning as a frequency variable element is used, the same effect can be obtained. . However, since the duty may be changed depending on the drive signal, the configuration may be complicated in that case.

  By the way, if the feedback signal path is long, parasitic components such as wiring capacitance increase, which may increase the timing skew between feedback signals and deteriorate the delay adjustment accuracy. There is a need.

  As described above, according to the present embodiment, the drive signal to the load is fed back to the timing generator 20e, and the delay (phase) of the drive signal is controlled and output. The variation factor can be made substantially zero, and the target load can be driven at high speed.

  Incidentally, the logic level of the drive signal of the CCD 10 or the like may be higher than the power supply voltage of the timing generator 20e. At this time, when the input breakdown voltage of the timing generator 20e is satisfied, there is no problem even if direct feedback is performed as shown in FIG. 4, but such a configuration cannot be adopted when the breakdown voltage is low.

  Therefore, if the input breakdown voltage of the timing generator 20e is not satisfied, the drive signal is divided and input at the load (CCD10, AFE23) input terminal (see FIG. 10), and the signal is fed back at the input terminal of the driver 20g. (See FIG. 11), inserting a level conversion element (LC: Level Conversion) 40 for converting the logic level of the drive signal of the CCD 10 or the like (see FIG. 12), etc. However, it should be noted that in these cases, since the signal from which the delay is originally detected is different from the feedback signal, the deviation of the delay correction becomes large (delay adjustment accuracy becomes low).

  A drive signal such as AFE23 may be input via a driver in order to align the timing with other signals even if the logic level is equivalent to the power supply voltage of the timing generator 20e. In this case, as shown in FIG. 13, no driver is required.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  In the first embodiment, it has been described that the delay between arbitrary signals is automatically adjusted using feedback. Here, considering the case where this is performed for all the drive signals, feedback of all the signals is necessary, leading to an increase in the terminals of the timing generator 20e. Therefore, in this embodiment, instead of feeding back all signals, an arbitrary signal is fed back and its delay state is monitored, and the delay (phase) of all signals is adjusted accordingly. It is.

  Here, FIG. 14 is a block diagram showing a load drive system when one feedback signal is used. At this time, as shown in FIG. 14, the polarity of the characteristic variation of all signals is made the same by not mounting the resistance / capacitance between the timing generator 20e and the load (CCD 10, AFE 23). This utilizes the small characteristic difference between the gates and terminals in the same package (characteristic tracking). Here, by not mounting the resistor / capacitance inserted for timing adjustment, the timing variation itself increases. However, by removing the resistance / capacitance whose characteristics vary independently, the variation factor can be limited to the timing generator 20e / driver 20g / load (CCD10, AFE23). The characteristic difference between them can be reduced. That is, since the delay state of an arbitrary reference signal and the delay state of other signals can be made substantially equal, for example, the delay (phase) of all signals can be controlled by feeding back only one signal. .

  FIG. 15 is a block diagram showing a configuration of the timing generator 20e. As shown in FIG. 15, the timing generator 20e of the present embodiment is different from that of FIG. 5 in that the feedback signal is one of S1_FB and that the delay detection unit (D-DET) 31 has an arbitrary S1_FB. This is that a delay from the internal signal Sr is detected. Although the delay (phase) of an arbitrary reference signal S1 is detected here, the operation itself is the same as in FIG.

  Thus, according to the present embodiment, it is possible to adjust and maintain the delay of an arbitrary signal with a simple configuration.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIGS. In addition, the same part as 1st Embodiment mentioned above or 2nd Embodiment is shown with the same code | symbol, and description is also abbreviate | omitted.

  In the first embodiment or the second embodiment, the drive signal input to the load (CCD10, AFE23) is fed back (FB) to the timing generator 20e, and the signal is delayed by hardware in the timing generator 20e. (Phase) is controlled, but delay control by software is also possible. This point will be described. In the present embodiment, it is assumed that the timing generator 20e includes a CPU (Central Processing Unit) (not shown), a memory, and the like, and has various arithmetic processing functions based on the operation of the CPU according to a program stored in the memory. .

  First, delay control processing at the time of two-signal feedback will be described. FIG. 16 is a flowchart showing a flow of delay control processing at the time of two-signal feedback. As shown in FIG. 16, the CPU detects the target delay amount (step S1), and detects the delay amount between the two signals (step S2).

  In subsequent step S3, it is determined whether or not the delay amount between the two signals detected in step S2 is within a predetermined error range with respect to the target delay amount. If the delay amount between the signals is within a predetermined error range with respect to the target delay amount (Yes in step S3), the delay amount correction is unnecessary, and the processing is ended as it is. On the other hand, when the delay amount between the signals is not within the predetermined error range with respect to the target delay amount (No in step S3), a delay correction amount (detection delay amount−target delay amount) is calculated (step S4). Delay correction processing is performed according to the calculated delay correction amount (step S5), and the process returns to step S3. If the delay amount between the signals is within a predetermined error range with respect to the target delay amount as a result of performing the delay correction processing (Yes in step S3), the delay amount does not need to be corrected, so the processing is performed as it is. Exit.

  Next, delay control processing at the time of one-signal feedback will be described. FIG. 17 is a flowchart showing a flow of delay control processing at the time of one-signal feedback. As shown in FIG. 17, the CPU detects a target delay amount (step S11), and detects a delay amount of an arbitrary signal (step S12).

  In subsequent step S13, it is determined whether or not the delay amount detected in step S12 is within a predetermined error range with respect to the target delay amount. If the delay amount between the signals is within a predetermined error range with respect to the target delay amount (Yes in step S13), the delay amount correction is unnecessary, and thus the processing is terminated. On the other hand, when the delay amount between the signals is not within the predetermined error range with respect to the target delay amount (No in step S13), a delay correction amount (detection delay amount−target delay amount) is calculated (step S14). Delay correction processing is performed according to the calculated delay correction amount (step S15), and the process returns to step S13. As a result of performing the delay correction process, when the delay amount falls within a predetermined error range with respect to the target delay amount (Yes in step S13), the delay amount correction is unnecessary, and thus the processing ends. .

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described with reference to FIG. The same parts as those in the first to third embodiments described above are denoted by the same reference numerals, and description thereof is also omitted. The present embodiment shows an application example to a digital copying machine 50 as an image forming apparatus.

  FIG. 18 is a block diagram showing a schematic configuration of a digital copying machine 50 according to the fourth embodiment of the present invention. The digital copying machine 50 includes an image scanner 1 configured as in the first to third embodiments described above, and an image on a sheet based on digital image data read by the image scanner 1. The printer 51 is an image printing apparatus that performs the formation, and a control unit 52 that controls the digital copying machine 50.

  With such a configuration, the drive signal input to the load such as the CCD 10 or the AFE 23 is fed back to the timing generator 20e, thereby controlling the delay (phase) of an arbitrary signal to thereby drive the load such as the CCD 10 or the AFE 23 at high speed. Since this is possible, the high productivity in the printer 51 can be improved.

  As the printing method of the printer 51, various methods such as an ink jet method, a sublimation type thermal transfer method, a silver salt photography method, a direct thermal recording method, and a melt type thermal transfer method can be used in addition to the electrophotographic method.

1 is a longitudinal front view showing a schematic configuration of an image scanner according to a first embodiment of the present invention. It is a block diagram which shows the drive control system of an image scanner. It is a block diagram which shows the CCD drive control system of the conventional image scanner. It is a block diagram which shows the CCD drive control system of an image scanner. It is a block diagram which shows the structure of a timing generator. It is a timing chart which shows delay control by feedback in a timing generator. It is a block diagram which shows the structure of a timing generator. It is a block diagram which shows the structure of a timing generator. It is a timing chart which shows delay control by feedback in a timing generator. It is a block diagram which shows the structure of a timing generator. It is a block diagram which shows the structure of a timing generator. It is a block diagram which shows the structure of a timing generator. It is a block diagram which shows the structure of a timing generator. It is a block diagram which shows the load drive system at the time of making the feedback signal concerning the 2nd Embodiment of this invention into one. It is a block diagram which shows the structure of the timing generator e. It is a flowchart which shows the flow of the delay control process at the time of 2 signal feedback concerning the 3rd Embodiment of this invention. It is a flowchart which shows the flow of the delay control process at the time of 1 signal feedback. It is a block diagram which shows schematic structure of the digital copying machine concerning the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Load drive device, image reading apparatus 10 Load, image sensor 20e Drive signal generation means 23 Load, AFE circuit 31 Delay detection means 32 Delay determination means 35 Delay control means 50 Image forming apparatus 51 Image printing apparatus

Claims (22)

Drive signal generating means for generating and outputting a drive signal to the load;
Feedback means for feeding back the drive signal output from the drive signal generating means to the load to the drive signal generating means;
With
The drive signal generating means generates and outputs a drive signal whose delay is controlled based on the drive signal fed back by the feedback means;
A load driving device. The drive signal generating means includes
Delay detection means for detecting a delay between two drive signals fed back by the feedback means;
A delay determining means for determining a target value of the delay;
Delay control means for controlling the delay detected by the delay detection means to be a target value determined by the delay determination means;
Having
The load driving device according to claim 1. The drive signal generating means includes
Delay detection means for detecting a delay between the drive signal fed back by the feedback means and an arbitrary internal signal;
A delay determining means for determining a target value of the delay;
Delay control means for controlling the delay detected by the delay detection means to be a target value determined by the delay determination means;
Having
The load driving device according to claim 1. The delay determining means determines a target value of the delay by selectively switching and outputting a plurality of divided voltages.
The load driving apparatus according to claim 2 or 3, wherein The delay determining means determines a target value of delay by switching and outputting a plurality of divided voltages using a D / A converter.
The load driving apparatus according to claim 2 or 3, wherein The delay determination means determines a target value of delay by any two signals obtained by DLL (Delay-Lock-Loop).
The load driving apparatus according to claim 2 or 3, wherein The delay target value determined by the delay determining means can be set in a register.
The load driving device according to any one of claims 2 to 6, wherein The delay control means uses a delay variable element.
The load driving device according to any one of claims 2 to 5, wherein The delay control means uses a frequency variable element,
The load driving device according to claim 6. The feedback means divides and inputs a drive signal at an input end of the load.
The load driving device according to any one of claims 1 to 9, wherein When the feedback means includes a driver for driving the load, a signal is fed back at an input terminal of the driver.
The load driving device according to any one of claims 1 to 9, wherein The feedback means includes a level conversion element that converts the logic level of the drive signal of the load.
The load driving device according to any one of claims 1 to 9, wherein A resistor and a capacitor for adjusting the timing of the driving signal are not mounted between the driving signal generating means and the load.
The load driving device according to claim 3. Drive signal generating means for generating and outputting a drive signal to a load used for image reading;
Feedback means for feeding back the drive signal output from the drive signal generating means to the load to the drive signal generating means;
With
The drive signal generating means generates and outputs a drive signal whose delay is controlled based on the drive signal fed back by the feedback means;
An image reading apparatus. The drive signal generating means includes
Delay detection means for detecting a delay between two drive signals fed back by the feedback means;
A delay determining means for determining a target value of the delay;
Delay control means for controlling the delay detected by the delay determination means to be a target value determined by the delay detection means;
Having
The image reading apparatus according to claim 14. The drive signal generating means includes
Delay detection means for detecting a delay between the drive signal fed back by the feedback means and an arbitrary internal signal;
A delay determining means for determining a target value of the delay;
Delay control means for controlling the delay detected by the delay determination means to be a target value determined by the delay detection means;
Having
The image reading apparatus according to claim 14. The load is an image sensor.
The image reading apparatus according to claim 14, wherein the image reading apparatus is an image reading apparatus. The load is an AFE (Analog Front End) circuit.
The image reading apparatus according to claim 14, wherein the image reading apparatus is an image reading apparatus. An image reading device according to any one of claims 14 to 18,
An image printing apparatus that forms and outputs an image according to the image data read by the image reading apparatus;
An image forming apparatus comprising: A delay detection function for detecting a delay between the two drive signals fed back by the feedback means;
A delay determination function for determining a target value of the delay;
A delay control function for controlling the delay detected by the delay detection function to be a target value determined by the delay determination function;
A program that causes a computer to execute. A delay detection function for detecting a delay between the drive signal fed back by the feedback means and an arbitrary internal signal;
A delay determination function for determining a target value of the delay;
A delay control function for controlling the delay detected by the delay detection function to be a target value determined by the delay determination function;
A program that causes a computer to execute. A drive signal output to the load is fed back to the drive signal generating means from a drive signal generating means for generating and outputting a drive signal to the load,
The drive signal generating means generates and outputs a drive signal whose delay is controlled based on the feedback drive signal.
A drive signal generation method characterized by the above.

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