JP2008071925A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can sufficiently reduce the occupied area of a resistive element formed in a semiconductor chip, and a technology which can easily carry out the adjustment of the resistance value. <P>SOLUTION: The semiconductor device forms a well resistor 5 composed of an n-type semiconductor region in a semiconductor substrate 12 into which a p-type impurity is introduced. On the well resistor 5, an insulating region 4 in which the insulating film is embedded in a groove is formed; on the insulating region 4, a plurality of polysilicon resistors 9a-9c are formed. In other words, on the well resistor 5, the plurality of polysilicon resistors 9a-9c are formed through the insulating region 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a resistor is formed on a semiconductor substrate.

  Japanese Patent Application Laid-Open No. 11-330385 (Patent Document 1) discloses a technique capable of forming a plurality of resistance elements at high density.

Specifically, a resistance element is formed inside the semiconductor substrate under the thick field oxide film that covers the surface of the semiconductor substrate. Further, a second resistance element made of a polycrystalline silicon layer is formed above the field oxide film.
Japanese Patent Laid-Open No. 11-330385

  An integrated circuit is formed on the semiconductor chip, and this integrated circuit includes, for example, an analog circuit. In an analog circuit, a circuit is configured using a resistance element and a capacitance element in addition to a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Therefore, in a semiconductor chip having an analog circuit, a resistor element and a capacitor element are formed in addition to the MISFET.

  For example, for a resistance element used in an analog circuit, a well resistance made of a semiconductor region formed inside a semiconductor substrate or a polysilicon resistance made of a polysilicon film formed on the semiconductor substrate is used. The well resistance is formed, for example, in a lower layer of an insulating region in which a groove is formed in a semiconductor substrate and an insulating film is embedded in the groove. On the other hand, the polysilicon resistor is formed in the upper layer of the insulating region. Since the well resistance and the polysilicon resistance exist in separate resistance regions formed on the semiconductor substrate, the area occupied by the resistance element composed of the well resistance and the polysilicon resistance increases. It contributed to the area increase.

  Here, in Japanese Patent Laid-Open No. 11-330385 (Patent Document 1), a well resistance is formed under a thick field oxide film covering the surface of a semiconductor substrate, and polysilicon is formed on the field oxide film in which the well resistance is formed. A technique for forming a resistor is disclosed. That is, a well resistor and a polysilicon resistor are formed on the upper and lower layers of one resistor region formed on the semiconductor substrate to reduce the area occupied by the resistor element.

  However, in Patent Document 1, since only one polysilicon resistor is formed on the well resistor, there is a problem that it is not possible to sufficiently reduce the area occupied by the resistance element. Further, there is no idea about adjusting the resistance value of the polysilicon resistor formed on the well resistor by using the polysilicon resistor, and there is a problem that the resistance value cannot be made highly accurate. .

  An object of the present invention is to provide a technique capable of sufficiently reducing the occupation area of a resistance element formed on a semiconductor chip. Another object of the present invention is to provide a technique capable of easily adjusting the resistance value.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention includes: (a) a semiconductor substrate; (b) a first resistor formed of a semiconductor region formed inside the semiconductor substrate; and (c) an insulation to a groove formed on the first resistor. An insulating region in which the film is embedded; and (d) a plurality of second resistors made of a conductor film formed on the insulating region.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The area occupied by the resistance element formed on the semiconductor chip can be sufficiently reduced. In addition, since a plurality of polysilicon resistors are formed, the resistance value can be easily adjusted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
The semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 1 is a plan view showing a resistance region 1A in which a resistor is formed in a region of a semiconductor chip. In the semiconductor chip, a transistor region where a MISFET is formed, a resistance region 1A where a resistor is formed, and the like are formed, and an integrated circuit is formed by electrically connecting these regions. In FIG. 1, for example, the resistance region 1 </ b> A is surrounded by an insulating region 2, and a p-type semiconductor region 3 is formed inside the semiconductor substrate inside the insulating region 2. Furthermore, an insulating region 4 is formed on the surface of the semiconductor substrate inside the p-type semiconductor region 3, and a well resistor 5 made of an n-type semiconductor region is formed below the insulating region 4. That is, a well resistor (first resistor) 5 made of an n-type semiconductor region is formed inside the semiconductor substrate below the insulating region 4. An opening 6a is provided in the insulating region 4, and a wiring 8a is formed through a plug 7a provided in the opening 6a. Similarly, an opening 6b is provided in the insulating region 4, and a wiring 8b is formed via a plug 7b provided in the opening 6b. That is, the well resistor 5 is electrically connected to the wiring 8a via the plug 7a provided in the opening 6a, and is also electrically connected to the wiring 8b via the plug 7b provided in the opening 6b. ing. As described above, the well resistor 5 is configured to be connectable to the outside by the wirings 8a and 8b.

  On the insulating region 4, for example, a plurality of polysilicon resistors (second resistors) 9a to 9c made of a polysilicon film (conductor film) are formed. The plurality of polysilicon resistors 9a to 9c are independently formed, and are electrically connected to the wiring 11a through the plug 10a on one side. Similarly, the other side is electrically connected to the wiring 11b via the plug 10b. Therefore, the plurality of polysilicon resistors 9a to 9c can be connected to the outside by the wirings 11a and 11b, respectively. In FIG. 1, the wiring 11a and the wiring 11b are formed so as to extend to the outside only for the polysilicon resistor 9a in order to make the drawing easy to see, but the polysilicon resistors 9b and 9c are similarly formed by the wirings 11a and 11b. It can be connected to the outside. Here, FIG. 1 illustrates an example in which the wirings 11a and 11b connected to the polysilicon resistors 9a to 9c are formed in different layers and drawn out in the same direction. However, the drawing method of the wirings 11a and 11b is as follows. However, the present invention is not limited to this, and for example, it is possible to arrange the wirings so as not to contact each other by the same layer wiring.

  As described above, a plurality of polysilicon resistors 9 a to 9 c are formed on the insulating region 4 as the resistance of another element. In the first embodiment, a plurality of polysilicon resistors 9 a to 9 c are formed on the insulating region 4, but only the plurality of polysilicon resistors 9 a to 9 c are formed on the insulating region 4. Instead, for example, a plurality of resistors made of a conductor film such as a metal film may be formed. In the first embodiment, an example is shown in which three resistors are formed as the plurality of polysilicon resistors 9a to 9c.

  From the above, in the first embodiment, the insulating region 4 is formed on the main surface (element formation surface) of the semiconductor substrate. One of the features of the present invention is that a well resistor 5 made of a semiconductor region is formed inside a semiconductor substrate below the insulating region 4, and a plurality of polysilicon resistors made of a polysilicon film is formed on the insulating region 4. 9a to 9c are formed. That is, one of the features of the present invention is that the well resistor 5 and the plurality of polysilicon resistors 9a to 9c are stacked in the thickness direction of the semiconductor substrate via the insulating region 4.

  Next, FIG. 2 is a cross-sectional view showing a cross section taken along line AA of FIG. A more detailed configuration will be described with reference to FIG. As shown in FIG. 2, the insulating region 2 is provided on the main surface of the semiconductor substrate 12 into which p-type impurities are introduced, and the insulating region 4 is provided inside the insulating region 2. The insulating region 2 and the insulating region 4 are formed by embedding an insulating film in a groove formed in the semiconductor substrate 12.

  A p-type semiconductor region 3 is formed inside the semiconductor substrate 12 below the insulating region 2, and a well resistor 5 made of an n-type semiconductor region is formed inside the semiconductor substrate 12 below the insulating region 4. Is formed. A p-type semiconductor region 3 is formed inside the semiconductor substrate 12 in a region between the insulating region 2 and the insulating region 4, and a p-type semiconductor region 3 a is formed on the p-type semiconductor region 3. A cobalt silicide film 13 is formed on the surface of the p-type semiconductor region 3a.

  Openings 6a and 6b are formed in the insulating region 4, and a cobalt silicide film 13 is formed on the surfaces of the openings 6a and 6b. An n-type semiconductor region 5a is formed under the cobalt silicide film 13, and a well resistor 5 is formed under the n-type semiconductor region 5a. That is, the well resistor 5 is formed in the lower layer of the insulating region 4, and the well resistor 5 is formed in the openings 6a and 6b via the n-type semiconductor region 5a formed in the openings 6a and 6b. It is electrically connected to the cobalt silicide film 13 formed on the surface.

  In the opening 6 a, a plug 7 a formed on the insulating film 15 is connected to the cobalt silicide film 13, and this plug 7 a is connected to a wiring 8 a formed on the insulating film 15. Similarly, in the opening 6b, a plug 7b formed on the insulating film 15 is connected to the cobalt silicide film 13, and the plug 7b is connected to a wiring 8b formed on the insulating film 15. Therefore, it is understood that the well resistor 5 is connected to the plugs 7a and 7b through the n-type semiconductor region 5a and the cobalt silicide film 13, and further connected to the wirings 8a and 8b through the plugs 7a and 7b. . That is, the well resistor 5 is configured to be connected to the outside of the resistance region by the wirings 8a and 8b.

  On the other hand, a polysilicon resistor 9b made of a polysilicon film is formed on the insulating region 4. A cobalt silicide film 13 is formed in a connection region between the polysilicon resistor 9b and the plugs 10a and 10b, and sidewalls 14 are formed at both ends of the polysilicon resistor 9b. In the first embodiment, the cobalt silicide film 13 is formed only in the connection region of the polysilicon resistor 9b with the plugs 10a and 10b. However, when the resistance value of the polysilicon resistor 9b is reduced, The cobalt silicide film 13 may be formed on the entire surface of the silicon resistor 9b.

  A plug 10a formed on the insulating film 15 is connected to one end side of the polysilicon resistor 9b, and the plug 10a is connected to a wiring 11a formed on the insulating film 15. Similarly, a plug 10b formed on the insulating film 15 is connected to the other end side of the polysilicon resistor 9b, and this plug 10b is connected to a wiring 11b formed on the insulating film 15. Therefore, the polysilicon resistor 9b is electrically connected to the wirings 11a and 11b, and can be connected to the outside of the resistance region by the wirings 11a and 11b.

  Next, FIG. 3 is a cross-sectional view showing a cross section taken along line BB in FIG. As shown in FIG. 3, a well resistor 5 made of an n-type semiconductor region is formed inside a semiconductor substrate 12 into which a p-type impurity has been introduced, and an insulating region 4 is formed on the well resistor 5. A plurality of polysilicon resistors 9 a to 9 c are formed on the insulating region 4. That is, the well resistor 5 is formed in the lower layer of the insulating region 4 in which the insulating film is buried in the groove formed in the main surface of the semiconductor substrate 12, and the plurality of polysilicon resistors 9 a to 9 c are formed on the insulating region 4. Yes.

  The resistance region in the first embodiment is configured as described above, and one of its features is that, as shown in FIG. 3, the well resistor 5 and the plurality of polysilicon resistors 9a are formed on the upper and lower layers of the insulating region 4, respectively. 1 to 9c, that is, the well resistor 5 and the plurality of polysilicon resistors 9a to 9c are formed so as to be stacked on the planar region where the insulating region 4 is formed. There is one.

  By configuring the resistance element in this way, the area occupied by the resistance element formed on the semiconductor chip can be sufficiently reduced.

  An integrated circuit is formed on the semiconductor chip, and this integrated circuit includes, for example, an analog circuit. In the analog circuit, a circuit is configured by using a resistance element and a capacitance element in addition to the MISFET. Therefore, in a semiconductor chip having an analog circuit, a resistor element and a capacitor element are formed in addition to the MISFET.

  For example, for a resistance element used in an analog circuit, a well resistance made of a semiconductor region formed inside a semiconductor substrate or a polysilicon resistance made of a polysilicon film formed on the semiconductor substrate is used. The well resistance is formed, for example, in a lower layer of an insulating region in which a groove is formed in a semiconductor substrate and an insulating film is embedded in the groove. On the other hand, the polysilicon resistor is formed in the upper layer of the insulating region. Since the well resistance and the polysilicon resistance are usually present in separate resistance regions formed on the semiconductor substrate, the area occupied by the resistance element composed of the well resistance or the polysilicon resistance increases, resulting in an analog circuit. This contributes to an increase in the overall area.

  Here, in Japanese Patent Laid-Open No. 11-330385 (Patent Document 1), a well resistance is formed under a thick field oxide film covering the surface of a semiconductor substrate, and polysilicon is formed on the field oxide film in which the well resistance is formed. A technique for forming a resistor is disclosed. That is, a well resistor and a polysilicon resistor are formed on the upper and lower layers of one resistor region formed on the semiconductor substrate to reduce the area occupied by the resistor element.

  However, in Patent Document 1, since only one polysilicon resistor is formed on the well resistor, the area occupied by the resistance element cannot be sufficiently reduced. A plurality of polysilicon resistors exist in a semiconductor chip, but when only one polysilicon resistor is formed on one well resistor, there are a plurality of polysilicon resistors not formed on the well resistor. The occupation area of the resistance element cannot be reduced. That is, the polysilicon resistor that is not formed on the well resistor needs to be formed in a different region that is different from the well resistor in a plan view, and therefore, the total area occupied by the resistance elements cannot be reduced sufficiently.

  On the other hand, in the first embodiment, a plurality of polysilicon resistors are formed on the well resistor via an insulating region. That is, a plurality of polysilicon resistors are integrated on one well resistor. For this reason, since the number of polysilicon resistors formed on the well resistance can be increased, the number of polysilicon resistors formed in an independent region different in plan from the well resistance can be drastically reduced. Therefore, the area occupied by the resistance element can be sufficiently reduced. In other words, in the first embodiment, by forming a plurality of polysilicon resistors on the well resistor via the insulating region, the area of the resistance element is reduced to a level that is not comparable to that of Patent Document 1. can do.

  As shown in FIG. 4, the effect of the first embodiment is that a plurality of resistance regions 1 </ b> A and 1 </ b> B in which a well resistor 5 is formed, and a plurality of polysilicon resistors 9 a to 9 </ b> It becomes remarkable by forming 9c. That is, a plurality of well resistors 5 are formed on the semiconductor chip, and a plurality of polysilicon resistors 9a to 9c are stacked on the well resistor 5 in each resistance region where the well resistors 5 are formed. Most of the plurality of polysilicon resistors formed on the semiconductor chip can be arranged on the well resistor 5. Thereby, the occupation area of the resistance element can be sufficiently reduced.

  Next, a method for manufacturing the resistance element in the first embodiment will be described with reference to the drawings. The resistance element according to the first embodiment is simultaneously formed in a manufacturing process of a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) formed in another region of the semiconductor chip.

  First, as shown in FIG. 5, a semiconductor substrate 20 made of a silicon single crystal into which a p-type impurity such as boron (B) is introduced is prepared. At this time, the semiconductor substrate 20 is in a state of a substantially wafer-shaped semiconductor wafer. Then, an element isolation region 21 that isolates elements is formed in the CMISFET formation region of the semiconductor substrate 20. The element isolation region 21 is provided to prevent the elements from interfering with each other. The element isolation region 21 can be formed by using, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. FIG. 5 shows the element isolation region 21 formed by the STI method. In the STI method, the element isolation region 21 is formed as follows. That is, the element isolation trench is formed in the semiconductor substrate 20 by using a photolithography technique and an etching technique. Then, a silicon oxide film is formed on the semiconductor substrate 20 so as to fill the element isolation trench, and then unnecessary silicon oxide formed on the semiconductor substrate 20 by chemical mechanical polishing (CMP). Remove the membrane. Thereby, the element isolation region 21 in which the silicon oxide film is buried only in the element isolation trench can be formed. At this time, insulating regions 22 and 23 formed in the same process as the element isolation region 21 are also formed in the resistance element formation region.

  Next, as shown in FIG. 6, an impurity is introduced into the active region isolated by the element isolation region 21 to form a well. For example, the p-type well 24 is formed in the n-channel MISFET formation region of the active region, and the n-type well 26 is formed in the p-channel MISFET formation region. The p-type well 24 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 20 by ion implantation. Similarly, the n-type well 26 is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 20 by ion implantation. Here, in the step of forming the p-type well 24, the p-type semiconductor region 25 is formed in the resistance element formation region, and in the step of forming the n-type well 26, the well resistance made of the n-type semiconductor region is formed in the resistance element formation region. 27 is formed.

  Subsequently, channel forming semiconductor regions (not shown) are formed in the surface region of the p-type well 24 and the surface region of the n-type well 26. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

Next, as shown in FIG. 7, a gate insulating film 28 is formed on the semiconductor substrate 20. The gate insulating film 28 is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film 28 is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film 28 may be a silicon oxynitride film (SiON). That is, nitrogen may be segregated at the interface between the gate insulating film 28 and the semiconductor substrate 20. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film 28 can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. Therefore, by using a silicon oxynitride film as the gate insulating film 28, it is possible to suppress a variation in threshold voltage caused by diffusion of impurities in the gate electrode toward the semiconductor substrate 20 side. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate 20 in an atmosphere containing nitrogen such as NO, NO _2, or NH ₃ . Further, after forming a gate insulating film 28 made of a silicon oxide film on the surface of the semiconductor substrate 20, the semiconductor substrate 20 is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film 28 and the semiconductor substrate 20. The same effect can be obtained also by making it.

  Further, the gate insulating film 28 may be formed of, for example, a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film. Conventionally, a silicon oxide film has been used as the gate insulating film 28 from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film 28 is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film 28, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric film capable of increasing the physical film thickness even with the same capacitance has been used. According to the high dielectric film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced.

For example, a hafnium oxide film (HfO ₂ film), which is one of hafnium oxides, is used as the high dielectric film. Instead of the hafnium oxide film, a hafnium aluminate film, an HfON film (hafnium oxynitride film) is used. ), HfSiO films (hafnium silicate films), HfSiON films (hafnium silicon oxynitride films), HfAlO films, and other hafnium-based insulating films can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Subsequently, a polysilicon film 29 is formed on the gate insulating film 28. The polysilicon film 29 can be formed using, for example, a CVD method. Then, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film 29 formed in the n-channel type MISFET formation region by using a photolithography technique and an ion implantation method. Similarly, a p-type impurity such as boron is introduced into the polysilicon film 29 formed in the p-channel MISFET formation region.

  Next, as shown in FIG. 8, the polysilicon film 29 is processed by etching using the patterned resist film as a mask to form a gate electrode 30a in the n-channel MISFET formation region, and in the p-channel MISFET formation region. A gate electrode 30b is formed. At this time, the polysilicon film 29 is also patterned in the resistance element forming region, and a plurality of polysilicon resistors 31 are formed on the insulating region 23. Thereby, the well resistor 27 and the plurality of polysilicon resistors 31 can be formed in the upper and lower layers via the insulating region 23.

  Here, an n-type impurity is introduced into the polysilicon film 29 in the gate electrode 30a in the n-channel MISFET formation region. Therefore, the work function value of the gate electrode 30a can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the n-channel MISFET can be reduced. On the other hand, a p-type impurity is introduced into the polysilicon film 29 in the gate electrode 30b in the p-channel MISFET formation region. Therefore, the work function value of the gate electrode 30b can be set to a value in the vicinity of the valence band of silicon (5.15 eV), so that the threshold voltage of the p-channel MISFET can be reduced. Thus, in the first embodiment, the threshold voltage can be reduced in both the n-channel MISFET and the p-channel MISFET (dual gate structure).

  Subsequently, as shown in FIG. 9, a shallow n-type impurity diffusion region 32 aligned with the gate electrode 30a is formed by using a photolithography technique and an ion implantation method. The shallow n-type impurity diffusion region 32 is a semiconductor region. Similarly, a shallow p-type impurity diffusion region 33 is formed in the p-channel type MISFET formation region. The shallow p-type impurity diffusion region 33 is formed in alignment with the gate electrode 30b. This shallow p-type impurity diffusion region 33 can be formed by using a photolithography technique and an ion implantation method.

  Next, as shown in FIG. 10, a silicon oxide film is formed on the semiconductor substrate 20. The silicon oxide film can be formed using, for example, a CVD method. Then, the silicon oxide film is anisotropically etched to form side walls 34 as shown in FIG. 10 on the side walls of the gate electrodes 30a and 30b. At this time, the side walls 34 are formed on the side walls of the plurality of polysilicon resistors 31 also in the resistance element forming region. Here, the sidewalls 34 are formed from a single layer film of a silicon oxide film, but the present invention is not limited to this. For example, the sidewalls 34 formed of a laminated film of a silicon nitride film and a silicon oxide film may be formed. Good.

  Subsequently, a deep n-type impurity diffusion region 35 aligned with the sidewall 34 is formed in the n-channel MISFET formation region by using a photolithography technique and an ion implantation method. The deep n-type impurity diffusion region 35 is a semiconductor region. The deep n-type impurity diffusion region 35 and the shallow n-type impurity diffusion region 32 form a source region. Similarly, a drain region is formed by the deep n-type impurity diffusion region 35 and the shallow n-type impurity diffusion region 32. Thus, by forming the source region and the drain region with the shallow n-type impurity diffusion region 32 and the deep n-type impurity diffusion region 35, the source region and the drain region can have an LDD (Lightly Doped Drain) structure. In this step, the n-type semiconductor region 36 is also formed in the resistance element formation region.

  Similarly, a deep p-type impurity diffusion region 37 aligned with the sidewall 34 is formed in the p-channel MISFET formation region. The deep p-type impurity diffusion region 37 and the shallow p-type impurity diffusion region 33 form a source region and a drain region. Therefore, the source region and the drain region also have an LDD structure in the p-channel type MISFET. In this step, the p-type semiconductor region 38 is also formed in the resistance element formation region.

  After forming the deep n-type impurity diffusion region 35 and the deep p-type impurity diffusion region 37 in this manner, a heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Thereafter, as shown in FIG. 11, a cobalt film is formed on the semiconductor substrate 20. At this time, a cobalt film is formed so as to be in direct contact with the gate electrodes 30a and 30b. Similarly, the cobalt film is also in direct contact with the deep n-type impurity diffusion region 35 and the deep p-type impurity diffusion region 37. Also in the resistance element forming region, the cobalt film is in direct contact with the p-type semiconductor region 38, the n-type semiconductor region 36, and a partial region of the polysilicon resistor 31. Note that direct contact of the cobalt film only on a partial region of the polysilicon resistor 31 is realized by covering a part of the surface of the polysilicon resistor 31 with a mask film such as an insulating film. Can do. In order to form a cobalt silicide film on the entire surface of the polysilicon resistor 31 in order to reduce the resistance of the polysilicon resistor 31, the cobalt film is in direct contact with the entire surface of the polysilicon resistor 31 without using a mask film. What should I do?

  The cobalt film can be formed using, for example, a sputtering method. Then, after forming the cobalt film, heat treatment is performed to react the polysilicon film constituting the gate electrodes 30a and 30b with the cobalt film, thereby forming a cobalt silicide film 39 as shown in FIG. As a result, the gate electrodes 30 a and 30 b have a laminated structure of the polysilicon film 29 and the cobalt silicide film 39. The cobalt silicide film 39 is formed to reduce the resistance of the gate electrodes 30a and 30b. Similarly, by the heat treatment described above, the silicon silicide film 39 reacts to form the cobalt silicide film 39 also on the surfaces of the deep n-type impurity diffusion region 35 and the deep p-type impurity diffusion region 37. Therefore, the resistance can be reduced also in the deep n-type impurity diffusion region 35 and the deep p-type impurity diffusion region 37. Also in the resistance element region, a cobalt silicide film 39 is formed on the p-type semiconductor region 38, the n-type semiconductor region 36, and a partial region of the polysilicon resistor 31.

  Then, the unreacted cobalt film is removed from the semiconductor substrate 20. In the first embodiment, the cobalt silicide film 39 is formed. However, for example, a nickel silicide film or a titanium silicide film may be formed instead of the cobalt silicide film 39.

  Next, as shown in FIG. 12, a silicon oxide film 40 is formed on the main surface of the semiconductor substrate 20. This silicon oxide film 40 can be formed using, for example, a CVD method using TEOS (tetraethyl orthosilicate) as a raw material. Thereafter, the surface of the silicon oxide film 40 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, a contact hole 41 is formed in the silicon oxide film 40 by using a photolithography technique and an etching technique. Then, a titanium / titanium nitride film 42 a is formed on the silicon oxide film 40 including the bottom surface and inner wall of the contact hole 41. The titanium / titanium nitride film 42a is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. The titanium / titanium nitride film 42a has, for example, a so-called barrier property that prevents tungsten, which is a material of a film to be embedded in a later step, from diffusing into silicon.

  Subsequently, a tungsten film 42 b is formed on the entire main surface of the semiconductor substrate 20 so as to fill the contact hole 41. The tungsten film 42b can be formed using, for example, a CVD method. Then, the plug 43 can be formed by removing the unnecessary titanium / titanium nitride film 42a and the tungsten film 42b formed on the silicon oxide film 40 by, for example, the CMP method.

  Next, a titanium / titanium nitride film 44a, an aluminum film 44b, and a titanium / titanium nitride film 44c are sequentially formed on the silicon oxide film 40 and the plug 43. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique, and the wiring 45 is formed. Furthermore, although wiring is formed in the upper layer of the wiring 45, description here is abbreviate | omitted. In this manner, the semiconductor device according to the first embodiment can be formed.

  According to the method for manufacturing a semiconductor device in the first embodiment, it is possible to form a resistance element in which a plurality of polysilicon resistors 31 are formed on the well resistor 27 via an insulating region in the step of forming the CMISFET.

(Embodiment 2)
In the first embodiment, as shown in FIG. 4, a plurality of resistance regions 1A and 1B in which well resistors 5 having the same shape are formed. The example which forms -9c was demonstrated. In the second embodiment, an example in which resistance regions having different well resistances are formed in a semiconductor chip and a polysilicon resistance is formed on each well resistance will be described.

  A plurality of well resistors are formed on the semiconductor chip, but these well resistors do not all have the same resistance value, and may have different resistance values. That is, an integrated circuit is formed on the semiconductor chip, and a resistive element is also used for this integrated circuit. In an integrated circuit, resistance elements having different resistance values are required depending on the circuit, and therefore, well resistors having different resistance values may be manufactured. In order to form well resistances having different resistance values, for example, the resistance value of the well resistance may be changed by changing the shape.

  An example of this case is shown in FIG. In FIG. 13, a resistance region 1A having a relatively large rectangular shape and a resistance region 1C having a relatively small rectangular shape are mixed in the semiconductor chip. In the resistance region 1 </ b> A, a well resistor 5 having a relatively large area is formed, and a plurality of polysilicon resistors 9 a to 9 c are formed on the well resistor 5 via the insulating region 4. That is, in the resistance region 1A, since the area of the well resistor 5 is large, a plurality of polysilicon resistors 9a to 9c can be arranged.

  On the other hand, a well resistor 53 having a relatively small area is formed in the resistance region 1C. Since the well resistor 53 has a small area, only one polysilicon resistor 57 is formed on the well resistor 53 via the insulating region 52.

  As described above, in the second embodiment, a resistance region in which a plurality of polysilicon resistors are formed on the well resistor and a resistance region in which one polysilicon resistor is formed on the well resistor depending on the size of the area of the well resistor. Will be mixed in the semiconductor chip. Also in this case, since a plurality of polysilicon resistors can be arranged on the well resistance having a large area via the insulating region, the occupation area of the resistance element can be reduced. Furthermore, since well resistances having different shapes can be formed on the semiconductor chip, well resistances having different resistance values can be formed.

  The configuration of the resistance region 1C is the same as that of the resistance region 1A except that the size is different. For example, the resistance region 1 </ b> C is also surrounded by the insulating region 50, and a p-type semiconductor region 51 is formed inside the semiconductor substrate inside the insulating region 50. Further, an insulating region 52 is formed on the surface of the semiconductor substrate inside the p-type semiconductor region 51, and a well resistor 53 made of an n-type semiconductor region is formed below the insulating region 52. That is, a well resistor 53 made of an n-type semiconductor region is formed inside the semiconductor substrate below the insulating region 52. The shape of the well resistor 53 is smaller than that of the well resistor 5 in the resistance region 1A.

  An opening 54a is provided in the insulating region 52, and a wiring 56a is formed through a plug 55a provided in the opening 54a. Similarly, an opening 54b is provided in the insulating region 52, and a wiring 56b is formed through a plug 55b provided in the opening 54b. That is, the well resistor 53 is electrically connected to the wiring 56a via the plug 55a provided in the opening 54a, and is also electrically connected to the wiring 56b via the plug 55b provided in the opening 54b. ing. As described above, the well resistor 53 is configured to be connected to the outside by the wirings 56a and 56b.

  On the insulating region 52, for example, one polysilicon resistor 57 made of a polysilicon film is formed. One polysilicon resistor 57 is electrically connected to the wiring 59a through the plug 58a on one side. Similarly, the other side is electrically connected to the wiring 59b via the plug 58b. Therefore, one polysilicon resistor 57 can be connected to the outside by the wirings 59a and 59b.

  As in the second embodiment, depending on the size of the area of the well resistance, there may be a mixture of a plurality of polysilicon resistors on the well resistance and a single polysilicon resistor on the well resistance. Also good. That is, it is not necessary to form a plurality of polysilicon resistors on all well resistors, and the amount of polysilicon resistors formed on the well resistors may be adjusted according to the shape of the well resistors.

(Embodiment 3)
In the first embodiment, the example in which the plurality of polysilicon resistors formed on the well resistor are used as independent separate elements has been described. In the third embodiment, an example in which a plurality of polysilicon resistors formed on a well resistor are electrically connected and used will be described.

  FIG. 14 is a plan view showing the configuration of the resistance element in the third embodiment. Since FIG. 14 has substantially the same configuration as the configuration of the resistance element in the first embodiment, different configuration points will be described.

  In FIG. 14, in the third embodiment, a plurality of polysilicon resistors 9 a to 9 c formed on the well resistor 5 via the insulating region 4 are connected in parallel. That is, the plurality of polysilicon resistors 9a to 9c are electrically connected to the wirings 60a and 60b via the plugs 10a and 10b. Thus, by connecting the plurality of polysilicon resistors 9a to 9c in parallel, a resistance element having a resistance value different from that when the plurality of polysilicon resistors 9a to 9c are used independently can be easily formed. That is, a plurality of polysilicon resistors 9a to 9c are formed on the well resistor 5, but depending on the resistance region, a plurality of polysilicon resistors 9a to 9c are connected in parallel, so that polysilicon having different resistance values is formed on the semiconductor chip. A plurality of resistors can be formed.

  Usually, in order to change the resistance value of the polysilicon resistor, it is conceivable to change the shape of the polysilicon resistor. However, according to the third embodiment, it is possible to form polysilicon resistors having different resistance values only by forming a plurality of polysilicon resistors having the same shape and changing the connection wiring. Therefore, polysilicon resistors having different resistance values can be easily formed. This can be easily realized for the first time by a configuration in which a plurality of polysilicon resistors are formed on a well resistor, and can be easily conceived from a configuration in which one polysilicon resistor is formed on a well resistor. It is something that cannot be done.

  Further, as shown in FIG. 15, among the plurality of polysilicon resistors 9a to 9c connected in parallel to each other, for example, the wiring 60a and 60b are laser trimmed so that the polysilicon resistor 9c is not connected to the polysilicon resistors 9a and 9b. The resistance value obtained by connecting the polysilicon resistor 9a and the polysilicon resistor 9b in parallel can also be realized. For example, in one resistance region, the polysilicon resistors 9a to 9c may be configured to be connected in parallel, and in another resistance region, only the polysilicon resistor 9a and the polysilicon resistor 9b may be configured to be connected in parallel. . Therefore, for example, wiring patterns for connecting the polysilicon resistors 9a to 9c in parallel in a plurality of resistance regions are formed in advance. In the resistance region where only the polysilicon resistor 9a and the polysilicon resistor 9b are desired to be connected in parallel, only the portion of the wirings 60a and 60b to which the polysilicon resistor 9c is connected may be cut by laser trimming. With this configuration, it is possible to easily form a resistance element having a desired resistance value.

  The plurality of polysilicon resistors 9a to 9c are not only connected in parallel, but can also be connected in series as shown in FIG. In FIG. 16, the polysilicon resistor 9a is connected to a wiring 61 serving as a lead-out wiring through a plug 10a, and is connected in series to the polysilicon resistor 9b by a wiring 62. The polysilicon resistor 9 b is connected in series with the polysilicon resistor 9 c by a wiring 63. Further, the polysilicon resistor 9c is connected to a wiring 64 serving as a lead wiring.

  Thus, by connecting the polysilicon resistors 9a to 9c in series instead of in parallel, resistance elements having different resistance values can be formed. In order to connect the polysilicon resistors 9a to 9c in series, the polysilicon resistors 9a to 9c may be electrically connected by changing the wiring pattern as shown in FIG.

  Further, when only the polysilicon resistors 9a and 9b in FIG. 15 are connected in parallel, it is also possible to connect them by changing the wiring pattern as in the case of FIG. That is, in FIG. 15, the wiring 60a and the wiring 60b can be extended to the front of the polysilicon resistor 9c, and the wiring pattern can be formed so as not to be connected to the polysilicon resistor 9c.

  As described above, according to the third embodiment, it is possible to easily form resistance elements having various resistance values by using a method of changing the connection relation of a plurality of polysilicon resistors or using laser trimming. Further, similarly to the first embodiment, the area of the resistance element can be reduced by forming a plurality of polysilicon resistors on the well resistor via the insulating region.

(Embodiment 4)
In the fourth embodiment, an example will be described in which a well resistor and a plurality of polysilicon resistors formed on the well resistor are electrically connected to form a combined resistor.

  FIG. 17 is a plan view showing a resistance element according to the fourth embodiment. Since the configuration of the resistance element in the fourth embodiment is substantially the same as the configuration of the resistance element in the first embodiment, a different configuration will be described.

  In FIG. 17, one of the features of the resistance element in the fourth embodiment is that the well resistor 5 and a plurality of polysilicon resistors 9 a to 9 c formed on the well resistor 5 are connected in series by a wiring 65. There is in being. FIG. 18 is a cross-sectional view taken along line AA in FIG. As can be seen from FIG. 18, the well resistor 5 is connected to the wiring 65 through the plug 7a, and the wiring 65 is connected to the polysilicon resistor 9b through the plug 10a. Accordingly, it can be seen from FIGS. 17 and 18 that the well resistor 5 and the plurality of polysilicon resistors 9 a to 9 c are connected in series by the wiring 65. Thus, by connecting the well resistor 5 and the plurality of polysilicon resistors 9a to 9c in series, combined resistors having different resistance values can be formed.

  Further, the well resistance 5 tends to vary more than the plurality of polysilicon resistances 9a to 9c. Even in such a case, the plurality of polysilicon resistors 9a to 9c are used as resistance elements for adjusting the resistance value of the well resistor 5 by electrically connecting the well resistor 5 and the plurality of polysilicon resistors 9a to 9c. You can also In particular, the resistance value of the well resistor 5 can be adjusted to increase by connecting the well resistor 5 and the plurality of polysilicon resistors 9a to 9c in series as in the fourth embodiment.

  As shown in FIG. 19, the resistance value of the well resistor 5 can be further finely adjusted by cutting the wiring 65 and the wiring 11b connected to the polysilicon resistor 9c by laser trimming. As in FIGS. 15 and 16 of the third embodiment, only the polysilicon resistors 9a and 9b are added to the well resistor 5 by changing the wiring pattern of the wiring 65 and the wiring 11b instead of the laser trimming. It is also possible to connect them. That is, in FIG. 19, the wiring 65 and the wiring 11b are not arranged on the polysilicon resistor 9c, and the wiring pattern can be such that the polysilicon resistor 9c and the well resistor 5 are not connected.

  As described above, according to the fourth embodiment, a combined resistor can be easily formed by connecting a well resistor and a plurality of polysilicon resistors in series. In other words, it can be said that the resistance value of the well resistance can be adjusted to increase by connecting the well resistance and the plurality of polysilicon resistors in series. Further, similarly to the first embodiment, the area of the resistance element can be reduced by forming a plurality of polysilicon resistors on the well resistor via the insulating region.

(Embodiment 5)
In the fifth embodiment, an example will be described in which a well resistor and a plurality of polysilicon resistors formed on the well resistor are electrically connected to form a combined resistor.

  FIG. 20 is a plan view showing a resistance element according to the fifth embodiment. Since the configuration of the resistance element in the fifth embodiment is substantially the same as the configuration of the resistance element in the first embodiment, a different configuration will be described.

  In FIG. 20, one of the features of the resistance element in the fifth embodiment is that a well resistor 5 and a plurality of polysilicon resistors 9a to 9c formed on the well resistor 5 are connected in parallel by a wiring 66 and a wiring 67. There is in being connected to. FIG. 21 is a cross-sectional view taken along line AA in FIG. As can be seen from FIG. 21, the well resistor 5 is connected to the wiring 66 through the plug 7a, and the wiring 66 is connected to the polysilicon resistor 9b through the plug 10a. Similarly, the well resistor 5 is connected to the wiring 67 through the plug 7b, and the wiring 67 is connected to the polysilicon resistor 9b through the plug 10b. Therefore, it can be seen from FIGS. 20 and 21 that the well resistor 5 and the plurality of polysilicon resistors 9 a to 9 c are connected in parallel by the wiring 66 and the wiring 67. Thus, by connecting the well resistor 5 and the plurality of polysilicon resistors 9a to 9c in parallel, combined resistors having different resistance values can be formed.

  Further, the resistance value of the polysilicon resistor usually tends to be as small as about 1/10 as compared with the resistance value of the well resistor. Even in such a case, the well resistor 5 and the plurality of polysilicon resistors 9a to 9c are electrically connected to use the well resistor 5 as a resistance element for adjusting the resistance values of the plurality of polysilicon resistors 9a to 9c. You can also In particular, as in the fifth embodiment, by connecting the well resistor 5 and the plurality of polysilicon resistors 9a to 9c in parallel, the resistance values of the polysilicon resistors 9a to 9c can be adjusted to decrease. .

  Further, as shown in FIG. 22, the resistance value of the polysilicon resistor can be further finely adjusted by cutting the wirings 66 and 67 connected to the polysilicon resistor 9c by laser trimming. As in FIGS. 15 and 16 of the third embodiment and FIG. 19 of the fourth embodiment, the wiring pattern of the wiring 66 and the wiring 67 is changed to replace the well resistance 5 in place of the laser trimming. It is also possible to connect only the polysilicon resistors 9a and 9b. That is, in FIG. 22, the wiring 66 and the wiring 67 are not arranged on the polysilicon resistor 9c, and the wiring pattern can be such that the polysilicon resistor 9c and the well resistor 5 are not connected.

  As described above, according to the fifth embodiment, a combined resistor can be easily formed by connecting a well resistor and a plurality of polysilicon resistors in parallel. In other words, it can be said that the resistance value of the polysilicon resistor can be adjusted in a decreasing direction by connecting the well resistor and the plurality of polysilicon resistors in parallel. Further, similarly to the first embodiment, the area of the resistance element can be reduced by forming a plurality of polysilicon resistors on the well resistor via the insulating region.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, the example in which the well resistance formed of the n-type semiconductor region is formed inside the semiconductor substrate into which the p-type impurity is introduced is described. However, the p-type semiconductor region is introduced into the semiconductor substrate into which the n-type impurity is introduced. The present invention can also be applied to the case of well resistance.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a top view which shows the structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows the cross section cut | disconnected by the AA line of FIG. It is sectional drawing which shows the cross section cut | disconnected by the BB line of FIG. 1 is a plan view showing a configuration of a semiconductor device in Embodiment 1. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 6 is a plan view showing a configuration of a semiconductor device in a second embodiment. It is a top view which shows the structure of the semiconductor device in Embodiment 3, Comprising: It is a figure which shows the example which connected the some polysilicon resistance in parallel. It is a top view which shows the structure of the semiconductor device in Embodiment 3, Comprising: It is a figure which shows the example which cut | disconnected some wiring connected to a polysilicon resistance using laser trimming. It is a top view which shows the structure of the semiconductor device in Embodiment 3, Comprising: It is a figure which shows the example which connected several polysilicon resistance in series. FIG. 10 is a plan view showing a configuration of a semiconductor device in a fourth embodiment, and is a diagram showing an example in which a well resistor and a plurality of polysilicon resistors are connected in series. It is sectional drawing which shows the cross section cut | disconnected by the AA line of FIG. It is a top view which shows the structure of the semiconductor device in Embodiment 4, Comprising: It is a figure which shows the example which cut | disconnected some wiring connected to a polysilicon resistance using laser trimming. FIG. 10 is a plan view showing a configuration of a semiconductor device in a fifth embodiment, and shows an example in which a well resistor and a plurality of polysilicon resistors are connected in parallel. It is sectional drawing which shows the cross section cut | disconnected by the AA line of FIG. FIG. 10 is a plan view showing a configuration of a semiconductor device in a fifth embodiment, and shows an example in which a part of a wiring connected to a polysilicon resistor is cut using laser trimming.

Explanation of symbols

1A resistance region 1B resistance region 1C resistance region 2 insulating region 3 p-type semiconductor region 4 insulating region 5 well resistor 6a opening 6b opening 7a plug 7b plug 8a wiring 8b wiring 9a polysilicon resistance 9b polysilicon resistance 9c polysilicon resistance 10a Plug 10b Plug 11a Wiring 11b Wiring 12 Semiconductor substrate 13 Cobalt silicide film 14 Side wall 15 Insulating film 20 Semiconductor substrate 21 Element isolation region 22 Insulating region 23 Insulating region 24 p-type well 25 p-type semiconductor region 26 n-type well 27 Well resistance 28 Gate insulating film 29 Polysilicon film 30a Gate electrode 30b Gate electrode 31 Polysilicon resistor 32 Shallow n-type impurity diffusion region 33 Shallow p-type impurity diffusion region 34 Side wall 35 Deep n-type impurity diffusion region 36 Type semiconductor region 37 deep p-type impurity diffusion region 38 p-type semiconductor region 39 cobalt silicide film 40 silicon oxide film 41 contact hole 42a titanium / titanium nitride film 42b tungsten film 43 plug 44a titanium / titanium nitride film 44b aluminum film 44c titanium / nitride Titanium film 45 Wiring 50 Insulating region 51 P-type semiconductor region 52 Insulating region 53 Well resistor 54a Opening 54b Opening 55a Plug 55b Plug 56a Wiring 56b Wiring 57 Polysilicon resistor 58a Plug 58b Plug 59a Wiring 59b Wiring 60a Wiring 60b Wiring 61 Wiring 62 wiring 63 wiring 64 wiring 65 wiring 66 wiring 67 wiring

Claims (5)

(A) a semiconductor substrate;
(B) a first resistor comprising a semiconductor region formed inside the semiconductor substrate;
(C) an insulating region in which an insulating film is embedded in a groove formed on the first resistor;
(D) A semiconductor device comprising a plurality of second resistors made of a conductor film formed on the insulating region. (A) a semiconductor substrate;
(B) a first resistor comprising a semiconductor region formed inside the semiconductor substrate;
(C) an insulating region in which an insulating film is embedded in a groove formed on the first resistor;
(D) a plurality of second resistors made of a conductor film formed on the insulating region;
The semiconductor device, wherein the first resistor and the plurality of second resistors are connected in series. (A) a semiconductor substrate;
(B) a first resistor comprising a semiconductor region formed inside the semiconductor substrate;
(C) an insulating region in which an insulating film is embedded in a groove formed on the first resistor;
(D) a plurality of second resistors made of a conductor film formed on the insulating region;
The semiconductor device, wherein the first resistor and the plurality of second resistors are connected in parallel. (A) a semiconductor substrate;
(B) comprising a plurality of resistance regions formed in the semiconductor substrate;
In each region of the plurality of resistance regions,
(C1) a first resistor comprising a semiconductor region formed inside the semiconductor substrate;
(C2) an insulating region in which an insulating film is embedded in a groove formed on the first resistor;
(C3) A semiconductor device, wherein a plurality of second resistors made of a conductor film formed on the insulating region are formed. (A) a semiconductor substrate;
(B) a first resistance region formed in the semiconductor substrate;
(C) a second resistance region formed on the semiconductor substrate;
In the first resistance region,
(D1) a first resistor comprising a semiconductor region formed inside the semiconductor substrate;
(D2) a first insulating region in which an insulating film is embedded in a groove formed on the first resistor;
(D3) A plurality of second resistors made of a conductor film formed on the first insulating region are formed,
In the second resistance region,
(E1) a third resistor comprising a semiconductor region formed inside the semiconductor substrate;
(E2) a second insulating region in which an insulating film is embedded in a groove formed on the third resistor;
(E3) A semiconductor device, wherein one fourth resistor made of a conductor film formed on the second insulating region is formed.

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