JP2008071852A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accomplish functioning as a sidewall spacer, and to transfer the stress of a stress film to a channel region. <P>SOLUTION: This manufacturing method of a semiconductor device 3 having a first transistor 1 having a first-conductivity-type channel and a second transistor 2 having a second-conductivity-type channel on a semiconductor region 11 comprises: a process for partially removing one portion of the sidewall insulation film so that at least the lowermost layer of the sidewall insulation film used when forming extension regions 14p, 15p, 14n and 15n remains at a semiconductor region 11 at both sides of gate electrodes 13p, 13n in the first and second transistors 1, 2, and forming insulation films 25p, 25n for covering sidewalls of respective gate electrodes 13p, 13n and respective extension regions 14p, 15p, 14n, 15n; and a process for forming stress films 31p, 31n for applying stress to the semiconductor region 11 at lower portions of the respective gate electrodes 13p, 13p by covering the semiconductor region 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device in which stress is applied to a channel formation flow rate by a stress liner film.

  As a technology for improving the driving capability of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the method of improving the mobility by using the high stress (stress) of the liner silicon nitride (SiN) film is the mainstream as the advanced semiconductor technology for the 65nm generation and beyond. It is. The liner silicon nitride film is formed after the MOSFET and the salicide layer are formed, and an insulating film (hereinafter referred to as a stress film) having a high stress is formed above the sidewall spacer, whereby stress ( This is a technique for improving carrier mobility by applying a tensile stress or a compressive stress (see, for example, Patent Document 1 and Non-Patent Document 1).

  Therefore, how the stress is applied to the channel portion sensitively affects the shape of the insulating film from the channel to the stress film, and greatly depends on the width and shape of the gate electrode and the sidewall spacer. Therefore, optimization of the sidewall spacer formation method is important not only for the formation of the MOSFET and the salicide layer, but also for the purpose of efficiently applying the stress of the stress film to the channel region.

  However, the optimization of the sidewall spacer shape is the opposite of the direction of optimizing the MOSFET and diffusion resistance characteristics and the direction of optimizing the effective transmission of stress from the stress film. It is difficult to construct a process that effectively applies stress while optimizing characteristics such as off.

  In addition, when applied to a dual stress liner process for forming a stress film having an optimum stress for both nMOSFET and pMOSFET, it is necessary to match the formation of nMOSFET and pMOSFET, and it is difficult.

Here, a conventional process example using a stress film in the case where the sidewall spacer structure is a two-layer structure of SIN / SiO ₂ will be described with reference to the manufacturing process cross-sectional views of FIGS.

As shown in FIG. 11A, an element isolation region 161 for separating an nMOSFET formation region and a pMOSFET formation region is formed on a silicon substrate 111, and an nMOSFET formation region and a pMOSFET formation region on the silicon substrate 111 are formed. At the same time, gate electrodes 113n and 113p having a gate length Lmin = 40 nm are formed through the gate insulating film 112. Next, extension diffusion layer regions 114p and 115p having a junction depth Xj = 30 nm are formed on the silicon substrate 111 on both sides of the gate electrodes 113n and 113p, and extension diffusion layer regions 114n and 115n are formed in a separate process. To do. Next, a silicon oxide (SiO ₂ ) film 121 is formed to a thickness of 15 nm so as to cover the gate electrodes 113n and 113p, and then a silicon nitride (SiN) film 122 is formed to a thickness of 50 nm. Next, the entire surface of the silicon nitride film 122 and the silicon oxide film 121 is etched back to form sidewall spacers 124 and sidewall spacers 125 having a width of 50 nm. Thereafter, ion implantation for forming the source / drain regions is performed for each, and further heat treatment for activation is performed to form source / drain regions 116p, 117p and source / drain regions 116n, 117n having a junction depth Xj = 130 nm. To do.

Next, as shown in FIG. 11 (2), the salicide layer 118p, the source / drain regions 116p, 117p, the source / drain regions 116n, 117n, and the silicon on the gate electrodes 113p, 113n are exposed. 119p, salicide layers 118n, 119n, 120n and salicide layers 120p, 120n are formed. Thereby, the resistance of the source / drain regions 116p, 117p, the source / drain regions 116n, 117n, and the gate electrodes 113p, 113n can be reduced. In the salicide layer forming step, first, nickel is formed to a thickness of 9 nm, then RTA is performed at 350 ° C., a nickel silicide layer is formed, and an unreacted nickel layer is formed by wet etching with sulfuric acid (H ₂ SO ₄ ). Remove. Further, RTA is performed at 500 ° C. to change the layer and form a low resistance nickel silicide layer. Before forming nickel, it is preferable to remove the natural oxide film on the film formation surface by wet etching to expose the silicon surface.

  Next, as shown in FIG. 12C, as the stress film, a stress film 131n having a tensile stress of 1 GPa is formed in the nMOSFET formation region. In this film formation, a silicon nitride film having a tensile stress of 1 GPa is formed to a thickness of 70 nm, for example. Further, a silicon oxide film (not shown) is formed to a thickness of 15 nm.

  Next, as shown in FIG. 12D, the stress film 131n and the silicon oxide film (not shown) in the pMOSFET formation region are removed by etching while masking the stress film 131n only in the nMOSFET formation region. To do.

  Next, as shown in FIG. 13 (5), a stress film 131p having a compressive stress of 2 GPa is formed as a stress film in the pMOSFET formation region. In this film formation, a silicon nitride film having a compressive stress of 2 GPa is formed to a thickness of 70 nm, for example. Therefore, the nMOSFET formation region has a three-layer structure of a silicon nitride film having a tensile stress, a silicon oxide film, and a silicon nitride film having a compressive stress from the lower layer.

  Next, as shown in FIG. 13 (6), the stress film 131p is masked so as to leave only the pMOSFET formation region, and the stress film 131p in the nMOS region is removed using the underlying silicon oxide film as an etching stopper. At this time, the boundary portion between nMOS and pMOS (on the element isolation region 161) has a structure in which a stress film 131n that applies tensile stress and a stress film 131p that applies compressive stress overlap.

Next, a conventional process using a stress film when the nMOS sidewall spacer structure is a SIN / SiO ₂ two-layer structure and the pMOS sidewall spacer structure is a SiO ₂ / SiN / SiO ₂ three-layer structure. An example will be described with reference to the manufacturing process cross-sectional views of FIGS.

As shown in FIG. 14A, an element isolation region 161 for separating an nMOSFET formation region and a pMOSFET formation region is formed on a silicon substrate 111, and an nMOSFET formation region and a pMOSFET formation region on the silicon substrate 111 are formed. In addition, after forming gate electrodes 113n and 113p having a gate length Lmin = 40 nm through the gate insulating film 112, an extension having a junction depth Xj = 30 nm is formed on the silicon substrate 111 on both sides of the gate electrodes 113n and 113p. Diffusion layer regions 114p and 115p are formed, and extension diffusion layer regions 114n and 115n are formed in a separate process. Next, a silicon oxide (SiO ₂ ) film 121 is formed to a thickness of 10 nm so as to cover the gate electrodes 113n, 113p, etc., and then a silicon nitride (SiN) film 122 is formed to a thickness of 50 nm, Further, a silicon oxide (SiO ₂ ) film 123 is formed to a thickness of 30 nm.

  Next, the silicon oxide film 123 in the upper layer of the nMOSFET formation region is removed by etching using a resist mask. Next, the entire surface of the silicon oxide film 123, the silicon nitride film 122, and the silicon oxide film 121 is etched back, and the width formed of the silicon nitride film 122 and the silicon oxide film 121 on both sides of the gate electrode 113n in the nMOSFET formation region. A side wall spacer 124 of 50 nm is formed, and a side wall spacer 125 having a width of 70 nm made of a silicon oxide film 123, a silicon nitride film 122, and a silicon oxide film 121 is formed on both sides of the gate electrode 113p in the pMOS region. Thereafter, ion implantation for forming source / drain regions is performed, and further activation heat treatment is performed to form source / drain regions 116p, 117p and source / drain regions 116n, 117n having a junction depth Xj = 130 nm. This ion implantation (I / I) process is performed for each of the nMOSFET and the pMOSFET.

Next, as shown in FIG. 14 (2), the salicide layer 118p, the source / drain regions 116p, 117p, the source / drain regions 116n, 117n, and the gate electrodes 113p, 113n are exposed to the regions exposed to silicon. 119p, salicide layers 118n, 119n, 120n and salicide layers 120p, 120n are formed. Thereby, the resistance of the source / drain regions 116p, 117p, the source / drain regions 116n, 117n, and the gate electrodes 113p, 113n can be reduced. In the salicide layer forming step, first, nickel is formed to a thickness of 9 nm, then RTA is performed at 350 ° C., a nickel silicide layer is formed, and an unreacted nickel layer is formed by wet etching with sulfuric acid (H ₂ SO ₄ ). Remove. Further, RTA is performed at 500 ° C. to change the layer and form a low resistance nickel silicide layer. Before forming nickel, it is preferable to remove the natural oxide film on the film formation surface by wet etching to expose the silicon surface. In this salicide process, nMOSFET and pMOSFET are formed simultaneously.

  Next, as shown in FIG. 15C, a stress film 131n having a tensile stress of 1 GPa is formed as a stress film in the nMOSFET formation region. In this film formation, a silicon nitride film having a tensile stress of 1 GPa is formed to a thickness of 70 nm, for example. Further, a silicon oxide film (not shown) is formed to a thickness of 15 nm.

  Next, as shown in FIG. 15D, the stress film 131n and the silicon oxide film (not shown) in the pMOSFET formation region are removed by etching while masking the stress film 131n only in the nMOSFET formation region. To do.

  Next, as shown in FIG. 16 (5), a stress film 131p having a compressive stress of 2 GPa is formed as a stress film in the formation region of the pMOSFET. In this film formation, a silicon nitride film having a compressive stress of 2 GPa is formed to a thickness of 70 nm, for example. Therefore, the nMOSFET formation region has a three-layer structure of a silicon nitride film having a tensile stress, a silicon oxide film, and a silicon nitride film having a compressive stress from the lower layer.

  Next, as shown in FIG. 17 (6), the stress film 131p is masked so as to leave only the pMOSFET formation region, and the stress film 131p in the nMOS region is removed using the underlying silicon oxide film as an etching stopper. At this time, the boundary portion between nMOS and pMOS (on the element isolation region 161) has a structure in which a stress film 131n that applies tensile stress and a stress film 131p that applies compressive stress overlap.

Republished patent WO2002 / 043151 H.S. Yang, et al. "Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing" 2004 IEEE IEDM (International Electron Devices Meeting) 2004

  The problem to be solved is that the effect of applying the stress of the stress film to the channel region is reduced by the thickness of the side wall spacer. When the side wall spacer is made thinner, the extension region becomes shorter and the MOSFET characteristics are reduced. It leads to deterioration. In this way, optimization of transistor characteristics and optimization of effectively transmitting stress from the stress film conflict, so that stress can be effectively applied while optimizing characteristics such as roll-off of the threshold voltage Vth. It is a difficult point to give.

  An object of the present invention is to perform a function as a sidewall spacer and to effectively transmit stress of a stress film to a channel region.

  The present invention according to claim 1 is a semiconductor in which a first transistor having a first conductivity type channel and a second transistor having a second conductivity type channel opposite to the first conductivity type are formed on a semiconductor region. In the method of manufacturing an apparatus, a part of the sidewall insulating film is formed so that at least a lowermost layer of the sidewall insulating film used when forming the extension region is left in the semiconductor region on both sides of the gate electrode of each transistor. Removing and forming an insulating film covering the side walls of the gate electrodes and the extension regions; and a stress film for applying stress to the semiconductor regions under the gate electrodes and covering the semiconductor regions. And a forming step.

  In the present invention according to claim 1, since the insulating film formed so as to cover the gate electrode side wall and the extension region is formed by removing a part of the side wall insulating film, the side wall insulating film The extension region can be determined by forming the source / drain region before removing a part of the film, and the stress film is formed after removing the part of the sidewall insulating film. However, since the sidewall insulating film that inhibits the stress transmission of the stress film becomes thin and the stress film approaches the channel region, the stress of the stress film is easily transmitted to the channel region.

  According to the first aspect of the present invention, since the stress applied to the channel region can be increased without changing the MOSFET physical parameters, the performance can be improved due to the increase in mobility, so that the on-current (Ion) -off-current There is an advantage that the effect can be enhanced in (Ioff). In addition, the compatibility with the process of forming a stress film having different stresses on both the pMOSFET and the nMOSFET is good, and it is possible to obtain an effect on both the nMOSFET and the pMOSFET.

  An embodiment (first example) of the present invention according to claim 1 will be described with reference to the manufacturing process sectional views of FIGS.

  As shown in FIG. 1A, an element isolation region 61 for separating an nMOSFET formation region and a pMOSFET formation region is formed in a semiconductor region 11, and an nMOSFET formation region and a pMOSFET formation region on the semiconductor region 11 are formed. Then, the gate electrode 13p of the pMOSFET and the gate electrode 13n of the nMOSFET are formed through the gate insulating film 12. The semiconductor region 11 may be a bulk silicon substrate, a silicon layer of an SOI substrate, or a compound semiconductor substrate. Here, a silicon substrate will be described as an example. The gate electrode 13 is formed with a gate length Lmin = 40 nm, for example.

  Next, extension regions 14p and 15p are formed in the semiconductor region 11 on both sides of the gate electrode 13p. Extension regions 14n and 15n are formed in the semiconductor region 11 on both sides of the gate electrode 13n. The extension regions 14p and 15p and the extension regions 14n and 15n are formed in an impurity diffusion layer region having a junction depth Xj = 30 nm, for example, by ion implantation. As this impurity, an n-type impurity is used when forming an nMOSFET, and a p-type impurity is used when forming a pMOSFET.

Next, a first sidewall insulating film 21 is formed on the semiconductor region 11 so as to cover the gate electrodes 13p, 13n, etc. as a plurality of layers (for example, two layers) of sidewall insulating films, such as silicon oxide (SiO _2). ) And the second sidewall insulating film 22 is formed of, for example, a silicon nitride (SiN) film. The silicon oxide film is formed with a thickness of 10 nm, for example, and the silicon nitride film is formed with a thickness of 50 nm, for example. Next, the entire surface of the second sidewall insulating film 22 and the first sidewall insulating film 21 is etched back to form sidewall insulating films 24p and 24n on both sides of the gate electrodes 13p and 13n.

  Thereafter, ion implantation for forming source / drain regions is performed, and further heat treatment for activation is performed, and source / drain regions 16p, 17p having a higher concentration than the extension regions 14p, 15p and a junction depth Xj = 130 nm. Form. Further, source / drain regions 16n and 17n having a higher concentration than the extension regions 14n and 15n and a junction depth Xj = 130 nm are formed. This ion implantation (I / I) process is performed for each of the nMOSFET and the pMOSFET.

Next, as shown in FIG. 1B, by the salicide process, the source / drain regions 16p and 17p and the source / drain regions 16n and 17n are exposed to the regions where the silicon is exposed from the source / drain regions. Low-resistance conductor layers 18p, 19p, 18n, and 19n are formed, and conductor layers 20p and 20n that are lower in resistance than the gate electrodes 13p and 13n are formed in regions where the silicon on the gate electrodes 13p and 13n is exposed. Form. As a result, the resistance of the source / drain regions 16p, 17p, the source / drain regions 16n, 17n, and the gate electrodes 13p, 13n can be reduced. An example of this salicide process will be described. First, a metal layer for forming silicide is formed. As this metal layer, for example, nickel is formed to a thickness of 9 nm. Thereafter, RTA is performed at 350 ° C. to form a metal silicide layer. Next, when the metal is nickel, the unreacted nickel layer is removed by wet etching with sulfuric acid (H ₂ SO ₄ ). Further, RTA at 500 ° C. is performed to transfer the nickel silicide layer to form a low resistance nickel silicide layer. Before forming nickel, it is preferable to remove the natural oxide film on the film formation surface by wet etching to expose the silicon surface. In addition to nickel, the metal layer includes a refractory metal such as hafnium (Hf) and tantalum (Ta), and palladium (Pd), platinum (Pt), gold (Au), etc. 13p, 13n, source / drain regions 16p, 17p, and source / drain regions 16n, 17n can be made of a metal material whose resistance is reduced.

  Next, as shown in FIG. 2 (3), the pMOSFET formation region is covered with a resist mask 51, and the second sidewall insulating film 22 in the nMOSFET formation region isotropically etched (see FIG. 1 (1)). ] Is removed. This isotropic etching is performed, for example, by wet etching using hot phosphoric acid. As a result, an insulating film 25n made of the first sidewall insulating film 21 was formed so as to cover the sidewall of the gate electrode 13n and the extension regions 14n and 15n. As described above, by performing isotropic etching, it is possible to remove the other side wall insulating films so as not to damage the first side wall insulating film 21 of at least the lowermost layer of the base. Since the insulating film 25n is made of the first sidewall insulating film 21, it is formed as a thin film having a thickness of 10 nm on the side wall of the gate electrode 13n and the extension regions 14n and 15n. Thus, by forming the film with a uniform thickness, the film can be formed with the minimum necessary film thickness, and can be made thinner than the conventional sidewall spacer. Thereafter, the resist mask 51 is removed.

  Next, as shown in FIG. 2D, a stress film 31n having a tensile stress of 1 GPa is formed as a stress film on the semiconductor region 11 (on the nMOSFET formation region and the pMOSFET formation region). The stress film 31n is a plasma-silicon nitride film, for example, having a film thickness of 20 nm to 100 nm, preferably 50 nm to 70 nm, by a plasma CVD method at a film forming temperature of 400 ° C., for example. Further, a silicon oxide film (not shown) is formed to a thickness of 15 nm, for example.

  Next, as shown in FIG. 3 (5), a mask (not shown) is formed so as to leave the silicon oxide film and the stress film 31n only in the nMOSFET formation region. The stress film 31n and the stress film 31n are removed by etching.

  Next, as shown in FIG. 3 (6), the second sidewall insulating film 22 in the pMOSFET formation region [1 (1) shown in FIG. 1 (1)] isotropically etched using the mask (not shown). )]] Is removed. This isotropic etching is performed, for example, by wet etching using hot phosphoric acid. As a result, the insulating film 25p made of the first sidewall insulating film 21 was formed so as to cover the side wall of the gate electrode 13p and the extension regions 14p and 15p. As described above, by performing isotropic etching, it is possible to remove the other side wall insulating films so as not to damage the first side wall insulating film 21 of at least the lowermost layer of the base. Since the insulating film 25p is made of the first sidewall insulating film 21, it is formed as a thin film having a thickness of 10 nm on the side wall of the gate electrode 13p and the extension regions 14p and 15p. Thus, by forming the film with a uniform thickness, the film can be formed with the minimum necessary film thickness, and can be made thinner than the conventional sidewall spacer.

  Next, as shown in FIG. 4 (7), a stress film 31p having a compressive stress of 2 GPa is formed as a stress film on the entire surface. The stress film 31p is a plasma-silicon nitride film, for example, having a thickness of 20 nm to 100 nm, preferably 50 nm to 70 nm, by a plasma CVD method at a film forming temperature of 400 ° C., for example.

  Next, as shown in FIG. 5 (8), a mask (not shown) is formed so as to leave the silicon oxide film and the stress film 31p only in the pMOSFET formation region, and the silicon oxide film (nMOSFET formation region ( The stress film 31p and the stress film 31p are removed by etching. At this time, a boundary portion (on the element isolation region 61) between the nMOSFET and the pMOSFET has a structure in which a stress film 31n that applies tensile stress and a stress film 31p that applies compressive stress overlap.

  In this way, the semiconductor region 11 is provided with the insulating film 25n made of the thin sidewall insulating film 21 on the side wall of the gate electrode 13n and the extension regions 13n and 14n, and the first conductivity type (n Type) first transistor 1 and the first conductivity type including the insulating film 25p made of the thin sidewall insulating film 21 on the side wall of the gate electrode 13p and the extension regions 13p, 14p, and the stress film 31p being formed. A semiconductor device 3 including the second transistor 2 of the second conductivity type (p-type) which is a conductivity type is formed.

  In the first embodiment, since the second sidewall insulating film 22 that has been left as a conventional sidewall spacer is removed, the stress films 31p and 31n are formed in the semiconductor region 11 below the gate electrodes 13p and 13n. Thus, the stress applied to the channel portion can be made stronger than that of the conventional structure. In addition, since a special process is not required, consistency with the conventional process is good. In addition, since it is only necessary to form the sidewall insulating film in a plurality of layers and to remove a part of the sidewall insulating film, there are few process changes.

Next, an embodiment (second example) according to the method for manufacturing a semiconductor device of the present invention will be described with reference to the manufacturing process cross-sectional views of FIGS. The second embodiment is an example in which the sidewall spacer structure of the nMOSFET has a two-layer structure of SIN / SiO _{2 and} the sidewall spacer structure of the pMOSFET has a three-layer structure of SiO ₂ / SiN / SiO ₂ .

  As shown in FIG. 6A, an element isolation region 61 for separating an nMOSFET formation region and a pMOSFET formation region is formed in the semiconductor region 11, and the nMOSFET formation region and the pMOSFET formation region on the semiconductor region 11 are formed. Then, the gate electrode 13p of the pMOSFET and the gate electrode 13n of the nMOSFET are formed through the gate insulating film 12. The semiconductor region 11 may be a bulk silicon substrate, a silicon layer of an SOI substrate, or a compound semiconductor substrate. Here, a silicon substrate will be described as an example. The gate electrode 13 is formed with a gate length Lmin = 40 nm, for example.

  Next, extension regions 14p and 15p are formed in the semiconductor region 11 on both sides of the gate electrode 13p. Extension regions 14n and 15n are formed in the semiconductor region 11 on both sides of the gate electrode 13n. The extension regions 14p and 15p and the extension regions 14n and 15n are formed in an impurity diffusion layer region having a junction depth Xj = 30 nm, for example, by ion implantation. As this impurity, an n-type impurity is used when forming an nMOSFET, and a p-type impurity is used when forming a pMOSFET.

Next, a first sidewall insulating film 21 is formed on the semiconductor region 11 so as to cover the gate electrodes 13p, 13n, etc. as a plurality of layers (for example, two layers) of sidewall insulating films, such as silicon oxide (SiO _2). ), The second sidewall insulating film 22 is formed of, for example, a silicon nitride (SiN) film, and the third sidewall insulating film 23 is formed of, for example, a silicon oxide (SiO ₂ ) film. The silicon oxide film of the first sidewall insulating film 21 is formed with a thickness of, for example, 10 nm, the silicon nitride film of the second sidewall insulating film 22 is formed with a thickness of, for example, 50 nm, and the third sidewall insulating film is formed. The silicon oxide film of the film 23 is formed with a thickness of 30 nm, for example.

  Next, the third sidewall insulating film 23 in the nMOSFET formation region is removed by etching using a resist mask (not shown). Next, the entire surface is etched back from the third sidewall insulating film 23 to the first sidewall insulating film 21, and the second sidewall insulating film 22 and the first sidewall insulating film 21 are formed on both sides of the gate electrode 13n. A side wall insulating film 26n is formed, and a side wall insulating film 26p including the third side wall insulating film 23, the second side wall insulating film 22, and the first side wall insulating film 21 is formed on both sides of the gate electrode 13p. To do. As described above, the number of stacked side wall insulating films is different between the side wall insulating film 26n formed in the nMOSFET formation region and the side wall insulating film 26p formed in the pMOSFET formation region.

  Thereafter, ion implantation for forming the source / drain regions is performed, and further, an activation heat treatment is performed, and the source / drain regions 16p, 17p having a higher concentration than the extension regions 14p, 15p and a junction depth Xj = 130 nm. Form. Further, source / drain regions 16n and 17n having a higher concentration than the extension regions 14n and 15n and a junction depth Xj = 130 nm are formed. This ion implantation (I / I) process is performed for each of the nMOSFET and the pMOSFET.

  Next, as shown in FIG. 6 (2), by the salicide process, the source / drain regions 16p and 17p and the silicon on the source / drain regions 16n and 17n are exposed from the source / drain regions. Low-resistance conductor layers 18p, 19p, 18n, and 19n are formed, and conductor layers 20p and 20n that are lower in resistance than the gate electrodes 13p and 13n are formed in regions where the silicon on the gate electrodes 13p and 13n is exposed. Form. As a result, the resistance of the source / drain regions 16p, 17p, the source / drain regions 16n, 17n, and the gate electrodes 13p, 13n can be reduced.

An example of this salicide process will be described. First, a metal layer for forming silicide is formed. As this metal layer, for example, nickel is formed to a thickness of 9 nm. Thereafter, RTA is performed at 350 ° C. to form a metal silicide layer. Next, when the metal is nickel, the unreacted nickel layer is removed by wet etching with sulfuric acid (H ₂ SO ₄ ). Further, RTA at 500 ° C. is performed to transfer the nickel silicide layer to form a low resistance nickel silicide layer. Before forming nickel, it is preferable to remove the natural oxide film on the film formation surface by wet etching to expose the silicon surface. In addition to nickel, the metal layer includes a high melting point metal such as hafnium (Hf) and tantalum (Ta), and palladium (Pd), platinum (Pt), gold (Au), etc. 13p, 13n, source / drain regions 16p, 17p, and source / drain regions 16n, 17n can be made of a metal material whose resistance is reduced.

  Next, as shown in FIG. 7C, the formation region of the pMOSFET is covered with a resist mask 51, and the second sidewall insulating film 22 in the formation region of the nMOSFET is removed by isotropic etching. This isotropic etching is performed, for example, by wet etching using hot phosphoric acid. As a result, an insulating film 25n made of the first sidewall insulating film 21 was formed so as to cover the sidewall of the gate electrode 13n and the extension regions 14n and 15n. As described above, by performing isotropic etching, it is possible to remove the other side wall insulating films so as not to damage the first side wall insulating film 21 of at least the lowermost layer of the base. Since the insulating film 25n is made of the first sidewall insulating film 21, it is formed as a thin film having a thickness of 10 nm on the side wall of the gate electrode 13n and the extension regions 14n and 15n. Thus, by forming the film with a uniform thickness, the film can be formed with the minimum necessary film thickness, and can be made thinner than the conventional sidewall spacer.

  Next, as shown in FIG. 7 (4), a stress film 31n having a tensile stress of 1 GPa is formed as a stress film on the semiconductor region 11 (on the nMOSFET formation region and the pMOSFET formation region). The stress film 31n is a plasma-silicon nitride film, for example, having a film thickness of 20 nm to 100 nm, preferably 50 nm to 70 nm, by a plasma CVD method at a film forming temperature of 400 ° C., for example. Further, a silicon oxide film (not shown) is formed to a thickness of 15 nm, for example.

  Next, as shown in FIG. 8 (5), a mask (not shown) is formed so as to leave the silicon oxide film and the stress film 31n only in the nMOSFET formation region. The stress film 31n and the stress film 31n are removed by etching.

  Next, as shown in FIG. 8 (6), after forming a mask 52 covering the nMOSFET formation region, the third sidewall insulating film 23 and the second sidewall insulating film 23 in the pMOSFET formation region are formed by isotropic etching. The sidewall insulating film 22 (see FIG. 6A) is removed. The isotropic etching for removing the second sidewall insulating film 22 made of silicon nitride is performed by, for example, wet etching using hot phosphoric acid. As a result, the third sidewall insulating film 23 is also lifted off and removed. The removal of the third sidewall insulating film 23 made of silicon oxide can be separately performed by wet etching using, for example, hydrofluoric acid.

  As a result, an insulating film 25p made of the first sidewall insulating film 21 was formed so as to cover the sidewall of the gate electrode 13p and the extension regions 14p and 15p. As described above, by performing isotropic etching, it is possible to remove the other side wall insulating films so as not to damage the first side wall insulating film 21 of at least the lowermost layer of the base. Since the insulating film 25p is made of the first sidewall insulating film 21, it is formed as a thin film having a thickness of 10 nm on the side wall of the gate electrode 13p and the extension regions 14p and 15p. Thus, by forming the film with a uniform thickness, the film can be formed with the minimum necessary film thickness, and can be made thinner than the conventional sidewall spacer. Thereafter, the resist mask 52 is removed. When processing the stress film 31n, the resist mask 52 may be formed and used as an etching mask. Further, another etching mask may be formed in the etching process of the stress film 31n.

  Next, as shown in FIG. 9 (7), a stress film 31p having a compressive stress of 2 GPa is formed as a stress film on the entire surface. The stress film 31p is a plasma-silicon nitride film, for example, having a thickness of 20 nm to 100 nm, preferably 50 nm to 70 nm, by a plasma CVD method at a film forming temperature of 400 ° C., for example.

  Next, as shown in FIG. 10 (8), a mask (not shown) is formed so as to leave the silicon oxide film and the stress film 31p only in the pMOSFET formation region. The stress film 31p and the stress film 31p are removed by etching. At this time, a boundary portion (on the element isolation region 61) between the nMOSFET and the pMOSFET has a structure in which a stress film 31n that applies tensile stress and a stress film 31p that applies compressive stress overlap.

  In this way, the semiconductor region 11 is provided with the insulating film 25n composed of the thin sidewall insulating film 21 on the gate electrode 13n side wall and the extension regions 13n and 14n, and the first conductivity type (n Type) first transistor 1 and the first conductivity type including the insulating film 25p formed of the thin sidewall insulating film 21 on the side wall of the gate electrode 13p and the extension regions 13p and 14p, and the stress film 31p being formed. A semiconductor device 3 including the second transistor 2 of the second conductivity type (p-type) which is a conductivity type is formed.

  In the second embodiment, the third side wall insulating film 23 and the second side wall insulating film 22 that have been left as side wall spacers in the past have been removed, so that the stress films 31p and 31n are correspondingly removed from the gate electrodes 13p and 13n. Since it is possible to approach the channel region formed in the lower semiconductor region 11, the stress applied to the channel portion can be made stronger than that in the conventional structure. In addition, since a special process is not required, consistency with the conventional process is good. In addition, since it is only necessary to form the sidewall insulating film in a plurality of layers and to remove a part of the sidewall insulating film, there are few process changes.

It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 1st Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed 2nd Example which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed the 1st example of the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed the 1st example of the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed the 1st example of the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed the 2nd example of the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed the 2nd example of the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed the 2nd example of the manufacturing method of the conventional semiconductor device. It is manufacturing process sectional drawing which showed the 2nd example of the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... 1st transistor, 2 ... 2nd transistor, 3 ... Semiconductor device, 11 ... Semiconductor region, 13p, 13n ... Gate electrode, 14p, 15p, 14n, 15n ... Extension region, 16p, 17p, 16n, 17n ... Source Drain region, 25p, 25n ... insulating film, 31p, 31n ... stress film

Claims (4)

A method of manufacturing a semiconductor device, wherein a first transistor having a first conductivity type channel and a second transistor having a second conductivity type channel opposite to the first conductivity type are formed on a semiconductor region,
A part of the sidewall insulating film is removed so as to leave at least the lowest layer of the sidewall insulating film used when forming the extension region in the semiconductor region on both sides of the gate electrode of each transistor, and each gate electrode Forming an insulating film covering the side wall and each extension region;
Forming a stress film that covers the semiconductor region and applies a stress to the semiconductor region below each gate electrode. Forming a conductor layer on the gate electrode and the source / drain region of each transistor;
The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film serves as a mask for forming the conductor layer. Forming a conductor layer on the gate electrode and the source / drain region of each transistor;
The step of forming the insulating film by removing a part of the sidewall insulating film is performed immediately before the step of forming the conductor layer or immediately after the step of forming the conductor layer. 2. A method of manufacturing a semiconductor device according to 1. The step of forming the stress film includes a step of forming a first stress film for applying stress to the first transistor and a step of forming a second stress film for applying stress to the second transistor.
The step of forming the insulating film includes a step of forming a first insulating film on the first transistor and a step of forming a second insulating film on the second transistor.
After forming the first insulating film of the first transistor by removing a part of the sidewall insulating film of the first transistor before forming the first stress film,
Removing a part of the sidewall insulating film of the second transistor to form a second insulating film of the second transistor;
The method of manufacturing a semiconductor device according to claim 1, wherein the second stress film is formed thereafter.

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