JP2008067485A - Power supply input level switching circuit and mobile terminal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply input level switching circuit and a mobile terminal constructed, such that their numbers of components are reduced and their circuit scales are small to solve the problems associated with conventional power supply input level switching circuits, wherein they are large in number of components and in circuit scale and a problem arises when they are applied to electronic devices, such as cellular phones, whose circuit arrangement area is limited. <P>SOLUTION: The power supply level switching circuit 200 is of small-scale circuitry and comprises four components, an AND gate 201, resistors 202, 203, and a p-channel FET 204. The level of power supply to a load device 101 can be switched by this level switching circuit. When a trigger signal 150 is at the low level, the FET 204 is turned on and the resistor 203 is bypassed; thus, substantially the same potential as a power supply 100 is applied to the load device 101. When the trigger signal 150 transitions to the high level, the FET 204 is turned off. As a result, the potential from the power supply 100 is attenuated by the resistor 203 before it is applied to the load device 101,thus the potential level is reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply input level switching circuit and a portable terminal, and more particularly to a power supply input level switching circuit in an electronic device that constitutes a circuit on a substrate and a portable terminal such as a mobile phone provided with the power input level switching circuit.

  As shown in FIG. 5, in an electronic apparatus in which the power supply 100 is directly connected to the load device 101, when the input level of the power supply 100 to the load device 101 is controlled using an operation of a certain function as a trigger, generally by software Control is being made.

  However, when the switching control of the power input level of the load device 101 is performed by software, it is necessary to change the software specification when changing the control method or the like, which requires a lot of work labor. There is a problem of complication.

  In view of this, it is conceivable to reduce the work effort when changing the software specifications by using hardware control instead of the power input level switching control. A method of performing power supply input level switching control by hardware control has been conventionally known (see, for example, Patent Document 1 and Patent Document 2).

  In the above-mentioned Patent Document 1, the power supply potential is level-shifted to supply the ECL high-level potential to the first node, and the ECL low-level potential to the second node, and the CMOS level. First and second P-channel MOS transistors that are complementarily turned on and off in response to the input of the first node, and outputs the potential of the first node to the output terminal through the first P-channel MOS transistor. In a CMOS-ECL level conversion circuit including a level switching circuit that outputs the potential of the second node to an output terminal through a P-channel MOS transistor, a resistor is connected to the output terminal as a load device. In this CMOS-ECL level conversion circuit, when the input signal of the level switching circuit is a low level of the CMOS level, the first P-channel MOS transistor is turned on and the potential of the first node is output to the output terminal. A configuration is disclosed in which the second P-channel MOS transistor is turned on when the CMOS level is high, and the potential of the second node is output to the output terminal. The potential of the output terminal corresponding to the power supply potential of the load device is the level. Switching is controlled according to the input signal level of the switching circuit.

  Further, the above-mentioned Patent Document 2 discloses a bridge circuit that rectifies alternating current, a transformer that transforms and outputs a voltage rectified by the bridge circuit, and an auxiliary that outputs a detection voltage that varies in proportion to the output voltage of the transformer. A coil, an attenuation resistor that generates an attenuation detection voltage obtained by attenuating the detection voltage from the auxiliary coil, a selection switching circuit that selects one of the attenuation detection voltage and the detection voltage, and an attenuation detection voltage selected by the selection switching circuit or A power supply circuit having a configuration including an overvoltage protection circuit that determines an output voltage state based on a detection voltage and forcibly stops operation of the power supply circuit when an excessive output voltage is generated is disclosed. Depending on the level of the detection voltage that is the input signal of the circuit, the potential (power supply potential) supplied from the selection switching circuit to the control IC that is the load device is attenuated or attenuated. It is switched controlled to no detection voltage.

JP-A-5-335498 Japanese Patent No. 3338309

  However, since the power input level switching circuits described in Patent Document 1 and Patent Document 2 do not use software for switching control of the power input level, the work effort when changing the software specifications can be reduced. There is a problem that the configuration has a large number of parts and the circuit scale is large. The problem that the circuit scale is large is particularly a problem when applied to an electronic device in which the circuit area such as a mobile phone is limited to a small size.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a power input level switching circuit and a portable terminal having a small number of parts and a small circuit scale.

  To achieve the above object, according to a first aspect of the present invention, there is provided a power supply input level switching circuit for switching a power supply input level applied to a load device, an attenuation element connected between the power supply and the load device, and attenuation when turned on. When the switch is turned off, the switching element that lowers the power input level to the load device and the power supply and the binary trigger signal are input and the logical operation result is switched. And a logic circuit that controls the switching element to be turned on or off by supplying the element as a switching signal.

  In this invention, since the switching element can be controlled to be turned on or off according to the logical value of the trigger signal, the power input level of the load device can be switched according to the logical value of the trigger signal.

  In order to achieve the above object, the second invention is characterized in that the switching element in the first invention is a P-channel field effect transistor, and its drain and source are connected in parallel to the attenuating element. And Further, the logic circuit may be an AND gate or a NAND gate.

  In order to achieve the above object, the present invention provides a source / source of a P-channel field effect transistor in which the source is connected to the connection point of the power source and the attenuating element and the gate is connected to the output terminal of the logic circuit. An attenuation element for guaranteeing operation is connected between the gates. In the present invention, when the output of the AND gate or NAND gate is not guaranteed, the high level output potential of the AND gate or NAND gate is not the same as the source potential of the P channel field effect transistor. The operation can be guaranteed by complementing the potential of the gate of the effect transistor.

  According to the present invention, the trigger signal is a driving voltage of the first device, and the load device is a second device. In the present invention, the power input level of the load device can be lowered using the drive voltage of the first device as a trigger signal.

  In order to achieve the above object, the present invention uses a trigger signal as a driving voltage for a microphone of a portable terminal, a load device as a key backlight for the portable terminal, and when a driving voltage for the microphone is applied, The switching element is turned off by the switching signal to reduce the luminance of the key backlight. According to the present invention, the luminance of the key backlight can be reduced when the driving voltage of the microphone of the portable terminal is applied, that is, when the microphone is used.

  In order to achieve the above object, the portable terminal of the present invention transmits a transmission voice signal collected by a microphone to a partner terminal, receives a reception voice signal from the partner terminal, and receives a reception voice from a speaker. A key backlight for enhancing the visual effect of a plurality of keys by emitting light from the back side to a plurality of translucent keys for input / output processing of desired information as well as a calling function for sounding In the portable terminal equipped, the attenuation element connected between the power supply and the power terminal of the key backlight, and the attenuation element is bypassed when turned on, and the voltage drop due to the attenuation element when turned off, to the key backlight When the microphone drive voltage is input, the switching element is turned off based on the logical operation result between the power supply and the microphone drive voltage. When the driving voltage is not input is characterized by having a logic circuit for turning on the switching elements based on the logical operation result of the power supply and the microphone of the drive voltage non Input level.

  In the present invention, when the microphone is not used, the switching element is turned on, and the power level is directly input from the power source to the key backlight. Therefore, the key backlight can be caused to emit light at a predetermined brightness. When using the switch, the switching element is turned off, and the key backlight is supplied with a voltage obtained by reducing the power level from the power supply by the voltage drop of the attenuating element, thus reducing the brightness of the key backlight and reducing power consumption. can do.

  According to the present invention, at least an attenuation element connected between a power supply and a load device, a switching element connected in parallel to the attenuation element, and a logic circuit for controlling the switching element on or off are provided. The power input level to the load device can be switched with a hardware configuration that has an extremely small number of parts, so the power input level can be switched with a smaller circuit configuration than before, and the power input level to the load device By reducing the power consumption, you can expect effects such as noise reduction by reducing current consumption and radiated power from the load device, and switching control of the power input level is not performed by software, so work when changing software specifications Labor can be eliminated.

  In addition, according to the present invention, the power input level can be switched with a small circuit configuration, and therefore, it is particularly suitable for application to a portable terminal having a limited circuit mounting area. Low power consumption can be realized by lowering the brightness of.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a circuit diagram of an embodiment of a power input level switching circuit according to the present invention. In the figure, a power supply input level switching circuit 200 includes a two-input AND gate 201 to which a power supply (power supply voltage) 100 and a trigger signal 150 are applied, resistors 202 and 203, and a gate as an output terminal of the AND gate 201. A P-channel field effect transistor (FET) 204 having a source connected to the connection point between the resistors 202 and 203 and the power supply 100 and a drain connected to the connection point between the resistor 203 and the load device 101. It is configured. The power supply 100 is connected to the load device 101 via a resistor 203 in series, and the resistor 202 is connected between the source and gate of the FET 204.

  Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. As shown in FIG. 2A, the trigger signal 150 is assumed to change from a low level to a high level at time t1. Here, the trigger signal 150 being at a low level means a case where the trigger signal 150 is within the range of the low level input of the AND gate 201, and the trigger signal 150 being at a high level means the threshold of the high level input of the AND gate 201. It is defined as the case where it exceeds. The power supply 100 is at a high level that exceeds the high level input threshold of the AND gate 201.

  When the trigger signal 150 is at a low level as shown at time t0 in FIG. 2A, one of the two inputs of the AND gate 201 is at a low level, so that the AND gate as shown in FIG. The output signal 201 becomes a low level. When the output signal of the AND gate 201 is at a low level, the potential difference between the source and gate of the P-channel FET 204 becomes larger than the threshold value, so that the P-channel FET 204 is turned on and the source and drain are energized.

  Therefore, the resistor 203 is bypassed by the P-channel FET 204, and the power source 100 is input to the load device 101 through the source and gate of the P-channel FET 204 without passing through the resistor 203. The operation is equivalent. At this time, the power input level of the load device 101 becomes a high level as shown in FIG.

  At this time, current leakage occurs in the path of the AND gate 201 from the power source 100 through the resistor 202. Therefore, the resistor 202 is set to a sufficiently large resistance value (for example, about 100 kΩ to 1 MΩ) as a countermeasure. ing.

  Next, it is assumed that the trigger signal 150 becomes high level at time t1 as shown in FIG. In this case, since both the two inputs of the AND gate 201 are at a high level, the output signal of the AND gate 201 becomes a high level at time t1, as shown in FIG. Further, since the driving power supply of the AND gate 201 is the same potential as the source voltage of the P-channel FET 204, the output level of the AND gate 201 is also substantially the same potential as the source voltage of the P-channel FET 204. In this case, since the potential between the source and the gate of the P-channel FET 204 is substantially the same, the P-channel FET 204 is turned off and the source and the drain are cut off.

  As a result, the power supply 100 is attenuated by the resistor 203 and then applied to the load device 101. Accordingly, the power input level of the load device 101 is lower than that before time t1, as shown in FIG. Here, for example, when the power supply 100 is 10 V, the current consumption of the load device 101 is 500 mA, and the resistance value of the resistor 203 is 10Ω, a voltage drop of 5 (= 10 × 0.5) V is generated by the resistor 203. Therefore, 5 (= 10−5) V is applied to the load device 101. That is, the power input level of the load device 101 is 5V lower than before time t1.

  Actually, in the above case, the power supply input level of the load device 101 is set to the parallel combined resistance value of the resistance value of the resistor 203 and the resistance between the source and drain of the P-channel FET 204 when off from the power supply 100. Although the voltage drop is reduced by the voltage drop multiplied by the supplied current, the resistance between the source and the drain of the P-channel FET 204 at the off time is extremely large. Therefore, in the above calculation, the resistance between the source and the drain of the P-channel FET 204 at the off time is calculated. Is ignored.

  Note that when the trigger signal 150 is at a high level, the output signal level of the AND gate 201 becomes the same potential as the source voltage of the P-channel FET 204, but there are cases where it does not become the same potential depending on the output characteristics of the AND gate 201. In this case, a potential difference is generated between the source and gate of the P-channel FET 204, the source and drain are not insulated, and the output from the power supply 100 does not pass through the resistor 203, so the input level to the load device 101 is designed. Does not switch to the street. As a countermeasure, the resistor 202 is inserted to supplement the potential of the gate of the P-channel FET 204 to assure operation.

  As described above, according to the present embodiment, the input voltage switching to the load device 101 is smaller than the conventional one consisting of only four parts, that is, the AND gate 201, the resistors 202 and 203, and the P-channel FET 204. Since it can be performed depending on the circuit scale, it does not require a relatively large mounting area, and is particularly suitable for application to an electronic device having a limited mounting area such as a mobile phone. Further, by reducing the input voltage to the load device 101, it is possible to expect effects such as noise reduction by reducing current consumption and reducing radiated power from the load device 101.

  Next, another embodiment of the present invention will be described. FIG. 3 shows a circuit diagram of another embodiment of the power input level switching circuit according to the present invention. In the figure, the same components as those in FIG. In the embodiment shown in FIG. 3, the power input level switching circuit 210 has a two-input NAND gate 211 to which a power supply (power supply voltage) 100 and a trigger signal 160 are applied, resistors 202 and 203, and the gate is a NAND gate 211. A P-channel FET 204 having a source connected to a connection point between the resistors 202 and 203 and the power supply 100 and a drain connected to a connection point between the resistor 203 and the load device 101. ing. The power supply 100 is connected to the load device 101 via a resistor 203 in series, and the resistor 202 is connected between the source and gate of the FET 204. That is, the power input level switching circuit 210 of the present embodiment is characterized in that a NAND gate 211 is provided in place of the AND gate 201 as compared with the power input level switching circuit 200 of FIG.

  Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. As shown in FIG. 4A, the trigger signal 160 changes from a high level to a low level at time t10. Here, the trigger signal 160 being at the low level means that the signal is within the range of the low level input of the NAND gate 211, and the trigger signal 160 being at the high level means the threshold value of the high level input of the NAND gate 211. It is defined as the case where it exceeds. The power supply 100 is at a high level that exceeds the high level input threshold of the NAND gate 211.

  When the trigger signal 160 is at a high level as shown at time t10 in FIG. 4 (A), both the two inputs of the NAND gate 211 are at a high level, so that the NAND gate as shown in FIG. 4 (B). The output signal 211 is at a low level. When the output signal of the NAND gate 211 is at a low level, the potential difference between the source and gate of the P-channel FET 204 becomes larger than the threshold value, so that the P-channel FET 204 is turned on and the source and drain are energized.

  Therefore, the resistor 203 is bypassed by the P-channel FET 204, and the power source 100 is input to the load device 101 through the source and gate of the P-channel FET 204 without passing through the resistor 203. The operation is equivalent. At this time, the power input level of the load device 101 becomes a high level as shown in FIG.

  Next, it is assumed that the trigger signal 160 becomes low level at time t11 as shown in FIG. In this case, since one of the two inputs of the NAND gate 211 is at a low level, the output signal of the NAND gate 211 becomes a high level at time t11 as shown in FIG. 4B. Further, since the driving power supply of the NAND gate 211 is the same potential as the source voltage of the P-channel FET 204, the output level of the NAND gate 211 is also substantially the same potential as the source voltage of the P-channel FET 204. In this case, since the potential between the source and the gate of the P-channel FET 204 is substantially the same, the P-channel FET 204 is turned off and the source and the drain are cut off.

  As a result, the power supply 100 is attenuated by the resistor 203 and then applied to the load device 101. Therefore, as shown in FIG. 4C, the power input level of the load device 101 is lower than before time t11.

  As described above, according to the present embodiment, as in the embodiment of FIG. 1, input voltage switching to the load device 101 is performed only at four points of the NAND gate 211, the resistors 202 and 203, and the P-channel FET 204. Therefore, the mounting area is relatively small and it is particularly suitable for application to an electronic device having a limited mounting area such as a mobile phone. Further, by reducing the input voltage to the load device 101, it is possible to expect effects such as noise reduction by reducing current consumption and reducing radiated power from the load device 101.

  1 and 3, when the trigger signals 150 and 160 are the drive voltages of a certain device A, the power input level to the other device B can be switched by this drive voltage. . As a result, reduction of current consumption and noise reduction by suppressing the radiated power from the device B can be expected. As an example of the above, for example, it is conceivable to lower the luminance by lowering the power input level of the key backlight using the drive voltage of the microphone of the mobile phone as a trigger signal.

  In other words, it has a call function that transmits a transmitted voice signal collected by a microphone to a partner terminal, receives a received voice signal from the partner terminal and generates a received voice from a speaker, and inputs / outputs desired information In a mobile phone having a key backlight for irradiating light from the back side to a plurality of translucent keys for improving the visual effect of the plurality of keys, a power source and a power terminal of the key backlight, When the microphone is not used, the microphone drive voltage is not input, the P-channel FET 204 is turned on, and a predetermined power supply level is supplied to the key backlight so that the key backlight is Light emitting operation is performed with brightness, but when using a microphone, the microphone backlight is applied and the P-channel FET 204 is turned off to darken the key backlight. Reduction of current consumption by the key backlight when using the microphone can be expected.

  The present invention is not limited to the above embodiment. For example, in each of the above embodiments, the resistor 203 is used as an attenuation element, but other elements (such as a diode) are used. Realization is also possible. If the output characteristics of the AND gate 201 and the NAND gate 211 shown in FIGS. 1 and 3 are guaranteed, the resistor 205 can be omitted. The present invention can be applied not only to mobile phones but also to portable terminals having portability such as notebook computers, PDAs, car navigation systems, and the like. Further, although a P-channel FET is used as a switching element, a bipolar transistor can also be used.

It is a circuit diagram of one embodiment of the present invention. 2 is a timing chart for explaining the operation of FIG. 1. It is a circuit diagram of other embodiments of the present invention. 4 is a timing chart for explaining the operation of FIG. 3. It is a block diagram of an example of the conventional power supply input level switching circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Power supply 101 Load device 150,160 Trigger signal 200,210 Power supply input level switching circuit 201 AND gate 202,203 Resistor 204 P channel type field effect transistor (FET)
211 NAND gate

Claims (7)

In the power input level switching circuit that switches the power input level applied to the load device,
An attenuating element connected between a power source and the load device;
A switching element that bypasses the attenuating element when on, and a voltage drop due to the attenuating element when off, lowering the power input level to the load device; and
And a logic circuit that inputs the power supply and a binary trigger signal, supplies a logical operation result thereof as a switching signal to the switching element, and controls the switching element to be turned on or off. Input level switching circuit.   2. The power input level switching circuit according to claim 1, wherein the switching element is a P-channel field effect transistor, and a drain and a source of the switching element are connected in parallel to the attenuation element.   2. The power input level switching circuit according to claim 1, wherein the logic circuit is an AND gate or a NAND gate.   Attenuation for guaranteeing operation between the source and gate of the P-channel field effect transistor having a source connected to a connection point between the power source and the attenuating element and a gate connected to an output terminal of the logic circuit 4. The power input level switching circuit according to claim 2, wherein elements are connected.   5. The power input level switching circuit according to claim 1, wherein the trigger signal is a drive voltage of a first device, and the load device is a second device. 6.   The trigger signal is a driving voltage of a microphone of a portable terminal, the load device is a key backlight of the portable terminal, and when the driving voltage of the microphone is applied, the switching signal is generated by a switching signal from the logic circuit. 5. The power input level switching circuit according to claim 1, wherein the element is turned off to reduce the luminance of the key backlight. 6. A transmission function that transmits a transmission voice signal collected by a microphone to a partner terminal, receives a reception voice signal from the partner terminal, and generates a reception voice from a speaker, and performs input / output processing of desired information. In a portable terminal equipped with a key backlight for irradiating light from the back side to a plurality of translucent keys for enhancing the visual recognition effect of the plurality of keys,
An attenuating element connected between a power source and a power terminal of the key backlight;
A switching element that bypasses the attenuating element when on, and a voltage drop due to the attenuating element when off, reducing the power input level to the key backlight; and
When the driving voltage of the microphone is input, the switching element is turned off based on a logical operation result between the power source and the driving voltage of the microphone, and when the driving voltage of the microphone is not input, the power source and the microphone A mobile terminal comprising: a logic circuit that turns on the switching element based on a logical operation result with a level when no drive voltage is input.

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