JP2008067349A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide adjusting power consumption each time during calculation processing to be fixed, regardless of the input data value. <P>SOLUTION: An IC card chip (1) includes an encryption co-processor (7) performing an encryption algorithm using an encryption key and encrypting secret information. The encryption coprocessor includes a two-wire/two-phase coding circuit (20), and a two-wire/two-phase system combination logic circuit (22) having a plurality of two-wire/two-phase system logic circuits (70). The two-wire/two-phase coding circuit converts input data (SI) by using one-wire/one-phase as a unit of one bit to a two-wire/two-phase code defining a logic value 1 (1, 0) or logic value 0 (0, 1) that is assumed as valid data, only during the period of changing from a halt phase, in which a clear (1, 1) that is invalid data inputs to all input connectors to an active phase in which valid data inputs to the all connectors. The two-wire/two-phase system logic circuit inverts a logic value input to an input connector with constant times through a predetermined logic function and delivers valid data to an output connector. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and relates to a semiconductor integrated circuit using a two-wire two-phase logic circuit that enables protection of secret information against eavesdropping of secret information using leakage signals such as power consumption and electromagnetic waves. It is related to effective technology.

  Without physically destroying the encryption key necessary to encrypt the secret information from the encryption circuit that encrypts or decrypts the secret information built in the smart card or the electronic device that holds the secret The method of taking out is known. As this method, for example, there is a differential power analysis (DPA) disclosed in Non-Patent Document 1. DPA is a kind of attack method for estimating an encryption key by utilizing the fact that there is a correlation between input data and power consumption associated with encryption processing.

  In an encryption method such as DES (Data Encryption Standard) or AES (Advanced Encryption Standard) in which the encryption operation F is known, the ciphertext O is expressed as O = F (I , K). Therefore, when there is a correlation between the ciphertext O and the power consumption W and the input plaintext I is known, the estimated value of the encryption key K to be obtained is all the values that the encryption key estimate K ′ can take. A correlation value between F (I, K ′) and power consumption W is calculated for K ′, and K ′ giving the largest correlation value can be obtained.

  The power analysis attack is a kind of DPA, and is made possible by the correlation between the value of the input data input to the arithmetic device and the power consumption generated in the arithmetic processing for the value of the input data. One factor that allows the encryption key to be estimated by a power analysis attack is that the encryption circuit is composed of a logic circuit using a logic element composed of a CMOS (Complementary Metal Oxide Semiconductor) with a pMOS transistor and an nMOS transistor as a pair. There is to be.

  The power consumption of a logic element composed of CMOS will be described using the simplest negative logic element. In a negative logic element composed of CMOS, the power supply line VDD is normally connected to the source terminal of the pMOS transistor, the ground line GND is connected to the source terminal of the nMOS transistor, and the input signal line VIN is the gate of the pMOS transistor and the nMOS transistor. The output signal line VOUT is connected to the drain terminals of the pMOS transistor and the nMOS transistor. The output signal line VOUT is normally connected to the input signal line VIN of the next logic element. Here, in order to simplify the description of the operation of a single negative logic element, a capacitor C equivalent to the gate is connected to the output signal line VOUT, and an electrode on one side of the capacitor C is connected to the ground line GND.

  When the input signal line VIN is displaced from High (or 1) to Low (or 0), the pMOS transistor becomes conductive between the source terminal and the drain terminal, and the nMOS transistor becomes nonconductive. A current flows from the power supply line VDD to the output signal line VOUT, and charges are accumulated in the capacitor C. As the charge is accumulated, the potential of the output signal line VOUT becomes High. If the input signal line VIN is kept in a high state as it is, the charge accumulation in the capacitor C exceeds an allowable amount, the charge accumulation stops, no current flows, and the potential of the output signal line VOUT is kept in the high state.

  When the input signal line VIN is displaced from Low to High, the nMOS transistor is in a conductive state between the source terminal and the drain terminal, and the pMOS transistor is in a non-conductive state. The electric charge accumulated in the capacitor C is discharged to the ground line GND through the source terminal and the drain terminal of the nMOS transistor. A current flows by releasing the electric charge. As the charge is discharged, the potential of the output signal line VOUT becomes Low. If the input signal line VIN is kept in a high state as it is, the electric charge disappears and no current flows, and the potential of the output signal line VOUT is kept low.

  As described above, in the logic element configured by CMOS, current is accumulated only when charge accumulation and discharge of the capacitor C occur, that is, when the potential of the output signal line VOUT changes from High to Low and from Low to High. Flow power is consumed. As long as the potential of the output signal line VOUT does not change, no electric power is consumed because there is no change in the charge of the capacitor C. Further, in the logic element, one signal line is usually represented as one bit, and the potential when the signal line is High is defined as a logical value 1, and the potential when the signal line is Low is defined as a logical value 0. For this reason, there is a correlation between the change in the logic value generated in the output signal lines of all the logic elements and the power consumption. That is, the arithmetic circuit using the logic element has a risk that the encryption key is easily estimated by DPA such as a power analysis attack.

  Patent Documents 1 and 2 use a two-wire two-phase code that is known to keep power consumption generated in arithmetic processing for data input to an arithmetic circuit constant in order to obtain high safety against DPA. A technique for performing arithmetic processing is disclosed.

Special table 2003-521201 gazette JP 2004-347975 A P. Kocher, J. Jaffe, and B. Jun, Differential Power Analysis, CRYPTO '99, LNCS1666, pp. 388-397,1999

  In a logic circuit composed of CMOS, a delay occurs between the time when the input value is determined by the load capacitance of the wiring connected to the output signal line and the time when the output value for the input is determined. For this reason, when a two-wire two-phase logic circuit using a two-wire two-phase code is configured with CMOS, the two-wire two-phase logic circuit outputs two signal lines and differs for each signal line. Since it has a load capacity, a difference occurs between the delay times of the two signal lines. For example, in a two-wire two-phase logic circuit, the two-wire two-phase code is cleared (1, 1), the logical value 0 (0, 1), and the logical value 1 (1, 0) are held, and the delay difference In the case where there is, there is a difference in the time when the output changes from the clear value to the logical value of either logical value 0 or logical value 1 after the logical value of the input is determined. That is, in the two-wire two-phase logic circuit, there is a difference in the time at which the logical values of the two signal lines change when the output is a logical value 0 and a logical value 1, and as a result, there is a difference in the time at which power is generated. Therefore, a difference occurs in the power consumption pattern with respect to the input value. In this case, the encryption key is easily estimated by the power analysis attack, and the security is lowered. The present inventor has found that it is necessary to make the correlation between the value of input data and power consumption extremely small in order to obtain high security against DPA such as a power analysis attack.

  On the other hand, Patent Document 1 discloses a logical operation circuit using a two-wire two-phase code, but describes a configuration necessary for reducing the correlation between the value of input data and power consumption. Absent. Further, in Patent Document 2, it is necessary to provide a latch circuit using a synchronization signal for input / output of each logical operation circuit, which causes a problem that the circuit scale increases and power consumption increases.

  Furthermore, the present inventor has found that the timing at which the output data of the two-wire two-phase logic circuit that performs the logical operation corresponding to the two-wire two-phase code changes in logic may cause a difference due to wiring delay or the like. . In other words, there is a case where it is not possible to realize equal length and equal capacity of the wiring in the LSI placement and wiring. For example, when the wiring lengths of the two signal lines of the output connector of the two-wire two-phase logic circuit are different, a difference occurs in the load capacity due to the wiring, and the charge / discharge current amount in the transistor is different. Since a plurality of 2-wire 2-phase logic circuits are cascade-connected in order to realize a desired logic operation, the next-stage 2-wire logic circuit is determined by the difference in the amount of current generated in the previous 2-wire 2-phase logic circuit. A difference occurs in the transient change of the voltage level applied to the two signal lines of the input connector of the two-phase logic circuit, and a difference occurs in the time when the transistor is turned on / off. As a result, the next-stage two-wire two-phase logic circuit has a problem in that the timing at which the input data logically changes varies depending on the wiring delay, resulting in a difference in the timing at which the output data logically changes. In this way, the present inventor has found that there is a need to make the correlation between the value of the input data and the power consumption extremely small even when the timing of the logical change of the input data is different.

  An object of the present invention is to provide a semiconductor integrated circuit using a two-wire two-phase logic circuit capable of keeping power consumption at each time during arithmetic processing regardless of the value of input data.

  Another object of the present invention is to provide a semiconductor integrated circuit using a two-wire two-phase logic circuit that can reduce power consumption without increasing the circuit scale.

  Still another object of the present invention is to provide a semiconductor integrated circuit using a two-wire two-phase logic circuit that makes it difficult to form a power consumption pattern for the value of the input data even when the timing at which the input data logically changes is different. Is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the 2-wire 2-phase logic circuit included in the 2-wire 2-phase combinational logic circuit, valid data is input to all input connectors from the idle phase in which clear, which is invalid data, is input to all input connectors. Only when the operation phase is changed, the logical value input to the input connector is inverted a predetermined number of times by a predetermined logical function to determine valid data in the output connector. As a result, until valid data is obtained for all input connectors, valid data is not confirmed for the output connector, and valid data is confirmed after a fixed number of toggles regardless of the logical value input to the input connector. Therefore, the power consumption at each time during the arithmetic processing can be made constant regardless of the value of the input data.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  Regardless of the value of the input data, the power consumption at each time during the arithmetic processing can be made constant. Further, power consumption can be reduced without increasing the circuit scale.

1. Representative Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  A semiconductor integrated circuit according to a representative embodiment of the present invention includes a processor (7) that executes an encryption algorithm using an encryption key and encrypts desired secret information. The processor includes a two-wire two-phase encoding circuit (20) and a two-wire two-phase combinational logic circuit (22). The two-wire two-phase encoding circuit converts the input data (SI) using the one-wire one-phase code, which is the secret information, into a first signal (1,0) indicating a logical value 1 in bit units, The data is converted into data (DRI0, DRI1) using a two-wire two-phase code that defines the second signal (0, 1) indicating the value 0. The two-wire two-phase combinational logic circuit includes a plurality of two-wire two-phase logic circuits (70) that perform a logical operation corresponding to the two-wire two-phase code, and encrypts the input data. The two-wire two-phase logic circuit includes a plurality of input connectors ((a0, a1), (b0, b1)) including a first signal line and a second signal line corresponding to the two-wire two-phase code. And output connectors (q0, q1). The two-wire two-phase logic circuit is configured so that the first signal or the second signal is supplied to all the input connectors from the initial state where the clear signal (1, 1) that is invalid information is input to all the input connectors. Only when a transition is made to a valid state in which the input signal is input, the logic value input to the input connector is inverted a predetermined number of times by a predetermined logic function, and the first signal or the second signal is output to the output connector. To do. In this specification, an input connector means an input terminal, and an output connector means an output terminal.

  As described above, in the two-wire two-phase logic circuit, the first signal or the second signal that is valid information is input to the initial state in which the clear signal that is invalid information is input to all the input connectors. When valid information is obtained for all the input connectors, valid information that is a calculation result of the logical function is determined in the output connector. In other words, when valid information is input to the input connector, even if there is a delay difference, valid information is determined for the output connector until valid information is available for all input connectors. Without changing, the clear signal is still input. This means that even when valid information is input to the input connector with a delay difference, there is no difference in the time at which the logical value of the output connector changes. There is no difference in the time when the power consumption associated with.

  Further, in the two-wire two-phase logic circuit, valid information determined by the output connector can be obtained by inverting a certain number of times by a logic function regardless of the first signal or the second signal. Here, the power consumption associated with the arithmetic processing by the logic function is correlated with the number of times that the plurality of logic elements invert the input value, that is, the number of toggles. For this reason, as in the case of a two-wire two-phase logic circuit, if the number of toggles is made constant regardless of the input value, the correlation between the input value and the power consumption accompanying the arithmetic processing for the input value can be reduced. Therefore, according to the semiconductor integrated circuit having the processor described above, the secret information, which is valid information, is encrypted by the arithmetic processing using the encryption key with the logic function of the two-wire two-phase logic circuit. However, the power consumption associated with the calculation process for the input value can be made constant for each time regardless of the input value. As a result, it is possible to avoid a risk that the encryption key is estimated even if a power analysis attack or the like is received during the calculation process of encryption of secret information by the processor.

  As another form, a two-wire one-line converter circuit (DRO0, DRO1) using the two-wire two-phase code output from the output connector to data (SO) using the one-wire one-phase code ( 23) is further provided. As described above, since the valid information encrypted by the two-wire two-phase logic circuit and determined in the output connector can be operated by an appropriate one-wire logic circuit, the processor can be The present invention can be applied to an appropriate semiconductor integrated circuit including a logic circuit.

  As yet another form, the two-wire two-phase logic circuit is configured to output the output if the clear signal is input to at least one of the input connectors during the transition from the initial state to the valid state. The clear signal is output to the connector. From the above, the logical value of the output connector does not change until valid information is obtained for all the input connectors. Thereby, the state change of the signal line of the two-wire two-phase logic circuit can be suppressed, and the power consumption can be reduced. Further, for example, there is no need to provide a synchronization signal for synchronizing input data or a latch circuit using the synchronization signal on the input side of the two-wire two-phase logic circuit. As a result, the circuit scale does not increase and the size can be reduced.

  As yet another form, the two-wire two-phase logic circuit repeats the transition from the initial state to the valid state. As described above, since invalid information exists between adjacent valid information, a power consumption pattern including only valid information does not occur.

  As yet another form, the two-wire two-phase logic circuit is configured to change the initial state according to a mode signal (MODE) for switching a correspondence relationship between the clear signal, the first signal, and the second signal and a logic value. The first signal line and the second signal line whose logic value changes are switched when transitioning from the active state to the valid state. From the above, since the correspondence between the value of the input data and the signal line of the output connector whose logical value changes with respect to the value of the input data can be switched by the mode signal, corresponding to the specific value of the input data, It is possible to avoid a situation in which the signal line of the output connector whose logical value changes is always specified. Thereby, the correlation between the value of input data and the power consumption pattern can be reduced.

  As yet another form, the two-wire two-phase combinational logic circuit further includes a negative logic circuit (201) that inverts a logical value at a front stage and a rear stage, and the negative logic circuit is enabled or disabled by the mode signal. Is done. From the above, when both of the negative logic circuits are valid, the two-wire two-phase code indicating the clear signal, the first signal, and the second signal is inverted, and then calculated by the two-wire two-phase combinational logic circuit. The operation result is further inverted. Thereby, even when the definition of the two-wire two-phase code is changed, a logical operation corresponding to the two-wire two-phase code can be performed. When both negative logic circuits are invalid, the definition of the two-wire two-phase code is not changed, and a logical operation corresponding to the two-wire two-phase code can be performed.

  As yet another form, the mode signal enables the negative logic circuit after the two-wire two-phase logic circuit is in the initial state. As described above, the two-wire two-phase logic circuit can change from the initial state to the valid state after changing the definition of the two-wire two-phase code.

  As yet another form, the mode signal has substantially the same probability that the logic values of the first signal line and the second signal line change during the operation period in the two-wire two-phase logic circuit. To switch randomly. As described above, since the change in the logic value at the output connector is randomly switched during the calculation period in the two-wire two-phase logic circuit, it is difficult to form a power consumption pattern in a part of the calculation period. Furthermore, since the probability that the logical value changes during the calculation period at the output connector is substantially the same between the first signal line and the second signal line, it accompanies the load capacity of the first signal line and the second signal line. There is no need to consider the delay difference, and it is difficult to form a power consumption pattern for the input value even in the entire calculation period. Therefore, even if a power analysis attack or the like is received during the calculation period, it is difficult to analyze the power consumption pattern and estimate the encryption key.

  As yet another form, a control circuit (15) for generating a control signal (CTRL) for controlling the two-wire two-phase encoding circuit is further provided. The two-wire two-phase encoding circuit changes a timing of outputting the clear signal, the first signal, and the second signal by the two-wire two-phase code according to the control signal. As described above, since the timing at which the 2-wire 2-phase logic circuit starts the arithmetic processing can be made variable, it is difficult to generate a power consumption pattern accompanying the arithmetic processing according to the input value.

  As yet another form, the two-wire two-phase logic circuit comprises a composite gate. As described above, the number of transistors constituting the two-wire two-phase logic circuit can be reduced, and downsizing can be achieved.

  As yet another form, the two-wire two-phase logic circuit defines a later timing among timings at which data input to the first signal line and the second signal line change logically. In synchronization with the timing signal, a logical operation corresponding to the two-wire two-phase code is started. As described above, the logical operation of the two-wire two-phase logic circuit is started after the data input to the first signal line and the second signal line change logic. For this reason, even when the timing at which the input data undergoes a logical change differs between the first signal line and the second signal line, the output data resulting from the logical operation of the two-wire two-phase logic circuit undergoes a logical change. Since it is difficult for a difference in timing to occur, it is difficult to form a power consumption pattern for the value of input data.

  As still another form, the two-wire two-phase combinational logic circuit includes a plurality of the two-wire two-phase logic circuits connected in cascade. The two-wire two-phase logic circuit includes an input gate circuit (141 to 144), a logic circuit (146 to 155), and a delay circuit (157). The input gate circuit changes the data ((a0, a1), (b0, b1)) given to the input connector most slowly among the plurality of timing signals (a2, b2) given to the timing input terminals. Capture in synchronization with the timing signal (A). The logic circuit receives the data taken in by the input gate circuit and performs a logic operation. The delay circuit generates a timing signal (B) obtained by delaying the slowest timing signal by a predetermined time from the timing at which the logic operation of the logic circuit is determined. The timing signal generated by the delay circuit is output from a timing output terminal and applied to the timing input terminal of the two-wire two-phase logic circuit in the subsequent stage. The predetermined time is longer than the wiring delay between the two-wire two-phase logic circuits. From the above, even if the timing at which the data applied to the input connector changes in logic is different, the logic circuit receives data from the input gate circuit at the timing at which the logic changes. Thereby, it is difficult for a difference to occur in the timing at which the output data of the two-wire two-phase logic circuit logically changes. Further, the timing signal delayed by the delay circuit is used to obtain the timing signal having the slowest change in the input gate circuit at the subsequent stage. For this reason, even in the subsequent two-wire two-phase logic circuit, it is difficult for a difference to occur in the timing at which the output data logically changes. Accordingly, in a plurality of cascade-connected two-wire two-phase logic circuits, even when the timing at which input data logically changes depends on the wiring delay and the logic delay, it is difficult to cause a difference in the timing at which output data logically changes. .

  As yet another form, for each bit of data using the two-wire two-phase code output from the two-wire two-phase encoding circuit, a first timing signal indicating the timing of transition from the initial state to the valid state is provided. A first timing generation circuit (206) for generating is further included. The two-wire two-phase logic circuit (140) in the first stage inputs the first timing signal for each bit of data given to the input connector, and the slowest change among the inputted first timing signals. A second timing generation circuit (145) that generates a second timing signal (A) that changes in synchronization with the first timing signal is provided. The input gate circuit of the two-wire two-phase logic circuit in the next stage supplies the logic circuit with data using the two-wire two-phase code in synchronization with the second timing signal. As described above, since the input gate circuit generates the second timing signal that changes in synchronization with the slowest change timing among the timings at which the state transitions for each bit of data, the data having the same timing is given to the logic circuit. It is done. For this reason, even in the first-stage two-wire two-phase logic circuit, a difference hardly occurs in the timing at which the output data undergoes logic change.

  As still another form, the clear signal is “1, 1”, the first signal is “1, 0”, and the second signal is “0, 1”. The first timing generation circuit includes gate circuits (210-1 to 210-n) that determine that two input logical values are different for each bit of data using the two-wire two-phase code. From the above, the first timing generation circuit outputs the first timing indicating the timing at which the state transitions for each bit of data by outputting, for example, “1” only when transitioning from the clear signal to the first signal or the second signal. A timing signal can be generated.

  As still another form, the two-wire two-phase combinational logic circuit includes a plurality of the two-wire two-phase logic circuits connected in cascade. The two-wire two-phase logic circuit latches data applied to the input connector in synchronization with a clock signal (NCLK) applied to a timing input terminal, and the latch circuit And a logic circuit (225) that receives the latched data and performs a logic operation. The clock signal is input in common to all the latch circuits. The period of the clock signal is larger than a delay amount including a logic delay until the logic operation of the logic circuit is determined and a wiring delay between the two-wire two-phase logic circuits. From the above, even if the logic change timing of the data input to the input connector varies depending on the logic delay or wiring delay, the logic change timing of the data applied to the logic circuit is made uniform by the latch circuit. As a result, in the two-wire two-phase logic circuit, it is difficult for a difference to occur in the timing at which the output data logically changes.

  As still another form, the two-wire two-phase combinational logic circuit includes a plurality of the two-wire two-phase logic circuits connected in cascade. The two-wire two-phase logic circuit includes a gate circuit (141 to 144) for outputting data given to the input connector in synchronization with a clock signal (PCLK) given to a timing input terminal, and the gate circuit. And logic circuits (146 to 155) that receive data output from and perform logic operations. The clock signal is input in common to the gate circuit of the two-wire two-phase logic circuit arranged in the same stage where the logic delay starting from the first two-wire two-phase logic circuit is substantially the same. The phase differs from stage to stage. The period of the clock signal is larger than a delay amount including a logic delay until the logic operation of the logic circuit is determined and a wiring delay between the two-wire two-phase logic circuits. As described above, the timing at which the logic of the data supplied to the logic circuit changes is aligned by the gate circuit synchronized with the clock signal input in common at the same stage. As a result, it is difficult for a difference to occur in the timing at which the output data undergoes a logical change.

2. Next, the embodiment will be described in more detail.
Embodiment 1
FIG. 1 illustrates the configuration of an IC card chip which is an example of a semiconductor integrated circuit according to Embodiment 1 of the present invention. The IC card chip 1 includes, for example, an input / output circuit 2, a central processing unit (CPU) 3, a control circuit 4, a data memory 5, a program memory 6, a cryptographic coprocessor 7, and a data bus 8. The control circuit 4 controls the input / output circuit 2, the CPU 3, the data memory 5, the program memory 6, the cryptographic coprocessor 7, and the data bus 8 to operate in cooperation. The CPU 3 inputs / outputs data between the input / output circuit 2, the data memory 5, and the cryptographic coprocessor 7 via the data bus 8 according to the program stored in the program memory 6, and the above-mentioned according to the program. Performs data processing.

  FIG. 2 illustrates the configuration of the cryptographic coprocessor 7. The cryptographic coprocessor 7 is an arithmetic circuit dedicated to encryption / authentication that performs high-speed processing by assisting the operation of the CPU 3. For example, the cryptographic coprocessor 7 reads an encryption key stored in an appropriate memory and encrypts it using this encryption key. Run the algorithm to encrypt the secret information. The cryptographic coprocessor 7 includes a bus conversion circuit 10, a data register 11, a two-wire two-phase arithmetic circuit 14, and a control circuit 15. The control circuit 15 controls the following processing. That is, secret information that is data to be processed by the cryptographic coprocessor 7 is temporarily stored in the data register 11 that temporarily stores data from the data bus 8 through the bus conversion circuit 10. The data stored in the data register 11 is input to the 2-wire 2-phase arithmetic circuit 14 and encrypted. The encrypted secret information that is the output of the two-wire two-phase arithmetic circuit 14 is temporarily stored in the data register 11. The encrypted secret information stored in the data register 11 is output to the data bus 8 via the bus conversion circuit 10.

  FIG. 3 illustrates the configuration of the two-wire two-phase arithmetic circuit 14. FIG. 26 exemplifies the correspondence relationship between the logical value and the two-wire two-phase code in the two-wire two-phase arithmetic circuit 14. Here, a two-wire two-phase code that defines a logical value 1 as (1, 0), a logical value 0 as (0, 1), and clear as (1, 1) is used. However, this does not limit the values of the two signal lines assigned to the two-wire two-phase code. Hereinafter, the logical value 1 and the logical value 0 are referred to as valid data of the two-wire two-phase code, and the clear is referred to as invalid data. The two-wire two-phase arithmetic circuit 14 includes a two-wire two-phase encoding circuit 20, a two-wire two-phase combinational logic circuit 22, and a two-wire one-line conversion circuit 23. The two-wire two-phase encoding circuit 20 is a circuit that converts input data SI using a one-wire one-phase code representing a logical value in one bit into a two-wire two-phase code and outputs it in a bit unit. The output timing is controlled by a control signal CTRL generated by the control circuit 15. The input data SI is confidential information. The two-wire two-phase combinational logic circuit 22 has a plurality of two-wire two-phase logic circuits (see FIGS. 7 to 10) that perform a logical operation corresponding to the two-wire two-phase code. When data represented by a signal is input, a logical operation process is performed using the two-wire two-phase logic circuit, and the result of the logical operation process is output as data represented by a two-wire two-phase code. This means that encryption of the secret information using the encryption key in the encryption coprocessor 7 is performed by a logical operation using a two-wire two-phase code. The 2-wire 1-wire conversion circuit 23 inputs the data represented by the 2-wire 2-phase code output from the 2-wire 2-phase combinational logic circuit 22, and converts the 2-wire 2-phase code valid data into a 1-bit logic. The data is converted into data SO using the 1-line 1-phase code represented by the value and output.

  FIG. 4 illustrates the configuration of the two-wire two-phase encoding circuit 20. The two-wire two-phase encoding circuit 20 includes D flip-flops 50-1 to 50-n, two-input OR logic elements 52-1 to 52-n, and 53-1 to 53-n. Here, the operation of the two-wire two-phase encoding circuit 20 will be described with reference to the timing chart of FIG. The two-wire two-phase encoding circuit 20 inputs n pieces of input data SI that is 1-bit secret information having 1 and 0 values, and inputs the input data SI in synchronization with the rising edge of the synchronization signal CLK. Each bit is held by the D flip-flops 50-1 to 50-n, and the logical value 0 (2-bit 2-phase code valid data is obtained by the outputs Q and QN of the D flip-flops 50-1 to 50-n. 0,1) or logical value 1 (1,0) is output.

  The outputs Q of the D flip-flops 50-1 to 50-n are connected to one input of the 2-input OR logic elements 52-1 to 52-n. The outputs QN of the D flip-flops 150-1 to 50-n are connected to one input of the two-input OR logic elements 53-1 to 53-n. Further, the control signal CTRL is input to the other inputs of the 2-input OR logic elements 52-1 to 52-n and 53-1 to 53-n, respectively. Thus, if the control signal CTRL is 0, the 2-wire 2-phase encoding circuit 20 outputs the output Q of the D flip-flops 50-1 to 50-n as output data (DRI0, DRI1) by the 2-wire 2-phase code. , The logical value 0 (0, 1) or the logical value 1 (1, 0), which is the value of QN, is output. At this time, valid data is input to the two-wire two-phase combinational logic circuit 22. Hereinafter, this state is referred to as an operating phase. Further, if the control signal CTRL is 1, the 2-wire 2-phase encoding circuit 20 outputs clear (1, 1) as output data (DRI0, DRI1) based on the 2-wire 2-phase code. At this time, invalid data is input to the two-wire two-phase combinational logic circuit 22. Hereinafter, this state is referred to as a resting phase. Thus, since the transition from the dormant phase to the active phase is repeated according to the cycle of the control signal CTRL, there is a dormant phase between adjacent active phases, and invalid data exists between valid data. The valid data is not continuous. Thereby, the power consumption pattern which consists only of effective data does not arise. Further, the cycle of the control signal CTRL may be changed instead of being fixed. Thereby, the timing at which the 2-wire 2-phase encoding circuit 20 outputs the output data (DRI0, DRI1) by the 2-wire 2-phase code can be made variable, and the timing at which the idle phase and the active phase are switched can be changed. Alternatively, the control signal CTRL having a different period may be provided independently for each bit of the input data SI of the two-wire two-phase encoding circuit 20.

  FIG. 5 illustrates the configuration of the two-wire / one-wire conversion circuit 23. The two-wire / one-wire conversion circuit 23 includes D flip-flops 51-1 to 51-n. Here, the operation of the 2-line 1-line conversion circuit 23 will be described with reference to the timing chart of FIG. Of the two signal lines having the two-wire two-phase code, one signal line is input to the D flip-flops 51-1 to 51-n, and the D flip-flops 51-1 to 51-n are input at the rising edge of the synchronization signal CLK. Holds the input value and outputs it. That is, the 2-wire 1-wire conversion circuit 23 converts the value input from one signal line, that is, the output data (DRO0, DRO1) of the 2-wire 2-phase combinational logic circuit 22 into the value of effective data of the 2-wire 2-phase code. Is converted into a 1-bit signal line and output to the data register 11 as data SO, for example. In addition, the 2-wire 1-line conversion circuit 23 clears (1, 1) or not yet clears the 2-wire 2-phase code of the input data at the timing when the valid data of the input data is held in the D flip-flops 50-1 to 50-n. If it is in use (0, 0), it can be determined that the operation of the two-wire two-phase combinational logic circuit 22 is abnormal.

  Next, as an example of a two-wire two-phase logic circuit included in the two-wire two-phase combinational logic circuit 22, a two-wire two-phase AND logic circuit that performs an AND logic operation using a two-wire two-phase code, and 2 Details of a two-wire two-phase XOR logic circuit that performs an XOR logic operation using a two-phase code will be described. FIG. 7 illustrates a configuration of a two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit 22. The 2-wire 2-phase AND logic circuit 70 includes 2-input NOR logic elements 71 to 74 and 3-input NOR logic elements 75 and 76. These logic elements 71 to 76 are configured using CMOS. The two-wire two-phase AND logic circuit 70 includes a first signal line and a second signal line to which input data (a0, a1) and (b0, b1) represented by a two-wire two-phase code are input, respectively. And two output connectors, and a first signal line for outputting output data (q0, q1) and a single output connector composed of a second signal line. In FIG. 27, the relationship between input and output for the 2-wire 2-phase AND logic circuit 70 is illustrated by 2-wire 2-phase codes. This correspondence will be described in detail with reference to FIG.

  FIG. 11 illustrates a Carnot diagram showing the output of the two-wire two-phase AND logic circuit 70. In the figure, [1] to [9] indicate output data (q0, q1) from the output connector, [1] is a pause phase, [2] [4] [7] [9] are operating phases. , [3], [5], [6], and [8] respectively show intermediate states indicating the transition from the rest phase to the active phase. Hereinafter, the operation when the input data (a0, a1) and the input data (b0, b1) are cleared (1, 1) to the active phase having the logical value 0 or the logical value 1 will be described. . Here, it is assumed that the time at which the input data (a0, a1) or the input data (b0, b1) changes from clear to logical value 0 or logical value 1 is not simultaneous. For example, when the input data (a0, a1) transitions from clear to logical value 0 or logical value 1 before the input data (b0, b1), the output data (q0, q1) is in an intermediate state [3] , [8]. Next, when the input data (b0, b1) shifts from the clear to the logical value 0 or the logical value 1 after the input data (a0, a1), the output data (q0, q1) becomes [2], [4 ], [7], and [9].

  On the other hand, when the input data (b0, b1) transitions from clear to logical value 0 or logical value 1 before the input data (a0, a1), the output data (q0, q1) is in an intermediate state [5]. , [6]. Next, when the input data (a0, a1) is delayed from the input data (b0, b1) and transitions from clear to logical value 0 or logical value 1, the output data (q0, q1) is [2], [4 ], [7], and [9].

  Hereinafter, in the 2-wire 2-phase AND logic circuit 70, the time at which the output data (q0, q1) changes is constant, and the power consumption when the output data (q0, q1) is determined is constant. Explain that. In FIG. 11, when the input changes from clear (1, 1) to logic value 0 (0, 1) or logic value 1 (1, 0), the two-input NOR logic elements 71 to 74 in the rest phase [1]. The output is 0, and in the intermediate states [3], [5], [6], [8], the outputs of the 2-input NOR logic elements 71 to 74 are 0, and the operating phases [2], [4], In [7] and [9], the output of any of the 2-input NOR logic elements 71 to 74 is 1, and any of the 3-input NOR logic elements 75 and 76 is 1. That is, in the two-wire two-phase AND logic circuit 70, when the transition is made from the idle phase to the active phase, any one of the outputs of the two-input NOR logic elements 71 to 74 arranged in the same stage is arranged in the same stage. Only the two outputs of the three-input NOR logic elements 75 and 76 are always inverted. As a result, the number of toggles is fixed, and the power consumption is always constant regardless of the input value. The number of toggles refers to the number of times that a logical value is inverted by a predetermined logical function. In the two-wire two-phase AND logic circuit 70, as described above, a plurality of logic elements are arranged so that only one of the outputs of the logic elements arranged in the same stage is inverted. Power consumption can be reduced by reducing the number of logic elements.

  In short, the two-wire two-phase AND logic circuit 70 is connected to all input connectors only when transitioning from the idle phase [1] to the active phase [2], [4], [7], [9]. When valid data is available, the logical value of the input data of the input connector is inverted a predetermined number of times, here twice by the logic function composed of the plurality of logic elements 71 to 76, and the valid data is determined in the output connector. To do. Before valid information is available for all input connectors, the output connector outputs invalid data as shown in the pause phase [1], intermediate state [3], [5], [6], [8]. Output. As a result, the state change of the signal lines in the two-wire two-phase AND logic circuit 70 can be suppressed, so that power consumption can be reduced. Furthermore, even when valid data is delayed and input to the input connector, there is no difference in the time at which the logical value of the output connector changes, and as a result, power consumption associated with arithmetic processing by the logical function occurs. There is no difference in time. This means that in the 2-wire 2-phase AND logic circuit 70, it is not necessary to consider the delay difference of all input connectors. Therefore, for example, there is no need to provide a synchronization signal for synchronizing the input data (a0, a1) and (b0, b1) or a latch circuit using the synchronization signal on the input side of the two-wire two-phase AND logic circuit 70. Therefore, the circuit scale does not increase and the size can be reduced.

  Further, in the two-wire two-phase AND logic circuit 70, valid data is determined in the output connector through a certain number of toggles regardless of the value of the input data. In consideration of the fact that the power consumption correlates with the number of toggles in the plurality of logic elements 71 to 76 composed of CMOS, the power consumption associated with the processing of the input data value and the input data value. This means that the correlation with can be reduced. Therefore, according to the cryptographic coprocessor 7, the number of toggles is fixed regardless of the value of the input data by performing the logical operation accompanying the encryption of the secret information using the two-wire two-phase AND logic circuit 70. The power consumption associated with the arithmetic processing on the input data can be made constant for each time regardless of the value of the input data. Thus, the encryption key is not estimated by a power analysis attack in which analysis is performed using the input value and the power consumption generated during the logical operation during the logical operation accompanying encryption in the cryptographic coprocessor 7. High safety can be obtained.

  On the other hand, an appropriate one-line arithmetic circuit using a one-line one-phase code that represents one bit with one signal line and the state of the signal line corresponds to the data value of one bit as it is, When the secret information is encrypted, there is a correlation between the input data of the one-wire arithmetic circuit and the power consumption generated by the arithmetic processing on the input data, and the encryption key can be easily obtained by a power analysis attack or the like. Will be estimated.

  In the above example, in the 2-wire 2-phase AND logic circuit 70, the clear of the 2-wire 2-phase code is (1, 1), but the clear of the 2-wire 2-phase code is (0, 0). Will be described with reference to FIG. FIG. 9 illustrates the configuration of another two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit 22. The 2-wire 2-phase AND logic circuit 80 includes 2-input NAND logic elements 81 to 84 and 3-input NAND logic elements 85 and 86. FIG. 13 illustrates a Carnot diagram showing the output of the two-wire two-phase AND logic circuit 80. The two-wire two-phase AND logic circuit 80 is configured according to the Carnot diagram of FIG. 13. In the figure, [1] to [9] are the output data (q0, q1), [1] indicates the idle phase, [2] [4] [7] [9] indicates the active phase, and [3] [5] [6] [8] indicate the intermediate state, respectively. Yes. Similarly to the two-wire two-phase AND logic circuit 70, the two-wire two-phase AND logic circuit 80 sets a fixed number of toggles regardless of the value of the input data only when transitioning from the idle phase to the active phase. After that, valid data is determined in the output connector. Therefore, according to the two-wire two-phase AND logic circuit 80, the correlation between the value of the input data and the accompanying power consumption can be reduced, and the estimation of the encryption key due to the power analysis attack can be avoided.

  FIG. 8 illustrates a configuration of a two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit 22. The 2-wire 2-phase XOR logic circuit 90 includes 2-input NOR logic elements 91-96. FIG. 12 illustrates a Carnot diagram illustrating the output of the two-wire two-phase XOR logic circuit 90. The two-wire two-phase XOR logic circuit 90 is configured according to the Carnot diagram of FIG. The two-wire two-phase XOR logic circuit 90, like the two-wire two-phase AND logic circuit 70, outputs only through a fixed number of toggles regardless of the value of the input data only when transitioning from the idle phase to the active phase. Confirm valid data in the connector.

  Here, in the above-described two-wire two-phase XOR logic circuit 90, an example in which the clear of the two-wire two-phase code is (1, 1) is shown, but the case where it is (0, 0) will be described with reference to FIG. explain. FIG. 10 illustrates a configuration of still another two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit 22. The 2-wire 2-phase XOR logic circuit 100 includes 2-input NAND logic elements 101 to 106. FIG. 14 illustrates a Carnot diagram illustrating the output of the two-wire two-phase XOR logic circuit 100. The two-wire two-phase XOR logic circuit 100 is configured according to the Carnot diagram of FIG. The two-wire two-phase XOR logic circuit 100, like the two-wire two-phase AND logic circuit 70, outputs only through a fixed number of toggles regardless of the value of the input data only when transitioning from the idle phase to the active phase. Confirm valid data in the connector.

<< Embodiment 2 >>
FIG. 15 illustrates the configuration of a two-wire two-phase arithmetic circuit that is an example of the logical arithmetic circuit according to the second embodiment of the present invention. In the following, functions and the like that are the same as those of the two-wire two-phase arithmetic circuit 14 illustrated in FIG. The two-wire two-phase arithmetic circuit 200 includes, for example, two negative logic circuits 201, a two-wire two-phase encoding circuit 21, a two-wire two-phase combinational logic circuit 202, and a two-wire one-line conversion circuit 23. FIG. 28 illustrates the correspondence between the logical value and the 2-wire 2-phase code for the 2-wire 2-phase arithmetic circuit 200. In the two-wire two-phase arithmetic circuit 200, if the two-wire two-phase code is changed according to the value of the switching signal MODE, and MODE = 0, (0, 1) is set to the logical value 0, and (1, 0) is set to the logical value 1. If = 1, the logical operation is performed with (0, 1) as the logical value 1 and (1, 0) as the logical value 0. In short, the negation logic circuit 201 negates and outputs the logic values of all input signal lines when the switching signal MODE is 1. The switching signal MODE is generated by, for example, the control circuit 15 and is given as shown in the timing chart of FIG.

  FIG. 16 illustrates the configuration of the negative logic circuit 201. The negation logic circuit 201 includes XOR logic elements 54-1 to 54-m. The input m input signal lines IN are connected to the XOR logic elements 54-1 to 54-m. When the switching signal MODE is 1, the XOR logic elements 54-1 to 54-m are connected to the input signal line IN. It operates to negate the logical value of.

  The two-wire two-phase combinational logic circuit 202 has a two-wire two-phase logic circuit (see FIGS. 18 and 19) that performs a logical operation using a two-wire two-phase code, and is represented by a two-wire two-phase code. When this data is input, logical operation processing is performed using this 2-wire 2-phase logic circuit, and the result of the logical operation processing is output as data represented by 2-wire 2-phase code.

  Thus, in the two-wire two-phase arithmetic circuit 200, when both the negative logic circuits 201 are valid, the input data SI is 2 after the correspondence between the logical value and the two-wire two-phase code is inverted. After being converted into a two-wire two-phase code by the two-wire two-phase encoding circuit 21, the two-wire two-phase combinational logic circuit 202 is operated, and the data represented by the two-wire two-phase code that is the result of the operation is further inverted. Is done. Therefore, the two-wire two-phase arithmetic circuit 200 can perform a logical operation corresponding to the two-wire two-phase code even when the definition of the two-wire two-phase code is changed. Further, the negative logic circuit 201 is enabled after the two-wire two-phase logic circuit included in the two-wire two-phase combinational logic circuit 202 enters a pause phase. In this way, the two-wire two-phase arithmetic circuit 200 can change the definition of the two-wire two-phase code and perform the transition from the sleep phase to the active phase in the two-wire two-phase logic circuit. it can. On the other hand, in the case of the two-wire two-phase arithmetic circuit 200, when both of the negative logic circuits 201 are invalid, the definition of the two-wire two-phase code is not changed and is the same as the two-wire two-phase arithmetic circuit 14 described above. Logical operations can be performed.

  Next, as an example of a two-wire two-phase logic circuit that inputs a switching signal MODE included in the two-wire two-phase combinational logic circuit 202, a two-wire two-phase equation that performs an AND logic operation using a two-wire two-phase code. A two-wire two-phase XOR logic circuit that performs an XOR logic operation using an AND logic circuit and a two-wire two-phase code will be described. FIG. 18 illustrates a configuration of a two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit 202. The 2-wire 2-phase AND logic circuit 130 includes 2-input NOR logic elements 131 to 132 and 3-input NOR logic elements 133 to 138. c is the same value as the switching signal MODE, and cn is a value obtained by negating the logical value of the switching signal MODE.

  FIG. 20 illustrates a Carnot diagram illustrating the operation of the two-wire two-phase AND logic circuit 130. The two-wire two-phase AND logic circuit 130 is configured according to the Carnot diagram of FIG. As shown in the drawing, the two-wire two-phase AND logic circuit 130 includes a first signal line and a second signal line whose logic values change in accordance with the switching signal MODE when transitioning from the idle phase to the active phase. Is switched. As a result, it is possible to avoid a situation in which the signal line of the output connector whose logical value changes is always specified corresponding to the specific value of the input data. For example, the two-wire two-phase AND logic circuit 130 operates as a two-wire two-phase AND logic circuit in FIG. 18 if c is 0, and operates as a two-wire two-phase OR logic circuit if c is 1. This is because when the logical function of the logic circuit is AND (logical product), when “&” is AND (logical product) and the logical function is “Z = X & Y”, the logical value of input / output is negated, A logical function equivalent to “Z = X & Y” is “−Z = −XV−Y”, where “−” is the negation of the input / output logical value and “V” is OR (logical sum). It is clear from In other words, negation logic circuit 201 negates the input / output logic value and switches the logic function of the two-wire two-phase logic circuit from OR (logical product) to OR (logical sum). A logic function equivalent to the two-wire two-phase AND logic circuit 130 in the case where both circuits 201 are effective can be obtained.

  Further, the switching signal MODE is random so that the probability that the logical values of the first signal line and the second signal line change during the calculation period in the two-wire two-phase AND logic circuit 130 is substantially the same. It is switched to. Thereby, when paying attention to a part of the calculation period by the two-wire two-phase AND logic circuit 130, it is difficult to form a power consumption pattern for the input value by switching the switching signal MODE at random. Further, even when attention is paid to the entire calculation period by the two-wire two-phase AND logic circuit 130, the probability that the logical value changes between the first signal line and the second signal line is substantially the same. It is difficult to form a power consumption pattern for the input value. Therefore, according to the two-wire two-phase arithmetic circuit 200, it is difficult to estimate the encryption key by analyzing the power consumption pattern even if a power analysis attack or the like is received during the calculation period.

  FIG. 19 illustrates a configuration of a two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit 202. Two-wire two-phase XOR logic circuit 110 includes 2-input NOR logic elements 111 to 116 and 2-input NAND logic elements 117 to 122. FIG. 21 illustrates a Carnot diagram illustrating the operation of the two-wire two-phase XOR logic circuit 110. The two-wire two-phase XOR logic circuit 110 is configured according to the Carnot diagram of FIG. In short, the 2-wire 2-phase XOR logic circuit 110 operates as a 2-wire 2-phase XOR logic circuit if c is 0 in FIG. 19, and operates as a 2-wire 2-phase XNOR logic circuit if c is 1. . Therefore, according to the two-wire two-phase arithmetic circuit 200 using the two-wire two-phase XOR logic circuit 110, high safety against a power analysis attack or the like can be ensured as described above.

  If a difference occurs in the timing at which the logical value changes in the input data for each bit of the 2-wire 2-phase logic circuit due to wiring delay or the like, a difference that cannot be ignored occurs in the timing at which the output data changes in logic. There is a case. Specifically, a plurality of two-wire two-phase logic circuits are cascade-connected to realize a predetermined logic operation. When there is a wiring delay or the like, for example, as shown in FIG. A difference D1 occurs at the time when the logical value changes between a0 and a1 in the input data (a0, a1). Further, in this two-wire two-phase logic circuit, a difference D2 occurs at the timing when the logic value changes between q0 and q1 in the 1-bit output data (q0, q1) according to the difference D1. If this difference D2 becomes too large, a power consumption pattern for the input value may be formed. For this reason, in the first and second embodiments, the wiring lengths of the first signal line and the second signal line of the output connector of the two-wire two-phase logic circuit in the IC layout are made equal to each other so that the load capacitance, the wiring resistance, etc. It is sufficient to control the variation of the elements that affect the delay. However, this requires an extra step for equalizing the wiring length in the IC layout.

  Each embodiment shown below assumes that the timing at which input data undergoes a logical change varies depending on wiring delays, etc., and even in such a case, it is difficult to form a power consumption pattern for the value of the input data. For having a configuration.

<< Embodiment 3 >>
FIG. 30 illustrates the configuration of a two-wire two-phase arithmetic circuit that is an example of a logical arithmetic circuit according to the third embodiment of the present invention. In the following, functions and the like that are the same as those of the two-wire two-phase arithmetic circuit 200 illustrated in FIG. The two-wire two-phase arithmetic circuit 205 includes, for example, two negative logic circuits 201, a two-wire two-phase encoding circuit 21, a synchronization generation circuit 206, a two-wire two-phase combinational logic circuit 207, a two-wire one-line conversion circuit 23, and the like. It has. The negation logic circuit 201 negates and outputs the logic values of all the input signal lines when the switching signal MODE is 1. The switching signal MODE is generated by, for example, the control circuit 15 and is given as shown in the timing chart of FIG. In the two-wire two-phase arithmetic circuit 205, as in the second embodiment, the two-wire two-phase code is converted into the logical value 0 and (1, 0) when MODE = 0 by changing the value of the switching signal MODE. ) Is a logical value 1, and if MODE = 1, a logical operation is performed with a logical value 1 (0, 1) and a logical value 0 (1,0).

  FIG. 31 illustrates the configuration of the synchronization generation circuit 206. The synchronization generation circuit 206 includes XOR logic elements 210-1 to 210-n and the like. Output data (DRI0, DRI1) of the two-wire two-phase encoding circuit 21 is input to the XOR logic elements 210-1 to 210-n for each bit, and the first timing is determined according to the truth table shown in FIG. A signal TS is generated. The first timing signal TS is input with a logical value 0 (0, 1) or a logical value 1 (1, 0) after, for example, clear (1, 1) is input as output data (DRI0, DRI1). Therefore, the signal is synchronized with the timing at which the state transitions for each bit of data. Further, the synchronization generation circuit 206 outputs the n-bit output data (DRI0, DRI1) as it is to the two-wire two-phase combinational logic circuit 207.

  The two-wire two-phase combinational logic circuit 207 has a plurality of two-wire two-phase logic circuits that are cascade-connected in order to realize a desired logic operation. FIG. 33 illustrates the configuration of a two-wire two-phase AND logic circuit that performs an AND logic operation using a two-wire two-phase code. The synchronization generation circuit 206 outputs n-bit output data (DRI0, DRI1) to the 2-wire two-phase combinational logic circuit 207, but here, typically, 2-bit output data ((DRI0 [1], DRI1 [ 1]) and (DRI0 [2], DRI1 [2])) are exemplified as input data ((a0, a1), (b0, b1)). Corresponding to this, FIG. 33 representatively illustrates the first timing signals TS [1], TS [2]. The two-wire two-phase AND logic circuit 140 receives an input connector to which input data ((a0, a1), (b0, b1)) is input and first timing signals TS [1], TS [2]. In addition, c indicating the same value as the switching signal MODE and cn indicating a value obtained by negating the logical value of the switching signal MODE are input. As shown in FIG. 34, the first timing signal TS [1] is set to “1” in synchronization with the later of the timing of transition of the state of the input data (a0, a1), that is, a0. The second timing signal TS [2] is set to “1” in synchronization with the later of the timings at which the state of the input data (b0, b1) transitions, that is, b0.

  The two-wire two-phase AND logic circuit 140 includes a two-input NAND logic element 145, an input gate circuit 158, a logic circuit 159, a delay circuit 157, and the like. Further, the two-wire two-phase AND logic circuit 140 includes an output connector that outputs output data (q0, q1), a timing output terminal that outputs a delay signal B described later, and the like. The first timing signals TS [1] and TS [2] are input to the 2-input NAND logic element 145, and as shown in FIG. 34, the input first timing signals TS [1] and TS [2] Of these, the second timing signal A that changes in synchronization with the latest timing, in this case, in synchronization with the first timing signal TS [1] and is set to “1” is generated. The second timing signal A is input to the input gate circuit 158.

  The input gate circuit 158 includes 2-input NOR logic elements 141 to 144. The input data a0, a1, b0, b1 are input to the 2-input NOR logic elements 141 to 144, respectively, and the second timing signal A is input in common as a control signal. In this way, the two-input NOR logic elements 141 to 144 take in a0, a1, b0, b1 in synchronization with the second timing signal A, and as shown in FIG. a0 ′, a1 ′, b0 ′, and b1 ′ are output to the logic circuit 159. The logic circuit 159 includes two-input NAND logic elements 146 and 147, three-input NAND logic elements 148 to 153, negative logic elements 154 and 155, and receives the data a0 ′, a1 ′, b0 ′, and b1 ′ to perform a logic operation. The result of the logic operation is output from the output connector as output data (q0, q1) to the input connector of the next-stage 2-wire 2-phase logic circuit (not shown). Since the output data (q0, q1) is the result of the logical operation by the logic circuit 159 that has received the data a0 ′, a1 ′, b0 ′, b1 ′ having the same timing from the input gate circuit 158, as shown in FIG. It is hard to make a difference in the logic change timing. Thus, among the plurality of two-wire two-phase AND logic circuits connected in cascade, in the first-stage two-wire two-phase AND logic circuit 140, the value of the input data is different even if the timing at which the input data logically changes is different. It is difficult to form a power consumption pattern.

  The two-wire two-phase AND logic circuit 140 sets the output q0 and the output q1 to logic 1 if either of the first timing signals TS [1], TS [2] is logic 1, and the first timing If the signals TS [1] and TS [2] are both logic 0, the operation is performed so as to obtain the output q0 and the output q1 according to the Carnot diagram shown in FIG. That is, the two-wire two-phase AND logic circuit 140 operates as a two-wire two-phase AND logic circuit if c is 0, as in the case of the two-wire two-phase AND logic circuit 130. Operates as a 2-wire 2-phase OR logic circuit.

  On the other hand, the 2-stage 2-phase AND logic circuit of the next stage has the same configuration as the 2-stage 2-phase AND logic circuit 140 of the first stage, but the signal received by the 2-input NAND logic element 145 is generated by the delay circuit 157. Delay signal B is used. The delay circuit 157 receives the second timing signal A via the negative logic element 156, and the timing at which the logic operation of the logic circuit 159 is determined, that is, the logic delay, and between the first and next two-wire two-phase AND logic circuits. The delay signal B is generated by delaying for a predetermined time further than the delay amount consisting of the wiring delay in FIG. That is, as shown in FIG. 34, the delay signal B is logically changed through the difference D3 by being delayed longer than the delay amount, and is set to “1”. The delay signal B is input to the two-input NAND logic element 145 of the next-stage two-wire two-phase AND logic circuit as described above instead of the first timing signals TS [1] and TS [2]. Used to generate the second timing signal A. In short, also in the next-stage 2-wire 2-phase AND logic circuit, as in the first-stage 2-wire 2-phase AND logic circuit 140, data having the same timing for logical change by the input gate circuit 158 is input to the logic circuit 159. Thus, it is difficult for a difference to occur in the timing at which the output data (q0, q1) logically changes.

  FIG. 35 illustrates the configuration of a two-wire two-phase XOR logic circuit that performs an XOR logic operation using a two-wire two-phase code. The two-wire two-phase XOR logic circuit 160 receives the first timing signals TS [1], TS [2] by the two-input NAND logic element 165, generates the second timing signal A1, and generates the three-input NOR logic elements 161- The data a0 ′, a1 ′, b0 ′, b1 ′ having the same logic change timing are output to the logic circuit 159A by the input gate circuit 158A composed of 164. The logic circuit 159A includes 2-input NOR logic elements 166 and 167 and 2-input NAND logic elements 168 to 173, receives the data a0 ′, a1 ′, b0 ′, and b1 ′, performs a logic operation, and outputs data (q0 , Q1) are output to the next two-wire two-phase XOR logic circuit. The two-wire two-phase XOR logic circuit 160 sets the output q0 and the output q1 to logic 1 if any of the first timing signals TS [1], TS [2] is logic 1, and the first timing If the signals TS [1] and TS [2] are both logic 0, the operation is performed so as to obtain the output q0 and the output q1 according to the Carnot diagram shown in FIG. In short, the two-wire two-phase XOR logic circuit 160 operates as a two-wire two-phase XOR logic circuit if c is 0, similarly to the two-wire two-phase XOR logic circuit 110, and if c is 1, Operates as a 2-wire 2-phase XNOR logic circuit.

  The delay circuit 175 receives the second timing signal A1 via the negative logic element 174, and includes a logic delay by the logic circuit 159A and a wiring delay between the first and next two-wire two-phase XOR logic circuits. The delay signal B1 is generated by delaying for a predetermined time further than the delay amount. The delay signal B1 is input to the 2-input NAND logic element 165 of the next-stage 2-wire 2-phase XOR logic circuit and used to generate the second timing signal A1. As a result, in a plurality of two-wire two-phase XOR logic circuits connected in cascade, even if the timing at which input data logically changes is different, the timing at which output data (q0, q1) logically changes is unlikely to vary.

  Therefore, according to the two-wire two-phase arithmetic circuit 205 including the two-wire two-phase combinational logic circuit 207 using the two-wire two-phase AND logic circuit 140 and the two-wire two-phase XOR logic circuit 160, a plurality of 2 Even when the timing at which the input data changes logically in a two-phase logic circuit varies depending on the wiring delay and logic delay, it is difficult to form a power consumption pattern for the input data value. Can be secured.

<< Embodiment 4 >>
36 illustrates another configuration of the two-wire two-phase combinational logic circuit 202 included in the two-wire two-phase arithmetic circuit 200 illustrated in FIG. In the following, functions and the like that are the same as those of the two-wire two-phase arithmetic circuit 200 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The two-wire two-phase combinational logic circuit 230 includes two-wire two-phase logic circuits 220-1 to 220-M that are cascade-connected in order to realize a desired logic operation. The two-wire two-phase logic circuits 220-1 to 220-M are connected in N stages by a two-wire two-phase combinational logic circuit 230, and the delay amount of each output data q is divided approximately equally for each stage. Are arranged to be. The two-wire two-phase combinational logic circuit 230 outputs data (DRI [1] to DRI [K]) using the two-wire two-phase code from the two-wire two-phase encoding circuit 21, and a synchronous clock signal NCLK described later. Etc. are input, and data (q [1] to q [K]) using a two-wire two-phase code is output. The synchronous clock signal NCLK is generated by the control circuit 15 illustrated in FIG. 2 and is commonly input to the two-wire two-phase logic circuits 220-1 to 220-M.

  FIG. 38 typically illustrates the configuration of a two-wire two-phase logic circuit 220-1. The two-wire two-phase logic circuit 220-1 includes an input connector to which data ((a0, a1), (b0, b1)) corresponding to the output data (DRI [1], DRI [2]) is input; It has a timing input terminal to which the synchronous clock signal NCLK is input and an output connector to which output data (q0, q1) is output. The above-mentioned c and cn are also input. The 2-wire 2-phase logic circuit 220-1 includes a latch circuit 226 and a 2-wire 2-phase logic circuit 225. The latch circuit 226 has D-type flip-flop circuits 221 to 224, holds data ((a0, a1), (b0, b1)) at the rising edge of the synchronous clock signal NCLK, respectively, and is a two-wire two-phase logic. Output to the circuit 225. The two-wire two-phase logic circuit 225 includes the two-wire two-phase AND logic circuit 130 or the two-wire two-phase XOR logic circuit 110 illustrated in FIGS. Further, the period of the synchronous clock signal NCLK is a logic delay until the logic operation of the two-wire two-phase logic circuit 225, which is a logic circuit of the two-wire two-phase logic circuits 220-1 to 220-M, is determined. It is larger than the delay amount including the wiring delay obtained by dividing the wiring delay of the entire two-wire two-phase combinational logic circuit 230 substantially equally in N stages. As shown in FIG. 37, the synchronous clock signal NCLK has N stages of two-wire two-phase logic circuits 220-1 to 220-M as compared with the control signal CTRL that controls the timing at which the idle phase and the active phase are switched. In order to operate, there are N periods in the idle phase and the active phase. In this way, the two-wire two-phase combinational logic circuit 230 is synchronized with the synchronous clock NCLK and the first-stage two-wire two-phase logic circuit 220-1 to the N-stage two-wire two-phase logic circuit 220. The operation can be performed so that the output data is determined after the input data is sequentially held until -M. In the two-wire two-phase logic circuits 220-1 to 220-M, the logic of the data supplied to the two-wire two-phase logic circuit 225 is different even if the timing at which the input data logic changes varies depending on the logic delay or wiring delay. The changing timings are made uniform by the latch circuit 226, and it is difficult for a difference to occur in the timing at which the logic of the output data changes.

  Therefore, according to the two-wire two-phase arithmetic circuit 200 using the two-wire two-phase combinational logic circuit 230, the timing at which the input data logically changes in the two-wire two-phase logic circuits 220-1 to 220-M is wired. Even if it differs depending on the delay or logic delay, it is difficult to form a power consumption pattern for the input data value, and high security against power analysis attacks can be ensured.

<< Embodiment 5 >>
FIG. 39 illustrates still another configuration of the two-wire two-phase combinational logic circuit 202 included in the two-wire two-phase arithmetic circuit 200 shown in FIG. In the following, description of functions and the like overlapping with the two-wire two-phase combinational logic circuit 230 illustrated in FIG. 36 will be omitted as appropriate. The two-wire two-phase combinational logic circuit 240 includes subordinate two-wire two-phase logic circuits 250-1 to 250-M in order to realize a desired logic operation. The two-wire two-phase logic circuits 250-1 to 250-M are connected in N stages by a two-wire two-phase combinational logic circuit 240, and the delay amount of each output data q is substantially the same in the same stage. Are arranged as follows. The two-wire two-phase combinational logic circuit 240 outputs data (DRI [1] to DRI [K]) using the two-wire two-phase code from the two-wire two-phase encoding circuit 21 and a synchronous clock signal (described later). PCLK [1] to PCLK [N]) and the like are input and data (q [1] to q [K]) using a two-wire two-phase code is output. The synchronous clock signals PCLK [1] to PCLK [N] are generated by the control circuit 15 illustrated in FIG. 2 and input in common to the same stages of the two-wire two-phase logic circuits 250-1 to 250-M. Has been. Here, the same stage is a 2-line 2-phase combinational logic circuit 240 in which the logic delays starting from the 2-stage 2-phase logic circuits 250-1 and 250-2 in the first stage are substantially the same. A state in which a two-phase logic circuit is arranged.

  FIG. 41 typically illustrates the configuration of a two-wire two-phase logic circuit 250-1. The two-wire two-phase logic circuit 250-1 includes an input connector to which data ((a0, a1), (b0, b1)) corresponding to the output data (DRI [1], DRI [2]) is input; It has a timing input terminal to which the synchronous clock signal PCLK [1] is input and an output connector to which output data (q0, q1) is output. The above-mentioned c and cn are also input. The two-wire two-phase logic circuit 250-1 is a two-wire two-phase AND logic circuit and is an input gate circuit as compared with the two-wire two-phase AND logic circuit 140 shown in FIG. The difference is that one input of the input NOR logic elements 141 to 144 is a synchronous clock signal PCLK [1], the absence of the delay circuit 157, and the like. In the 2-wire 2-phase logic circuit 250-1, since there is no delay circuit 157, a delay signal input to the timing input terminal of the next stage (for example, the second stage) is not generated. However, the synchronous clock signal PCLK [2] is input to the timing input terminal at the next stage instead of the delay signal.

  The period of the synchronous clock signal PCLK [1] is a logic composed of 2-input NAND logic elements 146 and 147, 3-input NAND logic elements 148 to 153, negation logic elements 154 and 155, etc. of the 2-wire 2-phase logic circuit 250-1. The delay amount is larger than the delay amount including the logic delay until the logic operation of the circuit is determined and the wiring delay between the two-wire two-phase logic circuits 250-1 and 250-3, for example. As shown in FIG. 40, the synchronous clock signals PCLK [1] to PCLK [N] are two-wire two-phase systems arranged in the same stage in the two-wire two-phase logic circuits 250-1 to 250-M. Each of the periods corresponding to the logic circuit has a different phase. In this way, in the two-wire two-phase combinational logic circuit 240, N stages of two-wire two-phase logic circuits to which the synchronous clocks PCLK [1] to PCLK [N] changing at N different phases correspond respectively. 250-1 to 250-M. The two-wire two-phase combinational logic circuit 240 is the N-th stage to which the synchronous clock PCLK [N] is input from the initial two-wire two-phase logic circuit 250-1 to which the synchronous clock PCLK [1] is input. The two-wire two-phase logic circuit 250-M operates in such a manner that the output is determined after the input is sequentially held.

  Further, when the synchronous clock signals PCLK [1] to PCLK [N] are 1, the 2-wire 2-phase logic circuits 250-1 to 250-M have the output data (q0, q1) of 1, and the synchronous clock signal If PCLK [1] to PCLK [N] are 0, output data (q0, q1) is obtained according to the Carnot diagram illustrated in FIG. 20 according to the input data ((a0, a1), (b0, b1)). To work. In short, in the two-wire two-phase logic circuits 250-1 to 250-M, even if the timing at which the logical change of the input data varies depending on the logic delay or wiring delay, it is synchronized with the synchronous clock signals PCLK [1] to PCLK [N]. Thus, the data a0 ′, a1 ′, b0 ′, b1 ′ having the same logic change timing are given to the logic circuit by the input gate circuit operating as described above. Therefore, in the two-wire two-phase logic circuits 250-1 to 250-M, it is difficult for a difference to occur in the timing at which the logic of the output data changes.

  FIG. 42 illustrates another configuration different from the two-wire two-phase logic circuit 250-1. The two-wire two-phase logic circuit 250-1A is a two-wire two-phase XOR logic circuit, and includes two-input NAND logic elements 168 to 173 as compared with the two-wire two-phase AND logic circuit shown in FIG. The other logic circuits are substantially the same. In other words, the two-wire two-phase logic circuit 250-1A has the same timing for changing the logic by the input gate circuit that operates in synchronization with the synchronous clock signal PCLK [1] even if the timing of the logic change of the input data is different. The data a0 ', a1', b0 ', b1' are given to the logic circuit, and it is difficult for a difference to occur in the timing at which the logic of the output data changes. Further, when the synchronous clock signals PCLK [1] to PCLK [N] are 1, the 2-wire 2-phase logic circuit 250-1A has the output data (q0, q1) of 1, and the synchronous clock signal PCLK [1]. When PCLK [N] is 0, the operation is performed so as to obtain the output data (q0, q1) according to the Carnot diagram illustrated in FIG. 21 according to the input data ((a0, a1), (b0, b1)). .

  Therefore, according to the two-wire two-phase arithmetic circuit 200 using the two-wire two-phase combinational logic circuit 240, the timing at which the input data logically changes in the two-wire two-phase logic circuits 250-1 to 250-M is wired. Even if it differs depending on the delay or logic delay, it is difficult to form a power consumption pattern for the input data value, and high security against power analysis attacks can be ensured.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary.

  For example, in the two-wire two-phase encoding circuit 20 illustrated in FIG. 4, the clear of the two-wire two-phase code is (1, 1), but the present invention is not limited to this. For example, when the clearing of the two-wire two-phase code is (0, 0), the two-input OR logic elements 52-1 to 52-n and 53-1 to the two-wire two-phase coding circuit 20 are used. 53-n may be changed to a 2-input AND logic element, and the logic value of the control signal CTRL may be negated.

  Further, as the two-wire two-phase logic circuit included in the two-wire two-phase combinational logic circuit 22, two-wire two-phase AND logic circuits 70 and 80 are illustrated in FIGS. Although the two-phase XOR logic circuits 90 and 100 are illustrated, the present invention is not limited to this. That is, the two-wire two-phase OR logic circuit is compared with the two-wire two-phase AND logic circuit 70 for input data (a0, a1), input data (b0, b1), and output data (q0, q1). Two corresponding wirings can be reversed, for example, by replacing a0 with a1 and a1 with a0. Similarly, the two-wire two-phase NOR logic circuit can be configured by reversing two wirings respectively corresponding to the output data (q0, q1) with respect to the two-wire two-phase OR logic circuit. The 2-wire 2-phase NAND logic circuit can be configured by reversing two wires corresponding to the output data (q0, q1) with respect to the 2-wire 2-phase AND logic circuit 70, respectively. Similarly, the 2-wire 2-phase XNOR logic circuit converts the input data (a0, a1), input data (b0, b1), and output data (q0, q1) to the 2-wire 2-phase XOR logic circuit 90. It can be configured by reversing two corresponding wires.

  Further, as the 2-wire 2-phase logic circuit, a configuration using a primitive gate is illustrated. According to this, a layout design can be performed using an existing cell library, the LSI design period can be shortened, and the circuit scale can be reduced. However, the present invention is not limited to this, and a two-wire two-phase logic circuit can be configured as a composite gate. For example, the two-wire two-phase AND logic circuit 70 and the two-wire two-phase XOR logic circuit 90 exemplified in the first embodiment can be composed of composite gates as shown in FIGS. Further, the two-wire two-phase AND logic circuit 130 illustrated in the second embodiment can be configured by a composite gate as illustrated in FIG. 24 or FIG. Furthermore, the two-wire two-phase XOR logic circuit 110 illustrated in the second embodiment can be configured by a composite gate as illustrated in FIG. 25 or FIG. In this way, since the number of transistors constituting the two-wire two-phase logic circuit can be reduced, the circuit scale can be reduced and the power consumption can be reduced.

  Furthermore, the two-wire two-phase AND logic circuit 140 illustrated in the third embodiment can be configured with a composite gate. FIG. 45 illustrates a two-wire two-phase AND logic circuit 140 composed of composite gates. In the following, functions and the like that are the same as those of the 2-wire 2-phase AND logic circuit 140 illustrated in FIG. The two-wire two-phase AND logic circuit 140 has a configuration using primitive gates such as NAND logic elements and NOR logic elements in FIG. 33, but here, a composite gate composed of CMOS is exemplified. Here, the clear value of the two-wire two-phase code in the two-wire two-phase AND logic circuit 140 is (0, 0). The two-wire two-phase AND logic circuit 140 includes pMOS transistors (p1 to p4), nMOS transistors (n1 to n17), negative logic elements 301 and 302, and the like.

  FIG. 46 illustrates the relationship between the input values of nMOS transistors (n4 to n17) other than the nMOS transistors (n1 to n3) and the nMOS transistors that are turned on. Input a corresponds to input data (a0, a1), input b corresponds to input data (b0, b1), and q corresponds to output data (q0, q1). In the two-wire two-phase AND logic circuit 140, the number of nMOS transistors that are turned on is three regardless of the input value, so the on-resistance of the nMOS transistor is constant. This means that even if the output is logic 1 or logic 0, the discharge current pattern from the load capacity of each output is the same. Therefore, even when the two-wire two-phase AND logic circuit 140 is configured with such a composite gate, it is difficult to form a power consumption pattern for an input value, and high safety against a power analysis attack can be ensured. Further, if the two-wire two-phase AND logic circuit 140 is formed of such a composite gate, the number of transistors can be reduced, so that the circuit scale can be reduced and the power consumption can be reduced.

  Further, in the two-wire two-phase AND logic circuits 70 and 80 and the two-wire two-phase XOR logic circuits 90 and 100 without the switching signal MODE according to the first embodiment, the output is performed regardless of whether the output is logic 1 or logic 0. In order to make the discharge current patterns from the load capacitors substantially the same, the on-resistances of the nMOS transistors may be arranged to be the same. Further, in the two-wire two-phase AND logic circuit 140 and the two-wire two-phase XOR logic circuit 160 in the third embodiment, the configuration using the switching signal MODE is illustrated, but the configuration is not limited thereto, and the switching signal MODE is not limited to this. It is good also as a structure which is not used.

  Furthermore, in the above-described 2-wire 2-phase AND logic circuit 140 and 2-wire 2-phase XOR logic circuit 160, an example in which 2-bit data is input and 1-bit data is output is shown, but the present invention is not limited thereto. The bit may correspond to an appropriate bit. As an example, a two-wire two-phase AND logic circuit or a two-wire two-phase XOR logic circuit in which 32-bit data is input and 16-bit data is output may be formed. In this case, instead of the 2-input NAND logic element 145 and the 2-input NOR logic element 165, a 32-input NAND logic element and a 32-input NOR logic element may be used, and the delay signals B and B1 may be used for each bit, that is, It is sufficient to output 16 outputs. Further, according to the present invention, the power consumption generated during the arithmetic processing can be made constant regardless of the value of the input data, and further, the power consumption can be made constant even at the time of computation. The present invention can be applied to an appropriate arithmetic device that is indispensable to obtain high security against power analysis attacks using the correlation of power.

It is a figure which illustrates the structure of the IC card chip which is an example of the semiconductor integrated circuit which concerns on Embodiment 1 of this invention. It is explanatory drawing which illustrates the structure of the encryption coprocessor shown in FIG. FIG. 3 is an explanatory diagram illustrating the configuration of a two-wire two-phase arithmetic circuit that is an example of the logical arithmetic circuit according to the first embodiment of the invention. FIG. 4 is an explanatory diagram illustrating a configuration of a two-wire two-phase encoding circuit illustrated in FIG. 3. FIG. 4 is an explanatory diagram illustrating the configuration of the two-wire / one-wire conversion circuit shown in FIG. 3. FIG. 4 is a timing chart showing an operation of the two-wire two-phase arithmetic circuit shown in FIG. 3. FIG. 4 is an explanatory diagram illustrating a configuration of a two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit illustrated in FIG. 3. FIG. 4 is an explanatory diagram illustrating a configuration of a two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit illustrated in FIG. 3. FIG. 4 is an explanatory diagram illustrating the configuration of another 2-wire 2-phase AND logic circuit included in the 2-wire 2-phase combinational logic circuit shown in FIG. 3. FIG. 4 is an explanatory diagram illustrating the configuration of still another two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit shown in FIG. 3. FIG. 8 is a Carnot diagram illustrating the operation of the two-wire two-phase AND logic circuit shown in FIG. 7. FIG. 9 is a Carnot diagram illustrating the operation of the two-wire two-phase XOR logic circuit illustrated in FIG. 8. FIG. 10 is a Carnot diagram illustrating the operation of another two-wire two-phase AND logic circuit shown in FIG. 9. FIG. 11 is a Carnot diagram illustrating the operation of still another two-wire two-phase XOR logic circuit illustrated in FIG. 10. It is explanatory drawing which illustrates the structure of the 2 line | wire 2 phase type arithmetic circuit which is an example of the logic arithmetic circuit which concerns on Embodiment 2 of this invention. FIG. 16 is an explanatory diagram illustrating the configuration of a negative logic circuit illustrated in FIG. 15. 16 is a timing chart showing the operation of the two-wire two-phase arithmetic circuit shown in FIG. FIG. 16 is an explanatory diagram illustrating a configuration of a two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit illustrated in FIG. 15. FIG. 16 is an explanatory diagram illustrating a configuration of a two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit illustrated in FIG. 15. FIG. 19 is a Carnot diagram illustrating the operation of the two-wire two-phase AND logic circuit shown in FIG. 18. FIG. 20 is a Carnot diagram illustrating the operation of the two-wire two-phase XOR logic circuit illustrated in FIG. 19. FIG. 8 is an explanatory diagram illustrating a configuration when the two-wire two-phase AND logic circuit illustrated in FIG. 7 is configured with a composite gate. FIG. 9 is an explanatory diagram illustrating a configuration when the two-wire two-phase XOR logic circuit illustrated in FIG. 8 is configured with a composite gate. It is explanatory drawing which illustrates the structure at the time of comprising the 2 line | wire 2 phase type AND logic circuit shown in FIG. 18 with a composite gate. FIG. 20 is an explanatory diagram illustrating a configuration when the two-wire two-phase XOR logic circuit illustrated in FIG. 19 is configured with a composite gate. FIG. 4 is an explanatory diagram illustrating a correspondence relationship between a logical value and a two-wire two-phase code for the two-wire two-phase arithmetic circuit illustrated in FIG. 3. It is explanatory drawing which illustrates the relationship of the input and output about a 2 wire 2 phase type | mold AND logic circuit shown in FIG. 7 with a 2 wire 2 phase code | symbol. FIG. 16 is an explanatory diagram illustrating a correspondence relationship between a logical value and a two-wire two-phase code for the two-wire two-phase arithmetic circuit illustrated in FIG. 15. It is explanatory drawing which shows the example which a difference produces in the timing to which the logic of output data changes by wiring delay difference. It is explanatory drawing which illustrates the structure of the 2 line | wire 2 phase type arithmetic circuit which is an example of the logic arithmetic circuit which concerns on Embodiment 3 of this invention. FIG. 31 is an explanatory diagram illustrating the configuration of a synchronization generation circuit shown in FIG. 30. It is explanatory drawing which illustrates the input-output correspondence regarding a synchronous production | generation circuit. FIG. 31 is an explanatory diagram illustrating the configuration of a two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit shown in FIG. 30; FIG. 34 is a timing chart showing an operation of the two-wire two-phase AND logic circuit shown in FIG. 33. FIG. 31 is an explanatory diagram illustrating the configuration of a two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit shown in FIG. 30; FIG. 16 is an explanatory diagram illustrating another configuration of the two-wire two-phase combinational logic circuit illustrated in FIG. 15. 37 is a timing chart showing an operation of the two-wire two-phase combinational logic circuit shown in FIG. 36. FIG. 37 is an explanatory diagram illustrating the configuration of a two-wire two-phase logic circuit included in the two-wire two-phase combinational logic circuit shown in FIG. 36. FIG. 16 is an explanatory diagram illustrating still another configuration of the two-wire two-phase combinational logic circuit illustrated in FIG. 15. 40 is a timing chart showing an operation of the two-wire two-phase combinational logic circuit shown in FIG. 39. FIG. 40 is an explanatory diagram illustrating the configuration of a two-wire two-phase AND logic circuit included in the two-wire two-phase combinational logic circuit illustrated in FIG. 39. FIG. 40 is an explanatory diagram illustrating a configuration of a two-wire two-phase XOR logic circuit included in the two-wire two-phase combinational logic circuit illustrated in FIG. 39. FIG. 19 is an explanatory diagram illustrating another configuration when the two-wire two-phase AND logic circuit illustrated in FIG. 18 is configured with a composite gate. FIG. 20 is an explanatory diagram illustrating another configuration when the two-wire two-phase XOR logic circuit illustrated in FIG. 19 is configured with a composite gate. FIG. 34 is an explanatory diagram exemplifying a configuration when the two-wire two-phase AND logic circuit shown in FIG. 33 is configured by a composite gate. FIG. 46 is an explanatory diagram illustrating the relationship between the input value of the 2-wire 2-phase AND logic circuit shown in FIG. 45 and the nMOS transistor that is turned on;

Explanation of symbols

1 IC card chip 2 I / O circuit 3 CPU
DESCRIPTION OF SYMBOLS 4 Control circuit 5 Data memory 6 Program memory 7 Cryptographic coprocessor 8 Data bus 10 Bus conversion circuit 11 Data register 14,200 Two-wire two-phase arithmetic circuit 20 Two-wire two-phase encoding circuit 22,202,207,230,240 Two-wire two-phase combinational logic circuit 23 Two-wire one-wire conversion circuit 70, 80, 130, 140, 180 Two-wire two-phase AND logic circuit 90, 100, 110, 160, 190 Two-wire two-phase XOR logic circuit 201 Negative logic circuit 206 Synchronization generation circuit

Claims (16)

A semiconductor integrated circuit having a processor that executes an encryption algorithm using an encryption key and encrypts desired secret information,
The processor has two lines for defining input data using a one-line one-phase code, which is the secret information, in a bit unit, a first signal indicating a logical value 1 and a second signal indicating a logical value 0 A two-wire two-phase encoding circuit for converting data using two-phase code;
A plurality of two-wire two-phase logic circuits that perform a logical operation corresponding to the two-wire two-phase code, and a two-wire two-phase combinational logic circuit that encrypts the input data,
The two-wire two-phase logic circuit has a plurality of input connectors composed of a first signal line and a second signal line corresponding to the two-wire two-phase code, and an output connector, and all the input connectors Is input to the input connector only when transitioning from the initial state in which a clear signal, which is invalid information, is input to the valid state in which the first signal or the second signal is input to all the input connectors A semiconductor integrated circuit that inverts a logical value a predetermined number of times by a predetermined logical function and outputs the first signal or the second signal to the output connector.   2. The semiconductor integrated circuit according to claim 1, further comprising: a two-wire one-line conversion circuit that converts data using the two-wire two-phase code output from the output connector into data using the one-wire one-phase code.   If the clear signal is input to at least one of the input connectors during the transition from the initial state to the valid state, the two-wire two-phase logic circuit outputs the clear signal to the output connector. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit outputs the data.   4. The semiconductor integrated circuit according to claim 1, wherein the two-wire two-phase logic circuit repeats a transition from the initial state to the valid state.   When the two-wire two-phase logic circuit transitions from the initial state to the valid state in response to a mode signal that switches the correspondence relationship between the clear signal, the first signal, and the second signal and a logical value. 5. The semiconductor integrated circuit according to claim 1, wherein the first signal line and the second signal line whose logic values change are switched.   6. The semiconductor integrated circuit according to claim 5, further comprising a negative logic circuit that inverts a logical value at a front stage and a rear stage of the two-wire two-phase combinational logic circuit, wherein the negative logic circuit is enabled or disabled by the mode signal. circuit.   7. The semiconductor integrated circuit according to claim 6, wherein the mode signal enables the negative logic circuit after the two-wire two-phase logic circuit is in the initial state.   The mode signal is randomly selected so that the probability that the logical values of the first signal line and the second signal line change is substantially the same during the calculation period in the two-wire two-phase logic circuit. 8. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is switched. A control circuit for generating a control signal for controlling the two-wire two-phase encoding circuit;
2. The semiconductor according to claim 1, wherein the two-wire two-phase encoding circuit changes a timing of outputting the clear signal, the first signal, and the second signal by the two-wire two-phase code in accordance with the control signal. Integrated circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the two-wire two-phase logic circuit is composed of a composite gate.   The two-wire two-phase logic circuit is synchronized with a timing signal that defines a later timing among timings at which data input to the first signal line and the second signal line change in logic. 2. The semiconductor integrated circuit according to claim 1, wherein a logical operation corresponding to the two-wire two-phase code is started. The two-wire two-phase combinational logic circuit has a plurality of the two-wire two-phase logic circuits connected in cascade,
The two-wire two-phase logic circuit includes an input gate circuit that captures data given to the input connector in synchronization with a timing signal that changes most slowly among a plurality of timing signals given to a timing input terminal;
A logic circuit that receives data taken in by the input gate circuit and performs a logic operation;
A delay circuit that generates a timing signal obtained by delaying the slowest change timing signal by a predetermined time from the timing at which the logic operation of the logic circuit is determined;
The timing signal generated by the delay circuit is output from a timing output terminal and is provided to the timing input terminal of the two-wire two-phase logic circuit in the subsequent stage,
2. The semiconductor integrated circuit according to claim 1, wherein the predetermined time is longer than a wiring delay between the two-wire two-phase logic circuits. First timing generation for generating a first timing signal indicating a timing of transition from the initial state to the valid state for each bit of data using the two-wire two-phase code output from the two-wire two-phase encoding circuit Further comprising a circuit;
The two-wire two-phase logic circuit in the first stage inputs the first timing signal for each bit of data applied to the input connector, and the first timing that is the slowest change among the input first timing signals. A second timing generation circuit that generates a second timing signal that changes in synchronization with the signal;
13. The semiconductor device according to claim 12, wherein the input gate circuit of the two-wire two-phase logic circuit in the next stage supplies data using the two-wire two-phase code to the logic circuit in synchronization with the second timing signal. Integrated circuit. The clear signal is “1, 1”, the first signal is “1, 0”, the second signal is “0, 1”,
The semiconductor integrated circuit according to claim 13, wherein the first timing generation circuit includes a gate circuit that determines that a logical value of two inputs is different for each bit of data using the two-wire two-phase code. The two-wire two-phase combinational logic circuit has a plurality of the two-wire two-phase logic circuits connected in cascade,
The two-wire two-phase logic circuit latches data applied to the input connector in synchronization with a clock signal applied to a timing input terminal;
A logic circuit that receives the data latched in the latch circuit and performs a logic operation;
The clock signal is input in common to all the latch circuits,
2. The semiconductor integrated circuit according to claim 1, wherein the period of the clock signal is larger than a delay amount including a logic delay until a logic operation of the logic circuit is determined and a wiring delay between the two-wire two-phase logic circuits. . The two-wire two-phase combinational logic circuit has a plurality of the two-wire two-phase logic circuits connected in cascade,
The two-wire two-phase logic circuit includes a gate circuit that outputs data given to the input connector in synchronization with a clock signal given to a timing input terminal;
A logic circuit that receives data output from the gate circuit and performs a logic operation;
The clock signal is input in common to the gate circuit of the two-wire two-phase logic circuit arranged in the same stage where the logic delay starting from the first two-wire two-phase logic circuit is substantially the same. The phase is different for each stage,
2. The semiconductor integrated circuit according to claim 1, wherein the period of the clock signal is larger than a delay amount including a logic delay until a logic operation of the logic circuit is determined and a wiring delay between the two-wire two-phase logic circuits. .

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