JP2008066532A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an upper electrode contact plug with stable contact resistance without causing charge-up damage to a capacitor. <P>SOLUTION: The device has: a lower electrode 108 formed in a bottom part and a side wall part of a first hole in a first layer insulating film 105 formed on a semiconductor substrate 100; a capacity insulating film 109 covering the lower electrode 108; an upper electrode 110 covering the capacity insulating film 109; an upper electrode contact part 112 which is formed in a bottom part and a side wall part of a second hole in the first layer insulating film 105 by extending a conductive film constituting the upper electrode 110; a second layer insulating film 114 formed on the first layer insulating film 105, the upper electrode 110 and the upper electrode contact part 112; and an upper electrode contact plug 120 which passes through the second layer insulating film 114 and is buried in the first contact hole reaching the upper electrode contact part 112. The second hole has an opening diameter larger than an opening diameter of the first hole. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a capacitor and a manufacturing method thereof.

  In recent years, along with higher integration, higher functionality, and higher speed of semiconductor integrated circuit devices, reduction of the area occupied by capacitors in a chip such as a DRAM (Dynamic Random Access Memory) has been demanded. On the other hand, for stable operation of the memory unit, it is necessary to realize a capacitor that secures a certain capacitance value. Therefore, as represented by, for example, a capacitor having a cylinder type or concave type structure, the capacitor structure is three-dimensional to increase the capacitor electrode area, thereby securing a sufficient capacitance value while reducing the capacitor occupation area. The capacitor is realized.

  However, when the semiconductor integrated circuit device is reduced in size, a step generated between the cell array region and the peripheral circuit region after the upper electrode forming step causes a processing defect in the subsequent metal wiring forming step. There is.

  Therefore, it has been proposed to reduce the thickness of the upper electrode in order to reduce the level difference between the cell array region and the peripheral circuit region. The semiconductor device according to the first conventional example will be described below with reference to FIG. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device according to the first conventional example.

  As shown in FIG. 9, the semiconductor device according to the first conventional example includes, as main components, a semiconductor substrate 500, a first interlayer insulating film 501, an etching stopper film 504, a second interlayer insulating film 505, and a second interlayer insulating film 505. Three-dimensional capacitor 511, in which three interlayer insulating film 513, lower electrode contact plug 502, peripheral circuit contact plug 503, lower electrode 508, capacitive insulating film 509 and upper electrode 510 are sequentially stacked in the capacitor forming hole. An upper electrode contact portion 512 in which a capacitor insulating film extending portion 509a and an upper electrode extending portion 510a are sequentially stacked, an upper electrode contact plug 517 in which a conductive film is embedded in the upper electrode contact hole, and the periphery Provided is a peripheral circuit contact plug 516 in which a conductive film is embedded in a circuit contact hole. There.

  Here, in the semiconductor device according to the first conventional example, the cell array region (that is, the region including the three-dimensional capacitor 511 formation region and the upper electrode contact portion 512 formation region) and the peripheral circuit region (that is, the peripheral circuit contact plug). The upper electrode 510 is thinned for the purpose of reducing the step D generated between the region 503 and the region including the region 516). Therefore, in the step of forming the upper electrode contact hole, the upper electrode contact hole not only penetrates the third interlayer insulating film 513 and reaches the upper electrode extension portion 510a. Since the penetrating portion 517a is formed in the upper electrode contact plug 517, as shown in FIG. 9, the penetrating portion 510a and the capacitor insulating film extending portion 509a are penetrated to reach the second interlayer insulating film 505. The problem arises that the contact resistance becomes unstable.

  In order to obtain stable contact resistance by preventing the upper electrode contact hole from penetrating, it has been proposed to make the upper electrode contact portion structure three-dimensional like the capacitor structure. Hereinafter, a method of manufacturing a semiconductor device having a contact portion for a three-dimensional upper electrode will be described with reference to FIGS. 10 (a) to (d) and FIGS. 11 (a) to (c) (for example, Patent Document 1). reference). 10 (a) to 10 (d) and FIGS. 11 (a) to 11 (c) are principal part process sectional views showing the semiconductor device manufacturing method according to the second conventional example.

  First, as shown in FIG. 10A, after a first interlayer insulating film 601 is formed on a semiconductor substrate 600 made of silicon, the first interlayer insulating film 601 is formed on the first interlayer insulating film 601 by lithography and dry etching. Each of the lower electrode contact hole and the peripheral circuit contact hole that penetrates the interlayer insulating film 601 and exposes the semiconductor substrate 600 is formed. Thereafter, each of the lower electrode contact plug 602 and the peripheral circuit contact plug 603 is embedded by embedding, for example, a tungsten film, a titanium film, or a titanium nitride film in each of the lower electrode contact hole and the peripheral circuit contact hole. Form. Subsequently, an etching stopper film 604 and a second interlayer insulating film 605 are sequentially formed on the first interlayer insulating film 601 and the contact plugs 602 and 603.

  Next, as shown in FIG. 10B, the lower electrode contact plug 602 is exposed through the etching stopper film 604 and the second interlayer insulating film 605 through the second interlayer insulating film 605 and the etching stopper film 604. The capacitor forming hole 606 is formed, and the first interlayer insulating film 601 is exposed through the second interlayer insulating film 605 and the etching stopper film 604 in the etching stopper film 604 and the second interlayer insulating film 605. A contact forming hole 607 is formed.

  Next, as shown in FIG. 10C, a lower electrode formation film made of, for example, a titanium nitride film is formed on the bottom and side walls of the holes 606 and 607 and the upper surface of the second interlayer insulating film 605. Subsequently, a desired portion in the lower electrode formation film is selectively removed by performing a CMP process or an entire etch back process. Thus, the lower electrode 608 is formed on the bottom and side walls of the capacitor forming hole 606, and the lower electrode extension 608a is formed on the bottom and side walls of the contact forming hole 607.

  Next, as shown in FIG. 10 (d), on the second interlayer insulating film 605, a capacitive insulating film forming film and an upper electrode forming film made of, for example, a titanium nitride film so as to cover the holes 606 and 607 are covered. Are sequentially formed. Subsequently, portions existing on the second interlayer insulating film 605 in the peripheral circuit region in the upper electrode forming film and the capacitor insulating film forming film are sequentially removed by lithography and dry etching. In this way, the three-dimensional capacitor 611 in which the lower electrode 608, the capacitor insulating film 609, and the upper electrode 610 are sequentially stacked in the capacitor forming hole 606 is formed, and the lower portion in the contact portion forming hole 607 is formed in the lower portion. The electrode extension 608a, the capacitive insulating film extension 609a, and the upper electrode extension 610a are sequentially stacked to form a three-dimensional upper electrode contact 612. At this time, a step D is generated between the cell array region (that is, the region including the three-dimensional capacitor 611 formation region and the three-dimensional upper electrode contact portion 612 formation region) and the peripheral circuit region.

  Next, as shown in FIG. 11A, a third interlayer insulating film 613 is formed on the second interlayer insulating film 605, the three-dimensional capacitor 611, and the three-dimensional upper electrode contact portion 612. Subsequently, planarization processing of the third interlayer insulating film 613 is performed by CMP processing. This eliminates the step between the cell array region and the peripheral circuit region.

  Next, as shown in FIG. 11B, a third interlayer insulating film 613, a second interlayer insulating film 613, an etching stopper film 604, a second interlayer insulating film 605, and a third interlayer insulating film 613 are formed by lithography and dry etching. A peripheral circuit contact hole 614 that penetrates the second interlayer insulating film 605 and the etching stopper film 604 and exposes the peripheral circuit contact plug 603 is formed, and the third interlayer insulating film 613 is formed in the third interlayer insulating film 613. Then, an upper electrode contact hole 615 that penetrates through and reaches the inside of the three-dimensional upper electrode contact portion 612 is formed.

  Next, as shown in FIG. 11 (c), for example, a tungsten film, a titanium film, or a titanium nitride film is embedded in each of the peripheral circuit contact hole 614 and the upper electrode contact hole 615, thereby forming a peripheral circuit contact hole. Each of the contact plug 616 and the upper electrode contact plug 617 is formed.

  As described above, the semiconductor device according to the second conventional example can be manufactured.

According to the second conventional example, the three-dimensional upper electrode contact portion 612 includes a lower electrode extension portion 608a, a capacitor insulating film extension portion 609a, and an upper electrode extension portion 610a in the contact portion forming hole 607 in order. Has an embedded configuration. Therefore, as shown in FIG. 11B, when the upper electrode contact hole 615 is formed, the upper electrode contact hole 615 includes the upper electrode extending portion 610a, the capacitive insulating film extending portion 609a, and the lower electrode. Since the extended portion 608a does not penetrate into the second interlayer insulating film 605, the upper electrode contact hole 615 can be prevented from penetrating. Therefore, as shown in FIG. 11C, an upper electrode contact plug 617 having a stable contact resistance can be obtained. Thus, in the second conventional example, the upper electrode contact hole 615 can be prevented from penetrating by making the upper electrode contact portion 612 three-dimensional.
JP 2002-26144 A

  However, the semiconductor device according to the second conventional example has the following problems.

  In the semiconductor device manufacturing method according to the second conventional example, the step of forming the peripheral circuit contact hole 614 and the step of forming the upper electrode contact hole 615 are performed in the same process. Here, the upper electrode contact hole 615 penetrates the third interlayer insulating film 613 and reaches the upper electrode contact portion 612, whereas the peripheral circuit contact hole 614 This is a contact hole that passes through the interlayer insulating film 613, the second interlayer insulating film 605, and the etching stopper film 604 and reaches the peripheral circuit contact plug 603. Therefore, the upper electrode extension portion 610a (upper electrode contact portion 612) exposed in the upper electrode contact hole 615 after the formation of the upper electrode contact hole 615 is a period until the peripheral circuit contact hole 614 is formed. , Exposed to plasma and etching gas. Due to this excessive exposure, the three-dimensional capacitor 611 is subjected to charge-up damage, and the withstand voltage of the capacitive insulating film 609 is deteriorated.

  In particular, when the capacitor occupation area is further reduced, it is necessary to enlarge the capacitor electrode area for the purpose of realizing a capacitor having a certain capacitance value or more. However, if the thickness of the second interlayer insulating film 605 is increased and the height of the lower electrode 608 is increased for the purpose of increasing the capacitor electrode area, the third interlayer insulating film 613 is increased in thickness. The peripheral circuit contact hole 614 that passes through the second interlayer insulating film 605 and the etching stopper film 604 and reaches the peripheral circuit contact plug 603 must be formed, and the upper electrode extension exposed in the upper electrode contact hole 615 must be formed. The installation portion 610a is further excessively exposed by the plasma and the etching gas, and the three-dimensional capacitor 611 is further subjected to charge-up damage.

In particular, when the area occupied by the capacitor is further reduced, a high dielectric film such as TaO _x , HfO _x , or ZrO _{x is used} as a capacitor insulating film for the purpose of realizing a capacitor that secures a capacitance value above a certain level. It is necessary to adopt. However, when a high dielectric film is used as the capacitor insulating film, the high dielectric film has a lower withstand voltage than conventional capacitor insulating films such as SiO ₂ or SiN, and therefore suppresses the charge-up damage to the capacitor as much as possible. There is a need.

  In view of the foregoing, an object of the present invention is to provide a semiconductor device including a contact plug for an upper electrode having stable contact resistance without causing charge-up damage to a capacitor, and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to the present invention is formed on a semiconductor substrate, and includes a first interlayer insulating film having a first hole and a second hole, and a bottom and a side wall of the first hole. A lower electrode made of a conductive film formed on the substrate, a capacitor insulating film covering the lower electrode, an upper electrode made of a conductive film covering the capacitor insulating film, and an upper electrode formed on the bottom and side walls of the second hole. An upper electrode contact portion formed by extending a conductive film constituting the first interlayer insulating film, an upper electrode, a second interlayer insulating film formed on the upper electrode contact portion, and a second interlayer insulating film An upper electrode contact plug made of a conductive film embedded in the first contact hole that penetrates the interlayer insulating film and reaches the upper electrode contact portion, and the second hole has an opening diameter of the first hole Has a larger opening diameter than Cage, characterized in that the contact plug for the upper electrode and the upper electrode are electrically connected.

  According to the semiconductor device of the present invention, the conductive film constituting the upper electrode is extended on the bottom and side walls of the second hole having an opening diameter larger than the opening diameter of the first hole. A U-shaped upper electrode contact portion (that is, a contact portion having a hole forming opening having a desired opening diameter) is formed. As a result, the upper electrode contact plug is in contact with the U-shaped upper electrode contact portion (in other words, the upper electrode contact portion exposed in the hole forming opening), so that a stable contact resistance can be obtained. Can do.

  In addition, according to the semiconductor device of the present invention, the capacitor is not subjected to charge-up damage due to dry etching during the first contact hole forming step, so that the breakdown voltage of the capacitor insulating film is prevented from deteriorating. can do.

  The semiconductor device according to the present invention preferably further includes a contact plug made of a conductive film embedded in a second contact hole penetrating the first interlayer insulating film and the second interlayer insulating film.

  In this case, the capacitor is not subjected to charge-up damage during the second contact hole formation step, and thus it is possible to suppress the breakdown voltage of the capacitor insulating film from being deteriorated.

  In the semiconductor device according to the present invention, the step generated between the contact surface of the conductive film constituting the upper electrode with the second interlayer insulating film and the contact surface of the conductive film with the contact plug for the upper electrode is 5 nm or less. It is preferable that

  As described above, in the semiconductor device according to the present invention, wet etching is employed instead of dry etching in the first contact hole forming step, so that the conductive film (in other words, the upper electrode contact portion) The conductive film constituting the upper electrode is not etched away.

  Therefore, a contact surface of the conductive film constituting the upper electrode with the second interlayer insulating film (in other words, a portion not exposed during the first contact hole forming step on the surface of the conductive film), and the conductive film The step difference between the contact surface with the upper electrode contact plug (in other words, the exposed portion of the surface of the conductive film during the first contact hole forming step) is 5 nm or less.

  In the semiconductor device according to the present invention, the shape of the portion present in the second interlayer insulating film in the upper electrode contact plug has a shape in which the inner diameter increases after the inner diameter decreases from the lower end toward the upper end. It is preferable.

  In the semiconductor device according to the present invention, the portion of the upper electrode contact plug existing in the second interlayer insulating film has a shape in which the inner diameter increases from the lower end toward the upper end. Is preferred.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a first hole in the first interlayer insulating film. Forming a second hole having an opening diameter larger than the opening diameter of the first hole in the first interlayer insulating film, and forming a lower portion on the bottom and side walls of the first hole; A step (c) of forming an electrode, a step (d) of forming a capacitive insulating film so as to cover the lower electrode, an upper electrode so as to cover the capacitive insulating film, and the bottom and side walls of the second hole After the step (e) and the step (e) of forming the upper electrode contact portion in which the conductive film constituting the upper electrode is continuously formed so as to have a hole forming opening in the portion, the first step A step (f) of forming a second interlayer insulating film on the interlayer insulating film; A step (g) of forming a first contact hole in the second interlayer insulating film through the second interlayer insulating film and exposing the upper electrode contact portion by etching, and conducting in the first contact hole; A step (h) of forming a contact plug for an upper electrode by embedding a film, and the step (f) includes forming a hole in a portion embedded in the hole forming opening in the second interlayer insulating film. Including a step of forming, wherein the step (g) includes a step of forming a first contact hole made of a hole.

  According to the method for manufacturing a semiconductor device of the present invention, it is desirable that the second hole having a larger opening diameter than the first hole (the second hole having a desired opening diameter) be formed on the bottom and side walls. An upper electrode contact portion in which conductive films constituting the upper electrode are continuously formed can be formed so as to have a hole forming opening having an opening diameter of. Thus, a desired void (void) is formed in a portion of the second interlayer insulating film embedded in the hole forming opening of the upper electrode contact portion in the second interlayer insulating film forming step. Can be formed. Furthermore, the first contact hole that exposes the upper electrode contact portion can be easily formed using the holes.

  In addition, according to the method of manufacturing a semiconductor device according to the present invention, the first contact hole forming process is performed by wet etching instead of dry etching. Therefore, the capacitor is dry etched during the first contact hole forming process. Therefore, the deterioration of the breakdown voltage of the capacitor insulating film can be suppressed.

  According to the method for manufacturing a semiconductor device of the present invention, the upper electrode contact plug is in contact with the upper electrode contact portion exposed in the first contact hole (in other words, in the hole forming opening). In addition, unlike the conventional example, the first contact hole does not penetrate the upper electrode contact portion during the first contact hole forming step, so that stable contact resistance can be obtained.

  In the method of manufacturing a semiconductor device according to the present invention, after the step (g) and before the step (h), the first interlayer insulating film and the second interlayer insulating film are provided with a second interlayer. A step (i) of forming a second contact hole penetrating the insulating film and the first interlayer insulating film, wherein the step (h) embeds the conductive film in the second contact hole, thereby forming the contact plug; It is preferable to further include the step of forming.

  By doing so, the first contact hole forming step is performed before the second contact hole forming step so that the resist film is embedded in the first contact hole and the second contact hole is formed. A hole forming step can be performed. Therefore, the upper electrode contact portion is not exposed in the first contact hole during the second contact hole forming step, and the upper electrode exposed in the first contact hole as in the conventional example. For example, the contact portion for the product is not exposed to plasma and etching gas. For this reason, since the capacitor is not subjected to charge-up damage, it is possible to prevent the breakdown voltage of the capacitor insulating film from deteriorating.

  In the method for manufacturing a semiconductor device according to the present invention, the step (f) preferably includes a step of forming a second interlayer insulating film made of a silicon oxide film by a CVD method.

  In the method for manufacturing a semiconductor device according to the present invention, the step (g) includes a step of forming a first contact hole by exposing a hole to the surface of the second interlayer insulating film by a CMP process. It is preferable.

  In this way, for example, the shape of the portion present in the second interlayer insulating film in the upper electrode contact plug is such that the inner diameter increases after the inner diameter decreases from the lower end toward the upper end. A contact plug for the upper electrode can be formed.

  In the method of manufacturing a semiconductor device according to the present invention, an opening is formed on the second interlayer insulating film above the vacancy after the step (f) and before the step (g). A step (j) of forming a protective film having a portion, and the step (g) forms a hole penetrating the second interlayer insulating film and communicating with the hole by wet etching using the protective film as a mask. A step of removing the protective film (k) after the step (g) and before the step (i), including the step of forming a first contact hole comprising holes and holes. ).

  In this case, for example, the upper electrode contact plug is formed such that the portion of the upper electrode contact plug existing in the second interlayer insulating film has a shape in which the inner diameter increases from the lower end toward the upper end. Can be formed.

  In the method for manufacturing a semiconductor device according to the present invention, the protective film is preferably a photoresist film.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, the first contact hole (upper electrode contact hole) is formed by wet etching instead of dry etching. Since the capacitor is not subjected to charge-up damage due to dry etching, it is possible to suppress the deterioration of the breakdown voltage of the capacitor insulating film. Furthermore, the resist film is embedded in the first contact hole by performing the first contact hole forming step before the second contact hole (for example, peripheral circuit contact hole) forming step. Thus, the second contact hole forming step can be performed. Therefore, the upper electrode contact portion is not exposed in the first contact hole during the second contact hole forming step, and the upper electrode exposed in the first contact hole as in the conventional example. For example, the contact portion for the product is not exposed to plasma and etching gas. For this reason, since the capacitor is not subjected to charge-up damage, it is possible to prevent the breakdown voltage of the capacitor insulating film from deteriorating.

  In addition, according to the semiconductor device and the manufacturing method thereof according to the present invention, the bottom portion of the second hole (contact portion forming hole) having an opening diameter larger than the opening diameter of the first hole (capacitor forming hole), and An upper electrode contact portion in which a conductive film constituting the upper electrode is continuously formed can be formed so as to have a hole forming opening having a desired opening diameter on the side wall portion. Thus, a desired void (void) is formed in a portion of the second interlayer insulating film embedded in the hole forming opening of the upper electrode contact portion in the second interlayer insulating film forming step. Can be formed. Furthermore, the first contact hole that exposes the upper electrode contact portion can be easily formed using the holes.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
1A to 1C, FIGS. 2A to 2C, and FIGS. 3A to 3C are described below with respect to a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The description will be given with reference. 1 (a) to (c), FIGS. 2 (a) to (c), and FIGS. 3 (a) to (c) are main portions showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention. It is process sectional drawing.

  First, as shown in FIG. 1A, after a first interlayer insulating film 101 is formed on a semiconductor substrate 100 made of silicon, the first interlayer insulating film 101 is formed on the first interlayer insulating film 101 by lithography and dry etching. Each of the lower electrode contact hole and the peripheral circuit contact hole that penetrates the interlayer insulating film 101 and exposes the semiconductor substrate 100 is formed. Thereafter, each of the lower electrode contact plug 102 and the peripheral circuit contact plug 103 is formed by embedding, for example, a tungsten film, a titanium film, or a titanium nitride film in each of the lower electrode contact hole and the peripheral circuit contact hole. Form. Subsequently, an etching stopper film 104 and a second interlayer insulating film 105 are sequentially formed on the first interlayer insulating film 101 and the contact plugs 102 and 103.

  Next, as shown in FIG. 1B, the upper electrode contact plug 102 is exposed through the second interlayer insulating film 105 and the etching stopper film 104 in the etching stopper film 104 and the second interlayer insulating film 105. The capacitor forming hole 106 is formed, and the second interlayer insulating film 105 and the etching stopper film 104 are penetrated through the etching stopper film 104 and the second interlayer insulating film 105 to expose the first interlayer insulating film 101. A contact forming hole 107 is formed.

  At this time, the opening diameter of the contact portion forming hole 107 in which the contact portion for the three-dimensional upper electrode is formed is larger than the opening diameter of the capacitor forming hole 106 in which the three-dimensional capacitor is formed. The holes 106 and 107 are formed. Here, for example, the opening diameter of the capacitor forming hole 106 is approximately 200 nm, and the opening diameter of the contact forming hole 107 is approximately 600 nm.

  Next, as shown in FIG. 1C, a lower electrode forming film made of, for example, a titanium nitride film is formed on the bottom and side walls of the holes 106 and 107 and the upper surface of the second interlayer insulating film 105. . Subsequently, a desired portion in the lower electrode formation film is selectively removed by performing a CMP process or an entire etch back process. In this manner, the lower electrode 108 is formed on the bottom and side walls of the capacitor forming hole 106, and the lower electrode extending portion 108 a is formed on the bottom and side walls of the contact forming hole 107.

  Here, when a desired portion in the lower electrode formation film is selectively removed by the entire surface etch-back process, since the opening diameter of the contact portion forming hole 107 is larger than the opening diameter of the capacitor forming hole 106, the entire surface exposure is performed. Since more ultraviolet rays are sometimes irradiated into the contact portion forming hole 107, the height of the resist film (not shown) embedded in the contact portion forming hole 107 is embedded in the capacitor forming hole 106. It is assumed that the height is lower than the height of the resist film (not shown). As a result, even if the portion existing in the contact portion forming hole 107 in the lower electrode forming film is removed excessively than the portion existing in the capacitor forming hole 106 in the lower electrode forming film, In the process (see FIG. 2A), the electrical characteristics of the upper electrode contact portion 112 formed in the contact portion forming hole 107 are not affected at all.

  Next, as shown in FIG. 2A, on the second interlayer insulating film 105, an upper electrode made of a capacitor insulating film and a titanium nitride film or the like is formed so as to cover the holes 106 and 107. Films are formed sequentially. Subsequently, portions existing on the second interlayer insulating film 105 in the peripheral circuit region in the capacitor insulating film forming film and the upper electrode forming film are removed by lithography and dry etching.

  In this way, the three-dimensional capacitor 111 in which the lower electrode 108, the capacitor insulating film 109, and the upper electrode 110 are sequentially stacked in the capacitor forming hole 106 is formed, and the lower portion 108 is formed in the contact portion forming hole 107. The electrode extension portion 108a, the capacitive insulating film extension portion 109a, and the upper electrode extension portion 110a (here, the “upper electrode extension portion” is a portion where the conductive film constituting the upper electrode 110 is continuously formed. The U-shaped three-dimensional upper electrode contact portion 112 is formed by sequentially laminating.

  At this time, since the opening diameter of the contact portion forming hole 107 is larger than the opening diameter of the capacitor forming hole 106, the lower electrode extending portion 108a, the capacitor insulating film extending portion 109a, The three-dimensional upper electrode contact portion 112 is not completely buried by the upper electrode extension portion 110a, and has an opening portion 113 having an opening diameter W of about 500 nm. At this time, a step D is generated between the cell array region and the peripheral circuit region.

  Next, as shown in FIG. 2B, a silicon oxide film is formed on the second interlayer insulating film 105, the three-dimensional capacitor 111, and the three-dimensional upper electrode contact portion 112 by plasma CVD using TEOS. A third interlayer insulating film 114 having a thickness of 500 nm is formed. At this time, since the three-dimensional upper electrode contact portion 112 has the opening 113 having a desired opening diameter (for example, 500 nm), the inside of the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114. Desired voids (holes) 115 are formed in the portion embedded in. Here, the desired void refers to a void in which the upper end portion of the void 115 is positioned higher than the upper surface of the upper electrode 110.

  Here, the position of the upper end portion of the void 115 is the film formation condition of the third interlayer insulating film 114 and the opening diameter of the opening 113 of the upper electrode contact portion 112 (that is, the opening diameter of the contact portion forming hole 107). It is determined in relation to. The correlation between the opening diameter of the opening 113 and the position of the upper end of the hole 115 and the correlation between the opening diameter of the opening 113 and the position of the side wall of the hole 115 will be described below with reference to FIGS. This will be described with reference to (a) to (c).

  FIG. 4 is a graph showing the correlation between the opening diameter of the opening and the position of the upper end of the hole, and the correlation between the opening diameter of the opening and the position of the side wall of the hole.

  Here, the result shown in FIG. 4 is that the opening diameter of the opening 113 is changed and the third interlayer insulating film 114 is formed under the constant film forming conditions of the third interlayer insulating film 114. It is the obtained result. Here, as a film forming condition of the third interlayer insulating film 114, the third interlayer insulating film 114 having a film thickness of about 500 nm is formed by a plasma CVD method using TEOS (tetraethyloxysilane) as a Si raw material. A case will be described as a specific example.

  The “position of the upper end of the hole” shown on the left vertical axis in FIG. 4 is the distance from the upper surface of the upper electrode 110 to the upper end of the holes 115, 315, and 415, while FIG. The “position of the hole side wall portion” shown on the right vertical axis of FIG. 4 is the distance from the side wall portion of the opening 113 to the side wall portion of the hole 115, in other words, in the third interlayer insulating film 114. This is the thickness of the portion present on the side wall of the opening 113 of the contact portion 112 for the three-dimensional upper electrode. Also, the ◆ shown in FIG. 4 is a plot of the position of the upper end of the hole at a certain opening diameter, while the □ shown in FIG. 4 is the position of the hole side wall at a certain opening diameter. Is.

  5A to 5C show the film formation conditions of the third interlayer insulating film 114 when the opening diameter of the opening 113 satisfies the ranges of 0 to 200 nm, 200 to 800 nm, and 800 to 1000 nm. FIG. 5B is a cross-sectional view showing a state when the third interlayer insulating film 114 is formed. Specifically, FIG. 5A shows a case where the opening diameter of the opening 113 satisfies 0 to 200 nm. FIG. 5B shows the case where the opening diameter of the opening 113 satisfies 200 to 800 nm, and FIG. 5C shows the case where the opening diameter of the opening 113 satisfies 800 to 1000 nm.

  When the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is smaller than 200 nm, the upper end of the void (hole) 315 is higher than the upper surface of the upper electrode 110 as shown in FIG. The third interlayer insulating film 114 is not formed on the side wall portion of the opening 113 of the three-dimensional upper electrode contact portion 112. Therefore, as shown in FIG. 4, when the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is smaller than 200 nm, the position of the upper end of the hole is 0 nm and the position of the hole side wall is 0 nm. It is.

  On the other hand, when the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is larger than 800 nm, the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 as shown in FIG. A concave groove (through hole) 415 is formed in a portion existing above the opening 113, and no void is generated. Therefore, as shown in FIG. 4, when the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is larger than 800 nm, the position of the upper end of the hole is 500 nm, and the position of the hole side wall is 100 nm. It is.

  That is, in the case where the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is 200 nm or more and 800 nm or less, as shown in FIG. A void (hole) 115 having an upper end at a position higher than the upper surface of the upper electrode 110 is formed in a portion embedded in the opening 113 of the three-dimensional upper electrode contact portion 112.

  As described above, when the third interlayer insulating film 114 having a thickness of 500 nm is formed by the plasma CVD method using TEOS, the opening of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 is formed. In order to form the desired void 115 in the portion embedded in 113, the opening diameter of the opening 113 of the contact portion 112 for the three-dimensional upper electrode needs to satisfy the range of 200 nm or more and 800 nm or less. There is.

  Next, as shown in FIG. 2C, the surface of the third interlayer insulating film 114 is planarized by CMP. Thus, the step D between the cell array region and the peripheral circuit region is eliminated, and the third interlayer insulating film 114 is formed in a portion embedded in the opening 113 of the three-dimensional upper electrode contact portion 112. The void 115 is exposed on the surface of the third interlayer insulating film 114.

  Here, in this embodiment, since the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is about 500 nm, the correlation between the opening diameter and the position of the upper end of the hole shown in FIG. Since the distance from the upper surface of the electrode 110 to the upper end portion of the void 115 (see the distance dx shown in FIG. 2B) is about 250 nm, the third interlayer insulating film 114 extends from the upper surface of the upper electrode 110 to a height of about 200 nm. The void 115 can be exposed on the surface of the third interlayer insulating film 114 by selectively removing the third interlayer insulating film 114 so as to remain. At this time, the opening diameter wa of the void 115A is about 80 nm.

  Next, as shown in FIG. 3A, the opening diameter of the void 115A is enlarged by wet etching, and the bottom of the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 and A portion existing on the side wall portion is removed to expose the upper electrode extending portion 110a. In this manner, an upper electrode contact hole 116 that penetrates the third interlayer insulating film 114 and exposes the three-dimensional upper electrode contact portion 112 is formed.

  Here, from the correlation between the opening diameter shown in FIG. 4 and the position of the hole side wall, the portion of the third interlayer insulating film 114 existing on the side wall of the opening 113 of the three-dimensional upper electrode contact portion 112 is shown. Since the film thickness, in other words, the distance from the sidewall portion of the opening 113 to the sidewall portion of the void 115 (see the distance dy shown in FIG. 2B) is about 50 nm, the third interlayer insulating film 114 is about 70 nm. By performing the substantial etching, the portion existing in the side wall portion of the opening portion 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 can be completely removed. At this time, the opening diameter wb of the upper electrode contact hole 116 is about 240 nm.

  As described above, in this embodiment, the upper electrode contact hole 116 is formed in the portion embedded in the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 in the step of forming the upper electrode contact hole 116. By using the void 115 thus formed, portions of the third interlayer insulating film 114 existing at the bottom and side walls of the opening 113 of the three-dimensional upper electrode contact portion 112 can be easily removed.

  In the present embodiment, since wet etching is employed instead of dry etching in the step of forming the upper electrode contact hole 116, the upper electrode extending portion 110a (in other words, the conductive film constituting the upper electrode 110 is formed). The conductive film constituting the continuous portion) is not etched away.

  Therefore, a portion of the surface of the conductive film that is not exposed in the step of forming the upper electrode contact hole 116 (in other words, a surface of the conductive film that is in contact with the third interlayer insulating film 114), and a surface of the conductive film The step (not shown) generated between the portion exposed in the step of forming the upper electrode contact hole 116 (in other words, the surface in contact with the upper electrode contact plug 120 in the conductive film) is 5 nm or less. is there.

  Next, as shown in FIG. 3B, the upper electrode contact hole 116 is buried on the third interlayer insulating film 114 by lithography, and the portion positioned above the peripheral circuit contact plug 103 is formed. A resist film 117 having an opening is formed. Thereafter, the portions of the third interlayer insulating film 114, the second interlayer insulating film 105, and the etching stopper film 104 that are exposed at the openings of the resist film 117 are sequentially removed by dry etching using the resist film 117 as a mask. Thus, the etching stopper film 104, the second interlayer insulating film 105, and the third interlayer insulating film 114 penetrate through the third interlayer insulating film 114, the second interlayer insulating film 105, and the etching stopper film 104, and the peripheral circuit. A peripheral circuit contact hole 118 exposing the contact plug 103 is formed. Thereafter, the resist film 117 is removed.

  At this time, since the resist film 117 is buried in the upper electrode contact hole 116, the upper electrode extension portion 110a is formed in the upper electrode contact hole 116 in the step of forming the peripheral circuit contact hole 118. Is not exposed, and the upper electrode extension exposed in the upper electrode contact hole is not exposed to plasma and etching gas as in the conventional example.

  Next, as shown in FIG. 3 (c), for example, a tungsten film, a titanium film, or a titanium nitride film is embedded in each of the peripheral circuit contact hole 118 and the upper electrode contact hole 116, so that it is used for the peripheral circuit. Each of the contact plug 119 and the upper electrode contact plug 120 is formed.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  In the present embodiment, as shown in FIG. 3C, the upper electrode contact plug 120 includes an upper electrode extending portion 110a (a three-dimensional upper electrode contact portion 112) exposed in the upper electrode contact hole 116 and the upper electrode contact hole 116. The upper electrode contact plug 120 and the upper electrode 110 are electrically connected. Further, the shape of the portion present in the third interlayer insulating film 114 in the upper electrode contact plug 120 has a shape in which the inner diameter increases after the inner diameter decreases from the lower end toward the upper end.

  According to the present embodiment, a desired opening diameter (for example, 500 nm) is formed on the bottom and side walls of the contact portion forming hole 107 having an opening diameter (for example, 600 nm) larger than the opening diameter (for example, 200 nm) of the capacitor forming hole 106. The three-dimensional upper electrode contact portion 112 in which the lower electrode extension portion 108a, the capacitor insulating film extension portion 109a, and the upper electrode extension portion 110a are sequentially stacked can be configured to have the opening 113. .

  Thus, the third interlayer insulating film 114 was embedded in the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 during the step of forming the third interlayer insulating film 114 (see FIG. 2B). A void 115 having an upper end at a position higher than the upper surface of the upper electrode 110 can be formed in the portion. Furthermore, the upper electrode contact hole 116 that exposes the three-dimensional upper electrode contact portion 112 can be easily formed using the void 115.

  In addition, according to the present embodiment, the process of forming the upper electrode contact hole 615 by dry etching is performed in the conventional example, whereas the process of forming the upper electrode contact hole 116 by wet etching is performed in the present embodiment. . For this reason, since the three-dimensional capacitor 111 is not subjected to charge-up damage due to dry etching in the step of forming the upper electrode contact hole 116, it is possible to suppress the breakdown voltage of the capacitor insulating film 109 from being deteriorated.

  Furthermore, according to the present embodiment, in the conventional example, the process of forming the peripheral circuit contact hole 614 and the process of forming the upper electrode contact hole 615 are performed in the same process, whereas in the present embodiment, the process for the peripheral circuit is performed. Prior to the contact hole 118 formation step, an upper electrode contact hole 116 formation step is performed. As a result, as shown in FIG. 3B, the step of forming the peripheral circuit contact hole 118 can be performed in a state where the resist film 117 is buried in the upper electrode contact hole 116. Therefore, in the process of forming the peripheral circuit contact hole 118, the upper electrode extension 110a is not exposed in the upper electrode contact hole 116, and is exposed in the upper electrode contact hole as in the conventional example. The upper electrode extension portion that is to be exposed is not exposed to plasma and etching gas. For this reason, since the three-dimensional capacitor 111 is not subjected to charge-up damage, it is possible to suppress the breakdown voltage of the capacitor insulating film 109 from being deteriorated.

  In addition, according to the present embodiment, the upper electrode contact plug 119 is exposed in the upper electrode contact hole 116 (in other words, in the opening 113 of the three-dimensional upper electrode contact portion 112). In the process of forming the upper electrode contact hole, the upper electrode contact hole penetrates the upper electrode contact portion and reaches the first interlayer insulating film as in the conventional example. Therefore, stable contact resistance can be obtained.

  In this embodiment, the opening 113 of the contact portion 112 for the three-dimensional upper electrode is formed under the film forming conditions for forming the third interlayer insulating film 114 having a thickness of 500 nm by the plasma CVD method using TEOS. The case where the opening diameter is adjusted to satisfy the range of 200 nm or more and 800 nm or less has been described as a specific example, but the present invention is not limited to this.

  For example, a desired void 115 is obtained in a portion embedded in the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 by changing the film formation condition of the third interlayer insulating film. Therefore, it is possible to change the range of the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 required for the purpose.

  Specifically, in this embodiment, the case where the side coverage (dy / dz) of the third interlayer insulating film 114 is 1/5 (20%) has been described as a specific example. Lowering the side coverage of the third interlayer insulating film 114 by changing the film forming conditions of the third interlayer insulating film, such as lowering the film thickness, increasing the film forming pressure, or lowering the substrate bias. Even in the case where the opening diameter of the opening 113 of the contact portion 112 is smaller than 200 nm, a desired void is formed in the portion embedded in the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114. 115 can be formed. Here, as shown in FIG. 2B, “dz” means the film thickness of the portion of the third interlayer insulating film 114 existing on the upper end portion of the void 115, in other words, from the upper end portion of the void 115. The distance to the surface of the third interlayer insulating film 114 (dz = 250 nm in the present embodiment) is shown. On the other hand, “dy” is a value in the third interlayer insulating film 114 as shown in FIG. The film thickness of the portion existing on the side wall of the opening 113 of the contact portion 112 for the three-dimensional upper electrode, in other words, the distance from the side wall of the opening 113 to the side wall of the void 115 (dy = 50 nm in this embodiment) Indicates.

(Second Embodiment)
6 (a) to (c), FIGS. 7 (a) to (c) and FIGS. 8 (a) to (c) are described below with respect to a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The description will be given with reference. 6 (a) to (c), FIGS. 7 (a) to (c), and FIGS. 8 (a) to (c) are main parts showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention. It is process sectional drawing. 6 (a) to (c), FIGS. 7 (a) to (c) and FIGS. 8 (a) to (c), the same components as those of the semiconductor device according to the first embodiment described above are used. The same symbol is attached. Therefore, in the present embodiment, the same description as in the first embodiment is not repeated.

  Here, the difference between the first embodiment and the present embodiment is as follows.

  The feature of the first embodiment described above is that the void 115 is exposed on the surface of the third interlayer insulating film 114 and then the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114. The upper electrode contact hole 116 that penetrates the third interlayer insulating film 114 and exposes the three-dimensional upper electrode contact portion 112 is formed by removing the portions present on the bottom and side walls of the first electrode.

  In contrast, the feature of this embodiment is that the third interlayer insulating film 114 is penetrated by etching using a protective film (for example, a photoresist film) 216 formed on the third interlayer insulating film 114 as a mask. A hole communicating with the opening 113 of the three-dimensional upper electrode contact portion 112 is formed, and further, at the bottom and side wall portions of the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114. The upper electrode contact hole 218 that penetrates the third interlayer insulating film 114 and exposes the three-dimensional upper electrode contact portion 112 is formed by removing the existing portion.

  In both the first embodiment and the second embodiment, the opening of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 during the step of forming the upper electrode contact holes 116 and 218. The point of using the void 115 formed in the portion embedded in 113 is a common point.

  As shown in FIGS. 6 (a) to (c) and FIG. 7 (a), the same steps as those in the first embodiment (see FIGS. 1 (a) to (c) and FIG. 2 (a)) are performed. Do. In this way, the three-dimensional capacitor 111 in which the lower electrode 108, the capacitor insulating film 109, and the upper electrode 110 are sequentially stacked in the capacitor forming hole 106 is configured, and in the contact forming hole 107, A U-shaped three-dimensional upper electrode contact portion 112 is formed by sequentially laminating a lower electrode extending portion 108a, a capacitive insulating film extending portion 109a, and an upper electrode extending portion 110a.

  Here, as shown in FIG. 6B, since the opening diameter of the contact portion forming hole 107 is larger than the opening diameter of the capacitor forming hole 106, as shown in FIG. The inside of the hole 107 is not completely filled by the lower electrode extension portion 108a, the capacitive insulating film extension portion 109a, and the upper electrode extension portion 110a. The three-dimensional upper electrode contact portion 112 has an opening diameter W Has an opening 113 of about 500 nm.

  Next, as shown in FIG. 7B, as in the first embodiment, the second interlayer insulating film 105, the three-dimensional capacitor 111, and the three-dimensional upper portion are formed by plasma CVD using TEOS. A third interlayer insulating film 114 made of a silicon oxide film and having a thickness of 500 nm is formed on the electrode contact portion 112. At this time, since the three-dimensional upper electrode contact portion 112 has the opening 113 having a desired opening diameter (for example, 500 nm), the inside of the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114. Desired voids (holes) 115 are formed in the portion embedded in.

  As described above, in the present embodiment, the deposition condition of the third interlayer insulating film 114 and the three-dimensional upper electrode contact portion 112 are set so that the upper end portion of the void 115 is positioned higher than the upper surface of the upper electrode 110. The opening diameter of the opening 113 (that is, the opening diameter of the contact portion forming hole 107) is adjusted. For example, when the third interlayer insulating film 114 having a film thickness of 500 nm is formed by plasma CVD using TEOS, it is based on the correlation between the opening diameter and the position of the upper end of the hole shown in FIG. Thus, the opening diameter of the opening 113 of the three-dimensional upper electrode contact portion 112 is adjusted so as to satisfy the range of 200 nm or more and 800 nm or less.

  Next, as shown in FIG. 7C, the level difference D between the cell array region and the peripheral circuit region is eliminated by planarizing the surface of the third interlayer insulating film 114 by CMP processing. . Here, the planarization step of the third interlayer insulating film 114 by the CMP process needs to be performed until the upper end portion of the void 115 is exposed on the surface of the third interlayer insulating film 114 in the first embodiment described above. On the other hand, in this embodiment, it is not necessary to perform the process until the upper end portion of the void 115 is exposed on the surface of the third interlayer insulating film 114.

  Thereafter, a photoresist film 216 having an opening 217 at a portion located above the void 115 is formed on the third interlayer insulating film 114 by photolithography.

  Next, as shown in FIG. 8A, wet etching using the photoresist film 216 as a mask penetrates the third interlayer insulating film 114 and communicates with the opening 113 of the three-dimensional upper electrode contact portion 112. In addition, the portions of the third interlayer insulating film 114 existing at the bottom and side walls of the opening 113 of the three-dimensional upper electrode contact portion 112 are removed to expose the upper electrode extending portion 110a. Let In this manner, an upper electrode contact hole 218 that penetrates the third interlayer insulating film 114 and exposes the three-dimensional upper electrode contact portion 112 is formed.

  As described above, in the present embodiment, the upper electrode contact hole 218 is formed in the portion embedded in the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 in the step of forming the upper electrode contact hole 218. By using the void 115 thus formed, portions of the third interlayer insulating film 114 existing at the bottom and side walls of the opening 113 of the three-dimensional upper electrode contact portion 112 can be easily removed.

  Next, as shown in FIG. 8B, the upper electrode contact hole 218 is embedded in the third interlayer insulating film 114 by lithography, and a portion positioned above the peripheral circuit contact plug 103 is formed. A resist film 219 having an opening is formed. Thereafter, the portions of the third interlayer insulating film 114, the second interlayer insulating film 105, and the etching stopper film 104 that are exposed at the opening of the resist film 219 are sequentially removed by dry etching using the resist film 219 as a mask. . Thereby, the third interlayer insulating film 114, the second interlayer insulating film 105, and the etching stopper film 104 penetrate the etching stopper film 104, the second interlayer insulating film 105, and the third interlayer insulating film 114. A peripheral circuit contact hole 220 exposing the peripheral circuit contact plug 103 is formed. Thereafter, the resist film 219 is removed.

  At this time, since the resist film 219 is embedded in the upper electrode contact hole 218, the upper electrode extension portion 110a is formed in the upper electrode contact hole 218 during the step of forming the peripheral circuit contact hole 220. Is not exposed, and the upper electrode extension exposed in the upper electrode contact hole is not exposed to plasma and etching gas as in the conventional example.

  Next, as shown in FIG. 8C, by embedding, for example, a tungsten film, a titanium film, or a titanium nitride film in each of the peripheral circuit contact hole 220 and the upper electrode contact hole 218, the peripheral circuit contact hole 220 is formed. Each of the contact plug 221 and the upper electrode contact plug 222 is formed.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  In the present embodiment, as shown in FIG. 8C, the upper electrode contact plug 222 includes an upper electrode extending portion 110a (a three-dimensional upper electrode contact portion 112) exposed in the upper electrode contact hole 218. The upper electrode contact plug 222 and the upper electrode 110 are electrically connected. Further, the shape of the portion of the upper electrode contact plug 222 existing in the third interlayer insulating film 114 has a shape in which the inner diameter increases from the lower end to the upper end.

  According to the present embodiment, a desired opening diameter (for example, 500 nm) is formed on the bottom and side walls of the contact portion forming hole 107 having an opening diameter (for example, 600 nm) larger than the opening diameter (for example, 200 nm) of the capacitor forming hole 106. The three-dimensional upper electrode contact portion 112 in which the lower electrode extension portion 108a, the capacitor insulating film extension portion 109a, and the upper electrode extension portion 110a are sequentially stacked can be configured to have the opening 113. .

  Thus, the third interlayer insulating film 114 was embedded in the opening 113 of the three-dimensional upper electrode contact portion 112 in the third interlayer insulating film 114 during the step of forming the third interlayer insulating film 114 (see FIG. 7B). A desired void 115 can be formed in the portion. Furthermore, the upper electrode contact hole 218 that exposes the three-dimensional upper electrode contact portion 112 can be easily formed using the void 115.

  In addition, according to the present embodiment, the process of forming the upper electrode contact hole 615 by dry etching is performed in the conventional example, whereas the process of forming the upper electrode contact hole 218 by wet etching is performed in the present embodiment. . Therefore, in the process of forming the upper electrode contact hole 218, the three-dimensional capacitor 111 is not subjected to charge-up damage due to dry etching, so that the breakdown voltage of the capacitor insulating film 109 can be suppressed from deteriorating.

  Furthermore, according to the present embodiment, in the conventional example, the process of forming the peripheral circuit contact hole 614 and the process of forming the upper electrode contact hole 615 are performed in the same process, whereas in the present embodiment, the process for the peripheral circuit is performed. Prior to the contact hole 220 forming step, an upper electrode contact hole 218 forming step is performed. As a result, as shown in FIG. 8B, the step of forming the peripheral circuit contact hole 220 can be performed with the resist film 219 buried in the upper electrode contact hole 218. Therefore, in the step of forming the peripheral circuit contact hole 220, the upper electrode extension 110a is not exposed in the upper electrode contact hole 218, and is exposed in the upper electrode contact hole as in the conventional example. The upper electrode extension portion that is to be exposed is not exposed to plasma and etching gas. For this reason, since the three-dimensional capacitor 111 is not subjected to charge-up damage, it is possible to suppress the breakdown voltage of the capacitor insulating film 109 from being deteriorated.

  Further, according to the present embodiment, the upper electrode contact plug 222 is exposed in the upper electrode contact hole 218 (in other words, in the opening 113 of the three-dimensional upper electrode contact portion 112). In the process of forming the upper electrode contact hole, the upper electrode contact hole penetrates the upper electrode contact portion and reaches the first interlayer insulating film as in the conventional example. Therefore, stable contact resistance can be obtained.

(Other embodiments)
In the first and second embodiments, the three-dimensional upper electrode contact portion includes the opening 113 having a desired opening diameter, the lower electrode extending portion 108a, the capacitive insulating film extending portion 109a, and the upper portion. Although the contact portion 112 in which the electrode extension portions 110a are sequentially stacked has been described as a specific example, the present invention is not limited to this. For example, the contact portion for the three-dimensional upper electrode may be a contact portion having the opening 113 having a desired opening diameter and including only the upper electrode extending portion 110a.

  In the first and second embodiments, the case where a capacitor having a concave structure is used as a three-dimensional capacitor has been described as a specific example. However, the present invention is not limited to this, for example, a cylinder A capacitor having a type or pin type structure may be used.

In the first and second embodiments, the case where the third interlayer insulating film 114 is formed by the plasma CVD method using TEOS as the Si raw material has been described as a specific example. However, the present invention is not limited to this. The third interlayer insulating film 114 may be formed by a plasma CVD method using, for example, SiH ₄ , Si ₂ H ₆ , or the like as the Si material.

  As a method for forming the contact hole for the upper electrode, in the first embodiment, after the void 115 is exposed on the surface of the third interlayer insulating film 114 by CMP, the third interlayer insulating is performed by wet etching. While a method of removing portions of the film 114 existing at the bottom and side walls of the opening 113 of the three-dimensional upper electrode contact portion 112 will be described as a specific example, in the second embodiment, the photoresist film 216 is formed as a film. By wet etching used as a mask, a hole penetrating the third interlayer insulating film 114 and communicating with the void 115 is formed, and further, an opening of the contact portion 112 for the three-dimensional upper electrode in the third interlayer insulating film 114 Although the method for removing the portions existing on the bottom and side walls of 113 has been described as a specific example, the present invention is not limited to this. No.

  INDUSTRIAL APPLICABILITY Since the upper electrode contact plug having stable contact resistance can be realized without causing charge-up damage to the capacitor, the present invention is useful for a semiconductor device having a capacitor and a method for manufacturing the same.

(a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows about the correlation with an opening diameter and the position of a hole upper end part, and the correlation with an opening diameter and the position of a hole side wall part. (a) to (c) are the cases where the third interlayer insulating film is formed under certain film forming conditions for the third interlayer insulating film when the opening diameters satisfy the respective ranges of 0 to 200 nm, 200 to 800 nm, and 800 to 1000 nm. It is sectional drawing which shows a state when forming a film | membrane. (a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing shown about the structure of the semiconductor device which concerns on a 1st prior art example. (a)-(d) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on a 2nd prior art example. (a)-(c) is principal part process sectional drawing shown about the manufacturing method of the semiconductor device which concerns on a 2nd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 101 1st interlayer insulation film 102 Lower electrode contact plug 103 Peripheral circuit contact plug 104 Etching stopper film 105 2nd interlayer insulation film 106 Capacitor formation hole 107 Contact part formation hole 108 Lower electrode 109 Capacitance insulation Membrane 110 Upper electrode 108a Lower electrode extension portion 109a Capacitance insulating film extension portion 110a Upper electrode extension portion 111 Three-dimensional capacitor 112 Three-dimensional upper electrode contact portion 113 Opening 114 Third interlayer insulating film 115, 115A (void)
216 Photoresist film 217 Opening 116, 218 Upper electrode contact hole 117, 219 Resist film 118, 220 Peripheral circuit contact hole 119, 221 Peripheral circuit contact plug 120, 222 Upper electrode contact plug D Cell array region and peripheral circuit Step difference from area W Opening diameter of opening of contact portion for three-dimensional upper electrode dx, dy, dz Distance wa, wb Opening diameter 315 Void (hole)
415 groove (through hole)
500, 600 Semiconductor substrate 501, 601 First interlayer insulating film 502, 602 Upper electrode contact plug 503, 603 Peripheral circuit contact plug 504, 604 Etching stopper film 505, 605 Second interlayer insulating film 606 Capacitor formation hole 607 Contact portion forming hole 508,608 Lower electrode 509,609 Capacitance insulating film 510,610 Upper electrode 608a Lower electrode extending portion 509a, 609a Capacitor insulating film extending portion 510a, 610a Upper electrode extending portion 511,611 Three-dimensional type Capacitor 612 Three-dimensional upper electrode contact portion 513, 613 Third interlayer insulating film 514, 614 Peripheral circuit contact hole 515, 615 Upper electrode contact hole 616 Peripheral circuit contact plug 617 Upper electrode contact Step between the tact plug 517a through section D cell array region and the peripheral circuit region

Claims (11)

A first interlayer insulating film formed on a semiconductor substrate and having a first hole and a second hole;
A lower electrode made of a conductive film formed on the bottom and side walls of the first hole;
A capacitive insulating film covering the lower electrode;
An upper electrode made of a conductive film covering the capacitive insulating film;
An upper electrode contact portion formed on the bottom and side wall portions of the second hole and having a conductive film constituting the upper electrode extended;
A second interlayer insulating film formed on the first interlayer insulating film, the upper electrode, and the upper electrode contact portion;
An upper electrode contact plug made of a conductive film embedded in a first contact hole that penetrates the second interlayer insulating film and reaches the upper electrode contact portion;
The second hole has an opening diameter larger than an opening diameter of the first hole;
The semiconductor device, wherein the upper electrode and the upper electrode contact plug are electrically connected. The semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, further comprising: a contact plug made of a conductive film embedded in a second contact hole penetrating the first interlayer insulating film and the second interlayer insulating film. The semiconductor device according to claim 1 or 2,
A step formed between a contact surface of the conductive film constituting the upper electrode with the second interlayer insulating film and a contact surface of the conductive film with the contact plug for the upper electrode is 5 nm or less. A semiconductor device. The semiconductor device according to claim 1,
The portion of the upper electrode contact plug existing in the second interlayer insulating film has a shape in which the inner diameter increases after the inner diameter decreases from the lower end toward the upper end. A semiconductor device. The semiconductor device according to claim 1,
A shape of a portion of the upper electrode contact plug in the second interlayer insulating film is such that the inner diameter increases from the lower end to the upper end. Forming a first interlayer insulating film on the semiconductor substrate (a);
Forming a first hole in the first interlayer insulating film and forming a second hole having an opening diameter larger than the opening diameter of the first hole in the first interlayer insulating film (b) )When,
Forming a lower electrode on the bottom and side walls of the first hole (c);
Forming a capacitor insulating film so as to cover the lower electrode (d);
An upper electrode is formed so as to cover the capacitive insulating film, and a conductive film constituting the upper electrode is continuously formed so as to have a hole forming opening at the bottom and side walls of the second hole. Forming an upper electrode contact portion (e),
A step (f) of forming a second interlayer insulating film on the first interlayer insulating film after the step (e);
Forming a first contact hole through the second interlayer insulating film and exposing the upper electrode contact portion in the second interlayer insulating film by wet etching;
A step (h) of forming a contact plug for the upper electrode by embedding a conductive film in the first contact hole,
The step (f) includes a step of forming a hole in a portion embedded in the hole forming opening in the second interlayer insulating film,
The method (g) includes a step of forming the first contact hole made of the holes. In the manufacturing method of the semiconductor device according to claim 6,
After the step (g) and before the step (h), the second interlayer insulating film and the first interlayer insulating film are formed on the first interlayer insulating film and the second interlayer insulating film. Forming a second contact hole penetrating through the interlayer insulating film of (i),
The method (h) further includes a step of forming a contact plug by embedding a conductive film in the second contact hole. In the manufacturing method of the semiconductor device according to claim 6,
The method (f) includes a step of forming the second interlayer insulating film made of a silicon oxide film by a CVD method. In the manufacturing method of the semiconductor device given in any 1 paragraph among Claims 6-8,
The step (g) includes the step of forming the first contact hole by exposing the hole to the surface of the second interlayer insulating film by a CMP process. Method. In the manufacturing method of the semiconductor device given in any 1 paragraph among Claims 6-8,
After the step (f) and before the step (g), a protective film having an opening in a portion located above the vacancy is formed on the second interlayer insulating film. Comprising the step (j) of
In the step (g), a hole that penetrates the second interlayer insulating film and communicates with the hole is formed by wet etching using the protective film as a mask. Forming the first contact hole comprising:
A method of manufacturing a semiconductor device, comprising the step (k) of removing the protective film after the step (g) and before the step (i). In the manufacturing method of the semiconductor device according to claim 10,
The method for manufacturing a semiconductor device, wherein the protective film is a photoresist film.

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