JP2008065953A - Nonvolatile semiconductor memory device and read-out method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and its read-out method where the reliability of reference resistance is high, and a read-out error can be prevented effectively, in a nonvolatile semiconductor memory device that uses a resistance memory element, storing a plurality of resistance states for which the resistance values are different. <P>SOLUTION: The nonvolatile semiconductor memory device uses the resistance memory element where the resistance memory material is held between a pair of electrodes and a resistance memory properties where the resistance state can be switched reversibly to a high-resistance state or to a low-resistance state is manifested by applying voltage. The device has a memory cell 10, having a resistance memory element 12 that manifests the resistance memory properties, and a reference cell 10<SB>R</SB>, which is referred to when read-out is performed from the memory cell 10 and has a reference resistance comprising a resistance memory element 12R where the resistance memory properties are not manifested. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device using a resistance memory element that stores a plurality of resistance states having different resistance values and a reading method thereof.

  In recent years, a nonvolatile semiconductor memory device called ReRAM (Resistance Random Access Memory) has attracted attention as a new memory element. The ReRAM uses a resistance memory element that has a plurality of resistance states with different resistance values and changes its resistance state by applying an electrical stimulus from the outside. For example, information about the high resistance state and the low resistance state of the resistance memory element By associating with "0" and "1", the memory element is used. The future of ReRAM is expected because of its high potential such as high speed, large capacity, and low power consumption.

  In the resistance memory element, a resistance memory material whose resistance state is changed by application of a voltage is sandwiched between a pair of electrodes. As a typical resistance memory material, an oxide material containing a transition metal is known.

FIG. 13 shows electrical characteristics of the resistance memory element. As shown in FIG. 13, when a voltage is gradually applied to the resistance memory element in the high resistance state, the resistance value decreases abruptly when the voltage exceeds a certain value (set voltage V _set ). The device transitions to a low resistance state. This operation is generally called “set”. On the other hand, when a voltage is gradually applied to the resistance memory element in the low resistance state, the resistance value increases rapidly when the voltage exceeds a certain value (reset voltage V _reset ), and the resistance memory element is in the high resistance state. Transition to. This operation is generally called “reset”.

  By these operations, the resistance state of the resistance memory element can be controlled by simply applying a voltage to the resistance memory element.

Data can be read by measuring a voltage applied to the resistance memory element when a predetermined read current is passed through the resistance memory element.
IG Baek et al., "Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses", Tech. Digest IEDM 2004, p. 587 M. Durlam et al., "A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects", 2002 Symposium on VLSI Circuits Digest of Technical Papers H. Honigschmid et al., "A non-volatile 2Mbit CBRAM memory core featuring advanced read and program control", 2006 Symposium on VLSI Circuits Digest of Technical Papers

  As one method of reading information stored in a nonvolatile semiconductor memory device using a resistance memory element, it is conceivable to compare the resistance value of a resistance memory element to be read with the resistance value of a reference resistance. In this case, the reference resistor is required to have high reliability and resistance value stability in order to prevent a read error. Here, as a reference resistor, it is effective to use a resistance memory element similar to that used for a memory cell in terms of the device configuration.

  However, in general, the resistance value when the resistance memory element is in a high resistance state varies greatly. Therefore, when a resistance memory element similar to that used for a memory cell is used as a reference resistance, a read error can be effectively prevented. I could not.

  An object of the present invention is to provide a nonvolatile semiconductor memory device and a reading method thereof, in which a reference resistor has high reliability and can effectively prevent a read error.

  According to one aspect of the present invention, a resistance memory material is sandwiched between a pair of electrodes, and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage. A nonvolatile semiconductor memory device using an element, the memory cell having a first resistance memory element that exhibits the resistance memory characteristic, and a reference cell that is referred to when reading the memory cell, the resistance cell There is provided a non-volatile semiconductor memory device having a reference cell having a reference resistance made of a second resistance memory element that does not exhibit memory characteristics.

  According to another aspect of the present invention, a resistance memory material is sandwiched between a pair of electrodes, and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage. A non-volatile semiconductor memory device using a resistance memory element, wherein the first resistance memory element exhibiting the resistance memory characteristics and a drain terminal are connected to one end of the first resistance memory element A plurality of memory cells each having a first transistor and arranged in a matrix; a reference resistor including a second resistance memory element that does not exhibit the resistance memory characteristics; and a drain terminal having the second transistor A plurality of reference cells each having a second transistor connected to one end of the resistance memory element and arranged in a first direction, and extending in parallel in the first direction In A plurality of signal lines, wherein each signal line is the other end of the first resistance memory element of the memory cells arranged in the first direction, or the reference cells arranged in the first direction. A plurality of bit lines connected to the other end of the second resistance memory element and a plurality of signal lines extending in parallel in a second direction intersecting the first direction. A plurality of word lines connected to the gate terminal of the first transistor of the memory cell and the gate terminal of the second transistor of the reference cell, each signal line being aligned in the second direction; A plurality of signal lines extending in parallel in the second direction, each signal line being connected to the source terminal of the first transistor and the reference of the memory cell arranged in the second direction; The second transistor of the cell Nonvolatile semiconductor memory device having a plurality of source lines connected to the source terminal is provided.

  According to still another aspect of the present invention, a resistance memory material is sandwiched between a pair of electrodes, and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is obtained by applying a voltage. A nonvolatile semiconductor memory device using a resistance memory element that develops, wherein a first resistance memory element that exhibits the resistance memory characteristics and a drain terminal are connected to one end of the first resistance memory element. Each having a first transistor and a plurality of memory cells arranged in a matrix, a reference resistor composed of a second resistance memory element not exhibiting the resistance memory characteristics, and a drain terminal having the second transistor A second transistor connected to one end of each of the resistance memory elements, and a plurality of reference cells arranged in a first direction, and a first transistor crossing the first direction. A plurality of signal lines extending in parallel to each other, each signal line including the other end of the first resistance memory element of the memory cell arranged in the second direction and the signal line A plurality of bit lines connected to the other end of the second resistance memory element of the reference cell, and a plurality of signal lines extending in parallel in the first direction and arranged in parallel. A plurality of words having a line connected to a gate terminal of the first transistor of the memory cell aligned in the first direction or a gate terminal of the second transistor of the reference cell aligned in the first direction And a plurality of signal lines extending in parallel in the first direction and each signal line being arranged in the first direction, the source terminal of the first transistor of the memory cell being arranged in the first direction Or the reference cells arranged in the first direction. The nonvolatile semiconductor memory device having a connected plurality of source lines to a source terminal of the second transistor is provided for.

  According to still another aspect of the present invention, a resistance memory material is sandwiched between a pair of electrodes, and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is obtained by applying a voltage. A nonvolatile semiconductor memory device using a resistance memory element that expresses, a memory cell having a first resistance memory element that exhibits the resistance memory characteristic, and a reference cell that is referred to when reading the memory cell. A read method for a nonvolatile semiconductor memory device having a reference cell having a reference resistance made of the second resistance memory element that does not exhibit the resistance memory characteristics, the first resistance memory element and the first resistance memory element A first voltage applied to the first resistance memory element and a voltage applied to the second resistance memory element when equal read currents are passed to the second resistance memory element. By comparing the second voltage, the non-volatile read method of a semiconductor memory device determines the resistance state of first resistive memory element is provided.

  According to the present invention, in a nonvolatile semiconductor memory device using a resistance memory element that switches between a high resistance state and a low resistance state by applying a voltage, a reference cell that is referred to when reading a memory cell is not subjected to forming processing. A resistance memory element, that is, a reference resistance composed of a resistance memory element that does not exhibit a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state, is used. The stability with respect to can be improved. Thereby, a stable reference voltage can be generated, and read errors can be effectively prevented.

[First Embodiment]
The nonvolatile semiconductor memory device and the reading method thereof according to the first embodiment of the present invention will be explained with reference to FIGS.

  1 is a circuit diagram showing the structure of the nonvolatile semiconductor memory device according to the present embodiment, FIGS. 2 and 3 are graphs showing current-voltage characteristics of the resistance memory element, and FIG. 4 is a temperature characteristic of the resistance value of the resistance memory element. FIG. 5 is a graph showing the holding characteristics of the resistance state of the resistance memory element.

  First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG.

In the row direction (horizontal direction in the drawing), a plurality of word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ ... And a plurality of source lines SL ₁ , SL ₂ . A plurality of bit lines BL _R , BL ₁ , BL ₂ , BL ₃ ... Are arranged in the column direction (vertical direction in the drawing).

At each intersection of the word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ ... And the bit lines BL ₁ , BL ₂ , BL ₃ . Each is formed. In each memory cell 10, the resistance memory element 12 has one end connected to the corresponding bit line BL and the other end connected to the drain terminal of the selection transistor 14. The source terminal of the selection transistor 14 is connected to the corresponding source line SL, and the gate terminal is connected to the corresponding word line WL. The source lines SL of the memory cells 10 adjacent in the column direction are shared.

At each intersection between the word lines _{WL 1, WL 2, WL 3} , WL 4 ... and the bit line BL _R, the reference cell 10 _R having a resistance memory element 12 _R and the selection transistor 14 _R is, respectively formed Yes. In each reference cell 10 _R, the resistance memory element 12 _R has one end connected to the bit line BL _R, the other end connected to the drain terminal of the select transistor 14 _R. The source terminal of the select transistor 14 _R is connected to a corresponding source line SL, and a gate terminal connected to a corresponding word line WL. The source line SL of the reference cell 10 _R adjacent in the column direction, are shared.

The drain terminals of the column selection transistors 16 ₁ , 16 ₂ , 16 ₃ ... Are connected to the ends of the bit lines BL ₁ , BL ₂ , BL ₃ . The write circuit 18 and the source terminal of the read transistor 20 are connected to the source terminals of the column selection transistors 16 ₁ , 16 ₂ , 16 ₃ . A read circuit 22 including a current conveyor and a sense amplifier is connected to the drain terminal of the read transistor 20.

The end of the bit line BL _R, the column drain terminal of the selection transistor 16 _R is connected. The source terminal of the column select transistor 16 _R, the read circuit 22 are connected.

As described above, in the nonvolatile semiconductor memory device according to the present embodiment, one memory cell 10 includes one resistance memory element 12 and one selection transistor 14. Further, the reference cell 10 _R that is referred to when the memory cell 10 is read is also configured by one resistance memory element 12 _R and one selection transistor 14 _R , similarly to the memory cell 10.

Here, the nonvolatile semiconductor memory device according to the present embodiment is characterized mainly to the resistance memory element 12 _R of the reference cell 10 _R. That is, in the nonvolatile semiconductor memory device according to the present embodiment, a resistance memory element that has not been subjected to the forming process is used as the resistance memory element 12 _R (reference resistance) of the reference cell 10 _R. In other words, the maximum voltage of the applied voltage history to the resistance memory element 12 of the memory cell 10 is equal to or higher than the forming voltage for expressing the resistance memory characteristics, whereas the resistance memory of the reference cell 10 _R is used. The maximum voltage in the applied voltage history to the element 12 _R is less than the forming voltage.

In addition, the element resistance of the resistance memory element 12 _R is larger than the resistance value when the resistance memory element 12 of the memory cell 10 is in the low resistance state, and the resistance value when the resistance memory element 12 of the memory cell 10 is in the high resistance state. Less than half.

Then, as the resistance memory element 12 _R of the reference cell 10 _R, the reason for using such a resistive memory element will be described with reference to FIGS.

  Generally, a resistance memory element does not have a resistance memory characteristic that can reversibly change between a high resistance state and a low resistance state by application of a voltage in an initial state immediately after element formation. In order to develop such resistance memory characteristics, it is necessary to perform a process called forming.

  In an initial state immediately after element formation, for example, as shown in FIG. 2, the resistance is high and the withstand voltage is very high. This withstand voltage is normally higher than the voltage required for setting and resetting. In this initial state, there is no change in resistance state such as set or reset.

  When a voltage higher than the withstand voltage is applied in the initial state, as shown in FIG. 2, for example, the value of the current flowing through the element increases rapidly, that is, the resistance memory element is formed. By performing such forming, the resistance memory element exhibits resistance memory characteristics that can reversibly change between a low resistance state and a high resistance state. Once forming is performed, the resistance memory element does not return to the initial state.

FIG. 3 is a graph showing current-voltage characteristics of a resistance memory element using NiO _y as a resistance memory material. In the figure, □ marks are characteristics during the forming process, ◯ marks are characteristics during the reset operation, and Δ marks are characteristics during the set operation.

As shown in FIG. 3, in the resistance memory element using NiO _y , the voltage required for the forming process is substantially equal to the set voltage for setting the resistance memory element to the low resistance state. That is, in the resistance memory element using NiO _y , a clear forming phenomenon as shown in FIG. 2 is not observed. However, as will be described later, the element characteristics change greatly depending on the presence or absence of the forming process.

FIG. 4 is a graph showing temperature characteristics of a resistance memory element using NiO _y as a resistance memory material. In the figure, ◯ indicates the characteristics of the element that is not subjected to forming, and Δ indicates the characteristics of the element in which the high resistance state is written after the forming process.

  As shown in FIG. 4, the resistance value of the element that is not subjected to forming is substantially the same as the resistance value of the element in which the high resistance state is written after the forming process. Further, the temperature characteristic of the resistance value of the element that has not been subjected to the forming process also substantially coincides with the temperature characteristic of the resistance value of the element in which the high resistance state is written after the forming process.

FIG. 5 is a graph showing data retention characteristics of a resistance memory element using NiO _y as a resistance memory material. The data retention characteristics shown in FIG. 5 are obtained by measuring a change in resistance value with time after baking at 250 ° C. after writing a predetermined resistance state in the resistance memory element. In the figure, the dotted line is the characteristic of the element that has not been subjected to the forming process. The element marked “HRS” in the figure is the characteristic of the element in which the high resistance state was written after the forming process, and the figure marked “LRS” Is a characteristic of the element in which a low resistance state is written after the forming process.

  As shown in FIG. 5, the element in which the low resistance state is written after the forming process maintains substantially the same resistance value even after 100 hours of baking. Further, although the resistance value of the element that has not been subjected to the forming process increases as the baking time increases, the variation in characteristics among a plurality of elements is small.

  On the other hand, an element in which a high resistance state is written after the forming process shows a similar change in resistance value as an element not subjected to the forming process, but the deterioration of element characteristics and the variation thereof due to baking are large. Some elements remain in a high resistance state after time baking, while other elements change to a low resistance state.

  As described above, the resistance memory element not subjected to the forming process has substantially the same resistance characteristics as the resistance memory element in which the high resistance state is written after the forming process, and the resistance memory element in which the high resistance state is written after the forming process. More stable than the device.

  In the resistance memory element in which the high resistance state is written after the forming process, the resistance value may vary by about twice in the worst case. For this reason, when such a resistance memory element is used as a resistance memory element for a reference cell, it is difficult to stably generate a reference voltage for reading.

However, as described above, the resistance memory element that has not been subjected to the forming process has substantially the same resistance value as the resistance memory element in which the high resistance state is written after the forming process, and the high resistance state is written after the forming process. It is more stable than resistive memory elements. Therefore, the resistance memory element in the initial state in which the forming process is not performed is extremely useful as the resistance memory element 12 _R for the reference cell 10 _R.

The reference cell 10 _R is used to generate a reference voltage for determining information stored in the memory cell 10 in comparison with a read voltage output from the memory cell 10 when the memory cell 10 is read. is there. For this reason, this reference voltage is approximately between the read voltage when the resistance memory element 12 of the memory cell 10 is in the low resistance state and the read voltage when the resistance memory element 12 of the memory cell 10 is in the high resistance state. It is desirable.

Further, considering that the resistance value of the resistance memory element in the high resistance state is about three orders of magnitude higher than the resistance value of the resistance memory element in the low resistance state, and that the resistance value of the resistance memory element in the high resistance state varies nearly twice. , the resistance value of the resistance memory element 12 _R of the reference cell 10 _R is greater than the resistance value when the resistance memory element 12 of memory cell 10 is in the low resistance state, the high resistance state resistance memory element 12 of memory cell 10 It is desirable that the resistance value is less than half of the resistance value.

Therefore, the resistance memory element 12 _R of the reference cell 10 _R, when the same layer structure as the resistance memory element 12 of memory cell 10, the element area of the resistance memory element 12 _R is the memory cell 10 resistance memory element 12 It is desirable that the element area be at least twice as large. The resistive memory element of the same device area the resistance memory element 12 of memory cell 10, may be configured resistive memory element 12 _R connected to multiple parallel.

3 to 5 are data when NiO _y is used as the resistance memory material of the resistance memory element, but the stability of the element characteristics before the forming process may be obtained when other resistance memory materials are used. It is thought that it is the same. That is, the forming process is considered to be accompanied by dielectric breakdown, and it is predicted that damage is introduced into the film along with the forming process. Therefore, the element in the initial state where the forming is not performed is considered to have more stable characteristics than the state after the forming for the other resistance memory materials.

Next, the forming method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG. Here, it is assumed that the memory cell 10 that performs the forming is the memory cell 10 connected to the word line WL ₁ and the bit line BL ₁ .

First, a predetermined voltage is applied to the gate terminal of the column selection transistor 16 ₁ is connected to the bit line BL _1, the column selection transistor 16 ₁ to the ON state.

At the same time as turning on the column selection transistor 16 _1, a predetermined voltage is applied to the word line WL _1, the selection transistor 14 in the ON state.

The source line SL _1, the reference potential, is connected to 0V, for example ground potential.

Then, the write circuit 18, the drain terminal of the column select transistors 16 _1, to apply the same or than this slightly larger bias voltage and the voltage required to forming the resistance memory element 12. As a result, a current path toward the source line SL ₁ is formed via the column selection transistor 16 ₁ , the bit line BL ₁ , the resistance memory element 12, and the selection transistor 14, and the applied bias voltage is the initial value of the resistance memory element 12. resistance, is distributed to each according to the channel resistance of the channel resistance and the select transistor 14 of the column selection transistor 16 _1.

In this case, the initial resistance of the resistance memory element 12, for sufficiently large in comparison with the channel resistance of the channel resistance and the selection transistors of the column selection transistor 16 _1, most of the bias voltage applied to the resistance memory element 12. As a result, a voltage exceeding the withstand voltage is applied to the resistance memory element 12 and a forming process is performed.

Then, after returning the bias voltage applied to the bit lines BL ₁ to zero, to clear the voltage applied to the voltage and the word line WL ₁ is applied to the gate terminal of the column select transistors 16 _1, to complete the operation of forming .

In the nonvolatile semiconductor memory device according to the present embodiment, as shown in FIG. 1, the word lines WL and the source lines SL are arranged in the row direction, and are connected to one word line WL (for example, the word line WL ₁ ). The memory cells 10 are connected to the same source line SL (for example, the source line SL ₁ ). Therefore, if a bias voltage is simultaneously applied to a plurality of bit lines BL (for example, BL _{1 to} BL ₃ ) in the forming operation, a plurality of memory cells 10 connected to the selected word line WL (for example, the word line WL ₁ ) are collectively collected. Forming is also possible.

In the nonvolatile semiconductor memory device according to the present embodiment, for the resistance memory element 12 _R of the reference cell 10 _R connected to the bit line BL _R, without forming process is maintained in the initial state. That is, the resistance memory element 12 _R, when before and used used, the forming voltage or more is prevented from being applied.

  Next, the writing method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG.

First, the rewriting operation from the high resistance state to the low resistance state, that is, the set operation will be described with reference to FIG. Here, it is assumed that the memory cell 10 to be rewritten is a memory cell 10 connected to the word line WL ₁ and the bit line BL ₁ .

First, a predetermined voltage is applied to the gate terminal of the column selection transistor 16 ₁ is connected to the bit line BL _1, the column selection transistor 16 ₁ to the ON state. At this time, the voltage applied to the gate terminal, the channel resistance of the column select transistor 16 _1, the resistance memory element 12 is sufficiently smaller than the resistance value R _H when the high-resistance state and the resistance memory element 12 is Control is performed so that the resistance value R _L is not negligible compared to the resistance value _{RL in} the low resistance state.

At the same time as turning on the column selection transistor 16 _1, a predetermined voltage is applied to the word line WL _1, the selection transistor 14 in the ON state. At this time, the voltage applied to the word line WL _1, so that the channel resistance of the selection transistor 14, the resistance memory element 12 is a small value negligible compared to the resistance value R _L when the low-resistance state, Control.

The source line SL _1, the reference potential, is connected to 0V, for example ground potential.

Then, the write circuit 18, the drain terminal of the column select transistors 16 _1, to apply the same or slightly larger bias voltage than this voltage required to set the resistance memory element 12. As a result, a current path toward the source line SL ₁ is formed via the column selection transistor 16 ₁ , the bit line BL ₁ , the resistance memory element 12 and the selection transistor 14, and the applied bias voltage is applied to the resistance memory element 12. the value R _H, is distributed to each according to the channel resistance of the channel resistance and the select transistor 14 of the column selection transistor 16 _1.

At this time, the resistance value R _H of the resistance memory element 12 is, for sufficiently large in comparison with the channel resistance of the channel resistance and the selection transistors of the column selection transistor 16 _1, most of the bias voltage applied to the resistance memory element 12 . Thereby, the resistance memory element 12 changes from the high resistance state to the low resistance state.

Then, after returning the bias voltage applied to the bit lines BL ₁ to zero, to clear the voltage applied to the voltage and the word line WL ₁ is applied to the gate terminal of the column select transistors 16 _1, completing the operation of the set .

In the nonvolatile semiconductor memory device according to the present embodiment, as shown in FIG. 1, the word lines WL and the source lines SL are arranged in the row direction, and are connected to one word line WL (for example, the word line WL ₁ ). The memory cells 10 are connected to the same source line SL (for example, the source line SL ₁ ). Therefore, if a bias voltage is simultaneously applied to a plurality of bit lines BL (for example, BL _{1 to} BL ₃ ) in the set operation, a plurality of memory cells 10 connected to the selected word line WL (for example, the word line WL ₁ ) are collectively collected. It is also possible to set.

Next, the rewriting operation from the low resistance state to the high resistance state, that is, the resetting operation will be described with reference to FIG. Here, it is assumed that the memory cell 10 to be rewritten is a memory cell 10 connected to the word line WL ₁ and the bit line BL ₁ .

First, a predetermined voltage is applied to the gate terminal of the column selection transistor 16 ₁ is connected to the bit line BL _1, the column selection transistor 16 ₁ to the ON state. At this time, the voltage applied to the gate terminal, the channel resistance of the column select transistor 16 _1, the resistance memory element 12 so that sufficiently smaller than the resistance value R _L when the low resistance state, and controls.

At the same time as turning on the column selection transistor 16 _1, a predetermined voltage is applied to the word line WL _1, the selection transistor 14 in the ON state. At this time, the voltage applied to the word line WL _1, the channel resistance of the selection transistor 14, the resistance memory element 12 so that sufficiently smaller than the resistance value R _L when the low resistance state, and controls.

The source line SL _1, the reference potential, is connected to 0V, for example ground potential.

Then, the write circuit 18, the drain terminal of the column select transistors 16 _1, to apply the same or slightly larger bias voltage than this voltage required to reset the resistance memory element 12. As a result, a current path toward the source line SL ₁ is formed via the column selection transistor 16 ₁ , the bit line BL ₁ , the resistance memory element 12 and the selection transistor 14, and the applied bias voltage is applied to the resistance memory element 12. the value R _L, is distributed to each according to the channel resistance of the channel resistance and the select transistor 14 of the column selection transistor 16 _1.

In this case, the channel resistance R of the channel resistance R _BS and the selection transistor 14 of the column selection transistors 16 _1, since sufficiently smaller than the resistance value R _L of the resistance memory element 12, most of the applied bias voltage resistance memory element 12 is applied. Thereby, the resistance memory element 12 changes from the low resistance state to the high resistance state.

  In the reset process, almost the entire bias voltage is distributed to the resistance memory element 12 at the moment when the resistance memory element 12 is switched to the high resistance state, so that the resistance memory element 12 is prevented from being set again by this bias voltage. There is a need. For this purpose, the bias voltage applied to the bit line BL must be smaller than the voltage required for setting.

That is, in the reset process, as the channel resistance of the channel resistance and the select transistor 14 of the column selection transistor 16 ₁ is sufficiently smaller than the resistance value R _L of the resistance memory element 12, thereby adjusting the gate voltages of these transistors The bias voltage applied to the bit line BL is set to be equal to or higher than the voltage necessary for resetting and lower than the voltage necessary for setting.

Then, after returning the bias voltage applied to the bit lines BL ₁ to zero, to clear the voltage applied to the voltage and the word line WL ₁ is applied to the gate terminal of the column select transistors 16 _1, completing the operation of the reset .

In the nonvolatile semiconductor memory device according to the present embodiment, as shown in FIG. 1, the word lines WL and the source lines SL are arranged in the row direction, and are connected to one word line WL (for example, the word line WL ₁ ). The memory cells 10 are connected to the same source line SL (for example, the source line SL ₁ ). Therefore, if a bias voltage is simultaneously applied to a plurality of bit lines BL (for example, BL _{1 to} BL ₃ ) in the set operation, a plurality of memory cells 10 connected to the selected word line WL (for example, the word line WL ₁ ) are collectively collected. It is also possible to reset.

Next, the reading method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG. Here, it is assumed that the memory cell 10 to be read is a memory cell 10 connected to the word line WL ₁ and the bit line BL ₁ .

First, each of a predetermined voltage is applied to the gate terminal of the column select transistors ₁₆ 1, 16 _R, column select transistors ₁₆ 1, the 16 _R in the ON state. At this time, the voltage applied to the gate terminal is controlled so that the channel resistances of the column selection transistors 16 ₁ and 16 _R are sufficiently smaller than the resistance value _RL of the resistance memory element 12.

At the same time as turning on the column selection transistors 16 ₁ and 16 _R , a predetermined voltage is applied to the word line WL ₁ to turn on the selection transistors 14 and 14 _R. At this time, the voltage applied to the word line WL _1, the channel resistance of the selection transistor 14, 14 _R, the resistance memory element 12 is to be sufficiently smaller than the resistance value R _L when the low resistance state, controlling .

The source line SL _1, the reference potential, is connected to 0V, for example ground potential.

Next, after the read transistor 20 is turned on, the bit line BL ₁ , BL _R is supplied with a predetermined predetermined value from the read circuit 22 via the read transistor 20 and the column selection transistors 16 ₁ , 16 _R. A read current I is supplied. At this time, the current flowing to the bit line _BL 1, BL _R, the voltage applied to the resistance memory element 12, 12 _R so as not to exceed the reset voltage of the resistance memory element 12, 12 _R, and controls.

Accordingly, the bit line BL _R, the reference voltage corresponding to the resistance value of the resistance memory element 12 _R of the reference cell 10 _R is outputted. Here, the resistance memory element 12 _R of the reference cell 10 _R is a stable initial state without performing the forming process, it is possible to generate a stable reference voltage.

On the other hand, the bit lines BL _1, the voltage corresponding to the resistance state of the resistance memory element 12 is output. That is, the resistance memory element 12 is at the low resistance state, since the element resistance of the resistance memory element 12 is smaller than the element resistance of the resistance memory element 12 _R, low read voltage is output than the reference voltage. Further, the resistance memory element 12 is at the high resistance state, since the element resistance of the resistance memory element 12 larger than the element resistance of the resistance memory element 12 _R, high read voltage is output than the reference voltage.

Then, the sense amplifier of the read circuit 22 compares the reference voltage of the read voltage and the bit line BL _R bit line BL _1, the read voltage of the bit lines BL ₁ is low is higher than the reference voltage of the bit line BL _R Depending on how, the resistance memory element 12 is judged to be in a low resistance state or a high resistance state.

  In this way, information stored in the memory cell 10 can be read.

  As described above, according to the present embodiment, in the nonvolatile semiconductor memory device using the resistance memory element that switches between the high resistance state and the low resistance state by voltage application, the reference cell that is referred to when the memory cell is read is formed. Since a resistance memory element that is not processed, that is, a resistance memory element that does not exhibit a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state, is configured using a reference resistor. Stability against thermal stress can be improved. Thereby, a stable reference voltage can be generated, and read errors can be effectively prevented.

[Second Embodiment]
A nonvolatile semiconductor memory device and a reading method thereof according to the second embodiment of the present invention will be described with reference to FIG. The same components as those in the nonvolatile semiconductor memory device according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  FIG. 6 is a circuit diagram showing the structure of the nonvolatile semiconductor memory device according to the present embodiment.

  First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG.

In the row direction (horizontal direction in the drawing), a plurality of word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ ... And a plurality of source lines SL ₁ , SL ₂ . A plurality of bit lines BL _R1 , BL _R2 , BL ₁ , BL ₂ ... Are arranged in the column direction (vertical direction in the drawing).

A memory cell 10 having a resistance memory element 12 and a select transistor 14 is formed at each intersection of the word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ ... And the bit lines BL ₁ , BL ₂ . ing. In each memory cell 10, the resistance memory element 12 has one end connected to the corresponding bit line BL and the other end connected to the drain terminal of the selection transistor 14. The source terminal of the selection transistor 14 is connected to the corresponding source line SL, and the gate terminal is connected to the corresponding word line WL. The source lines SL of the memory cells 10 adjacent in the column direction are shared.

Reference cells 10 _R each having a resistance memory element 12 _R and a select transistor 14 _R are respectively connected to the intersections of the word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ ... And the bit lines BL _R1 , BL _R2. Is formed. In each reference cell 10 _R, the resistance memory element 12 _R has one end connected to the bit line BL _R, the other end connected to the drain terminal of the select transistor 14 _R. The source terminal of the select transistor 14 _R is connected to a corresponding source line SL, and a gate terminal connected to a corresponding word line WL. The source line SL of the reference cell 10 _R adjacent in the column direction, are shared.

In FIG. 6, the resistance memory element 12 _R and the selection transistor 14 _R of the reference cell 10 _R connected to the bit line BL _R1 are represented as a resistance memory element 12 _R1 and a selection transistor 14 _R1 , respectively, and are connected to the bit line BL _R2 . the reference cell 10 _R of the resistance memory element 12 _R and the select transistor 14 _R which are connected, represent respectively the resistance memory element _{12 R2} and a select transistor _{14 R2.}

The drain terminals of the column selection transistors 16 ₁ , 16 ₂ ... Are connected to the ends of the bit lines BL ₁ , BL ₂ . The write circuit 18 and the source terminal of the read transistor 20 are connected to the source terminals of the column select transistors 16 ₁ , 16 ₂ . A read circuit 22 including a current conveyor and a sense amplifier is connected to the drain terminal of the read transistor 20.

One _{ends of} the bit lines BL _R1 and BL _R2 are connected, and the drain node of the column selection transistor 16 _R is connected to this connection node. The source terminal of the column select transistor 16 _R, the read circuit 22 are connected.

Thus, the non-volatile semiconductor memory device according to the present embodiment, the basic configuration of the memory cell 10 and reference cell 10 _R is similar to the nonvolatile semiconductor memory device according to the first embodiment.

The nonvolatile semiconductor memory device according to the present embodiment is mainly characterized in that two reference cells _10R are provided corresponding to each word line WL. That is, in the non-volatile semiconductor memory device according to the present embodiment, during a read, the two reference cells of the reference cell 10 _R connected to the reference cell 10 _R and the bit line BL _R2 connected to the bit line BL _R1 10 _A reference voltage is generated using _R.

The resistance memory element that has not been subjected to the forming process is used as the resistance memory element 12 _R of the reference cell 10 _R , as in the nonvolatile semiconductor memory device according to the first embodiment, but the resistance memory of the reference cell 10 _R The non-volatile semiconductor memory device according to the first embodiment is different in that the element area of the element 12 _{R and} the element area of the resistance memory element 12 of the memory cell 10 are the same.

By configuring the reference cell 10 _R using the resistance memory element 12 _R having the same element area as the resistance memory element 12 of the memory cell 10, the entire cell block can be configured with a repetitive pattern of cells having the same structure. Thereby, the structure of a cell block can be simplified and design man-hours can be reduced.

Next, the reading method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG. Here, it is assumed that the memory cell 10 to be read is a memory cell 10 connected to the word line WL ₁ and the bit line BL ₁ . The forming method and the writing method for the nonvolatile semiconductor memory device according to the present embodiment are the same as the writing method for the nonvolatile semiconductor memory device according to the first embodiment.

First, each of a predetermined voltage is applied to the gate terminal of the column select transistors ₁₆ 1, 16 _R, column select transistors ₁₆ 1, the 16 _R in the ON state. At this time, the voltage applied to the gate terminal is controlled so that the channel resistances of the column selection transistors 16 ₁ and 16 _R are sufficiently smaller than the resistance value _RL of the resistance memory element 12.

At the same time as turning on the column selection transistors 16 ₁ and 16 _R , a predetermined voltage is applied to the word line WL ₁ to turn on the selection transistors 14, 14 _{R 1} and 14 _{R 2} . At this time, the voltage applied to the word line WL _1, so that the channel resistance of the selection transistor _{14, 14} R1, _{14 R2,} the resistance memory element 12 is sufficiently smaller than the resistance value _{R L} when the low resistance state ,Control.

The source line SL _1, the reference potential, is connected to 0V, for example ground potential.

Next, after the read transistor 20 is turned on, the read circuit 22 connects the bit line BL ₁ and the bit lines BL _R1 and BL _R2 via the read transistor 20 and the column selection transistors 16 ₁ and 16 _R. , Predetermined read currents equal to each other are supplied. That is, the read current output from the read circuit 22 when the I, the read current I flows through the bit line BL _1, respectively read current I / 2 flows in the bit line _{BL R1} and _{BL R2.} At this time, the read current flowing in the bit lines _{BL 1, BL R1, BL R2,} the voltage applied to the resistance memory element _{12, 12} R1, _{12 R2} exceeds the reset voltage of the resistance memory element _{12, 12} R1, _{12 R2} Control so that there is no.

Thereby, the reference voltage V _ref corresponding to the resistance value of the resistance memory elements 12 _R1 and 12 _R2 of the reference cell 10 _R is output to the bit lines BL _R1 and BL _R2 . That is, the resistance values of the resistance memory elements 12 _R1 and 12 _R2 that are not subjected to forming are substantially equal to the resistance value _RH in the high resistance state of the resistance memory element 12, and thus the reference output to the bit lines BL _R1 and BL _R2. The voltage V _ref is V _ref ≈I × R _H / 2.

On the other hand, the read voltage V _read corresponding to the resistance state of the resistance memory element 12 is output to the bit line BL ₁ . That is, when the resistance memory element 12 is in a low resistance state, a read voltage of V _read ≈I × _RL is output, and when the resistance memory element 12 is in a high resistance state, a read voltage of V _read ≈I × _RH is output. Is done.

The resistance value _RH when the resistance memory element 12 is in the high resistance state is approximately three orders of magnitude greater than the resistance value _RL when the resistance memory element 12 is in the low resistance state. Therefore, the reference voltage V _ref is a value approximately between the read voltage V _read when the resistance memory element 12 is in the low resistance state and the read voltage V _read when the resistance memory element 12 is in the high resistance state.

Then, the sense amplifier of the read circuit 22 compares the reference voltage of the bit lines BL ₁ of the read voltage and the bit line _BL R1, _{BL R2,} the bit lines BL ₁ of the read voltage _{V read} bit line _BL R, _{BL R2} It is determined whether the resistance memory element 12 is in a low resistance state or a high resistance state depending on whether it is higher or lower than the reference voltage _Vref .

  In this way, information stored in the memory cell 10 can be read.

  As described above, according to the present embodiment, in the nonvolatile semiconductor memory device using the resistance memory element that switches between the high resistance state and the low resistance state by voltage application, the reference cell that is referred to when the memory cell is read is formed. Since a resistance memory element that is not processed, that is, a resistance memory element that does not exhibit a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state, is configured using a reference resistor. Stability against thermal stress can be improved. Thereby, a stable reference voltage can be generated, and read errors can be effectively prevented.

[Third Embodiment]
A nonvolatile semiconductor memory device and a reading method thereof according to the third embodiment of the present invention will be described with reference to FIG. The same components as those in the nonvolatile semiconductor memory device according to the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 7 is a circuit diagram showing the structure of the nonvolatile semiconductor memory device according to the present embodiment.

  First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG.

In the row direction (horizontal direction in the drawing), a plurality of word lines WL _R , WL ₁ , WL ₂ , WL ₃ ... And a plurality of source lines SL ₁ , SL ₂ . A plurality of bit lines BL ₁ , BL ₂ , BL ₃ , BL ₄ ... Are arranged in the column direction (vertical direction in the drawing).

At each intersection between the word lines WL ₁ , WL ₂ , WL ₃ ... And the bit lines BL ₁ , BL ₂ , BL ₃ , BL ₄ . Each is formed. In each memory cell 10, the resistance memory element 12 has one end connected to the corresponding bit line BL and the other end connected to the drain terminal of the selection transistor 14. The source terminal of the selection transistor 14 is connected to the corresponding source line SL, and the gate terminal is connected to the corresponding word line WL.

Reference cells 10 _R each having a resistance memory element 12 _R and a select transistor 14 _R are formed at each intersection of the word line WL _R and the bit lines BL ₁ , BL ₂ , BL ₃ , BL ₄ . Yes. In each reference cell 10 _R , the resistance memory element 12 _R has one end connected to the corresponding bit line BL and the other end connected to the drain terminal of the selection transistor 14 _R. The source terminal of the select transistor 14 _R is connected to the source line SL _1, the gate terminal is connected to the word line WL _R.

A write circuit 18 and a read circuit 22 including a current conveyor and a sense amplifier are connected to end portions of the bit lines BL ₁ , BL ₂ , BL ₃ , BL ₄ .

Thus, the non-volatile semiconductor memory device according to the present embodiment, the basic configuration of the memory cell 10 and reference cell 10 _R is similar to the nonvolatile semiconductor memory device according to the first and second embodiments.

The main characteristic of the nonvolatile semiconductor memory device according to the present embodiment is the cells connected to a common word line WL _R, that is used as a reference cell 10 _R.

The resistance memory element that has not been subjected to the forming process is used as the resistance memory element 12 _R of the reference cell 10 _R , similarly to the nonvolatile semiconductor memory device according to the first embodiment. In addition, the resistance value of the resistance memory element 12 _R is larger than the resistance value when the resistance memory element 12 of the memory cell 10 is in the low resistance state, and the resistance value when the resistance memory element 12 of the memory cell 10 is in the high resistance state. This is also the same as the nonvolatile semiconductor memory device according to the first embodiment in that it is less than or equal to half.

Next, the reading method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG. Here, it is assumed that the memory cell 10 to be read is a memory cell 10 connected to the word line WL ₁ and the bit line BL ₁ . Furthermore, reference cell 10 _R to be used in the read is assumed to be a word line WL _R and the bit line BL ₂ connected to the reference cell 10 _R. Note that the writing method of the nonvolatile semiconductor memory device according to the present embodiment is the same as the writing method of the nonvolatile semiconductor memory device according to the first embodiment.

First, the column selection circuit 24 selects the bit line BL (BL ₁ ) to which the memory cell 10 to be read is connected and the bit line BL (for example, BL ₂ ) to which the reference cell 10 _R is connected. The bit line selected for reference may be any bit line other than the bit line to which the memory cell 10 to be read is connected.

At the same time as selecting the bit line BL, a predetermined voltage is applied to the word lines WL _R and WL ₁ , and the selection transistor 14 of the memory cell 10 connected to the word line WL ₁ and the reference cell connected to the word line WL _R The 10 _R selection transistor 14 _R is turned on. At this time, the voltages applied to the word lines WL _R and WL ₁ are set so that the channel resistances of the select transistors 14 and 14 _R are sufficiently smaller than the resistance value _RL when the resistance memory element 12 is in the low resistance state. ,Control.

The source line SL _1, the reference potential, is connected to 0V, for example ground potential.

Next, the selected bit lines BL ₁ and BL ₂ are connected to the read circuit 22 by the column selection circuit 24. Then, a predetermined read current I which is equal to each other is supplied from the read circuit 22 to each of the bit lines BL ₁ and BL ₂ via the column selection circuit 24. At this time, the current flowing to the bit line _BL 1, BL _2, the voltage applied to the resistance memory element 12, 12 _R so as not to exceed the reset voltage of the resistance memory element 12, 12 _R, and controls.

Thus, bit line BL _2, the reference voltage corresponding to the resistance value of the resistance memory element 12 _R of the reference cell 10 _R is outputted. On the other hand, the bit lines BL _1, the voltage corresponding to the resistance state of the resistance memory element 12 is output. That is, the resistance memory element 12 is at the low resistance state, since the element resistance of the resistance memory element 12 is smaller than the element resistance of the resistance memory element 12 _R, low read voltage is output than the reference voltage. Further, the resistance memory element 12 is at the high resistance state, since the element resistance of the resistance memory element 12 larger than the element resistance of the resistance memory element 12 _R, high read voltage is output than the reference voltage.

Then, the sense amplifier of the read circuit 22 compares the read voltage and the reference voltage of the bit line BL ₂ bit line BL _1, the read voltage of the bit lines BL ₁ is low is higher than the reference voltage of the bit line BL ₂ Depending on how, the resistance memory element 12 is judged to be in a low resistance state or a high resistance state.

  In this way, information stored in the memory cell 10 can be read.

  As described above, according to the present embodiment, in the nonvolatile semiconductor memory device using the resistance memory element that switches between the high resistance state and the low resistance state by voltage application, the reference cell that is referred to when the memory cell is read is formed. Since a resistance memory element that is not processed, that is, a resistance memory element that does not exhibit a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state, is configured using a reference resistor. Stability against thermal stress can be improved. Thereby, a stable reference voltage can be generated, and read errors can be effectively prevented.

[Fourth Embodiment]
A nonvolatile semiconductor memory device and a method for manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIGS. The same components as those in the nonvolatile semiconductor memory device according to the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted or simplified.

  8 is a plan view showing the structure of the nonvolatile semiconductor memory device according to the present embodiment, FIG. 9 is a schematic cross-sectional view showing the structure of the nonvolatile semiconductor memory device according to the present embodiment, and FIGS. 10 to 12 are nonvolatile diagrams according to the present embodiment. 11 is a process cross-sectional view illustrating the method for manufacturing the conductive semiconductor memory device.

  In the present embodiment, an example of a specific structure for realizing the circuit configuration of the nonvolatile semiconductor memory device according to the first embodiment shown in FIG. 1 and a manufacturing method thereof will be described.

  First, the structure of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIGS. 9 is a cross-sectional view taken along the line AA ′ of FIG.

  An element isolation film 32 that defines an element region is formed on the silicon substrate 30. Each element region has a rectangular shape that is long in the X direction. The plurality of active regions are arranged in a staggered pattern.

  On the silicon substrate 30 on which the element isolation film 32 is formed, a plurality of word lines WL extending in the Y direction are formed. Two word lines WL are extended in each element region. Source / drain regions 36 and 38 are formed in the active regions on both sides of the word line WL. Thus, two selection transistors each including the gate electrode 34 also serving as the word line WL and the source / drain regions 36 and 38 are formed in each element region. Two select transistors formed in one element region share the source / drain region 36.

  An interlayer insulating film 40 is formed on the silicon substrate 30 on which the selection transistor 12 is formed. A contact plug 46 connected to the source / drain region 36 and a contact plug 48 connected to the source / drain region 38 are embedded in the interlayer insulating film 40.

  On the interlayer insulating film 40, the source line 50 electrically connected to the source / drain region 36 (source terminal) via the contact plug 46 and the source / drain region 38 (drain terminal) via the contact plug 48 are provided. And a relay wiring 52 electrically connected to each other. As shown in FIG. 8, the source line 50 (SL) is formed extending in the Y direction.

  An interlayer insulating film 54 is formed on the interlayer insulating film 40 on which the source line 50 and the relay wiring 52 are formed. A contact plug 58 connected to the relay wiring 52 is embedded in the interlayer insulating film 54.

  A resistance memory element 66 is formed on the interlayer insulating film 54 in which the contact plug 58 is embedded. The resistance memory element 66 is made of a lower electrode 60 electrically connected to the source / drain region 38 via the contact plug 58, the relay wiring 52 and the contact plug 48, and a resistance memory material formed on the lower electrode 60. The resistance memory layer 62 and the upper electrode 64 formed on the resistance memory layer 62 are included.

  An interlayer insulating film 68 is formed on the interlayer insulating film 54 on which the resistance memory element 66 is formed. A contact plug 72 connected to the upper electrode 64 of the resistance memory element 66 is embedded in the interlayer insulating film 68.

  A bit line 74 electrically connected to the upper electrode 64 of the resistance memory element 66 through the contact plug 72 is formed on the interlayer insulating film 68 in which the contact plug 72 is embedded. As shown in FIG. 8, the bit line 74 (BL) is formed extending in the X direction.

In FIG. 8, a resistance memory element 66 _R connected to the lowest bit line 74 (BL _R ) is a resistance memory element for a reference cell, and the element area is connected to another bit line 74 (BL). The element area of the resistance memory element 66 is larger.

  Thus, the nonvolatile semiconductor memory device constituting the memory cell array shown in FIG. 1 is formed.

  Next, the method for manufacturing the nonvolatile semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, an element isolation film 32 that defines an element region is formed in the silicon substrate 30 by, for example, STI (Shallow Trench Isolation).

  Next, a selection transistor having a gate electrode 34 and source / drain regions 36 and 38 is formed on the element region of the silicon substrate 30 in the same manner as in a normal MOS transistor manufacturing method (FIG. 10A).

  Next, after a silicon oxide film is deposited on the silicon substrate 30 on which the selection transistor is formed by, for example, a CVD method, the surface of the silicon oxide film is polished by, for example, a CMP method, and the surface is made of a silicon oxide film and is flattened. An interlayer insulating film 40 is formed.

  Next, contact holes 42 and 44 reaching the source / drain regions 36 and 38 are formed in the interlayer insulating film 40 by photolithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, CVD, these conductive films are etched back, and contact plugs 46 and 48 electrically connected to the source / drain regions 36 and 38 in the contact holes 42 and 44, respectively. Is formed (FIG. 10B).

  Next, after depositing a conductive film on the interlayer insulating film 40 in which the contact plugs 46 and 48 are embedded, for example, by the CVD method, the conductive film is patterned by photolithography and dry etching, and the source / drain regions are connected via the contact plug 46. A source line 50 electrically connected to 36 and a relay wiring 52 electrically connected to the source / drain region 38 through the contact plug 48 are formed (FIG. 10C).

  Next, a silicon oxide film is deposited on the interlayer insulating film 40 on which the source line 50 and the relay wiring 52 are formed by, for example, a CVD method, and then the surface of the silicon oxide film is polished by, for example, a CMP method to form a silicon oxide film. An interlayer insulating film 54 having a planarized surface is formed.

  Next, a contact hole 56 reaching the relay wiring 52 is formed in the interlayer insulating film 54 by photolithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, the CVD method, the conductive film is etched back and electrically connected to the source / drain region 38 in the contact hole 56 through the relay wiring 52 and the contact plug 48. The contact plug 58 is formed (FIG. 11A).

  Next, a platinum film, for example, is deposited on the interlayer insulating film 54 with the contact plugs 58 embedded by, for example, a sputtering method.

Next, a TiO _x film is deposited on the platinum film by, for example, laser ablation, sol-gel, sputtering, MOCVD, or the like to form a TiO _x film.

Next, for example, a platinum film is deposited on the TiO _x film by, for example, sputtering.

Next, the laminated film of platinum film / TiO _x film / platinum film is patterned by photolithography and dry etching. Thus, the lower electrode 60 made of a platinum film and electrically connected to the source / drain region 38 via the contact plug 58, the relay wiring 52 and the contact plug 48, and the TiO _x film formed on the lower electrode 60. A resistance memory element 66 having a resistance memory layer 62 and an upper electrode 64 made of a platinum film formed on the resistance memory layer 62 is formed (FIG. 11B).

In addition to TiO _x , for example, NiO _x , YO _x , CeO _x , MgO _x , ZnO _x , ZrO _x , HfO _x , WO _x , NbO _x , TaO can be used as the resistance memory material constituting the resistance memory layer 62. _x , CrO _x , MnO _x , AlO _x , VO _x , SiO _{x and the} like can be applied. In addition, an oxide material including a plurality of metals and semiconductor atoms such as Pr _1-x Ca _x MnO ₃ , La _1-x Ca _x MnO ₃ , SrTiO ₃ , YBa ₂ Cu ₃ O _y , and LaNiO can also be applied. . These resistance memory materials may be used alone or in a laminated structure.

Further, as an electrode material constituting the lower electrode 60 and the upper electrode 64, in addition to platinum, for example, Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN it can be applied _{TiN, Ru, ITO, NiO,} IrO, SrRuO, CoSi 2, WSi 2, NiSi, MoSi 2, TiSi 2, Al-Si, Al-Cu, an Al-Si-Cu or the like. The electrode material constituting the lower electrode 60 and the electrode material constituting the upper electrode 64 may be the same or different.

  Next, a silicon oxide film is deposited on the interlayer insulating film 54 on which the resistance memory element 66 is formed by, for example, a CVD method, and then the surface of the silicon oxide film is polished by, for example, a CMP method to be a flat surface made of a silicon oxide film. An interlayer insulating film 68 is formed.

  Next, a contact hole 70 reaching the upper electrode 64 of the resistance memory element 66 is formed in the interlayer insulating film 68 by photolithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, the CVD method, the conductive film is etched back to form a contact plug 72 connected to the upper electrode 64 of the resistance memory element 66 in the contact hole 70 (FIG. 12). (A)).

  Next, after depositing a conductive film on the interlayer insulating film 68 in which the contact plug 72 is embedded, the conductive film is patterned by photolithography and dry etching, and the upper electrode 64 of the resistance memory element 66 is electrically connected via the contact plug 72. Connected bit lines 74 are formed (FIG. 12B).

  Next, if necessary, an upper wiring layer or the like is further formed to complete the nonvolatile semiconductor device.

  Thereafter, when the nonvolatile semiconductor memory device is used, the forming process is not performed on the resistance memory element of the reference cell, and the forming process is performed only on the resistance memory element of the memory cell.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above embodiment, the circuit configuration is such that the write voltage and the read current are applied to the bit line BL side, but the circuit configuration may be such that the write voltage and the read current are applied to the source line SL side.

Further, in the second embodiment, although substantially R _{H /} 2 the resistance of the reference cell by connection reference cells 10 _R leading to the two bit lines BL in parallel, three or more bit lines the reference cell 10 _R leading to BL are connected in parallel, the substantial resistance value of the reference cell may be further lowered.

As described above, since the resistance value of the resistance memory element in the high resistance state varies nearly double, it is assumed that a sufficient read margin cannot be secured only by setting the substantial resistance value of the reference cell to R _H / 2. The In such a case, by connecting the reference cells connected to three or more bit lines BL in parallel, the substantial resistance value of the reference cells can be further lowered, and the read margin can be improved. Since the resistance value of the resistance memory element in the low resistance state is about three orders of magnitude lower than the resistance value of the resistance memory element in the high resistance state, the read margin in the low resistance state is not lowered by lowering the resistance value of the reference cell. .

In the second embodiment, the element area of the resistance memory element 12 _R of the reference cell 10 _R is the same as the element area of the resistance memory element 12 of the memory cell 10. The element area may be different from the element area.

In the third embodiment, the element area of the resistance memory element 12 _R of the reference cell 10 _R is set to be twice or more the element area of the resistance memory element 12 of the memory cell 10. Similarly, the same element area as that of the resistance memory element 12 of the memory cell 10 may be used. In this case, as in the second embodiment, the resistance value of the reference cell can be substantially reduced to R _H / 2 or less by connecting the reference cells connected to two or more bit lines in parallel. .

  In the first to third embodiments, it is assumed that the resistance value of the resistance memory element that has not been subjected to the forming process is substantially equal to the resistance value of the resistance memory element to which the high resistance state has been written after the forming process. The resistance value of the resistance memory element that has not been subjected to the forming process and the resistance value of the resistance memory element to which the high resistance state has been written after the forming process are not necessarily the same. If the resistance value of the resistance memory element that has not been subjected to the forming process is different from the resistance value of the resistance memory element in which the high resistance state has been written after the forming process, the memory cell and the reference cell are considered in consideration of the difference between these resistance values. The element area of the resistance memory element may be set.

  Further, the structure of the nonvolatile semiconductor memory device according to the fourth embodiment shows an example of realizing the circuit configuration shown in FIG. 1, and the structure of the nonvolatile semiconductor memory device is not limited to this.

  As detailed above, the characteristics of the present invention are summarized as follows.

(Supplementary Note 1) A nonvolatile memory using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes, and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage. A semiconductor memory device,
A memory cell having a first resistance memory element that exhibits the resistance memory characteristics;
A non-volatile semiconductor comprising: a reference cell that is referred to when reading the memory cell, and has a reference resistance made of a second resistance memory element that does not exhibit the resistance memory characteristics Storage device.

(Supplementary note 2) Non-volatile using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage. A semiconductor memory device,
Each of the first resistance memory elements exhibiting the resistance memory characteristics and a first transistor having a drain terminal connected to one end of the first resistance memory element are arranged in a matrix. A plurality of memory cells;
A reference resistance composed of a second resistance memory element not exhibiting the resistance memory characteristics, and a second transistor having a drain terminal connected to one end of the second resistance memory element, A plurality of reference cells arranged in a first direction;
A plurality of signal lines extending in parallel in the first direction, each signal line being the other end of the first resistance memory element of the memory cell arranged in the first direction Or a plurality of bit lines connected to the other end of the second resistance memory element of the reference cells arranged in the first direction,
A plurality of signal lines extending in parallel and extending in a second direction intersecting the first direction, wherein each signal line of the memory cells lined up in the second direction; A plurality of word lines connected to a gate terminal of a transistor and a gate terminal of the second transistor of the reference cell;
A plurality of signal lines extending in parallel in the second direction, each signal line being connected to the source terminal of the first transistor and the reference of the memory cell arranged in the second direction; A non-volatile semiconductor memory device comprising: a plurality of source lines connected to a source terminal of the second transistor of the cell.

(Supplementary Note 3) A nonvolatile memory using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage. A semiconductor memory device,
Each of the first resistance memory elements exhibiting the resistance memory characteristics and a first transistor having a drain terminal connected to one end of the first resistance memory element are arranged in a matrix. A plurality of memory cells;
A reference resistance composed of a second resistance memory element not exhibiting the resistance memory characteristics, and a second transistor having a drain terminal connected to one end of the second resistance memory element, A plurality of reference cells arranged in a first direction;
A plurality of signal lines extending in parallel and extending in a second direction intersecting the first direction, wherein each signal line of the memory cells lined up in the second direction; A plurality of bit lines connected to the other end of the resistance memory element and the other end of the second resistance memory element of the reference cell;
A plurality of signal lines extending in parallel in the first direction, wherein each signal line is a gate terminal of the first transistor of the memory cell arranged in the first direction, or A plurality of word lines connected to gate terminals of the second transistors of the reference cells arranged in a first direction;
A plurality of signal lines extending in parallel in the first direction, each signal line being a source terminal of the first transistor of the memory cell arranged in the first direction, or A non-volatile semiconductor memory device comprising: a plurality of source lines connected to source terminals of the second transistors of the reference cells arranged in a first direction.

(Appendix 4) In the nonvolatile semiconductor memory device according to any one of appendices 1 to 3,
The maximum voltage of the applied voltage history to the second resistance memory element is less than the forming voltage for expressing the resistance memory characteristics capable of reversibly switching between the high resistance state and the low resistance state. A non-volatile semiconductor memory device.

(Supplementary note 5) In the nonvolatile semiconductor memory device according to any one of supplementary notes 1 to 4,
The resistance value of the reference resistor is larger than the resistance value when the first resistance memory element is in the low resistance state, and is equal to or less than ½ of the resistance value when the first resistance memory element is in the high resistance state. A non-volatile semiconductor memory device characterized by the above.

(Appendix 6) In the nonvolatile semiconductor memory device according to Appendix 5,
The element area of the second resistance memory element is at least twice as large as the element area of the first resistance memory element.

(Appendix 7) In the nonvolatile semiconductor memory device according to any one of appendices 1 to 6,
The non-volatile semiconductor memory device, wherein the second resistance memory element has the same layer structure as the first resistance memory element.

(Supplementary note 8) In the nonvolatile semiconductor memory device according to supplementary note 4,
A non-volatile semiconductor memory device comprising a plurality of the bit lines to which the reference cells are connected.

(Supplementary note 9) In the nonvolatile semiconductor memory device according to supplementary note 8,
The nonvolatile semiconductor memory device, wherein a resistance value of the reference resistor is the same as a resistance value when the first resistance memory element is in the high resistance state.

(Supplementary Note 10) A nonvolatile memory using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage. A memory cell having a first resistance memory element that exhibits the resistance memory characteristics, and a reference cell that is referred to when reading the memory cell, and exhibits the resistance memory characteristics A non-volatile semiconductor memory device having a reference cell having a reference resistance made of a second resistance memory element,
A first voltage applied to the first resistance memory element and a second resistance memory when a read current equal to each other is passed through the first resistance memory element and the second resistance memory element. A read method for a nonvolatile semiconductor memory device, wherein a resistance state of the first resistance memory element is determined by comparing with a second voltage applied to the element.

(Additional remark 11) In the reading method of the non-volatile semiconductor memory device according to additional remark 10,
The resistance value of the reference resistor is larger than the resistance value when the first resistance memory element is in the low resistance state, and is equal to or less than ½ of the resistance value when the first resistance memory element is in the high resistance state. And
When the first voltage is greater than the second voltage, it is determined that the first resistance memory element is in a high resistance state;
When the first voltage is smaller than the second voltage, it is determined that the first resistance memory element is in a low resistance state.

1 is a circuit diagram showing a structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. It is a graph (the 1) which shows the current-voltage characteristic of a resistance memory element. It is a graph (the 2) which shows the current-voltage characteristic of a resistance memory element. It is a graph which shows the temperature characteristic of the resistance value of a resistance memory element. It is a graph which shows the retention characteristic of the resistance state of a resistance memory element. FIG. 6 is a circuit diagram showing a structure of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing a structure of a nonvolatile semiconductor memory device according to a third embodiment of the present invention. FIG. 6 is a plan view showing a structure of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. It is process sectional drawing (the 1) which shows the manufacturing method of the non-volatile semiconductor memory device by 4th Embodiment of this invention. It is process sectional drawing (the 2) which shows the manufacturing method of the non-volatile semiconductor memory device by 4th Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the non-volatile semiconductor memory device by 4th Embodiment of this invention. It is a graph which shows the electrical property of a resistance memory element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory cell _10R ... Reference cell 12 ... Resistance memory element 14 ... Selection transistor 16 ... Column selection transistor 18 ... Write circuit 20 ... Read transistor 22 ... Read circuit 24 ... Column selection circuit 30 ... Silicon substrate 32 ... Element isolation 34 ... Gate electrodes 36, 38 ... Source / drain regions 40, 54, 68 ... Interlayer insulating films 42, 44, 56, 70 ... Contact holes 46, 48, 58, 72 ... Contact plugs 50 ... Source lines 52 ... Relay wires 60 ... Lower electrode 62 ... Resistance memory layer 64 ... Upper electrode 66 ... Resistance memory element 74 ... Bit line

Claims (5)

A nonvolatile semiconductor memory device using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage Because
A memory cell having a first resistance memory element that exhibits the resistance memory characteristics;
A non-volatile semiconductor comprising: a reference cell that is referred to when reading the memory cell, and has a reference resistance made of a second resistance memory element that does not exhibit the resistance memory characteristics Storage device. A nonvolatile semiconductor memory device using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage Because
Each of the first resistance memory elements exhibiting the resistance memory characteristics and a first transistor having a drain terminal connected to one end of the first resistance memory element are arranged in a matrix. A plurality of memory cells;
A reference resistance composed of a second resistance memory element not exhibiting the resistance memory characteristics, and a second transistor having a drain terminal connected to one end of the second resistance memory element, A plurality of reference cells arranged in a first direction;
A plurality of signal lines extending in parallel in the first direction, each signal line being the other end of the first resistance memory element of the memory cell arranged in the first direction Or a plurality of bit lines connected to the other end of the second resistance memory element of the reference cells arranged in the first direction,
A plurality of signal lines extending in parallel and extending in a second direction intersecting the first direction, wherein each signal line of the memory cells lined up in the second direction; A plurality of word lines connected to a gate terminal of a transistor and a gate terminal of the second transistor of the reference cell;
A plurality of signal lines extending in parallel in the second direction, each signal line being connected to the source terminal of the first transistor and the reference of the memory cell arranged in the second direction; A non-volatile semiconductor memory device comprising: a plurality of source lines connected to a source terminal of the second transistor of the cell. A nonvolatile semiconductor memory device using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage Because
Each of the first resistance memory elements exhibiting the resistance memory characteristics and a first transistor having a drain terminal connected to one end of the first resistance memory element are arranged in a matrix. A plurality of memory cells;
A reference resistance composed of a second resistance memory element not exhibiting the resistance memory characteristics, and a second transistor having a drain terminal connected to one end of the second resistance memory element, A plurality of reference cells arranged in a first direction;
A plurality of signal lines extending in parallel and extending in a second direction intersecting the first direction, wherein each signal line of the memory cells lined up in the second direction; A plurality of bit lines connected to the other end of the resistance memory element and the other end of the second resistance memory element of the reference cell;
A plurality of signal lines extending in parallel in the first direction, wherein each signal line is a gate terminal of the first transistor of the memory cell arranged in the first direction, or A plurality of word lines connected to gate terminals of the second transistors of the reference cells arranged in a first direction;
A plurality of signal lines extending in parallel in the first direction, each signal line being a source terminal of the first transistor of the memory cell arranged in the first direction, or A non-volatile semiconductor memory device comprising: a plurality of source lines connected to source terminals of the second transistors of the reference cells arranged in a first direction. The nonvolatile semiconductor memory device according to claim 1,
The resistance value of the reference resistor is larger than the resistance value when the first resistance memory element is in the low resistance state, and is equal to or less than ½ of the resistance value when the first resistance memory element is in the high resistance state. A non-volatile semiconductor memory device characterized by the above. A nonvolatile semiconductor memory device using a resistance memory element in which a resistance memory material is sandwiched between a pair of electrodes and a resistance memory characteristic capable of reversibly switching between a high resistance state and a low resistance state is exhibited by application of a voltage A memory cell having a first resistance memory element that exhibits the resistance memory characteristic, and a reference cell that is referred to when reading the memory cell, and is a second cell that does not exhibit the resistance memory characteristic A method for reading a nonvolatile semiconductor memory device having a reference cell having a reference resistance made of a resistive memory element,
A first voltage applied to the first resistance memory element and a second resistance memory when a read current equal to each other is passed through the first resistance memory element and the second resistance memory element. A read method for a nonvolatile semiconductor memory device, wherein a resistance state of the first resistance memory element is determined by comparing with a second voltage applied to the element.

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