JP2008065654A - Image processing apparatus, method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus, method and program capable of making maximum use of the processing ability of each processing means by minimizing the number of times of communication with the processing means best suited for a device control process, if the processing means best suited for image processing performs a plurality of image processes on a number of small areas. <P>SOLUTION: A CPU 13 issues an instruction to start image processes upon selecting one list of execution order from a plurality of lists of execution order stored in a ROM 116. In response to the instruction to start the image processes, a DSP 114 transfers from the ROM 116 to a high-speed memory 115 an image processing program that conforms to the order of executing the image processes, shown in the one list of execution order selected by the CPU 113, to implement the image processes. Based on the results of the image processes and the selected one list of execution order, the image processing program for use in the next image process is selected and transferred to the high-speed memory 115 to implement the image process. This operation is repeated, and when it is over the CPU 113 is notified. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing apparatus that implements a plurality of document processing functions such as fax transmission, fax reception, printing, scanning, copying, and the like by a plurality of processing means, an image processing method executed by the image processing apparatus, and the image processing method. The present invention relates to the described image processing program.

  In recent years, it has multiple document processing functions such as fax transmission, fax reception, printing, scanning, copying, etc., and it is called a multifunction multifunction device, digital multifunction device, multifunction printer, all-in-one printer, multifunction fax, etc. Many image processing apparatuses have been commercialized. In this multifunctional image processing apparatus, various combinations of image processing are required depending on functions.

  For example, in fax transmission, image data read by a scanner is corrected by a filter process, and the MH (Modified Huffman) method, MR (Modified Relatively Element Address Design) method, MMR (Modified MR) method, JBIG (Joint Bi-Lem). After encoding by a coding experts group) or the like, it is transmitted from the communication interface.

  In fax reception, the fax code data received by the communication interface is decoded, enlarged or reduced in accordance with the recording paper, color-converted, and then printed out by the printer.

  In copying, image data read by a scanner is corrected by filter processing, enlarged or reduced in accordance with recording paper, color converted, halftone processed, and then printed out by a printer.

  In the print processing, image data is generated based on a print command received by the communication interface, color conversion is performed, halftone processing is performed, and then printing is performed by the printer.

  In the scan process, image data read by the scanner is corrected by a filter process, encoded by a JPEG (Joint Photographic Experts Group) method, and then output to a computer from a communication interface or stored in an external storage device.

  The multifunctional image processing apparatus performs processing such as processing means that mainly performs control processing and processing means that mainly performs image processing in order to enable a combination of various image processing according to the functions described above. Although at least two processing means for sharing are provided, there are always conflicting demands for speeding up and cost reduction, and various techniques for realizing this demand have been proposed (for example, Patent Documents 1 to 3).

  That is, for example, (Patent Documents 1 and 2) include a CPU that is optimal processing means for device control processing and a DSP (Digital Signal Processor) that is optimal for image processing, and the CPU controls the DSP to perform image processing. A technique for realizing an image processing apparatus that satisfies both high speed and low price by executing is disclosed.

In (Patent Document 3), a CPU that is a processing unit that is optimal for device control processing and a processor that can dynamically reconfigure a hardware configuration that is optimal for image processing (hereinafter referred to as “reconfigurable processor”). And a CPU that controls the reconfigurable processor to execute image processing, thereby realizing a technology for realizing an image processing apparatus that satisfies both high speed and low price.
JP 2002-245447 A Japanese Patent Laid-Open No. 2004-252948 International Publication No. 01/016710 Pamphlet

  However, the conventional technology has the following problems. Hereinafter, although the case where the DSP disclosed in (Patent Documents 1 and 2) is used will be described, the same problem occurs when the reconfigurable processor disclosed in (Patent Document 3) is used.

  In general, document processing is realized by a combination of a plurality of image processings. However, since the DSP program memory is expensive because high speed is required, the capacity is small and it is not possible to secure a capacity capable of storing a large number of programs simultaneously. Therefore, in the above conventional technique, the CPU transfers the DSP program to the program memory of the DSP and instructs the DSP to start executing the program. And the operation | movement of receiving that from the DSP which image processing was completed is performed repeatedly.

  In this case, in a situation where it is not possible to secure a memory capable of storing image data for one page due to a request for price reduction, the image is divided into small areas, and a plurality of image processes are performed for each small area. Therefore, in the CPU, it is necessary to perform processing related to the DSP as many times as the number of combined image processing times the number of small regions, and the processing load on the CPU increases. That is, it becomes a factor of CPU performance degradation.

  In addition, the transfer processing of the DSP program is usually performed by a direct memory access controller (DMAC), and the completion notification is generally realized by an interrupt. Similarly, notification of completion of image processing from the DSP to the CPU is generally realized by interruption. As described above, when interrupts are frequently input to the CPU, the performance is greatly reduced. Furthermore, the overhead of DSP program transfer also causes a reduction in CPU performance.

  Therefore, in the conventional technology, a high-performance CPU that compensates for the performance degradation, that is, a more expensive CPU must be used, and the original problems of high speed and low price cannot be achieved.

  The present invention has been made in view of the above, and when the processing means optimal for image processing executes a plurality of image processing on a large number of small regions, the number of times of communication with the processing means optimal for apparatus control processing An object of the present invention is to obtain an image processing apparatus, an image processing method, and an image processing program capable of minimizing the processing capacity and utilizing the processing capability of each processing means to the maximum.

  To achieve the above object, an image processing apparatus according to the present invention stores a plurality of execution order lists indicating a plurality of image processing execution orders and a plurality of image processing programs. And a first processing means for selecting one execution order list from a plurality of execution order lists stored in the first storage means and issuing an image processing start instruction in the course of device control, Second storage means used for storing the image processing program, and image processing indicated in one execution order list selected by the first processing means in response to an instruction to start the image processing Based on the image processing program stored in the second storage means, issuing a request to transfer and store the image processing program according to the execution order from the first storage means to the second storage means Characterized in that it comprises a second processing means for performing image processing.

  According to this invention, when the second processing means receives an image processing start instruction from the first processing means that mainly controls the apparatus, the second processing means receives the second processing means without receiving the instruction from the first processing means. A plurality of image processing can be performed continuously according to the execution order list stored in the means. Since the first processing means receives only one notification when the plurality of continuous image processes are completed, the processing load on the first processing means is greatly reduced. Therefore, the second image processing is performed by dividing the target image shown in the execution order list for one image processing into a plurality of small regions while suppressing the deterioration of the performance of the first processing unit that mainly controls the apparatus. Therefore, it is possible to realize a high-speed and low-cost image processing apparatus.

  According to the present invention, it is possible to minimize the performance degradation of the processing means optimum for the apparatus control process, and it is possible to obtain a high-speed and inexpensive image processing apparatus.

  Exemplary embodiments of an image processing apparatus, an image processing method, and an image processing program according to the present invention are explained in detail below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the image processing apparatus 100 according to the first embodiment is mainly configured by a CPU 113 as a microprocessor, which is a first processing unit optimal for apparatus control processing. A sensor 111 is connected to the CPU bus 120 managed by the CPU 113 via a sensor interface 112, an external storage device 109 is connected via an external storage interface 110, and a scanner engine 101 is connected via a scanner interface 102. The printer engine 103 is connected via the printer interface 104, and the display device 106 and the input device 107 constituting the operation panel are connected via the panel controller 108.

  In addition, the CPU bus 120 managed by the CPU 113 includes a ROM 116, a RAM 117, an interrupt controller 119, a communication interface 105, a DSP 114 as a processor, which is a second processing means optimal for image processing, and a first storage means. High-speed memory 115 and DMAC 118, which are two storage means, are connected to each other.

  Under the control of the scanner interface 102, the scanner engine 101 reads a document placed on the scanner document table in accordance with a control signal fetched from the CPU bus 120 by the scanner interface 102 and generates digitized image data. The data is output from the interface 102 onto the CPU bus 120.

  Under the control of the printer interface 104, the printer engine 103 prints image data captured by the printer interface 104 from the CPU bus 120 on a recording sheet.

  The communication interface 105 communicates with a computer (not shown) and a fax device (not shown) via a communication line (not shown), and image data and fax data received from the communication line are transferred to the CPU bus 120. The image data and the fax data output from the CPU bus 120 are sent to the communication line.

  The display device 106 and the input device 107 constituting the operation panel operate under the control of the panel controller 108, respectively. The panel controller 108 displays a message for the operator fetched from the CPU bus 120 and operator input information acquired from the input device 107 on the display device 106. Further, the panel controller 108 outputs information input to the input device 107 by the operator on the CPU bus 120.

  The external storage device 109 is an information recording medium such as various types of memory cards, hard disks, and floppy (registered trademark) disks. The external storage interface 110 controls the writing of data to the external storage device 109 according to the write control signal fetched from the CPU bus 120 and reads the data from the external storage device 109 according to the read control signal fetched from the CPU bus 120. Control to output above.

  Under the control of the sensor interface 112, the sensor 111 detects various states of the printer engine 103 (the presence / absence of recording paper, the state of the recording paper cassette, the temperature / humidity around the apparatus, the presence / absence of a recording paper jam, etc.). The sensor 111 detects a paper feed state in the automatic paper feeder when the scanner engine 101 is equipped with an automatic paper feeder. The sensor interface 112 outputs the various information detected by the sensor 111 on the CPU bus 120.

  The ROM 116 serving as the first storage means includes at least a control program executed by the CPU 113, a plurality of image processing programs executed by the DSP 114, an execution control program, and a plurality of executions indicating the execution order of the plurality of image processes. An ordered list is stored.

  The RAM 117 temporarily stores image data, code data, and work data for the CPU 113 under the control of the CPU 113.

  The CPU 113 controls the scanner engine 101, the printer engine 103, the communication interface 105, the display device 106, and the input device 107 based on the control program stored in the ROM 116. Further, the CPU 113 selects the execution order list corresponding to the document processing instructed from the plurality of execution order lists stored in the ROM 116 at the time of document processing, instructs the DSP 114 to start processing, and if necessary, images Performs data division processing. That is, the CPU 113 is configured to execute all device control processes other than image processing.

  The DSP 114 as the second processing means performs image processing using the high-speed memory 115 as the second storage means connected by a dedicated high-speed bus (see FIG. 2).

  The high-speed memory 115 is composed of a no-wait memory that can read and write at a speed higher than the operation speed of the DSP 114 with a small capacity. The program executed by the DSP 114, input / output data when the DSP 114 performs image processing, and selection by the CPU 113 The executed execution order list is stored.

  The DMAC 118 performs data transfer processing between the ROM 116 and RAM 117 and the high-speed memory 115 in accordance with instructions from the CPU 113.

  The interrupt controller 119 arbitrates interrupt signals from the sensor interface 112, the external storage interface 110, the scanner interface 102, the printer interface 104, the panel controller 108, the communication interface 105, the DSP 114, and the DMAC 118 to the CPU 113.

  FIG. 2 is a diagram for explaining the flow of image processing executed at the time of fax reception, fax transmission, copy, print, and scan in the image processing apparatus shown in FIG. With reference to FIG. 1, image processing performed during various types of document processing and control processing related to the image processing will be described.

  In FIG. 2, the DSP 114 performs scanner engine correction processing 201, filter processing 202, data compression processing 203, data expansion processing 204, zoom processing 205, and image data stored in the high-speed memory 115 during corresponding document processing. Corresponding image processing is performed among the color conversion processing 206, the printer engine correction processing 207, and the halftone processing 208.

  The scanner engine correction process 201 is image processing related to shading correction, gamma correction, background removal, and the like. The filter processing 202 is image processing related to sharpening, smoothing, edge enhancement, and the like. The data compression process 203 and the data expansion process 204 are image processes related to RLE, MH, MR, MMR, JBIG, JPEG, and the like. The zoom process 205 is an image process related to enlargement or reduction of image data. The color conversion process 206 is an image process used when converting RGB into CMY, CMYK, or K. The printer engine correction processing 207 is image processing related to gamma correction performed in accordance with the printing characteristics of the printer engine 103. The halftone processing 208 is image processing related to gradation processing using a simple binarization method, a dither method, an error diffusion method, a screen method, or the like.

  In the document processing 210 for fax reception, under the control of the CPU 113, the communication interface 105 temporarily stores the fax code data received from the partner fax machine in the RAM 117, and the DMAC 118 transfers the fax code data from the RAM 117 to the high-speed memory 115. When the DSP 114 receives the start instruction, the DSP 114 does not communicate with the CPU 113, and the data decompression process 204 that decodes the fax code data stored in the high-speed memory 115 into image data, the zoom process 205 for the decoded image data, and color conversion Processing 206 and printer engine correction processing 207 are executed in succession, and the CPU 113 is notified of the end. As a result, under the control of the CPU 113, the DMAC 118 transfers the image data from the high-speed memory 115 to the RAM 117, and the printer interface 104 outputs the image data from the RAM 117 to the printer engine 103.

  In document processing 211 for fax transmission, under the control of the CPU 113, the scanner interface 102 temporarily stores an image read by the scanner engine 101 in the RAM 117, and the DMAC 118 transfers image data from the RAM 117 to the high-speed memory 115. When the DSP 114 receives the start instruction, the DSP 114 converts the image data stored in the high-speed memory 115 into fax code data for the image data stored in the high-speed memory 115 without communicating with the CPU 113. Data compression processing 203 is executed continuously, and the CPU 113 is notified of the end. As a result, under the control of the CPU 113, the DMAC 118 transfers the fax code data from the high-speed memory 115 to the RAM 117, and the communication interface 105 transmits the fax code data from the RAM 117 to the partner fax machine.

  In document processing 212 for the copy instruction, under the control of the CPU 113, the scanner interface 102 temporarily stores the image data read by the scanner engine 101 in the RAM 117, and the DMAC 118 transfers the image data from the RAM 117 to the high-speed memory 115. Upon receiving the start instruction, the DSP 114 performs scanner engine correction processing 201, filter processing 202, zoom processing 205, color conversion processing 206, and printer for image data stored in the high-speed memory 115 without communicating with the CPU 113. The engine correction process 207 and the halftone process 208 are continuously executed to notify the CPU 113 of the end. As a result, under the control of the CPU 113, the DMAC 118 transfers the image data from the high-speed memory 115 to the RAM 117, and the printer interface 104 outputs the image data from the RAM 117 to the printer engine 103.

  In document processing 213 for the print instruction, under the control of the CPU 113, the communication interface 105 temporarily stores the print command received from the partner computer in the RAM 117, the CPU 113 interprets the print command and generates image data, and the DMAC 118 generates the image data. Are transferred from the RAM 117 to the high-speed memory 115. Upon receiving the start instruction, the DSP 114 continuously executes the color conversion process 206, the printer engine correction process 207, and the halftone process 208 for the image data stored in the high-speed memory 115 without communicating with the CPU 113. Then, the CPU 113 is notified of the end. As a result, under the control of the CPU 113, the DMAC 118 transfers the image data from the high-speed memory 115 to the RAM 117, and the printer interface 104 outputs the image data from the RAM 117 to the printer engine 103.

  In the document processing 214 in response to the scan instruction, the image data read by the scanner engine 101 is temporarily stored in the RAM 117 under the control of the CPU 113, and the DMAC 118 transfers the image data from the RAM 117 to the high-speed memory 115. Upon receiving the start instruction, the DSP 114 converts the image data stored in the high-speed memory 115 into code data for the image data stored in the high-speed memory 115 without communicating with the CPU 113, the filter process 202, and the data. The compression process 203 is continuously executed, and the CPU 113 is notified of the end. As a result, under the control of the CPU 113, the DMAC 118 transfers the code data from the high speed memory 115 to the RAM 117, and the communication interface 105 transmits the code data from the RAM 117 to the partner computer.

  FIG. 3 is a diagram illustrating an example of band division for an image to be processed. The CPU 113 divides the image to be processed into a number of substantially equal-valued small regions (hereinafter referred to as “bands”) 301 as shown in FIG. 3, for example, and stores image data of at least one band 301 in the RAM 117. Thus, control is performed so that image processing for each band 301 can be performed. Assume that image processing described below is performed for each band 301.

  FIG. 4 is a flowchart for explaining the processing procedure of the CPU at the time of starting the image processing apparatus shown in FIG. 1 and thereafter. The “step” indicating the processing procedure is hereinafter simply referred to as “S”. In FIG. 4, when the image processing apparatus is activated, the CPU 113 issues an instruction for transferring the execution control program stored in the ROM 116 to the high-speed memory 115 to the DMAC 118 (S401), and whether or not an instruction for document processing is input. Monitor (S402). When document processing is instructed (S402: Yes), control processing (data transfer processing, image processing start instruction issuance, end confirmation, etc.) corresponding to the instructed document processing is executed (S403). When an end notification of image processing corresponding to the instructed document processing is received, the process returns to S402 to monitor the presence / absence of input of the document processing instruction. As described above, the CPU 113 stores the execution control program in the high-speed memory 115 when the image processing apparatus is started up (S401), and thereafter repeats the process of S403 every time there is a document processing instruction input (S402: Yes). .

  FIG. 5 is a flowchart for explaining the processing procedure of the CPU at the time of copy processing, which is one of document processing performed by the image processing apparatus shown in FIG. That is, FIG. 5 shows an example of the processing content in S403 shown in FIG.

  In FIG. 5, when the CPU 113 recognizes the occurrence of the copy process by the operation of the input device 107 by the operator, the CPU 113 selects the execution order list corresponding to the copy process from the plurality of execution order lists stored in the ROM 116, and selects the selected execution order list. The DMAC 118 is caused to execute processing for transferring the execution order list to the high-speed memory 115 (S501). When the transfer ends, the DMAC 118 issues an interrupt to the CPU 113 to notify the end of transfer.

  In parallel, the CPU 113 instructs the scanner engine 101 to acquire image data for one band through the scanner interface 102, and causes the scanner interface 102 to store the acquired image data in the RAM 117 (S502). Then, the CPU 113 issues an instruction to transfer the image data for one band from the RAM 117 to the high-speed memory 115 to the DMAC 118 (S503), and upon receiving the transfer end interrupt, stores it in the high-speed memory 115 to the DSP 114. An instruction to start image processing for image data for one band in accordance with the execution order list thus issued is issued (S504), and an image processing completion notification from the DSP 114 is awaited (S505). The CPU 113 controls other control processes such as the scanner engine 101, the printer engine 103, and the panel controller 108 until an interrupt indicating an image processing completion notification is received from the DSP 114 (S505: No).

  Upon receiving an image processing completion notification from the DSP 114 (S505: Yes), the CPU 113 determines whether image processing for one page has been completed (S506). If the processing has been completed (S506: Yes), The printer interface 104 is instructed to print image data on the printer engine 103 (S507). On the other hand, if the processing for one page is not completed in S506 (S506: No), the processing from S502 to S506 is repeated until the processing for one page is completed (S506: Yes).

  The operation of the CPU 113 in other document processing is different from the copy processing in that only the input / output destination of image data and the execution order list to be selected are different.

  FIG. 6 is a diagram showing an example of an execution order list stored in the ROM shown in FIG. The execution order list 601 shown in FIG. 6 includes a plurality of lines of descriptors 609 to 615. Each of the descriptors 609 to 615 collects information related to one image process. In FIG. 6, as information related to one image processing, for example, an image processing number 602, a leading address 603 of the ROM 116 storing the image processing program, a size 604 of the image processing program, and the image processing Processing methods 605, 606, 607, and 608 for the processing results 0, 1, 2, and 3 of the program are shown. In the processing methods 605 to 608, “next image processing number 602” is indicated according to the image processing results 0 to 3. However, if the number of the image process to be executed next is “255”, this indicates that the process is to be terminated.

  For example, in the descriptor 610, the image processing number 602 is “1”, the head address 603 of the ROM 116 in which the image processing program is stored is “0x00100200”, and the size 604 of the image processing program is “0x00000030 bytes”. It is. The processing methods 605 to 608 for the image processing result are “2”, “4”, “255”, and “255”.

  Processing methods 605 to 608 in this case indicate the following contents. That is, if the image processing result is “0”, the corresponding processing method 605 is “2”, so the processing of the image processing number “2” is performed next. If the image processing result is “1”, the corresponding processing is performed. Since the method 606 is “4”, the image processing number “4” is processed next. If the image processing result is “2” or “3”, the corresponding processing methods 607 and 608 are “255”. It indicates that the process is to be terminated.

  Such an execution order list 601 is prepared for each document processing of fax transmission, fax reception, copy, scan, and print. For example, in the copy execution order list, the scanner engine correction process 201, the filter process 202, the zoom process 205, the color conversion process 206, the printer engine correction process 207, and the halftone process 208 are sequentially executed. There is one descriptor for each process.

  FIG. 7 is a flowchart for explaining the processing procedure of the DSP at the time of image processing performed by the image processing apparatus shown in FIG. The processing procedure shown in FIG. 7 is the content of the execution control program transferred and stored in the high-speed memory 115 in the procedure (S401) shown in FIG. The DSP 114 executes image processing according to the execution control program.

  In FIG. 7, the process of S701 is a part of the process executed by the CPU 113 in the procedure (S403) shown in FIG. That is, the CPU 113 receives an instruction to execute certain document processing (S402: Yes), and in S403, first, instructs the DMAC 118 to transfer image data for one band stored in the RAM 117 to the high-speed memory 115. At the same time, the procedure (S501) shown in FIG. 5 is also executed to request the DMAC 118 to transfer the corresponding execution order list to the high-speed memory 115. Upon receiving a transfer completion notification interrupt from the DMAC 118, the CPU 113 issues an interrupt instructing the DSP 114 to start image processing for one band.

  Therefore, upon receiving an instruction (interrupt) for starting image processing for one band from the CPU 113, the DSP 114 selects the first descriptor in the execution order list stored in the high-speed memory 115. Referring to FIG. 6, the descriptor 609 is selected (S702).

  The DSP 114 indicates the start address 603 “0x00100000” in the ROM 116 of the image processing program indicated by the selected descriptor 609 and the size 604 “0x000000A0” to the DMAC 118 and instructs to transfer from the ROM 116 to the high-speed memory 115. (S703).

  When the DSP 114 receives an interruption notifying the completion of transfer from the DMAC 118, the DSP 114 performs image processing on the image data for one band transferred to the high speed memory 115 in S701 in accordance with the image processing program transferred to the high speed memory 115 by the DMAC 118. The processed image data is stored in the high-speed memory 115 (S704), the next descriptor is selected according to the processing result of the image processing program (S705), and it is checked whether or not the next descriptor exists (S706). .

  As a result, when the next descriptor exists (S706: Yes), the processing from S703 to S706 is repeated. When the next descriptor does not exist (S706: No), the image data processed for the DMAC 118 is stored in the high-speed memory. 115 issues an instruction to transfer data to the RAM 117 (S707), and upon receiving an interrupt notification of completion of transfer from the DMAC 118, issues an interrupt notification notifying the CPU 113 that image processing has been completed to the interrupt controller 119. A request is made (S708).

  This will be specifically described with reference to FIG. The “next descriptor selection” in S705 is performed based on the image processing result in S704. The determination of “whether there is a next descriptor” in S706 is performed based on the contents of the processing methods 605 to 608 for the selected descriptor.

  If the processing result of the image processing instructed by the descriptor 609 at the top of the execution order list 601 is “1”, the processing method 606 is “1”, so in S705, the processing of the image processing number 1 is performed. Descriptor 610 is selected. When the processing result of the image processing instructed by the descriptor 610 is “0”, the processing method 605 is “2”, so that the processing of the image processing number 2, that is, the descriptor 611 is processed in S 705. A process is selected. On the other hand, if the processing result of the image processing instructed by the descriptor 610 is “2 or 3”, the processing methods 607 and 608 are “255”, so that it is determined in S706 that the image processing has ended (706: No).

  If the processing of the descriptor 611 is selected in S705, the processing methods 605 to 608 in the descriptor 612 to the descriptor 614 do not have the end number “255”, so that the descriptor 612 to the descriptor 615 are subsequently processed in the same procedure. Selected sequentially. In the image processing indicated by the descriptor 615, the processing method 605 to 608 is “255” regardless of whether the processing result is “0” to “3”. It is determined to end (706: No).

  As described above, when the DSP 114 receives an instruction to start image processing from the CPU 113, the DSP 114 can continuously perform a plurality of image processing in accordance with the execution order list stored in the high-speed memory 115 without receiving an instruction from the CPU 113. Since the interrupt input to the CPU 113 is only once at the completion of the continuous image processing, the processing load on the CPU 113 is greatly reduced.

  Therefore, according to the first embodiment, a plurality of processing target images divided into a large number of small regions (bands) are suppressed while suppressing a decrease in performance of the CPU 113 that is a first processing unit that mainly performs apparatus control. Since the image processing can be executed by the DSP 114 as the second processing means, a high-speed and low-cost image processing apparatus can be realized.

  Here, the image processing method implemented in the first embodiment is described as follows: “In ROM 116, a plurality of execution order lists indicating the execution order of a plurality of image processes and a plurality of programs for image processing are prepared. “The first step”, “the step of selecting one execution order list from a plurality of execution order lists indicating the execution order of a plurality of image processes” in S501 executed by the CPU 113, and the DSP 114 "Step of transferring the corresponding image processing program to the second storage means" in S703, "Step of executing the transferred image processing program" executed in S704, and S703 in the DSP 114 To “step of repeating the image processing shown in the execution order list in the execution order” in S706. The image processing program describes these steps so that the computer can execute them.

  The CPU 113 as the first processing means and the DSP 114 as the second processing means shown in the first embodiment are not necessarily each a single processor. For example, each processing means may be composed of a plurality of IC chips. Further, these processors do not exist individually, and the cores of the respective processors may be configured together in a single IC.

  In the first embodiment, it has been described that the execution control program and the image processing program stored in advance in the ROM 116 are used. However, these programs are transferred to the RAM 117 and stored in the RAM 117 by an initialization process or the like. The program may be used. In this case, the RAM 117 can be said to be the first storage means.

  Further, the DSP 114 may be configured to directly input the data of the RAM 117 using the CPU bus 120 and directly output the data to the RAM 117. Although the image processing time increases, if this is not a problem, it is an effective measure in terms of simplifying the apparatus configuration.

  Furthermore, although it has been described that the high-speed memory 115 stores the execution order list selected by the CPU 113, the program executed by the DSP 114, and the input / output data when the DSP 114 performs image processing, these are stored in another memory. May be.

(Embodiment 2)
FIG. 8 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 2 of the present invention. In FIG. 8, components that are the same as or equivalent to the components shown in FIG. 1 (Embodiment 1) are given the same reference numerals. Here, the description will be focused on the portion related to the second embodiment.

  As shown in FIG. 8, an image processing apparatus 800 according to the second embodiment is configured around a CPU 801 in place of the CPU 113 shown in FIG. 1 (first embodiment). A CPU bus 808 in place of the CPU bus 120 managed by the CPU 801 has a sensor interface 112, an external storage interface 110, a scanner interface 102, a printer interface 104, a panel controller 108, and a RAM 117 shown in FIG. 1 (first embodiment). And the communication interface 105, the ROM 805 instead of the ROM 116, the interrupt controller 807 instead of the interrupt controller 119, the sub CPU 802 instead of the DSP 114 and the high speed memory 115, the high speed memory 804 and the reconfigurable processor 803, and the DMAC 118. A DMAC 806 is connected.

  Similar to the CPU 113, the CPU 801 is a microprocessor as a first processing unit, and controls the scanner engine 101, the printer engine 103, the communication interface 105, the display device 106, and the input device 107 in the same manner to perform operations other than image processing. Control operations such as executing all device control processes, selecting an execution order list to be executed from a plurality of execution order lists, and instructing the sub CPU 801 as the second processing means to start processing. Configured to do.

  The sub CPU 802 is a processor as second processing means. The reconfigurable processor 803 is a processor as a third processing unit. Both are connected to a high-speed memory 804 as a second storage means by a dedicated high-speed bus. With this configuration, the sub CPU 802 and the reconfigurable processor 803 cooperate to realize the function of the DSP 114 shown in FIG. 1 (Embodiment 1).

  Based on the execution control program for the sub CPU 802 stored in the high speed memory 804, the sub CPU 802 interprets the execution order list selected by the CPU 801 stored in the high speed memory 804 and determines the image processing to be executed next. It is configured to perform operations such as requesting the DMAC 806 to transfer image processing configuration information corresponding to image processing from the ROM 805 to the high-speed memory 804, and instructing the reconfigurable processor 803 to start processing. Yes.

  Although the specific configuration will be described later, the reconfigurable processor 803 is a processor that can dynamically reconfigure the internal hardware configuration in accordance with the image processing configuration information stored in the high-speed memory 804. The sub-CPU 802 Is executed in accordance with the execution order list stored in the high-speed memory 804.

  The high-speed memory 804 is composed of a no-wait memory capable of reading and writing at a speed higher than the operation speed of the sub CPU 802 and the reconfigurable processor 803 with a small capacity, and the execution control program for the sub CPU 802 and the execution order selected by the CPU 801 A list, configuration information for image processing of the reconfigurable processor 803, and input / output data when the reconfigurable processor 803 performs image processing are stored.

  A ROM 805 serving as a first storage unit includes at least a control program executed by the CPU 801, a plurality of pieces of image processing configuration information for the reconfigurable processor 803, an execution control program for the sub CPU 802, and a plurality of execution order lists. Is stored.

  The DMAC 806 performs data transfer between the ROM 805 and RAM 117 and the high-speed memory 804.

  The interrupt controller 807 arbitrates interrupt signals from the sensor interface 112, the external storage interface 110, the scanner interface 102, the printer interface 104, the panel controller 108, the communication interface 105, the sub CPU 802, and the DMAC 806 to the CPU 801.

  Here, the configuration of the reconfigurable processor 803 will be described in detail. The reconfigurable processor 803 includes an input / output interface, a memory, a plurality of processor elements, and a signal line that selectively connects them. One processor element includes an ALU (Arithmetic and Logical Unit), a multiplier, a register, a selector, and a signal line connecting them. The function of each processor element, the input / output interface, the memory, and the connection between the processor elements are determined by the image processing configuration information.

  For example, when realizing the multiply-accumulate function, the first processor element connects the first input to the input interface, connects the second input to the output of the second processor element, and inputs the two inputs. Multiplication is performed by a multiplier, and the result is output. The second processor element connects the first input to the output of the first processor element, connects the second input to the memory, adds the two inputs at the ALU, and outputs the result to the output interface. Configure to output to memory. That is, the multiplication function is realized by the first processor element, the addition function is realized by the second processor element, and the product-sum function is realized by connecting them.

  As described above, the reconfigurable processor 803 dynamically reconfigures the internal hardware configuration based on the image processing configuration information stored in the high-speed memory 804. The behavior of the reconfigured reconfigurable processor 803 is similar to that of dedicated hardware, not a processor. Therefore, by switching a plurality of pieces of image processing configuration information, it becomes possible to handle a plurality of dedicated hardware as if they existed.

  The flow of image processing during document processing (fax reception, fax transmission, copying, printing, scanning) performed by the image processing apparatus 800 according to the second embodiment is the same as that shown in FIG. The image processing is realized by the reconfigurable processor 803 processing each data of the image divided into the bands 301 as shown in FIG.

  The processing procedure of the CPU 801 at the time of starting the image processing apparatus 800 according to the second embodiment and thereafter is the same as that in FIGS. In other words, when the image processing apparatus 800 is activated, the execution control program in S401 shown in FIG. 4 can be replaced with the execution control program for the sub CPU 802 and the image processing configuration information. Further, the processing of S403 shown in FIG. 4 which is transfer control related to the image processing executed by the CPU 801 when document processing is instructed after the image processing apparatus 800 is activated is executed according to the procedure illustrated in FIG. 5 can be applied by replacing the DSP 114 with the sub CPU 802. The execution order list used in the second embodiment can be applied by replacing the image processing program with the image processing configuration information in each descriptor shown in FIG.

  Therefore, hereinafter, the operation of the sub CPU 802 that realizes the operation corresponding to the image processing operation of the DSP 114 (FIG. 7) will be described with reference to FIG. FIG. 9 is a flowchart for explaining the processing procedure of the sub CPU at the time of image processing of the image processing apparatus shown in FIG. The processing procedure shown in FIG. 9 is the contents of the execution control program for the sub CPU 802 transferred and stored in the high-speed memory 804 in the procedure (S401) shown in FIG.

  In FIG. 9, the process of S901 is a part of the process executed by the CPU 801 in the procedure (S403) shown in FIG. That is, the CPU 801 receives an instruction to execute a certain document processing (S402: Yes), and in S403, first, instructs the DMAC 806 to transfer image data for one band stored in the RAM 117 to the high-speed memory 804. At the same time, the procedure (S501) shown in FIG. 5 is also executed to request the DMAC 806 to transfer the corresponding execution order list to the high-speed memory 804. Upon receiving a transfer completion notification interrupt from the DMAC 806, the CPU 801 issues an interrupt instructing the sub CPU 802 to start image processing for one band.

  Therefore, when the sub CPU 802 receives an instruction (interrupt) for starting image processing for one band from the CPU 801, the sub CPU 802 sets the first descriptor in the execution order list stored in the high speed memory 804 in the procedure (S403) shown in FIG. select. Referring to FIG. 6, the descriptor 609 is selected (S902).

  The sub CPU 802 indicates the start address 603 “0x00100000” and the size 604 “0x000000A0” in the ROM 805 of the image processing configuration information indicated by the selected descriptor 609 to the DMAC 806 and transfers the ROM 805 to the high-speed memory 804. An instruction is issued (S903).

  When the sub CPU 802 receives an interrupt notifying the completion of transfer from the DMAC 806, the sub CPU 802 instructs the reconfigurable processor 803 to start image processing (S904), and waits for completion of the image processing (S905).

  The reconfigurable processor 803 receives a start instruction from the sub CPU 802, determines the hardware configuration according to the image processing configuration information transferred to the high speed memory 804 by the DMAC 806, and image data for one band transferred to the high speed memory 804 in step S901. When the processed image data is stored in the high speed memory 804, the sub CPU 802 is notified of the completion of the processing.

  Upon receiving the processing completion notification from the reconfigurable processor 803 (S905: Yes), the sub CPU 802 selects the next descriptor according to the processing result of the reconfigurable processor 803 (S906), and the next descriptor exists. It is checked whether or not (S907).

  As a result, if the next descriptor exists (S907: Yes), the processing from S903 to S907 is repeated. If the next descriptor does not exist (S907: No), the image data processed for the DMAC 806 is stored in the high-speed memory. An instruction (interrupt) is issued to transfer to the RAM 117 from 804 (S908), and upon receiving an interrupt notifying the completion of transfer from the DMAC 806, an interrupt notifying the CPU 801 that image processing has been completed to the interrupt controller 807 Is issued (S909).

  This will be specifically described with reference to FIG. The “next descriptor selection process” in S906 is performed based on the image processing result in the reconfigurable processor 803. Then, the determination process of “whether there is a next descriptor” in S907 is performed based on the contents of the processing methods 605 to 608 for the selected descriptor.

  If the processing result of the image processing instructed by the descriptor 609 at the head of the execution order list 601 is “1”, the processing method 606 is “1”, so in S906, the processing of the image processing number 1 is performed. Descriptor 610 is selected. If the processing result of the image processing instructed by the descriptor 610 is “0”, the processing method 605 is “2”. Therefore, in S906, the processing of the image processing number 2, that is, the descriptor 611 A process is selected. On the other hand, when the processing result of the image processing instructed by the descriptor 610 is “2 or 3”, the processing methods 607 and 608 are “255”, so that it is determined in S907 that the image processing has ended (S907: No).

  If the processing of the descriptor 611 is selected in S906 and the determination in S907 is affirmative (S907: Yes), the descriptors 612 to 615 are sequentially selected in the same procedure. In the image processing indicated by the descriptor 615, the processing method 605 to 608 is “255” regardless of whether the processing result is “0” to “3”. (S907: No).

  As described above, when the sub CPU 802 receives the image processing start instruction from the CPU 801, the sub CPU 802 prepares the configuration information in the high speed memory 804, issues the image processing start instruction to the reconfigurable processor 803, and reconfigurable processor 803. Can perform a plurality of image processing while reconstructing according to the configuration information stored in the high-speed memory 804 without receiving an instruction from the CPU 801. Since the interrupt input to the CPU 801 is only once when a plurality of continuous image processes are completed, the processing load on the CPU 801 is greatly reduced.

  Therefore, according to the second embodiment, a plurality of processing target images divided into a large number of small regions (bands) are suppressed while suppressing a decrease in performance of the CPU 801 that is a first processing unit that mainly performs apparatus control. Since the image processing can be executed in cooperation with the sub CPU 802 as the second processing means and the reconfigurable processor 803 as the third processing means, similarly to the first embodiment, the image processing can be performed at high speed and at a low price. An image processing apparatus can be realized.

  In addition, according to the second embodiment, the reconfigurable processor 803, which is the third processing means, can change the hardware configuration in accordance with the image processing configuration information, thereby improving the degree of freedom of image processing. be able to.

  Here, the image processing method implemented in the second embodiment will be described. Image processing including processing means (reconfigurable processor 803) that can change the configuration of hardware that performs image processing according to configuration information. In the image processing method in the apparatus, “a plurality of execution order lists indicating the execution order of a plurality of image processes and a plurality of pieces of configuration information for performing image processing are prepared in a first storage unit (ROM 805). A process, a process in which the CPU 801 “selects one execution order list from the plurality of execution order lists stored in the ROM 805 and issues an image processing start instruction”, and a sub CPU 802 “provides an instruction to start the image processing. Upon receipt (requested to be transferred to the DMAC 806), the configuration information in accordance with the execution order of the image processing shown in one execution order list selected by the CPU 801 is R The process of transferring from the M805 to the second storage means (high-speed memory 804) "and the sub CPU 802 receives from the DMAC 806" the start instruction to the reconfigurable processor 803 in response to the completion of the transfer process to the high-speed memory 804 " The step of reading the configuration information stored in the high-speed memory 804 ”and the sub CPU 802“ based on both the result of the image processing performed by the reconfigurable processor 803 and the selected execution order list. Determining whether or not the configuration information used in the next image processing can be selected. If it can be selected, it issues a request to transfer and store the selected configuration information in the second storage means. Step of performing image processing end processing (notification processing to the CPU 801) by means ”. The image processing program describes these steps so that the computer can execute them.

  Note that the CPU 801 as the first processing means, the sub CPU 802 as the second processing means, and the reconfigurable processor 803 as the third processing means shown in the second embodiment are each a single processor. There is no necessity to do. For example, each processing means may be composed of a plurality of IC chips. Further, these processors do not exist individually, and the cores of the respective processors may be configured together in a single IC.

  Also, the execution control program and configuration information stored in the ROM 805 have been described as being used. However, the execution control program and configuration information stored in the RAM 117 are transferred from the ROM 805 to the RAM 117 by initialization processing or the like. You may make it do. In this case, it can be said that the RAM 117 is the first storage means.

  The CPU 801 has been described as transferring the execution order list from the ROM 805 to the high-speed memory 804. However, the CPU 801 may store the execution order list in the RAM 117 by an initialization process or the like, and notify the sub CPU 802 of the stored address. Also, a unique symbol may be attached to the execution order list and designated by that symbol. That is, the sub CPU 802 only needs to be able to specify one execution order list, and the format is not limited.

  Further, the execution order list selected by the CPU 801, the program executed by the sub CPU 802, the configuration information for the reconfigurable processor 803, and the input / output when the reconfigurable processor 803 performs image processing are stored in the high-speed memory 804. Although described as storing data, these may be stored in another memory.

  Further, the reconfigurable processor 803 may be configured to directly input the data of the RAM 117 and output it directly to the RAM 117 using the CPU bus 809. Although the image processing time increases, if this is not a problem, it is an effective measure in terms of simplifying the apparatus configuration.

(Embodiment 3)
FIG. 10 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 3 of the present invention. In FIG. 10, the same reference numerals are given to the same or equivalent components as those shown in FIG. 1 (Embodiment 1). Here, the description will be focused on the portion related to the third embodiment.

  As shown in FIG. 10, the image processing apparatus 1000 according to the third embodiment is configured around a CPU 1001 instead of the CPU 113 shown in FIG. 1 (first embodiment). A CPU bus 1007 in place of the CPU bus 120 managed by the CPU 1001 has a sensor interface 112, an external storage interface 110, a scanner interface 102, a printer interface 104, a panel controller 108, and a RAM 117 shown in FIG. 1 (first embodiment). The communication interface 105, the ROM 1004 in place of the ROM 116, the interrupt controller 1006 in place of the interrupt controller 119, the DSP 114, the high speed memory 115, and the high speed memory 1003 in place of the DMAC 118, the reconfigurable processor 1002 and the DMAC 1005 are connected. ing.

  Further, the high-speed memory 1003 and the reconfigurable processor 1002 and the high-speed memory 1003 and the DMAC 1005 are respectively connected by dedicated high-speed buses.

  Similar to the CPU 113, the CPU 1001 is a microprocessor as a first processing unit, and controls the scanner engine 101, the printer engine 103, the communication interface 105, the display device 106, and the input device 107 in the same manner, and other than image processing. All device control processes are executed, an execution order list to be executed is selected from a plurality of execution order lists, and the reconfigurable processor 1002 as the second processing means is instructed to start image processing. It is comprised so that control operation | movement may be performed.

  The high-speed memory 1003 as the second storage means is configured with a no-wait memory that can read and write at a high speed that is higher than the operation speed of the reconfigurable processor 1002 with a small capacity, and configuration information (execution control configuration) of the reconfigurable processor 1002 Information and image processing configuration information), an execution order list selected by the CPU 801, and input / output data when the reconfigurable processor 1002 performs image processing.

  The ROM 1004 as the first storage means includes at least a control program executed by the CPU 1001, a plurality of configuration information for the reconfigurable processor 1002 (configuration information for execution control and configuration information for image processing), and a plurality of execution order lists. Is stored.

  The DMAC 1005 performs data transfer between the ROM 1004 and the RAM 117 and the high-speed memory 1003 based on a request from the reconfigurable processor 1002.

  The interrupt controller 1006 arbitrates interrupt signals from the sensor interface 112, the external storage interface 110, the scanner interface 102, the printer interface 104, the panel controller 108, the communication interface 105, and the DMAC 1005 to the CPU 1001.

  Now, the reconfigurable processor 1002 is a processor as a second processing means. The basic configuration is the same as that of the reconfigurable processor 803 shown in FIG. 8 (Embodiment 2), but the reconfigurable processor 1002 according to Embodiment 3 is “ALU (Arithmetic and Logical Unit), A processor block composed of a plurality of processor elements is composed of a multiplier, a register, a selector and a signal line connecting them.

  The plurality of processor blocks can dynamically reconfigure the internal hardware configuration for each processor block according to the configuration information stored in the high-speed memory 1003. Image processing for performing image processing A processor block and an execution control processor block that controls execution of image processing in the image processing processor block are configured.

  That is, in the third embodiment, the reconfigurable processor 1002 is configured with a corresponding execution control processor block according to the configuration information for execution control transferred from the ROM 1004 to the high-speed memory 1003 at the time of initialization processing of the apparatus, and the like. When the image processing start instruction is received, the execution control processor block interprets the execution order list stored in the high speed memory 1003 to determine the next image processing to be executed, and requests the DMAC 1005 to perform the image processing. Corresponding configuration information is transferred from the ROM 1004 to the high-speed memory 1003, and configuration information for image processing is prepared in the high-speed memory 1003. Then, a corresponding image processing processor block is configured according to the image processing configuration information stored in the high-speed memory 1003, and the image processing processor block is configured to perform image processing.

  Here, the flow of image processing during document processing (fax reception, fax transmission, copying, printing, scanning) performed by the image processing apparatus 1000 according to the third embodiment is the same as that shown in FIG. The “image processing processor block” of the reconfigurable processor 1002 is realized by processing each data of the image divided into the bands 301 as shown in FIG.

  Further, the processing procedure of the CPU 1001 at the time of starting the image processing apparatus 1000 according to the third embodiment and thereafter is the same as that shown in FIGS. That is, when the image processing apparatus 1000 is activated, the execution control program in S401 shown in FIG. 4 can be applied by replacing the configuration information for the reconfigurable processor 1002 (execution control configuration information). Further, the processing of S403 shown in FIG. 4 which is transfer control related to the image processing executed by the CPU 1001 when the document processing is instructed after the image processing apparatus 1000 is activated is executed according to the procedure illustrated in FIG. 5 can be applied by replacing the DSP 114 with the reconfigurable processor 1002. The execution order list used in the third embodiment can be applied by replacing the image processing program with the image processing configuration information in each descriptor shown in FIG. 6 as in the second embodiment.

  Therefore, hereinafter, the “execution control processor block” of the reconfigurable processor 1002 will be described with reference to FIG. FIG. 11 is a flowchart for explaining the processing procedure in the execution control processor block of the reconfigurable processor shown in FIG. The processing procedure shown in FIG. 11 is the contents of the configuration information for execution control transferred and stored in the high-speed memory 1003 in the procedure (S401) shown in FIG. 4 at the time of startup, and the “execution control processor corresponding to the reconfigurable processor 1002”. An instruction to configure a “block” and a procedure of processing performed in the configured “execution control processor block” are shown.

  In FIG. 11, the process of S1101 is a part of the process executed by the CPU 1001 in the procedure (S403) shown in FIG. That is, the CPU 1001 receives an instruction to execute a certain document process (S402: Yes), and in S403, first, instructs the DMAC 1005 to transfer image data for one band stored in the RAM 117 to the high-speed memory 1003. At the same time, the procedure (S501) shown in FIG. 5 is also executed to request the DMAC 1005 to transfer the corresponding execution order list to the high-speed memory 1003. Upon receiving a transfer completion notification interrupt from the DMAC 1005, the CPU 1001 issues an interrupt instructing the reconfigurable processor 1002 to start image processing for one band.

  Therefore, the reconfigurable processor 1002 has one band from the CPU 1001 in a state where the execution control processor block is configured according to the configuration information for execution control stored in the high speed memory 1003 in the procedure (S401) shown in FIG. When an instruction to start image processing (interrupt) is received, each process of S1102 to S1109 is performed in the control processor block.

  That is, the execution control processor block selects the first descriptor of the execution order list stored in the high speed memory 1003 in the procedure (S403) shown in FIG. Referring to FIG. 6, the descriptor 609 is selected (S1102).

  The control processor block indicates the start address 603 “0x00100000” and the size 604 “0x000000A0” in the ROM 1004 of the image processing configuration information indicated by the selected descriptor 609 to the DMAC 1005 and transfers the information from the ROM 1004 to the high-speed memory 1003. The image processing configuration information for the selected descriptor is prepared in the high-speed memory 1003 (S1103). Then, in the reconfigurable processor 1002, the image processor block is configured in accordance with the image processing configuration information prepared in the high speed memory 1003. Therefore, the control processor block performs the high speed memory 1003 on the image processor block in S1101. The image processing is performed on the image data for one band transferred to, the processed image data is instructed to be stored in the high-speed memory 1003 (S1104), and the completion of the image processing is waited (S1105).

  When the image processing in the image processing processor block is completed (S1105: Yes), the execution control processor block selects the next descriptor according to the processing result of the image processing (S1106), and whether or not the next descriptor exists. (S1107).

  As a result, if the next descriptor exists (S1107: Yes), the processing from S1103 to S1107 is repeated. If the next descriptor does not exist (S1107: No), the image data processed for the DMAC 1005 is stored in the high-speed memory. An instruction (interrupt) is issued to transfer to the RAM 117 from 1003 (S1108), and upon receiving an interrupt notifying the completion of transfer from the DMAC 1005, an interrupt notifying the CPU 1001 that image processing has been completed to the interrupt controller 1006 Is issued (S1109).

  Note that the descriptor selection process (S1106) in the execution order list and the next candidate presence / absence determination process (S1107) in the image process are performed in the same procedure as described in the second embodiment, and thus description thereof is omitted. .

  As described above, the reconfigurable processor 1002 has an execution control processor block first, and then receives an image processing start instruction from the CPU 1001, and the execution control processor block is stored in the high-speed memory 1003. By repeating the preparation of the configuration information constituting the image processor block in the high-speed memory 1003 according to the order list, a plurality of image processes are continuously performed while reconfiguring the image processor block without receiving an instruction from the CPU 1001. It can be carried out. Since the interrupt input to the CPU 1001 is only once at the completion of the continuous image processing, the processing load on the CPU 1001 is greatly reduced.

  Therefore, according to the third embodiment, the second processing means performs a plurality of image processing on the image divided into a large number of small regions (bands) while suppressing a decrease in performance of the CPU 1001 as the first processing means. Therefore, it is possible to realize a high-speed and low-cost image processing apparatus as in the first embodiment.

  In addition, according to the third embodiment, the reconfigurable processor 1002, which is the second processing means, can change the hardware configuration in accordance with the image processing configuration information, thereby improving the degree of freedom of image processing. be able to.

  Here, when the image processing method implemented in the third embodiment is shown, the hardware configuration for performing the image processing can be changed according to the configuration information, and the hardware for performing the execution control of the image processing Is an image processing method in an image processing apparatus including processing means (reconfigurable processor 1002) that can be configured in accordance with configuration information, and includes “a plurality of execution order lists and execution controls indicating the execution order of a plurality of image processes; “A step of preparing a plurality of pieces of configuration information indicating the configuration of hardware for performing each image processing in the first storage unit (ROM 1004)” and “the CPU 1001 stores the ROM 1004 in the ROM 1004 with respect to the reconfigurable processor 1002”. The configuration information indicating the configuration of hardware that performs execution control is given, and the ROM 1004 A step of giving an instruction to start image processing when one execution order list is selected from the plurality of execution order lists to be memorized, and “the CPU 1001 responds to a request from the reconfigurable processor 1002 in accordance with the request from the reconfigurable processor 1002. The hardware configuration for performing the corresponding image processing in the second storage means (high-speed memory 1003) readable by the processor 1002 according to the execution order of the image processing indicated in the selected execution order list is shown. And a step of waiting for an end notification from the reconfigurable processor 1002 so that the configuration information is transferred and stored from the ROM 1004 so that image processing corresponding to the configuration information can be performed. The image processing program describes these steps so that the computer can execute them.

  Note that the CPU 1001 as the first processing means and the reconfigurable processor 1002 as the second processing means shown in the third embodiment are not necessarily a single processor. For example, each processing means may be composed of a plurality of IC chips. Further, these processors do not exist individually, and the cores of the respective processors may be configured together in a single IC.

  In the third embodiment, the high-speed memory 1003 stores the execution order list selected by the CPU 1001, configuration information for the reconfigurable processor 1002, and input / output data when the reconfigurable processor 1002 performs image processing. However, these may be stored in another memory.

  Further, the reconfigurable processor 1002 may be configured to directly input the data of the RAM 117 using the CPU bus 1007 and directly output the data to the RAM 117. Although the image processing time increases, if this is not a problem, it is an effective measure in terms of simplifying the apparatus configuration.

  In addition, in the first to third embodiments, the following modifications can be adopted.

  (1) The execution order list may be stored in the RAM without being transferred to the high-speed memory, and the stored address may be notified to the second processing means. Also, a unique symbol may be attached to the execution order list and designated by that symbol. That is, it is only necessary that the second processing means can identify one execution order list, and the format is not limited.

  (2) Regarding the execution order list, in FIG. 6, four processing methods 605 to 608 are shown as processing methods (candidates for the next image processing) for the image processing results in each descriptor. The number of processing candidates is not limited to four, and may be other than four or may be variable length. Conversely, when it is not necessary to select the next image processing to be performed according to the processing result of the image processing, each descriptor has a column (605 to 608) of a processing method (candidate for the next image processing to be performed) for the image processing result. ) May be omitted. The address 603 storing the image processing program or the configuration information in each descriptor and its size 604 can be notified to the second processing means separately from the execution order list. That is, the execution order list is not particularly limited as long as it can indicate the order in which a plurality of image processes are executed.

  (3) Further, it has been described that all the image data for one band is transferred to the high-speed memory for processing. May be divided into smaller blocks for transfer processing.

  As described above, the image processing apparatus, the image processing method, and the image processing program according to the present invention can realize a high-speed image processing at a low cost by suppressing a decrease in the performance of the processing means optimal for the apparatus control process. Useful.

1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. 1 is a diagram for explaining the flow of image processing executed at the time of fax reception, fax transmission, copy, print, and scan in the image processing apparatus shown in FIG. The figure which shows an example of the band division with respect to the image which should be processed The flowchart explaining the processing procedure of CPU at the time of starting of the image processing apparatus shown in FIG. The flowchart explaining the processing procedure of CPU at the time of the copy process which is one of the document processes implemented with the image processing apparatus shown in FIG. The figure which shows an example of the execution order list | wrist stored in ROM shown in FIG. 1 is a flowchart for explaining a processing procedure of a DSP during image processing performed by the image processing apparatus shown in FIG. Block diagram showing a configuration of an image processing apparatus according to Embodiment 2 of the present invention. 8 is a flowchart for explaining the processing procedure of the sub CPU at the time of image processing performed by the image processing apparatus shown in FIG. Block diagram showing the configuration of an image processing apparatus according to Embodiment 3 of the present invention. 10 is a flowchart for explaining a processing procedure in the execution control processor block of the reconfigurable processor shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image processing apparatus 101 Scanner engine 102 Scanner interface 103 Printer engine 104 Printer interface 105 Communication interface 106 Display apparatus 107 Input apparatus 108 Panel controller 109 External storage apparatus 110 External storage interface 111 Sensor 112 Sensor interface 113 CPU (optimum for apparatus control processing) Microprocessor as first processing means)
114 DSP (processor which is the second processing means most suitable for image processing)
115 High-speed memory 116 Communication controller 116 ROM
117 RAM
118 DMAC
119 Interrupt controller 120 CPU bus 201 Scanner engine correction process 202 Filter process 203 Data compression process 204 Data decompression process 205 Zoom process 206 Color conversion process 207 Printer engine correction process 210 Document process for fax reception 211 Document process for fax transmission 212 Copy instruction Document Processing 213 Document Processing for Print Instruction 214 Document Processing for Scan Instruction 301 Band 601 Execution Order List 800 Image Processing Device 801 CPU
802 Sub CPU
803 Reconfigurable processor 804 High-speed memory 805 ROM
806 DMAC
807 Interrupt controller 808 CPU bus 1000 Image processing apparatus 1001 CPU
1002 Reconfigurable processor 1003 High-speed memory 1004 ROM
1005 DMAC
1006 Interrupt controller 1007 CPU bus

Claims (13)

First storage means for storing a plurality of execution order lists indicating a plurality of image processing execution orders and a plurality of image processing programs;
A first processing means for selecting one execution order list from a plurality of execution order lists stored in the first storage means in the course of device control and issuing an image processing start instruction;
Second storage means used to store at least the image processing program;
In response to the start instruction of the image processing, an image processing program according to the execution order of the image processing shown in one execution order list selected by the first processing means is stored in the first storage means from the first storage means. A second processing unit that issues a request for transfer and storage to the second storage unit and performs image processing based on the image processing program stored in the second storage unit;
An image processing apparatus comprising: The second processing means determines whether or not an image processing program to be used in the next image processing can be selected based on both the image processing result and the selected execution order list, A request for transferring and storing the selected image processing program in the second storage means is issued, and if the selection cannot be made, the image processing is terminated and a notice to that effect is sent to the first processing means. The image processing apparatus according to claim 1. The image processing apparatus according to claim 1, wherein the first processing unit is a microprocessor, and the second processing unit is a DSP. First storage means for storing a plurality of execution order lists indicating the execution order of a plurality of image processing and a plurality of configuration information indicating the configuration of hardware for performing image processing;
A first processing means for selecting one execution order list from a plurality of execution order lists stored in the first storage means in the course of device control and issuing an image processing start instruction;
Second storage means used to store at least the configuration information;
Configuration information according to the execution order of the image processing shown in one execution order list selected by the first processing means in response to the start instruction of the image processing is sent from the first storage means to the second storage. Second processing means for issuing a request to transfer and store the means;
Third processing means for receiving a start instruction from the second processing means and changing the hardware configuration in accordance with the configuration information stored in the second storage means to perform corresponding image processing;
An image processing apparatus comprising: The second processing unit determines whether the configuration information used in the next image processing is selectable based on both the result of the image processing performed by the third processing unit and the selected one execution order list. If it can be selected and selected, it issues a request to transfer and store the selected configuration information to the second storage means. If it cannot be selected, the image processing in the third processing means is terminated and the fact is The image processing apparatus according to claim 4, wherein the image processing apparatus notifies the first processing means. A first storage means for storing a plurality of execution order lists indicating the execution order of a plurality of image processes and a plurality of pieces of configuration information indicating hardware configurations for performing each of execution control and image processing;
A first processing means for selecting one execution order list from a plurality of execution order lists stored in the first storage means in the course of device control and issuing an image processing start instruction;
Second storage means used to store configuration information indicating at least hardware configuration for performing the image processing;
A second processing unit that can change a hardware configuration for performing image processing according to configuration information and that can configure hardware for performing execution control of the image processing according to configuration information, the first processing unit Execution of the image processing shown in the one execution order list selected by the first processing unit is a hardware configuration corresponding to the configuration information indicating the configuration of the hardware that performs the execution control stored in the storage unit An execution control operation for issuing a request to transfer and store the configuration information indicating the hardware configuration for performing the corresponding image processing in accordance with the order from the first storage unit to the second storage unit; and the second storage unit An image processing operation for changing the hardware configuration according to the configuration information indicating the configuration of the hardware for performing the image processing stored in the means and performing the corresponding image processing; And second processing means for executing in this order by receiving an instruction to start the image processing,
An image processing apparatus comprising: In the execution control operation of the second processing means, a hardware configuration for performing the image processing used in the next image processing based on both the result of the image processing in the image processing operation and the selected execution order list If the selection can be selected, a request for transferring and storing the selected configuration information to the second storage means is issued. If the selection cannot be selected, the fact that the image processing has been completed is issued. The image processing apparatus according to claim 6, wherein the image processing apparatus notifies the first processing unit. 8. The execution order list for one image process indicates the order of individual image processes in which the target image is divided into a plurality of small regions. Image processing device. A first step of preparing in a first storage means a plurality of execution order lists indicating a plurality of image processing execution orders and a plurality of image processing programs;
A second step of selecting one execution order list from the plurality of execution order lists stored in the first storage unit and issuing an image processing start instruction;
In response to the image processing start instruction, an image processing program according to the execution order of the image processing shown in one execution order list selected in the second step is stored in the second storage unit from the first storage unit. A third step of transferring to the storage means;
A fourth step of performing image processing based on the image processing program stored in the second storage unit;
Based on both the result of image processing in the fourth step and the selected one execution order list, it is determined whether or not an image processing program to be used in the next image processing can be selected. A fifth step of transferring the stored image processing program to the second storage means and performing an end processing of the image processing if it cannot be selected;
An image processing method comprising: An image processing method in an image processing apparatus comprising processing means capable of changing the configuration of hardware for performing image processing according to configuration information,
A first step of preparing in a first storage means a plurality of execution order lists indicating a plurality of image processing execution orders and a plurality of the configuration information for performing image processing;
A second step of selecting one execution order list from the plurality of execution order lists stored in the first storage unit and issuing an image processing start instruction;
In response to the start instruction of the image processing, the configuration information according to the execution order of the image processing shown in the one execution order list selected in the second step is stored in the second storage from the first storage means. A third step of transferring to the means;
A fourth step of giving an instruction to read the configuration information stored in the second storage means to the processing means and executing image processing;
Based on both the result of the image processing performed by the processing means and the selected one execution order list, it is determined whether or not the configuration information used in the next image processing can be selected. A fifth step of transferring the stored configuration information to the second storage unit and performing an end process of the image processing in the processing unit if the selection cannot be made;
An image processing method comprising: An image processing method in an image processing apparatus including a processing unit that can change a configuration of hardware that performs image processing according to configuration information and that can configure hardware that performs execution control of the image processing according to configuration information. There,
A first step of preparing, in a first storage means, a plurality of execution order lists indicating the execution order of a plurality of image processes, and a plurality of pieces of configuration information indicating a hardware configuration for performing each of execution control and image processing; ,
From the plurality of execution order lists stored in the first storage unit, the processing unit is provided with configuration information indicating the configuration of hardware that performs the execution control stored in the first storage unit. A second step of giving an instruction to start image processing when one execution order list is selected;
In response to a request from the processing means, the second storage means that can be read by the processing means corresponds to the execution order of the image processing shown in the one execution order list selected in the second step. The configuration information indicating the configuration of the hardware that performs the image processing is transferred and stored from the first storage unit so that image processing corresponding to the configuration information can be performed, and an end notification from the processing unit is waited for. A third step;
An image processing method comprising: 12. The execution order list for one image process indicates the order of individual image processes in which the target image is divided into a plurality of small areas. Image processing method. An image processing program, wherein each step of the image processing method according to any one of claims 9 to 11 is described so as to be executable by a computer.

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