JP2008065136A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of preventing a shift of gradation cased by variations in the thickness of a film used to form an auxiliary capacitance and obtaining stable gradation-luminance characteristics. <P>SOLUTION: A frequency output from an oscillator 31 constituted of an nMOS type thin film transistor and pMOS type thin film transistor provided with detection capacitance having a layer structure similar to that of an auxiliary capacitance 21 is detected, and the potential amplitude of a power supply line Y connected to the auxiliary capacitance 21 is adjusted based on the detected frequency. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique of an active matrix liquid crystal display device provided with a switch element, an auxiliary capacitor, and a pixel electrode for each pixel.

  In recent years, active matrix liquid crystal display devices having a switch element, an auxiliary capacitor, and a pixel electrode for each section divided by a plurality of signal lines and a plurality of scanning lines wired so as to intersect each other have been actively developed. ing.

  FIG. 18 is a structural diagram showing the structure of an active matrix liquid crystal display device. A liquid crystal material (not shown) is held between the opposing array substrate 100 and the counter substrate 200. A backlight (not shown) is disposed on the back surface of the array substrate 100. On the array substrate 100, a polarizing plate 29 and a glass substrate 6a are arranged from the side far from the liquid crystal material. On the counter substrate 200, a counter electrode 24, a color filter 28, a glass substrate 6 b, and a polarizing plate 29 are arranged from the side closer to the liquid crystal material. A plurality of signal lines S and a plurality of scanning lines G are arranged in a matrix on the top of the glass substrate 6a. At each intersection of each signal line S and each scanning line G, a MOS pixel is provided. A transistor SW and a pixel electrode 22 are arranged.

  Next, a circuit configuration formed on the glass substrate 6a of the liquid crystal display device shown in FIG. 18 will be described. FIG. 19 is a circuit diagram illustrating an example of a circuit configuration of an active matrix liquid crystal display device. The source electrode of the pixel transistor SW is connected to the signal line S, the gate electrode is connected to the scanning line G, and the auxiliary capacitor 21 and the pixel electrode 22 are connected to the drain electrode. A liquid crystal capacitor 23 is sandwiched between the pixel electrode 22 and the counter electrode 24. The other terminal of the auxiliary capacitor 21 that is not connected to the drain electrode is connected to the power supply wiring Y. The pixel transistor SW, auxiliary capacitor 21, pixel electrode 22, liquid crystal capacitor 23, and counter electrode 24 constitute a pixel in the screen portion of the liquid crystal display device.

  Next, the overall configuration of the liquid crystal display panel having the circuit configuration of the liquid crystal display device shown in FIG. 19 will be described. FIG. 20 is a circuit diagram showing a basic configuration of a liquid crystal display panel. In the display unit 2 of the liquid crystal display panel, the pixels described with reference to FIG. 19 are arranged at intersections of n × m matrix wirings composed of n rows of scanning lines G1 to Gn and m columns of signal lines S1 to Sm. . The signal lines S1 to Sm are connected to the signal line drive circuit 8, the scan lines G1 to Gn are connected to the scan line drive circuit 9, and the power supply lines Y1 to Yn are connected to the power supply circuit 5.

  Note that the signal lines S1 to Sm, the scanning lines G1 to Gn, the power supply lines Y1 to Yn, the pixel transistor SW, the auxiliary capacitor 21, and the pixel electrode 22 are formed on the insulating glass substrate 6a as described in FIG. Is formed. The signal line driving circuit 8, the scanning line driving circuit 9, and the power supply circuit 5 are also arranged on the same glass substrate 6a.

  Next, an operation principle of the active matrix liquid crystal display device will be described with reference to FIGS. The driving of the dot matrix type liquid crystal display arranged in n × m is a line sequential sampling in which the image data signals supplied simultaneously to the signal lines S1 to Sm are sampled by the scanning line signals sequentially supplied to the scanning lines G1 to Gn. This is done by driving.

  When a certain time (T1 to Tn) is assigned to each scanning line G, when a scanning line signal is applied to the scanning line G1 at a certain selection time T1, all the pixel transistors SW11 arranged on the scanning line G1. ... SW1m is turned on and changes to a switched on state. As a result, the image data signal transmitted to the signal lines S1 to Sm is transmitted to the pixel electrode 22 through the pixel transistors SW11 to SW1m and also supplied to the auxiliary capacitor 21. When the image data signal is supplied to the auxiliary capacitor 21, the electric potential of the power supply wiring Y1 connected to the auxiliary capacitor 21 is changed to redistribute the charge of the auxiliary capacitor 21, and the voltage applied to the pixel electrode 22 is changed. decide. A method for determining the voltage of the pixel electrode 22 in this way is called a capacitive coupling driving method. As this type of liquid crystal display device, for example, the one described in Patent Document 1 is known. As a result, a voltage difference is generated between the pixel electrode 22 and the counter electrode 24, and the alignment of liquid crystal molecules in the liquid crystal capacitor 23 is controlled. Thereby, the brightness of the incident light of the backlight shown in FIG. 18 is adjusted, and color display according to the image data signal can be performed via the color filter 28.

  In the next selection time T2, all the pixel transistors SW11 to SW1m in the scanning line G1 are turned off, and the pixels selected by the scanning line G1 are electrically disconnected from the signal lines S1 to Sm. At this time, the image displayed by the selection time T1 is held by the auxiliary capacitor 21 until the next scanning line signal is applied to the scanning line G1. On the other hand, all the pixel transistors SW21 to SW2m arranged on the scanning line G2 are turned on, and the image data signal is transmitted to the pixel electrode 22 and supplied to the auxiliary capacitor 21. Thereafter, the same operation is repeated to display one frame.

There are many uses for liquid crystal display devices, but especially for liquid crystal display devices for mobile terminals, there is a strong need for high definition and high brightness. To display images such as photographs clearly, the gradation of the liquid crystal panel It is required that the luminance characteristics do not vary.
JP 2001-255851 A

  However, in the capacitive coupling drive type liquid crystal display device described above, variation in writing of the video signal voltage applied through the pixel transistor SW occurs due to variations in the film thickness of the film forming the auxiliary capacitance, and the gray level and the like. There was a problem that display characteristics deteriorated.

  The present invention has been made in view of the above, and an object of the present invention is to prevent deterioration of display characteristics of a liquid crystal display device.

  A liquid crystal display device according to a first aspect of the present invention includes a display unit including a switch element, an auxiliary capacitor, and a pixel electrode for each section divided by a plurality of scanning lines and a plurality of signal lines, and a layer similar to the auxiliary capacitor A first oscillator having a structure detection capacity; a first frequency counter for counting the frequency output from the first oscillator; a first register for storing the counted frequency; A converter for converting the stored frequency into the adjustment value based on the relationship between the frequency output from the first oscillator and the adjustment value of the potential amplitude of the auxiliary capacitor; and the converted adjustment value And an adjuster for adjusting the potential amplitude of the power supply wiring connected to the auxiliary capacitor.

  In the present invention, the frequency output from the first oscillator having the detection capacitor having the same layer structure as the auxiliary capacitor is detected, and the potential amplitude of the power supply wiring connected to the auxiliary capacitor is detected based on this frequency. By adjusting the frequency, the variation in the frequency of the first oscillator corresponds to the variation in the film thickness of the auxiliary capacitor. Therefore, the gradation shift due to the film thickness variation can be prevented with a simple configuration, and the stable gradation- Luminance characteristics can be obtained.

  The liquid crystal display device according to a second aspect of the present invention is characterized in that the first oscillator is a circuit in which an inverter composed of a thin film transistor having the detection capacitor is cascaded in an odd number of stages.

  In the liquid crystal display device according to the third aspect of the present invention, a resistor is connected between the output terminal of the inverter and the input terminal of the inverter connected to the next stage of the inverter, and the input terminal of the inverter and the power supply line are connected. The detection capacitor is further provided in between.

  In a liquid crystal display device according to a fourth aspect of the present invention, an inverter composed of thin film transistors having the detection capacitance is connected in an odd number of stages in a loop, and the inverter is connected to the output terminal of the inverter and the next stage of the inverter A second oscillator having a reference capacitor having a structure different from that of the detection capacitor between the input terminal of the inverter and a power supply line, and the second oscillator A second frequency counter that counts the frequency output from the second frequency counter, a second register that stores the frequency counted by the second frequency counter, and a difference between the frequencies stored in the first register and the second register. A difference calculator for calculating, and the converter includes a predetermined difference between the frequency output from the first oscillator and the second oscillator and the auxiliary capacity. Based on the relationship between the adjustment value of the potential amplitude, and converting the difference frequency calculated by the difference calculator to the adjustment value.

  In the present invention, the same layer as that of the auxiliary capacitor based on the relationship between the frequency difference output from the first and second oscillators determined in advance and the adjustment value of the potential amplitude of the auxiliary capacitor. Since the difference between the frequencies output from the first oscillator having the detection capacitor having the structure and the second oscillator having the reference capacitor having a structure different from the detection capacitor is converted into an adjustment value, the first oscillation is performed. The potential amplitude of the power supply wiring connected to the auxiliary capacitor can be adjusted by using the frequency excluding the influence of the thin film transistor characteristics of the thin film transistor and other parasitic capacitances, and more stable gradation-luminance characteristics can be obtained. .

The liquid crystal display device according to a fifth aspect of the present invention is characterized in that the detection capacitor contains an impurity having a concentration set to 1E19 atoms / cm ^{3 to} 1E22 atoms / cm ³ in the channel portion.

In the present invention, since the impurity having a concentration set to 1E19 atoms / cm ^{3 to} 1E22 atoms / cm ³ is contained in the channel portion of the detection capacitor, the operation of the first oscillator and / or the second oscillator is stabilized. Can be.

  According to the present invention, it is possible to prevent gradation shift due to film pressure variation of the film forming the auxiliary capacitor, and to obtain stable gradation-luminance characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a configuration diagram showing a schematic configuration of the liquid crystal display device according to the first embodiment. The array substrate 100 is obtained by forming a display unit 2, an auxiliary capacitance detection circuit 3, an auxiliary capacitance voltage adjustment circuit 4, and a power supply circuit 5 on a translucent substrate. A thin film transistor (TFT) is employed as a transistor in each circuit in order to enable formation on a light-transmitting substrate.

  In the display unit 2, a plurality of scanning lines G and a plurality of signal lines S are wired so as to intersect with each other, and a pixel is provided for each section divided by the scanning lines G and the signal lines S. Each pixel includes a switch element SW, an auxiliary capacitor 21, a pixel electrode 22, a liquid crystal capacitor 23, and a counter electrode 24. Here, the switch element SW is a MOS type thin film transistor. The gate electrode of the switch element SW is connected to the scanning line G, the source electrode is connected to the signal line S, and the drain electrode is connected to the auxiliary capacitor 21 and the pixel electrode 22. A power supply wiring Y is connected to the other terminal of the auxiliary capacitor 21. In the present liquid crystal display device, a counter substrate having a counter electrode 24 is disposed opposite to the array substrate 100 with a liquid crystal layer interposed therebetween, and the pixel electrode 22 in the array substrate 100 and the counter electrode 24 in the counter substrate sandwich a liquid crystal capacitor 23. Arranged to face each other.

  Next, the layer structure of the MOS thin film transistor and the auxiliary capacitor 21 constituting the switch element SW will be briefly described. FIG. 2 is a cross-sectional view showing a layer structure of the nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb and the auxiliary capacitor 21. The nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb and the auxiliary capacitor 21 have a layer structure having a gate insulating film 71 having the same thickness. Specifically, on the glass substrate 6a and the undercoat 7, A channel 70 made of silicon (p-Si), a gate insulating film 71, a gate electrode 72, an interlayer insulating film 73, and a source / drain electrode 74 are provided. The gate insulating film 71 functions as a gate oxide film capacitor as a dielectric for storing charges in the nMOS thin film transistor SWa and the pMOS thin film transistor SWb and the auxiliary capacitor 21.

  Each channel 70 contains phosphorus or boron impurities. In the case of the nMOS type thin film transistor SWa, a high concentration phosphorus is contained in a portion in contact with the source / drain electrode 74, and a low concentration phosphorus is contained therein. In the case of the pMOS type thin film transistor SWb, high concentration boron is contained in the portion in contact with the source / drain electrode 74. In the case of the auxiliary capacitor 21, high concentration phosphorus is contained in the entire region of the channel 70.

FIG. 3 is a graph showing the relationship between the voltage and the gate oxide film capacitance when the concentrations of impurities contained in the channel 70 are different. When the impurity concentration is low, the gate oxide film capacitance greatly depends on the voltage change, so that the operations of the nMOS type thin film transistor SWa and pMOS type thin film transistor SWb and the auxiliary capacitor 21 become unstable and affect the operation of the liquid crystal display device. . On the other hand, when the impurity concentration is high, the gate oxide film capacitance with respect to the change in voltage is constant, so that the voltage dependency is very low. Therefore, it becomes possible to stabilize the operation of the nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb and the auxiliary capacitor 21 by containing a high concentration impurity set to 1E19 atoms / cm ^{3 to} 1E22 atoms / cm ^3. .

  Next, the operation of the pixel when the scanning line G and the signal line S are driven will be described with reference to the waveform diagram of FIG. In FIG. 4, the video signal voltage on the signal line S is indicated by Vs, the scanning line signal voltage on the scanning line G is indicated by Vg, the voltage of the auxiliary capacitor 21 is indicated by Vcs, and the voltage of the counter electrode 24 is indicated by Vcom. Here, the voltage Vcom of the counter electrode 24 is constant.

  When the scanning signal voltage Vg temporarily becomes high level at the first timing, the video signal voltage Vs at that time is applied to the auxiliary capacitor 21, and the auxiliary capacitor voltage Vcs is determined by the video signal voltage Vs and the voltage of the power supply wiring Y. It is determined. The figure shows a state where the auxiliary capacitance voltage Vcs has increased. Then, when the scanning signal voltage Vg temporarily becomes high level at the second timing, the video signal voltage Vs at that time is applied to the auxiliary capacitor 21, and is also assisted by the video signal voltage Vs and the voltage of the power supply wiring Y. A capacitance voltage Vcs is determined. The figure shows a state where the auxiliary capacitance voltage Vcs is lowered. Thus, the voltage Vcs of the auxiliary capacitor 21 has an amplitude ΔVcs corresponding to the video signal voltage Vs and the voltage of the power supply wiring Y.

  Next, the description returns to FIG. The auxiliary capacitance detection circuit 3 includes an oscillator 31, a frequency counter 32, and a register 33. The frequency output from the oscillator 31 is counted by the frequency counter 32, temporarily stored in the register 33, and then transmitted to the auxiliary capacitance voltage adjustment circuit 4.

  FIG. 5 is a circuit diagram showing a circuit configuration of the oscillator 31 in the present embodiment. The oscillator 31 is composed of a MOS type thin film transistor having a detection capacitor having a layer structure similar to that of the auxiliary capacitor 21. Specifically, the nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb shown in FIG. 2 are connected in series. The inverter is composed of a ring oscillator circuit in which five stages are cascaded in a loop. When the input / output is looped, a logical value obtained by inverting the logical value input to the input terminal of each inverter returns to the input terminal, so that the inversion of the input is repeated indefinitely and operates as an oscillator. Further, the source electrodes of all the nMOS type thin film transistors SWa are connected to the power source VSS, and the source electrodes of all the pMOS type thin film transistors SWb are connected to the power source VDD to which a current voltage different from the power source VSS is supplied.

  The frequency f of the oscillator 31 composed of the ring oscillator circuit is determined by the following equation using the delay time τpd of the inverter and the number N of inverters.

f = 1 / (2 × τpd × N) (1)
The delay time τpd is determined by the following equation using the saturation current Ion (nch) of the nMOS type thin film transistor and the saturation current Ion (pch) of the pMOS type thin film transistor. Note that k is a coefficient.

τpd = k × (1 / Ion (nch) + 1 / Ion (pch)) (2)
Further, the saturation current Ion of the MOS transistor is determined by the following equation using the carrier mobility μ, the gate width W, the gate length L, the gate oxide film capacitance C per unit area, the gate voltage Vgs, and the threshold voltage Vth.

Ion = (1/2) × μ × C (W / L) × (Vgs−Vth) ² (3)
In Expression (3), since the gate voltage Vgs and the threshold voltage Vth are fixed values, the frequency f is proportional to the gate oxide film capacitance C from the relationship of Expression (1) to Expression (3). FIG. 6 is a graph showing the relationship between the frequency f output from the oscillator 31 and the gate oxide film capacitance C in the present embodiment. The frequency is obtained in this way because the film thickness variation of the auxiliary capacitor 21 corresponds to the frequency variation output from the oscillator 31. That is, the variation in frequency output from the oscillator 31 corresponds to the variation in gate oxide film capacitance as shown in FIG. Since the oscillator 31 is configured by using the nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb having a detection capacitor having the same layer structure as that of the auxiliary capacitor 21, the variation in the frequency output from the oscillator 31 is an auxiliary value. This corresponds to the variation in the gate oxide film capacitance of the capacitor 21, and as a result, corresponds to the variation in the film thickness of the gate insulating film 71 in the auxiliary capacitor 21.

  Returning to FIG. 1, the auxiliary capacitance voltage adjustment circuit 4 will be described. The auxiliary capacitance voltage adjustment circuit 4 includes a converter 41, a digital / analog converter 42, an amplifier 43, and an adjustment device 44, and a power source connected to the auxiliary capacitance 21 based on the frequency output from the auxiliary capacitance detection circuit 3. The potential amplitude of the wiring Y is adjusted. The adjustment method will be described next.

  FIG. 7 is a graph showing the gradation-luminance characteristics. In the figure, the ideal characteristic is indicated by a reference line L1. When the frequency detected by the auxiliary capacitance detection circuit 3 is high, the potential fluctuation ΔV when the auxiliary capacitance voltage Vcs is inverted increases, so that the polarizing plates are arranged orthogonally so that light is transmitted when no voltage is applied. In the case of the normally white mode, as shown by a curve L2 in FIG. This is because the potential fluctuation ΔV is determined by the following equation.

ΔV = ΔVcs × Ccs / Ctotal (4)
Here, Ctotal is a total capacity including an auxiliary capacity Ccs, a liquid crystal capacity (capacitance of the liquid crystal layer) Ccl, and a parasitic capacity Ctft of the thin film transistor, and is expressed by the following equation.

Ctotal = Ccs + Ccl + Ctft + (5)
Since the potential fluctuation ΔV is determined as shown in Equation (4), when the frequency detected by the auxiliary capacitance detection circuit 3 is high, the capacitance Ccs also increases proportionally as shown in FIG. Increases the luminance by adjusting the potential amplitude ΔVcs of the power supply wiring Y connected to the auxiliary capacitor 21 in a decreasing direction. Further, when the detected frequency is low, the luminance shifts in the direction of increasing the luminance as shown by the curve L3 in FIG. 7, and thus the luminance is lowered by adjusting the potential amplitude ΔVcs in the increasing direction.

  FIG. 8 is a graph showing the relationship between the frequency f of the oscillator 31 detected by the auxiliary capacitance detection circuit 3 and the adjustment value of the potential amplitude ΔVcs of the auxiliary capacitance 21. Such a relationship is previously determined in the conversion table, and the auxiliary capacitance voltage adjustment circuit 4 performs adjustment based on this relationship. The converter 41 converts the frequency stored in the register 33 into a potential amplitude ΔVcs based on this conversion table. The converted potential amplitude ΔVcs is converted into an analog signal by the digital / analog converter 42, amplified by a predetermined magnification by the amplifier 43, and transmitted to the adjuster 44. The adjuster 44 adjusts the potential amplitude of the power supply wiring Y connected to the auxiliary capacitor 21 based on the converted potential amplitude ΔVcs of the analog signal.

  Note that the method of adjusting the potential amplitude of the power supply wiring Y using the adjustment value of the potential amplitude ΔVcs is not limited to this. For example, after being amplified by the amplifier 43, it can be converted into an analog signal by the digital-analog converter 42. It is also possible to transmit the analog signal converted by the digital-analog converter 42 to the adjuster 44 without going through the amplifier 43. The adjuster 44 can not only add the adjustment value to the potential amplitude but also use subtraction, multiplication, division, and the like.

  According to the present embodiment, the frequency output from the oscillator 31 composed of the nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb having the detection capacitor having the same layer structure as the auxiliary capacitor 21 is detected, and this frequency is detected. By adjusting the potential amplitude of the power supply wiring Y connected to the auxiliary capacitor 21 based on the above, the variation in the frequency of the oscillator 31 corresponds to the variation in the film thickness of the auxiliary capacitor 21. Gradation shift due to variation can be prevented, and stable gradation-luminance characteristics can be obtained.

  According to the present embodiment, the auxiliary capacitance voltage adjustment circuit 4 is based on the predetermined relationship between the frequency output from the oscillator 31 and the adjustment value of the potential amplitude ΔVcs of the auxiliary capacitance 21. Thus, the auxiliary capacitance voltage adjustment circuit 4 can be realized with a simple configuration and accurate adjustment can be realized.

According to the present embodiment, the channel portion of the nMOS type thin film transistor SWa and the pMOS type thin film transistor SWb contains the impurity having a concentration set to 1E19 atoms / cm ^{3 to} 1E22 atoms / cm ³ , so that the operation of the oscillator 31 is stabilized. Can be.
[Modification]

  FIG. 9 is a circuit diagram showing a modification of the circuit configuration of the oscillator 31. In the oscillator 31 in this modification, a resistor 25 is further connected between the output terminal of the inverter described above and the input terminal of the inverter connected to the next stage, and between the input terminal of the inverter and the power source VSS. Further, a detection capacitor 26 having a layer structure similar to that of the auxiliary capacitor 21 is further provided. FIG. 10 is a configuration diagram showing the configuration of the detection capacitor 26. In the detection capacitor 26, a gate insulating film 71 is sandwiched between the gate electrode 72 and polysilicon containing a high concentration impurity. About the effect in the case of containing a high concentration impurity, it is the same as the effect demonstrated above. This polysilicon corresponds to the channel 70 of the auxiliary capacitor 21 shown in FIG.

  Returning to FIG. 9, when the delay time τrc formed by the product of the resistor 25 and the detection capacitor 26 is sufficiently larger than the delay time τpd of the inverter alone, the frequency of the oscillator 31 uses the delay time τrc and the number N of inverters. Is determined by the following equation.

f = 1 / (2 × τrc × N) (6)
Here, since the delay time τrc is proportional to the film thickness of the gate insulating film 71 of the detection capacitor 26, the frequency f is inversely proportional to the gate oxide film capacitance C of the detection capacitor 26 from Equation (6). FIG. 11 is a graph showing the relationship between the frequency f output from the oscillator 31 of this modification and the gate oxide film capacitance C. As described above, since the film thickness variation of the auxiliary capacitor 21 corresponds to the frequency variation output from the oscillator 31, the auxiliary capacitor detection circuit 3 including the oscillator 31 of the present modification shown in FIG. The potential amplitude of the power supply wiring Y connected to the auxiliary capacitor 21 can be adjusted by preliminarily defining in the conversion table the relationship between the frequency f detected by the above and the adjustment value of the potential amplitude ΔVcs of the auxiliary capacitor 21. become.

  Specifically, when the frequency detected by the auxiliary capacitance detection circuit 3 is high, the capacitance Ccs decreases as shown in FIG. 11, so that the auxiliary capacitance voltage adjustment circuit 4 is connected to the power supply wiring Y connected to the auxiliary capacitance 21. The luminance is lowered by adjusting the potential amplitude ΔVcs in the direction of increasing. Further, when the detected frequency is low, the luminance is shifted as shown by a curve L2 in FIG. 7, so that the luminance is increased by adjusting the potential amplitude ΔVcs to be smaller.

  The other configurations and operations are the same as the configurations and operations described above, and thus a duplicate description is omitted here.

  According to this modification, the frequency output from the oscillator 31 including the detection capacitor 26 having the same layer structure as that of the auxiliary capacitor 21 is detected, and the power supply wiring Y connected to the auxiliary capacitor 21 based on this frequency. By adjusting the potential amplitude of the oscillator 31, the variation in the frequency of the oscillator 31 corresponds to the variation in the film thickness of the auxiliary capacitor 21, so that the gradation shift due to the film thickness variation can be prevented with a simple configuration and stable. A gradation-luminance characteristic can be obtained.

  According to this modification, as with the effect described above, the auxiliary capacitance voltage adjustment circuit 4 can be realized with a simple configuration and accurate adjustment can be realized.

According to this modification, the polysilicon of the detection capacitor 26 contains impurities having a concentration set to 1E19 atoms / cm ^{3 to} 1E22 atoms / cm ³ , so that the operation of the oscillator 31 can be stabilized.

[Second Embodiment]
FIG. 13 is a configuration diagram illustrating a schematic configuration of the liquid crystal display device according to the second embodiment. The auxiliary capacitance detection circuit 3 in the present embodiment further includes a second oscillator 31 ′, a second frequency counter 32 ′, a second register 33 ′, and a difference calculator 34. Since the other configuration is the same as that of the first embodiment, a duplicate description is omitted here. In the present embodiment, the modified oscillator 31, the frequency counter 32, and the register 33 described with reference to FIG. 9 in the first embodiment are replaced with the first oscillator 31, the first frequency counter, respectively. 32 and the first register 33.

  FIG. 14 is a circuit diagram showing a circuit configuration of the second oscillator 31 '. The configuration of the second oscillator 31 ′ in the present embodiment is basically the same as the configuration of the first oscillator 31, but between the input terminal of the inverter and the power source VSS, the detection capacitor 26 and Includes a reference capacitor 27 having a different structure. FIGS. 15 and 16 are configuration diagrams showing an example of the configuration of the reference capacitor 27. The reference capacitor 27 shown in FIG. 15 has an interlayer insulating film 73 sandwiched between the gate electrodes 72, and the reference capacitor 27 shown in FIG. 16 has an interlayer insulating film 73 between the gate electrode 72 and the source / drain electrodes 74. Is pinched.

  As described in the first embodiment, the film thickness variation of the auxiliary capacitor 21 corresponds to the frequency variation output from the first oscillator 31. However, the frequency output from the first oscillator 31 includes the influence of the thin film transistor characteristics of the MOS thin film transistor constituting the first oscillator 31 and other parasitic capacitances. Therefore, the auxiliary capacitance detection circuit 3 uses a second transmitter 31 ′ having a reference capacitor 27 having a structure different from that of the detection capacitor 26, and uses the second frequency counter to calculate the frequency output from the second transmitter 31 ′. After counting at 32 ′ and temporarily storing it in the second register 33 ′, the difference calculator 34 calculates the difference in frequency output from the first oscillator 31 and the second oscillator 31 ′. Eliminate effects such as characteristics.

  The auxiliary capacitance voltage adjustment circuit 4 determines the relationship between the difference frequency Δf detected from the auxiliary capacitance detection circuit 3 shown in FIG. 17 and the adjustment value of the potential amplitude ΔVcs of the auxiliary capacitance 21 in advance in the conversion table. The potential amplitude of the power supply wiring Y connected to the capacitor 21 is adjusted. A specific method for adjusting the potential amplitude of the power supply wiring Y is the same as the adjustment method described in the modification of the first embodiment, and thus a duplicate description is omitted here.

  Further, the operation of the other configuration is the same as the operation described in the first embodiment, and therefore, a duplicate description is omitted here.

  The insulating film that constitutes the reference capacitor 27 is not limited to the interlayer insulating film 73, and other insulating films having a known frequency may be used.

  According to the present embodiment, the auxiliary frequency is determined based on the relationship between the predetermined frequency difference output from the first oscillator 31 and the second oscillator 31 ′ and the adjustment value of the potential amplitude of the auxiliary capacitor 21. A first oscillator 31 including a detection capacitor 26 having a layer structure similar to the capacitor 21 and a second oscillator including a reference capacitor 27 including an interlayer insulating film 73 having a structure different from that of the detection capacitor 26. Since the difference in frequency output from 31 'is converted into an adjustment value, it is connected to the auxiliary capacitor 21 using a frequency that eliminates the influence of the thin film transistor characteristics of the MOS thin film transistor constituting the oscillator and other parasitic capacitances. The potential amplitude of the power supply wiring Y can be adjusted, and more stable gradation-luminance characteristics can be obtained.

  According to the present embodiment, the potential is determined based on the relationship between the predetermined frequency difference output from the first oscillator 31 and the second oscillator 31 ′ and the adjustment value of the potential amplitude of the auxiliary capacitor 21. By adjusting the amplitude ΔVcs, the auxiliary capacitance voltage adjusting circuit 4 can be realized with a simple configuration and accurate adjustment can be realized.

It is a block diagram which shows schematic structure of the liquid crystal display device in 1st Embodiment. It is sectional drawing which shows the layer structure of an nMOS type thin film transistor and a pMOS type thin film transistor, and an auxiliary capacity. It is a graph which shows the relationship between the voltage and gate oxide film capacity | capacitance in case the density | concentration of the impurity contained in the channel differs. It is a figure which shows the voltage waveform of each part in a pixel. It is a circuit diagram which shows the circuit structure of the oscillator in 1st Embodiment. It is a graph which shows the relationship between the frequency output from the oscillator in 1st Embodiment, and gate oxide film capacity | capacitance. It is a graph which shows a gradation-luminance characteristic. It is a graph which shows the relationship between the frequency of the oscillator detected by the auxiliary capacity detection circuit, and the adjustment value of the potential amplitude of an auxiliary capacity. It is a circuit diagram which shows the modification of the circuit structure of an oscillator. It is a block diagram which shows the structure of the capacity | capacitance for a detection. It is a graph which shows the relationship between the frequency output from the oscillator of this modification, and gate oxide film capacity | capacitance. It is a graph which shows the relationship between the frequency detected by the auxiliary capacity detection circuit provided with the oscillator of this modification, and the adjustment value of the electric potential amplitude of an auxiliary capacity. It is a block diagram which shows schematic structure of the liquid crystal display device in 2nd Embodiment. It is a circuit diagram which shows the circuit structure of a 2nd oscillator. It is a block diagram which shows an example of a structure of the capacity | capacitance for reference. It is a block diagram which shows an example of a structure of the capacity | capacitance for reference. It is a graph which shows the relationship between the frequency detected from the auxiliary capacity detection circuit in 2nd Embodiment, and the adjustment value of the electric potential amplitude of an auxiliary capacity. It is a structural diagram showing the structure of an active matrix driving type liquid crystal display device. It is a circuit diagram showing an example of a circuit configuration of an active matrix liquid crystal display device. It is a circuit block diagram which shows the basic composition of a liquid crystal display panel.

Explanation of symbols

C: Gate oxide film capacitance G, G1-Gn: Scan line L1: Reference line L2, L3 ... Curve S, S1-Sm ... Signal line SW, SW11-SWnm ... Pixel transistor, switch element SWa ... nMOS type thin film transistor SWb ... pMOS Type thin film transistor VDD, VSS: power supply Y, Y1 to Yn ... power supply wiring f ... frequency 1 ... array substrate 2 ... display unit 3 ... auxiliary capacitance detection circuit 4 ... auxiliary capacitance voltage adjustment circuit 5 ... power supply circuit 6, 6a, 6b ... glass Substrate 7 ... Undercoat layer 8 ... Signal line drive circuit 9 ... Scan line drive circuit 21 ... Auxiliary capacitance 22 ... Pixel electrode 23 ... Liquid crystal capacitance 24 ... Counter electrode 25 ... Resistance 26 ... Detection capacitance 27 ... Reference capacitance 28 ... Color Filter 29 ... Polarizing plate 31 ... Oscillator, first oscillator 31 '... Second oscillator 32 ... Frequency counter, first frequency cowl 32 '... second frequency counter 33 ... register, first register 33' ... second register 34 ... difference calculator 41 ... conversion table 42 ... digital / analog converter 43 ... amplifier 44 ... adder 70 ... channel 71 ... gate insulation Film 72 ... Gate electrode 73 ... Interlayer insulating film 74 ... Source / drain electrode 100 ... Array substrate 200 ... Counter substrate

Claims (5)

A display unit including a switch element, an auxiliary capacitor, and a pixel electrode for each section divided by a plurality of scanning lines and a plurality of signal lines;
A first oscillator including a detection capacitor having a layer structure similar to the auxiliary capacitor;
A first frequency counter for counting the frequency output from the first oscillator;
A first register for storing the counted frequency;
A converter that converts the stored frequency into the adjustment value based on a predetermined relationship between the frequency output from the first oscillator and the adjustment value of the potential amplitude of the auxiliary capacitor;
A regulator that adjusts the potential amplitude of the power supply wiring connected to the auxiliary capacitor, based on the converted adjustment value;
A liquid crystal display device comprising:   2. The liquid crystal display device according to claim 1, wherein the first oscillator is a circuit in which an inverter composed of a thin film transistor having the detection capacitor is cascade-connected in an odd number of stages. 5.   A resistor is connected between an output terminal of the inverter and an input terminal of an inverter connected to the next stage of the inverter, and the detection capacitor is further provided between the input terminal of the inverter and a power line. The liquid crystal display device according to claim 2. An inverter composed of thin film transistors having the detection capacitance is connected in an odd number of stages in a loop, and a resistor is connected between the output terminal of the inverter and the input terminal of the inverter connected to the next stage of the inverter, A second oscillator having a reference capacitor having a structure different from that of the detection capacitor between the input terminal of the inverter and a power line;
A second frequency counter that counts the frequency output from the second oscillator;
A second register for storing the frequency counted by the second frequency counter;
A difference calculator for calculating a difference between the frequencies stored in the first register and the second register;
The converter uses a difference calculator based on a predetermined relationship between the frequency difference output from the first oscillator and the second oscillator and the adjustment value of the potential amplitude of the auxiliary capacitor. 4. The liquid crystal display device according to claim 3, wherein the calculated difference frequency is converted into the adjustment value. 5. The liquid crystal display device according to claim 1, wherein the detection capacitor contains an impurity having a concentration set to 1E19 atoms / cm ^{3 to} 1E22 atoms / cm ³ in a channel portion.

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