JP2008053543A - Laminated chip component - Google Patents

Laminated chip component Download PDF

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JP2008053543A
JP2008053543A JP2006229499A JP2006229499A JP2008053543A JP 2008053543 A JP2008053543 A JP 2008053543A JP 2006229499 A JP2006229499 A JP 2006229499A JP 2006229499 A JP2006229499 A JP 2006229499A JP 2008053543 A JP2008053543 A JP 2008053543A
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conductor pattern
insulating film
film layer
electrode
elements
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Satoshi Higuchi
聡 樋口
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FDK Corp
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FDK Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip component that is advantageous in increasing the number of elements to be formed inside even in chip reduction, and can excellently obtain performance as a functional element. <P>SOLUTION: A chip 1 is formed by laminating insulating films (a) of ceramic material and conductor patterns (b) in an appropriate order. In insulating films a1 to a10, no conductor pattern is formed in upper and lower outer-most layers a1, a10 but conductor patterns (b) are formed from inside insulating film layer a2 to insulating film layer a9, respectively, and they are defined as capacitance elements and inductance elements and connected mutually to provide a configuration of a low-pass filter. Inductance elements (b22, b32) are formed on the same plane as electrodes b21, b31 of the capacitance elements in the insulating film layers a2, a3, and connected in series to provide a serial resonance circuit. In the insulating film layers a4, a5, inductance elements on the same plane as the capacitance elements are also similarly connected in series to provide a serial resonance circuit but paired film layers are overlapped oppositely and set so as not to overlap portions of the inductance elements. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、積層チップ部品に関するもので、より具体的には、セラミック材料の絶縁膜と導体パターンを適宜な順に積層してなるチップ体について、容量素子および誘導素子をなす導体パターンの配置構成の改良に関する。   The present invention relates to a multilayer chip component. More specifically, a chip body formed by laminating an insulating film of a ceramic material and a conductor pattern in an appropriate order has an arrangement configuration of a conductor pattern that forms a capacitive element and an inductive element. Regarding improvement.

周知のように、チップ部品と呼ばれる電子部品は、表面実装に使用するためリード端子を廃して小片形状に小型化しており、チップ体の表面に形成した電極を、基板表面へ接触させて直接にはんだ付けすることになる。チップ部品としては、セラミック材料の絶縁膜と導体パターンを適宜な順に積層することによりチップ体を形成し、当該チップ体の内部に導体パターンによる電極体を内蔵し、これはコンデンサ(容量素子)やインダクタ(誘導素子)など、単体の機能素子として構成することもあるが、例えば特許文献1,2などに見られるように、チップ体には容量素子および誘導素子を適宜に内蔵させてローパスフィルタ等に構成することが行われている。   As is well known, an electronic component called a chip component has been reduced in size to a small piece by eliminating the lead terminal for use in surface mounting, and the electrode formed on the surface of the chip body is directly brought into contact with the substrate surface. It will be soldered. As a chip component, a chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern in an appropriate order, and an electrode body with a conductor pattern is built in the chip body. Although it may be configured as a single functional element such as an inductor (inductive element), for example, as seen in Patent Documents 1 and 2, etc., a low-pass filter or the like by appropriately incorporating a capacitive element and an inductive element in the chip body It has been configured to.

図1は積層チップ部品の従来の一例であり、各層を分離して示す斜視図である。そして、図2は図1に示す積層チップ部品の電気的な構成を説明する等価回路図である。   FIG. 1 is an example of a conventional multilayer chip component, and is a perspective view showing each layer separately. 2 is an equivalent circuit diagram for explaining the electrical configuration of the multilayer chip component shown in FIG.

この積層チップ部品は、チップ体1の内部に容量素子および誘導素子を内蔵し、それら相互の接続によりローパスフィルタとして動作する構成になっている。チップ体1は、絶縁膜aをa1からa8までの8層とし、上下の最外層a1,a8には導体パターンを形成しないが、第2の絶縁膜層a2から第7の絶縁膜層a7についてそれぞれ導体パターンbを形成している。   This multilayer chip component has a configuration in which a capacitive element and an inductive element are built in the chip body 1 and operates as a low-pass filter by their mutual connection. The chip body 1 has eight insulating films a1 to a8, and no conductor pattern is formed on the upper and lower outermost layers a1 and a8, but the second insulating film layer a2 to the seventh insulating film layer a7. Each conductor pattern b is formed.

絶縁膜層a2上には、容量素子C2の電極となる導体パターンb21を長方形状に形成し、導体パターンb21は一方端の出力電極側の縁部に達している。絶縁膜層a3上には、容量素子C1,C2の電極となる導体パターンb31を中央部に長方形状に形成し、導体パターンb31は側方の接地電極側の縁部に達している。絶縁膜層a4上には、容量素子C0,C1の電極となる導体パターンb41を長方形状に形成し、導体パターンb41は他方端の入力電極側の縁部に達している。絶縁膜層a5上には、容量素子C0の電極となる導体パターンb51を長方形状に形成し、導体パターンb51は一方端の出力電極側の縁部に達している。絶縁膜層a6上には、誘導素子L0のコイル部となる導体パターンb61を形成し、導体パターンb61は他方端の入力電極側の縁部から略J字状に引き回して先端が導体により上層a7の導体パターンb71と接続させている。つまり、絶縁膜層a7上には、誘導素子L0のコイル部となる導体パターンb71を形成し、導体パターンb71は一方端の出力電極側の縁部から略L字状に引き回して先端が導体により下層a6の導体パターンb61と接続させている。   On the insulating film layer a2, a conductor pattern b21 serving as an electrode of the capacitive element C2 is formed in a rectangular shape, and the conductor pattern b21 reaches the edge on the output electrode side at one end. On the insulating film layer a3, a conductor pattern b31 serving as the electrodes of the capacitive elements C1 and C2 is formed in a rectangular shape in the center, and the conductor pattern b31 reaches the edge on the side of the side ground electrode. On the insulating film layer a4, a conductor pattern b41 serving as the electrodes of the capacitive elements C0 and C1 is formed in a rectangular shape, and the conductor pattern b41 reaches the other edge of the input electrode side. On the insulating film layer a5, a conductor pattern b51 to be an electrode of the capacitive element C0 is formed in a rectangular shape, and the conductor pattern b51 reaches the edge on the output electrode side at one end. On the insulating film layer a6, a conductor pattern b61 serving as a coil portion of the inductive element L0 is formed. The conductor pattern b61 is drawn in a substantially J shape from the edge on the input electrode side of the other end, and the tip is formed by the conductor to form the upper layer a7. The conductor pattern b71 is connected. That is, on the insulating film layer a7, the conductor pattern b71 that becomes the coil portion of the induction element L0 is formed, and the conductor pattern b71 is drawn in an approximately L shape from the edge on the output electrode side of one end, and the tip is formed by the conductor. The conductor pattern b61 of the lower layer a6 is connected.

チップ体1の内部のローパスフィルタは、図2に示すようにπ型の構成であり、入出力間に容量素子C0と誘導素子L0を並列に接続するとともに、入力側および出力側それぞれに容量素子C1,C2を接続し、これら容量素子C1,C2の他端は接地電極へ引き出して接地する構成になっている。
特開平7−336176号公報 特開平11−103229号公報
The low-pass filter inside the chip body 1 has a π-type configuration as shown in FIG. 2, and a capacitive element C0 and an inductive element L0 are connected in parallel between the input and output, and capacitive elements are provided on the input side and the output side, respectively. C1 and C2 are connected, and the other ends of these capacitive elements C1 and C2 are drawn to the ground electrode and grounded.
JP 7-336176 A JP-A-11-103229

近年は、携帯電話機などの電子機器の薄型,軽量,高機能化により、これを構成する電子部品について小型化,高性能化,高周波化の要求が高いレベルで求められている。すなわち、積層チップ部品について小チップ化を進めたいが、その場合でも機能素子としての性能が低下したのでは回路素子には使用できないという問題となり、積層チップ部品は小型であることと、機能素子として高性能であることが強く求められる。   In recent years, as electronic devices such as mobile phones become thinner, lighter, and more functional, there is a high demand for miniaturization, higher performance, and higher frequency with respect to the electronic components that constitute the electronic devices. In other words, we would like to advance the miniaturization of multilayer chip parts, but even in that case, if the performance as a functional element deteriorates, it becomes a problem that it cannot be used as a circuit element. High performance is strongly demanded.

上記した図1,2のローパスフィルタの例で言うと、絶縁膜層が8層の構成において減衰が15dB程度であり、これは20dB程度は減衰を得たい。そこで減衰を大きく得るには、フィルタ回路を多段の構成にする必要があるが、多段の回路にすることは内部に形成する素子の数が増えるので、必然的にチップサイズが大きくなってしまい、相反する問題になっている。   In the example of the low-pass filter shown in FIGS. 1 and 2 described above, the attenuation is about 15 dB in the configuration of eight insulating film layers, and this is about 20 dB. Therefore, in order to obtain a large attenuation, the filter circuit needs to have a multi-stage configuration. However, since the number of elements formed in the multi-stage circuit increases, the chip size inevitably increases. It is a conflicting problem.

この発明は上記した課題を解決するもので、その目的は、小チップ化においても内部に形成する素子数を増すことができるとともに、機能素子としての性能を良好に得ることができる積層チップ部品を提供することにある。   SUMMARY OF THE INVENTION The present invention solves the above-described problems, and an object of the present invention is to provide a multilayer chip component that can increase the number of elements formed therein even in the miniaturization of the chip and can obtain good performance as a functional element. It is to provide.

上記した目的を達成するために、本発明に係る積層チップ部品は、セラミック材料の絶縁膜と導体パターンを適宜な順に積層することによりチップ体を形成し、当該チップ体について少なくとも容量素子をなす膜層および誘導素子をなす膜層を有するものであって、容量素子の電極となる導体パターンの近辺に、導体パターンを引き回す形態に形成し、当該引き回し導体パターンは容量素子の電極となる2つの膜層それぞれに設けて層間で接続して誘導素子の一つとし、当該誘導素子および同一膜層にある前記容量素子とを直列に接続させて直列共振回路とし、直列共振回路をなす対の膜層は2セットを備えて互いに逆向きに重なり誘導素子の部位が重畳しない設定とする構成にする。   In order to achieve the above-described object, a multilayer chip component according to the present invention forms a chip body by laminating an insulating film of a ceramic material and a conductor pattern in an appropriate order, and a film that forms at least a capacitive element for the chip body. And a film layer that forms an inductive element, and is formed in a form in which a conductor pattern is routed in the vicinity of a conductor pattern that serves as an electrode of a capacitive element, and the routed conductor pattern includes two films that serve as electrodes of the capacitive element A pair of film layers forming a series resonant circuit by connecting each of the layers and connecting between the layers to form one of the inductive elements, connecting the inductive element and the capacitive element in the same film layer in series to form a series resonant circuit Is provided with two sets, which are configured to overlap each other in the opposite direction so that the inductive element portions do not overlap.

また、容量素子の電極となる導体パターンは、長手方向について階段状に幅が狭くなる凸形状に形成し、対向する2パターンを逆向きに重畳させる設定とするとよい。また、チップ体の内部にある容量素子および誘導素子は、互いの接続をローパスフィルタとなる接続にするようにしてもよい。   In addition, the conductor pattern serving as the electrode of the capacitor element is preferably formed in a convex shape having a stepwise narrow width in the longitudinal direction, and two opposing patterns are overlapped in the opposite direction. Further, the capacitive element and the inductive element in the chip body may be connected to each other as a low-pass filter.

したがって本発明では、容量素子の電極となる導体パターンの近辺に形成した引き回し導体パターンは、層間で接続するので誘導素子として機能し、当該誘導素子および同一膜層にある容量素子とが直列共振回路となるので、共振点の調整が行える。つまり、これら引き回し導体パターンは、長さを適宜に変更でき、任意に形成が行えることから誘導素子のインダクタンス値を適宜に設定でき、減衰特性における共振点を容易に調整することができる。   Therefore, in the present invention, the routing conductor pattern formed in the vicinity of the conductor pattern serving as the electrode of the capacitive element functions as an inductive element because it is connected between the layers, and the inductive element and the capacitive element in the same film layer are connected in series. Therefore, the resonance point can be adjusted. That is, these lead conductor patterns can be appropriately changed in length and can be arbitrarily formed. Therefore, the inductance value of the inductive element can be appropriately set, and the resonance point in the attenuation characteristic can be easily adjusted.

さらに、直列共振回路をなす対の膜層は2セットを互いに逆向きに重ねて誘導素子の部位が重畳しない設定としている。このため、磁束が鎖交しなくなり、干渉がなくなるので周波数特性を良好に保つことができる。   Further, the pair of film layers forming the series resonance circuit are set so that two sets are stacked in opposite directions so that the portion of the inductive element does not overlap. For this reason, since the magnetic flux is not interlinked and interference is eliminated, the frequency characteristics can be kept good.

この場合、容量素子の電極と同一平面に誘導素子を形成することから、チップ体について積層数を増すことなく内部に形成する素子数を増すことができる。   In this case, since the induction element is formed in the same plane as the electrode of the capacitive element, the number of elements formed inside can be increased without increasing the number of stacked layers of the chip body.

本発明に係る積層チップ部品では、容量素子の電極と同一平面に誘導素子を形成し、両者を直列共振回路とすることから、チップ体について積層数を増すことなく内部に形成する素子数を増すことができ、共振点の調整が行える。これは例えばローパスフィルタの構成とするものでは、減衰特性における共振点の調整が行えることであり、減衰特性の調整が容易に行える。   In the multilayer chip component according to the present invention, the induction element is formed in the same plane as the electrode of the capacitive element, and both are formed as a series resonance circuit. Therefore, the number of elements formed inside the chip body is increased without increasing the number of layers. The resonance point can be adjusted. For example, in the case of a low-pass filter configuration, the resonance point in the attenuation characteristic can be adjusted, and the attenuation characteristic can be easily adjusted.

したがって、小チップ化においても内部に形成する素子数を増すことに有利があり、追加形成した素子は特性改善のための調整用とすることができる。その結果、機能素子としての性能を良好に得ることができる。   Therefore, it is advantageous to increase the number of elements formed inside even in a small chip, and the additionally formed elements can be used for adjustment for improving characteristics. As a result, the performance as a functional element can be favorably obtained.

さらに、直列共振回路をなす対の膜層は2セットを互いに逆向きに重ねて誘導素子の部位が重畳しない設定としているので、磁束が鎖交しなくなり、干渉がなくなるので周波数特性を良好に保つことができる。   Furthermore, since the pair of film layers forming the series resonance circuit are set so that two sets are overlapped in opposite directions so that the part of the inductive element does not overlap, the magnetic flux is not interlinked and the interference is eliminated, so that the frequency characteristics are kept good. be able to.

図3は本発明の好適な一実施の形態を示している。本形態において積層チップ部品は、セラミック材料の絶縁膜aと導体パターンbを適宜な順に積層することによりチップ体1を形成し、当該チップ体1について少なくとも容量素子をなす膜層および誘導素子をなす膜層を有し、それら素子の相互の接続によりローパスフィルタの構成にしている。   FIG. 3 shows a preferred embodiment of the present invention. In this embodiment, the multilayer chip component forms a chip body 1 by laminating an insulating film a made of a ceramic material and a conductor pattern b in an appropriate order, and forms at least a film layer and an inductive element that form a capacitive element for the chip body 1. A film layer is provided, and a low-pass filter is configured by interconnecting these elements.

チップ体1は図4に示すように、略矩形状の小片に形成するが、そのチップ体1の対向2面に、入力電極2および出力電極3をそれぞれ設けるとともに、側面には接地電極4,5を設ける構成を採る。チップ体1の内部のローパスフィルタは、図5に示すように、基本的にはπ型の構成であり、入出力間に容量素子C0と誘導素子L0を並列に接続するとともに、入力側には誘導素子L1および容量素子C1を直列に接続し、容量素子C1の他端は接地電極4へ引き出して接地し、そして出力側には誘導素子L2および容量素子C2を直列に接続し、容量素子C2の他端は接地電極5へ引き出して接地する構成になっている。   As shown in FIG. 4, the chip body 1 is formed in a substantially rectangular small piece. The input electrode 2 and the output electrode 3 are provided on the two opposing surfaces of the chip body 1, and the ground electrode 4 is provided on the side surface. The structure which provides 5 is taken. As shown in FIG. 5, the low-pass filter inside the chip body 1 basically has a π-type configuration, and a capacitive element C0 and an inductive element L0 are connected in parallel between the input and output. The inductive element L1 and the capacitive element C1 are connected in series, the other end of the capacitive element C1 is drawn to the ground electrode 4 and grounded, and the inductive element L2 and the capacitive element C2 are connected in series on the output side, and the capacitive element C2 The other end of each is pulled out to the ground electrode 5 and grounded.

チップ体1の形成は印刷積層法では、セラミック材料からなる絶縁ペーストと、導体材料からなる導体ペーストとを交互にスクリーン印刷していくもので、それらペーストは1回刷り出す(塗る)と厚みが例えば3〜5μmになり、これを塗っては乾燥させて積み重ねていく。チップ部品の製造では、ワークとしては生産性の面から複数個分の大きさのワーク積層体を製作し、そのワーク積層体を十分に乾燥させた後に各単体に切断して焼成する。   The chip body 1 is formed by printing the insulating paste made of a ceramic material and the conductor paste made of a conductor material alternately by a screen printing method, and the paste has a thickness when printed (applied) once. For example, it becomes 3 to 5 μm, and this is applied, dried and stacked. In the manufacture of chip parts, a workpiece laminate having a plurality of sizes is manufactured as a workpiece from the viewpoint of productivity, and the workpiece laminate is sufficiently dried and then cut into individual pieces and fired.

セラミック材料には、例えばガラスを添加して低温焼結化した誘電体セラミックスを使用する。例えば、ホウケイ酸ガラスをアルミナに体積で70:30の比率に混合した誘電体材料を使用し、これにビヒクルとしてエチルセルロースとテレピネールと分散剤,可塑剤を混合したものを配合して混練し、印刷用の絶縁ぺーストとすることができる。セラミック材料としては、他にも例えばフェライト等の磁性セラミックスを使用してもよい。   As the ceramic material, for example, dielectric ceramics added with glass and sintered at a low temperature is used. For example, a dielectric material in which a borosilicate glass is mixed with alumina in a volume ratio of 70:30 is used, and a mixture of a mixture of ethyl cellulose, terpineol, a dispersant, and a plasticizer is mixed and kneaded as a vehicle. It can be used as an insulation paste. In addition, for example, magnetic ceramics such as ferrite may be used as the ceramic material.

導体ペーストには銀ペーストを使用し、上記したビヒクルに混合する。また、導体ペーストは銀パラジウムでもよい。   A silver paste is used as the conductor paste and is mixed with the vehicle described above. The conductor paste may be silver palladium.

具体的には、絶縁膜aは図3に示すa1からa10までの10層とし、上下の最外層a1,a10には導体パターンを形成しないが、第2の絶縁膜層a2から第9の絶縁膜層a9についてそれぞれ導体パターンbを形成している。   Specifically, the insulating film a has 10 layers from a1 to a10 shown in FIG. 3, and no conductive pattern is formed on the upper and lower outermost layers a1 and a10, but the second insulating film layer a2 to the ninth insulating film. A conductor pattern b is formed for each film layer a9.

絶縁膜層a2上には、容量素子C2の電極となる導体パターンb21を入力電極2側に略方形に形成するとともに、引き回し導体パターンb22を形成し、引き回し導体パターンb22は導体パターンb21の角部から略J字状に引き回して先端が導体により上層a3の導体パターンb32と接続させている。つまり、絶縁膜層a3上には、誘導素子L2のコイル部となる引き回し導体パターンb32を形成し、引き回し導体パターンb32は出力電極3側の縁部から螺旋状に引き回して先端が導体により下層a2の導体パターンb22と接続させている。そして、絶縁膜層a3上には、容量素子C2の電極となる導体パターンb31を入力電極2側に略方形に形成し、導体パターンb31は両側に張り出し部を有し、それぞれ接地電極4,5側の縁部に達している。これにより、絶縁膜層a2と絶縁膜層a3との積層部位は、誘導素子L2と容量素子C2とが直列に接続し、直列共振回路を構成している。   On the insulating film layer a2, a conductor pattern b21 to be an electrode of the capacitive element C2 is formed in a substantially square shape on the input electrode 2 side, and a lead conductor pattern b22 is formed. The lead conductor pattern b22 is a corner portion of the conductor pattern b21. The leading end is connected to the conductor pattern b32 of the upper layer a3 by a conductor. That is, on the insulating film layer a3, the lead conductor pattern b32 that becomes the coil portion of the induction element L2 is formed, and the lead conductor pattern b32 is spirally drawn from the edge on the output electrode 3 side, and the tip is lower layer a2 by the conductor. The conductor pattern b22 is connected. On the insulating film layer a3, a conductor pattern b31 to be an electrode of the capacitive element C2 is formed in a substantially square shape on the input electrode 2 side, and the conductor pattern b31 has projecting portions on both sides, and the ground electrodes 4 and 5 respectively. Reached the side edge. Thereby, in the laminated portion of the insulating film layer a2 and the insulating film layer a3, the inductive element L2 and the capacitive element C2 are connected in series to form a series resonance circuit.

絶縁膜層a4上には絶縁膜層a3と同一の導体パターンb41,b42を逆向きに形成し、絶縁膜層a5上には絶縁膜層a2と同一の導体パターンb51,b52をやはり逆向きに形成していて、絶縁膜層a4,a5の積層部位は、誘導素子L1と容量素子C1とが直列に接続し、直列共振回路を構成している。   The same conductive patterns b41 and b42 as the insulating film layer a3 are formed in the reverse direction on the insulating film layer a4, and the same conductive patterns b51 and b52 as the insulating film layer a2 are also set in the reverse direction on the insulating film layer a5. In the laminated portion of the insulating film layers a4 and a5, the inductive element L1 and the capacitive element C1 are connected in series to form a series resonance circuit.

つまり、絶縁膜層a4上には、誘導素子L1のコイル部となる引き回し導体パターンb42を形成し、引き回し導体パターンb42は入力電極2側の縁部から螺旋状に引き回して先端が導体により上層a5の導体パターンb52と接続させている。そして、絶縁膜層a4上には、容量素子C1の電極となる導体パターンb41を出力電極3側に略方形に形成し、導体パターンb41は両側に張り出し部を有し、それぞれ接地電極4,5側の縁部に達している。一方、絶縁膜層a5上には、容量素子C1の電極となる導体パターンb51を出力電極3側に略方形に形成するとともに、引き回し導体パターンb52を形成し、引き回し導体パターンb52は導体パターンb51の角部から略J字状に引き回して先端が導体により下層a4の導体パターンb42と接続させている。   That is, on the insulating film layer a4, the routing conductor pattern b42 that becomes the coil portion of the inductive element L1 is formed. The routing conductor pattern b42 is spirally drawn from the edge on the input electrode 2 side, and the tip is formed by the conductor to the upper layer a5. The conductor pattern b52 is connected. On the insulating film layer a4, a conductor pattern b41 to be an electrode of the capacitive element C1 is formed in a substantially square shape on the output electrode 3 side. The conductor pattern b41 has projecting portions on both sides, and the ground electrodes 4 and 5 respectively. Reached the side edge. On the other hand, on the insulating film layer a5, a conductor pattern b51 serving as an electrode of the capacitive element C1 is formed in a substantially square shape on the output electrode 3 side, and a lead conductor pattern b52 is formed. The lead conductor pattern b52 is formed of the conductor pattern b51. The end is connected to the conductor pattern b42 of the lower layer a4 by a conductor with a leading end drawn in a substantially J shape from the corner.

絶縁膜層a6上には、誘導素子L0のコイル部となる導体パターンb61を形成し、導体パターンb61は入力電極2側の縁部から略J字状に引き回して先端が導体により上層a7の導体パターンb71と接続させている。つまり、絶縁膜層a7上には、誘導素子L0のコイル部となる導体パターンb71を形成し、導体パターンb71は出力電極3側の縁部から略L字状に引き回して先端が導体により下層a6の導体パターンb61と接続させている。   On the insulating film layer a6, a conductor pattern b61 serving as a coil portion of the induction element L0 is formed. The conductor pattern b61 is drawn in a substantially J shape from the edge on the input electrode 2 side, and the tip is a conductor of the upper layer a7 by a conductor. It is connected to the pattern b71. That is, on the insulating film layer a7, the conductor pattern b71 that becomes the coil portion of the induction element L0 is formed, and the conductor pattern b71 is drawn in an approximately L shape from the edge on the output electrode 3 side, and the leading end thereof is the lower layer a6 by the conductor. The conductor pattern b61 is connected.

絶縁膜層a8上には、容量素子C0の電極となる導体パターンb81を中央部に形成している。この導体パターンb81は長手方向について階段状に幅が狭くなる凸形状に形成し、細幅の頂部が出力電極3側の縁部に達している。   On the insulating film layer a8, a conductor pattern b81 serving as an electrode of the capacitive element C0 is formed at the center. The conductor pattern b81 is formed in a convex shape whose width is narrowed stepwise in the longitudinal direction, and the narrow top reaches the edge on the output electrode 3 side.

絶縁膜層a9上には、容量素子C0の電極となる導体パターンb91を中央部に形成し、これは下層a8の導体パターンb81とは逆向きに重畳させる設定になっている。つまり導体パターンb91は、長手方向について階段状に幅が狭くなる凸形状に形成するが、細幅の頂部が入力電極2側の縁部に達している。   On the insulating film layer a9, a conductor pattern b91 serving as an electrode of the capacitive element C0 is formed in the center, and this is set to overlap with the conductor pattern b81 of the lower layer a8 in the opposite direction. That is, the conductor pattern b91 is formed in a convex shape whose width is narrowed stepwise in the longitudinal direction, but the narrow top reaches the edge on the input electrode 2 side.

絶縁膜層a2上の引き回し導体パターンb22および絶縁膜層a3上の引き回し導体パターンb32は、図6(a),(c)に示すように、容量素子C2の電極となる導体パターンb21,b31の近辺にそれぞれ形成し、層間で接続するので誘導素子L2として機能する。そして、引き回し導体パターンb22が導体パターンb21と連なって誘導素子L2が容量素子C2と直列となり、直列共振回路をなし、共振点の調整が行える。つまり、これら引き回し導体パターンb22,b32は、長さを適宜に変更でき、任意に形成が行える。したがって、誘導素子L2のインダクタンス値を適宜に設定でき、減衰特性における共振点を容易に調整することができる。   As shown in FIGS. 6A and 6C, the lead conductor pattern b22 on the insulating film layer a2 and the lead conductor pattern b32 on the insulating film layer a3 are formed of the conductor patterns b21 and b31 serving as the electrodes of the capacitive element C2. Since it is formed in the vicinity and connected between the layers, it functions as the induction element L2. Then, the lead conductor pattern b22 is connected to the conductor pattern b21, the inductive element L2 is in series with the capacitive element C2, and a series resonance circuit is formed, so that the resonance point can be adjusted. That is, the lengths of the lead conductor patterns b22 and b32 can be appropriately changed and can be arbitrarily formed. Therefore, the inductance value of the induction element L2 can be set as appropriate, and the resonance point in the attenuation characteristic can be easily adjusted.

絶縁膜層a4上の引き回し導体パターンb42および絶縁膜層a5上の引き回し導体パターンb52についても同様であり、これらは誘導素子L1として機能し、容量素子C1との直列共振回路をなし、これにより、減衰特性における共振点の調整が行える。   The same applies to the lead conductor pattern b42 on the insulating film layer a4 and the lead conductor pattern b52 on the insulating film layer a5. These function as the inductive element L1 and form a series resonance circuit with the capacitive element C1, thereby The resonance point in the damping characteristic can be adjusted.

さらに、直列共振回路をなす対の膜層a2,a3および膜層a4,a5との2セットは、互いに逆向きに重なり、誘導素子L2,L1の部位が重畳しない設定としているので磁束が鎖交しなくなり、干渉がなくなるので周波数特性を良好に保つことができる。   Further, the two sets of the film layers a2 and a3 and the film layers a4 and a5 forming the series resonance circuit overlap in opposite directions, and the portions of the inductive elements L2 and L1 are set not to overlap, so that the magnetic flux is linked. Since no interference occurs, the frequency characteristics can be kept good.

容量素子C0の電極は、長手方向について階段状に幅が狭くなる凸形状に形成し、これら導体パターンb81(図7(a))および導体パターンb91(図7(b))とは、対向する互いを逆向きに重畳させる設定になっているので(図7(c))、重なり面積を見ると、両者に位置ズレがあったとしてもその影響が現れにくい相互関係になる。つまり、導体パターンb81と導体パターンb91とは、対向して重なり合う中央部位が電極として有効な領域となり、この有効領域の両側にある階段部位がズレ量に対するマージンとなるため、対向する位置関係にズレがあっても、ズレ量が階段部位の幅までは中央の有効領域分の面積が保たれる。したがって、導体パターンの形成や積層において位置ズレがあっても容量素子C0の電極の相互間には影響が少なくなり、容量値を適正に確保することができる。その結果、減衰特性について共振点のばらつきを防ぐことができ、周波数特性を安定に得ることができる。   The electrode of the capacitive element C0 is formed in a convex shape having a stepwise narrow width in the longitudinal direction, and is opposed to the conductor pattern b81 (FIG. 7A) and the conductor pattern b91 (FIG. 7B). Since they are set to overlap each other in the opposite direction (FIG. 7 (c)), when the overlapping area is viewed, even if there is a positional deviation between them, the influence is unlikely to appear. In other words, the conductive pattern b81 and the conductive pattern b91 have a central portion that is opposed and overlapped as an effective region as an electrode, and the staircase portions on both sides of the effective region are margins for the amount of displacement, so that the positional relationship between the conductive pattern b81 and the conductive pattern b91 is shifted. Even if there is a gap, the area corresponding to the effective area in the center is maintained until the deviation amount reaches the width of the staircase portion. Accordingly, even if there is a positional deviation in the formation or lamination of the conductor pattern, the influence between the electrodes of the capacitive element C0 is reduced, and the capacitance value can be ensured appropriately. As a result, the resonance characteristics can be prevented from varying in the attenuation characteristics, and the frequency characteristics can be obtained stably.

本発明に係るローパスフィルタの構成、つまり図5に示す等価回路について数値解析を行ったところ、図8に示すような減衰特性を得た。図8には、図2に示した従来例の等価回路における減衰特性も併せてプロットしてある。同図から明らかなように、従来例のローパスフィルタの構成では減衰を15dB程度しか得られなかったが、本発明に係るローパスフィルタの構成では28dB程度を得ることができ、周波数特性を良好に得られることを確認した。   When the numerical analysis was performed on the configuration of the low-pass filter according to the present invention, that is, the equivalent circuit shown in FIG. 5, attenuation characteristics as shown in FIG. 8 were obtained. FIG. 8 also plots attenuation characteristics in the equivalent circuit of the conventional example shown in FIG. As can be seen from the figure, the low pass filter configuration of the conventional example can obtain only about 15 dB of attenuation, but the low pass filter configuration of the present invention can obtain about 28 dB, and the frequency characteristics can be obtained satisfactorily. It was confirmed that

このように、対の膜層a2,a3および膜層a4,a5との2セットは、容量素子Cの電極と同一平面に誘導素子Lを形成し、両者を直列共振回路とすることから、チップ体1について積層数を増すことなく内部に形成する素子数を増すことができ、共振点の調整が行える。これはローパスフィルタの構成では、減衰特性における共振点の調整が行えることであり、減衰特性の調整が容易に行える。   Thus, the two sets of the pair of film layers a2 and a3 and the film layers a4 and a5 form the inductive element L on the same plane as the electrode of the capacitive element C, and both form a series resonance circuit, so that the chip The number of elements formed inside the body 1 can be increased without increasing the number of stacked layers, and the resonance point can be adjusted. This is because the resonance point in the attenuation characteristic can be adjusted in the configuration of the low-pass filter, and the attenuation characteristic can be easily adjusted.

したがって、小チップ化においても内部に形成する素子数を増すことに有利があり、追加形成した素子は特性改善のための調整用とすることができ、その結果、機能素子としての性能を良好に得ることができる。   Therefore, it is advantageous to increase the number of elements formed inside even in a small chip, and the additionally formed element can be used for adjustment for improving characteristics, and as a result, the performance as a functional element is improved. Obtainable.

積層チップ部品の従来の一例であり、各層を分離して示す斜視図である。FIG. 6 is a perspective view illustrating a conventional multilayer chip component, with each layer separated. 図1に示す積層チップ部品の電気的な構成を説明する等価回路図である。FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the multilayer chip component shown in FIG. 1. 本発明に係る積層チップ部品の一実施の形態であり、各層を分離して示す斜視図である。FIG. 2 is a perspective view showing an embodiment of the multilayer chip component according to the present invention, with each layer separated. 図3に示す積層チップ部品の外観を説明する斜視図である。It is a perspective view explaining the external appearance of the multilayer chip component shown in FIG. 図3に示す積層チップ部品の電気的な構成を説明する等価回路図である。FIG. 4 is an equivalent circuit diagram illustrating an electrical configuration of the multilayer chip component shown in FIG. 3. 導体パターンを説明する平面図であり、(a)は第2層、(b)は第3層をそれぞれ示している。It is a top view explaining a conductor pattern, (a) has shown the 2nd layer and (b) has shown the 3rd layer, respectively. 導体パターンを説明する平面図であり、(a)は第9層、(b)は第8層をそれぞれ示し、(c)は第8層上へ第9層を積層した状態を示している。It is a top view explaining a conductor pattern, (a) shows a 9th layer, (b) shows an 8th layer, respectively, (c) has shown the state which laminated | stacked the 9th layer on the 8th layer. ローパスフィルタをなす積層チップ部品の減衰特性を示すグラフ図である。It is a graph which shows the attenuation | damping characteristic of the multilayer chip component which makes a low-pass filter.

符号の説明Explanation of symbols

1 チップ体
2 入力電極
3 出力電極
4,5 接地電極
a 絶縁膜
a1 第1の絶縁膜層
a2 第2の絶縁膜層
a3 第3の絶縁膜層
a4 第4の絶縁膜層
a5 第5の絶縁膜層
a6 第6の絶縁膜層
a7 第7の絶縁膜層
a8 第8の絶縁膜層
a9 第9の絶縁膜層
a10 第10の絶縁膜層
b 導体パターン
b21,b22,b31,b32,b41,b42,b51,b52,b61,b71,b81,b91 導体パターン
C0,C1,C2 容量素子
L0,L1,L2 誘導素子
DESCRIPTION OF SYMBOLS 1 Chip body 2 Input electrode 3 Output electrode 4, 5 Ground electrode a Insulating film a1 1st insulating film layer a2 2nd insulating film layer a3 3rd insulating film layer a4 4th insulating film layer a5 5th insulation Film layer a6 6th insulating film layer a7 7th insulating film layer a8 8th insulating film layer a9 9th insulating film layer a10 10th insulating film layer b Conductor patterns b21, b22, b31, b32, b41, b42, b51, b52, b61, b71, b81, b91 Conductor patterns C0, C1, C2 Capacitance elements L0, L1, L2 Inductive elements

Claims (3)

セラミック材料の絶縁膜と導体パターンを適宜な順に積層することによりチップ体を形成し、当該チップ体について少なくとも容量素子をなす膜層および誘導素子をなす膜層を有する積層チップ部品であって、
前記容量素子の電極となる前記導体パターンの近辺に、導体パターンを引き回す形態に形成し、当該引き回し導体パターンは前記容量素子の電極となる2つの膜層それぞれに設けて層間で接続して前記誘導素子の一つとし、当該誘導素子および同一膜層にある前記容量素子とを直列に接続させて直列共振回路とし、前記直列共振回路をなす対の膜層は2セットを備えて互いに逆向きに重なり前記誘導素子の部位が重畳しない設定とすることを特徴とする積層チップ部品。
A chip body is formed by laminating an insulating film of a ceramic material and a conductor pattern in an appropriate order, and a laminated chip component having at least a film layer forming a capacitive element and a film layer forming an inductive element for the chip body,
A conductor pattern is formed in the vicinity of the conductor pattern serving as the electrode of the capacitor element, and the lead conductor pattern is provided on each of the two film layers serving as the electrode of the capacitor element and connected between the layers. As one of the elements, the inductive element and the capacitive element in the same film layer are connected in series to form a series resonance circuit, and the pair of film layers forming the series resonance circuit are provided in two sets and are opposite to each other. Overlap The laminated chip component, wherein the inductive element portion is set not to overlap.
前記容量素子の電極となる前記導体パターンは、長手方向について階段状に幅が狭くなる凸形状に形成し、対向する2パターンを逆向きに重畳させる設定とすることを特徴とする請求項1に記載の積層チップ部品。   The conductive pattern serving as an electrode of the capacitive element is formed in a convex shape having a stepwise narrow width in the longitudinal direction, and two opposing patterns are set to overlap in opposite directions. The laminated chip component as described. 前記チップ体の内部にある前記容量素子および前記誘導素子は、互いの接続をローパスフィルタとなる接続にすることを特徴とする請求項1あるいは2の何れかに記載の積層チップ部品。

3. The multilayer chip component according to claim 1, wherein the capacitor element and the inductive element in the chip body are connected to each other as a low-pass filter.

JP2006229499A 2006-08-25 2006-08-25 Laminated chip component Pending JP2008053543A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112908611A (en) * 2016-01-20 2021-06-04 株式会社村田制作所 Coil component

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335866A (en) * 1991-08-16 1993-12-17 Tdk Corp High frequency filter
JPH0897662A (en) * 1994-09-26 1996-04-12 Mitsubishi Materials Corp Lc composite component
JP2003142973A (en) * 2001-11-02 2003-05-16 Ngk Spark Plug Co Ltd Filter
JP2003152489A (en) * 2001-11-05 2003-05-23 Samsung Electro Mech Co Ltd Array type noise reducing filter
JP2006190774A (en) * 2005-01-05 2006-07-20 Murata Mfg Co Ltd Laminated ceramic electronic component

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335866A (en) * 1991-08-16 1993-12-17 Tdk Corp High frequency filter
JPH0897662A (en) * 1994-09-26 1996-04-12 Mitsubishi Materials Corp Lc composite component
JP2003142973A (en) * 2001-11-02 2003-05-16 Ngk Spark Plug Co Ltd Filter
JP2003152489A (en) * 2001-11-05 2003-05-23 Samsung Electro Mech Co Ltd Array type noise reducing filter
JP2006190774A (en) * 2005-01-05 2006-07-20 Murata Mfg Co Ltd Laminated ceramic electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112908611A (en) * 2016-01-20 2021-06-04 株式会社村田制作所 Coil component
CN112908611B (en) * 2016-01-20 2023-05-09 株式会社村田制作所 Coil component

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