JP2008047029A - Redundancy method and computer program for storage system and cache - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system of configuration making efficient use of a cache in a controller with a cache memory for storing part of data in a storage device. <P>SOLUTION: Controllers 0, 1 which are connected to a host computer, are accessed by correspondent magnetic disk devices, and are connected to each other in communication includes: cache memories (209a, 209b); cache configuration information (208a, 208b) for managing configuration information of the cache memories; device configuration information (211a, 211b) for storing correspondence between a region of the cache memory and a master controller; and processors (210a, 210b). Since the controllers manage exclusion and region ensuring of the cache memories individually and can arrange write cache data, redundant data of the write cache data, and read cache data in arbitrary regions on the same cache memory, the cache memories can be used effectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a storage system, and is particularly suitable when applied to cache control in which each controller has a cache memory and prevents the loss of data in order to retain the same data in each controller. The present invention relates to a system, a cache redundancy method, and a computer program.

  Storage systems represented by disk array devices are equipped with a cache memory to buffer the slow access speed of storage devices such as physical disk devices and improve performance such as the number of inputs / outputs per unit time and throughput. ing.

  In general, since the area with high access frequency is limited in the entire capacity of the disk array device, data in the area with high access frequency is temporarily stored in the cache memory, so that it can be transferred to a host computer such as a host computer. Can be speeded up.

  In the case of a read request from the host computer, a search is performed to determine whether or not the read request data in the cache memory exists in the cache memory (cache hit) (cache miss), and if the read request data is in the cache memory Return that data to the host computer. On the other hand, if there is no read request data, the data corresponding to the read request is read from the magnetic disk device, written to the cache memory, and the read data is returned to the host computer.

  On the other hand, if the request from the host computer is a write request, when the write data received from the host is written to the cache memory, the completion of the write processing is returned to the host computer, and the magnetic disk device requiring processing time is returned. Are processed collectively at a later time, whereby control for improving the response performance to the write request is performed.

  In this case, if the data in the cache memory is destroyed due to a failure of the cache memory or the like, the corresponding data cannot be written to the magnetic disk.

  Similarly, since a response indicating that the end of the write process has already been completed is reported to the host computer, the write process is not retried. As a result, the corresponding data is lost.

  Therefore, in the storage, in order to prevent the loss of write data due to the destruction of the cache memory, the cache memory is made redundant. When the storage receives a write process from the host computer, the storage writes to the plurality of cache memories. Even if one cache memory fails, write data is written from the other cache memory and no data is lost.

  In addition, as publications related to storage for redundancy, the descriptions in Patent Document 1, Patent Document 2, Patent Document 3, and the like described below are referred to.

JP 2003-167782 A JP-A-9-146842 Special table 2004-538532 gazette

  Recently, as the capacity of magnetic disk units has increased, the number of accesses to storage has increased, and the efficiency of caches to fill the performance gap of magnetic disk units has been improved, especially for read requests that account for the majority of accesses to storage units. Effective use is becoming necessary.

  Also, as a request for storage, when multiple controllers write to the same area overlap, when any one of the write data is written on each cache memory and the area on each cache memory is read, The same data is required. This is called "guarantee of data consistency". Reference is made to the descriptions in Patent Document 1, Patent Document 2, and Patent Document 3 as storage cache control methods for ensuring redundancy and data consistency.

  However, the storage disclosed in Patent Document 1 performs data redundancy at the same address of the cache memory that has been made redundant, regardless of read / write data, and therefore requires redundancy. Even read data without data consumes each cache memory and is wasted.

  Further, in the system described in Patent Document 2, a cache area is held in a redundant controller for each processor of each controller, and the cache area by the processor of the redundant controller is usually compared with the cache area. Prohibiting access eliminates the need for exclusive processing to ensure consistency. However, each controller must hold the redundant data area of the other controller. For this reason, even if the redundant data area is empty, it cannot be used and the cache memory cannot be used effectively.

  Further, in the system described in Patent Document 3, redundancy and consistency processing are performed, but each controller is required to have a read cache, a write cache, and a mirror cache. In other words, each controller needs to prepare a cache memory for a different purpose, and a dedicated cache memory must be prepared. Therefore, the cache memory cannot be effectively used.

  Therefore, a main object of the present invention is to provide a system, a method, and a program that enable effective use of a cache memory in a controller having a cache memory for storing a part of data of a storage apparatus.

  Another object of the present invention is to provide a system, method, and program for realizing multiple redundancy when write data is made redundant.

  Still another object of the present invention is to provide a system, method, and program for improving the transfer efficiency of control information transferred to make write data redundant.

  The invention disclosed in the present application has the following configuration.

  The system according to the first aspect (side surface) of the present invention includes a plurality of controllers, each of which is connected to a corresponding higher-level device, and is connected to each other for communication and accessible to the corresponding storage device. In the storage system, each of the plurality of controllers includes a cache memory for storing a part of the data of the storage device, and a cache processing unit that performs access control of the cache memory. Each of the controllers further stores and holds device configuration information that defines the correspondence between the logical address area from the host device and the master controller assigned to the area, and the device configuration information includes: The plurality of controllers have the same contents. In the present invention, in the controller that has received the access request from the host device, the cache processing means refers to the device configuration information in the controller and relates to an area for storing data corresponding to the address of the access request The master controller is determined, and the cache processing means of the master controller performs exclusive processing of the data storage destination area of the cache memory of the master controller, and stores the data in a redundant manner. When there is a redundant controller having a cache memory to be cached, exclusive processing of the cache memory in the master controller is performed prior to exclusive processing of the cache memory in the redundant controller. In the exclusion process of the area, it is confirmed whether or not the area is exclusive. If the area is already exclusive, the exclusion is performed after the exclusion of the area is released, and the area is excluded. If not, the area is exclusive.

  In the present invention, in the controller that has received a write request from the host device, the cache processing means refers to the device configuration information in the controller and determines a controller to be a master with respect to an area for storing write data. The cache processing means of the master controller checks whether the write data storage area of the cache memory of the master controller is already exclusive, and the area is exclusive In this case, after waiting until the exclusion of the area is released, the exclusion is performed, and when the area is not excluded, the area is excluded, and the write data is to be stored redundantly. When there is a redundant controller with memory, the redundant controller Ahead exclusive processing Yasshumemori, exclusive process of the cache memory of the controller of the master is performed.

  In the present invention, the cache processing means of the controller that has received a write request from the host device, if the controller that is the master for the cache memory area corresponding to the write request is not its own controller, When the controller is instructed to perform a cache search and receives the completion of the cache search from the master controller, the cache processing means of the controller that has received a write request from the host device, and other redundant destinations If there is a controller, a cache search is performed by the cache processing means of the other controller at the redundant destination, and write data is written in the cache memory area of each controller.

  In the present invention, each of the plurality of controllers includes cache configuration information for managing configuration information of the cache memory area, and the plurality of controllers refer to the same content with respect to the cache configuration information. It is good.

In the present invention, the cache processing means of the controller that has received the write request from the host device refers to the device configuration information based on the logical address of the write request, and stores the write request data. Determine a master controller for performing exclusion of the corresponding area on the cache memory, request the cache processing means of the determined master controller to perform the exclusion processing of the area,
The cache processing means of the master controller checks whether the designated area is already in its own cache memory and is exclusive with other access requests,
If the area is exclusive by another access request, wait until the exclusive processing of the area ends,
If the area is not excluded by another access request, the area is excluded,
On the other hand, if the specified area is not on the cache memory and should be newly secured, after securing a new area on the cache memory, the newly secured area is exclusive,
A configuration may be adopted in which the controller that has received the write request from the higher-level device is notified that the exclusion process in the master controller has been completed.

In the present invention, the cache processing means of the controller that has received the write request determines at least one redundant destination controller having a cache memory to be made redundant with respect to the write request, and the cache of the redundant destination controller is determined. Request processing means exclusive processing of the area for redundancy by write request,
The cache processing means of the redundant destination controller performs exclusion after waiting until the exclusion is released when the area for performing redundancy is excluded by another,
If it is not excluded by others, exclusive of the area for performing the redundancy,
If the area for performing the redundancy is new, the area for performing the redundancy is newly secured and exclusive,
The cache processing means of the redundant destination controller notifies the controller cache processing means that has received the write request from the higher-level device that the exclusive processing has been completed,
The cache processing means of the controller that has received the write request from the host device,
Wait for the exclusion completion response from the controller that issued the request for exclusive processing of the area for redundancy, and after completing the exclusive processing of the corresponding area of the cache memory in each controller, the master controller and the redundant controller The write data received from the host device may be written into the corresponding area of the cache memory to realize redundancy for a plurality of controllers with respect to the write data.

  In the present invention, when the plurality of controllers receive a write request to the same area, first, the master controller performs exclusion of the cache memory area so that another write request for the same area is It is also possible to wait by the controller cache processing means, and to perform control so as not to write to the same area for the other redundant controllers.

In the present invention, the cache processing means of the controller that has received the read request from the host device, for the area that stores the data of the read request, the own controller is the master of the area or the redundant destination controller. Make a decision on whether or not
In the case of a master or redundant destination controller, check whether there is a storage area for the read request data in the cache memory,
If there is an area storing the data in the cache memory, check whether the area is exclusive;
If the area is exclusive by another request, do the exclusion after waiting until the area is released,
If the area is not excluded by another request, the area data in the cache memory may be transmitted to the host device after the area is excluded.

In the present invention, when the area of the read request data does not exist in the cache memory, a new area is secured on the cache memory, and after the newly secured area is excluded, the storage area Data may be read from the device, stored in the newly secured area, and then transmitted to the host device.
The cache processing means of the controller that has received the read request from the host device, if its own controller is not the master or redundant destination controller for the area storing the read request data, the master or redundant destination for the area. Requesting exclusive processing of the area to any one of the controllers
The cache processing means of the controller that has received the exclusive processing request includes:
Check whether there is an area for storing read request data on the cache memory of the controller,
If there is an area for storing the read request data on the cache memory, check whether the area is exclusive;
If the area is exclusive by another request, do the exclusion after waiting until the area is released,
If the area is not excluded by another request, the area is excluded, the completion of the exclusion of the area is notified to the controller that received the read request from the host device,
The cache processing means of the controller may read data in an area on the cache memory of the controller for which exclusion is performed, and transmit the data to the host device.

In the present invention, in the controller that has received the exclusion request, if the data of the read request does not exist in the cache memory, a new area is secured on the cache memory and the newly secured area is excluded. After the data is read from the storage device and stored in the newly secured area, the completion of exclusion of the newly secured area is notified to the controller that received the read request from the host device,
The cache processing means of the controller may read data in an area on the cache memory of the controller for which exclusion is performed, and transmit the data to the host device.

In the present invention, the cache processing means of the controller that has received the write request from the host device refers to the device configuration information in the controller, and masters the cache memory area corresponding to the write data of the write request. If the controller that has received the write request from the host device is the master controller, the cache search and the cache memory are exclusive for the area where the write data is stored,
If the controller that received the access request from the host device is not the master, send a cache search instruction to the master controller,
The master controller performs a cache search and an exclusive area for storing write data in the cache memory,
Subsequently, when there is a redundant destination controller, the cache processing means of the redundant destination controller performs an exclusion of an area for storing write data in the cache search and the cache memory,
Subsequently, write data is written from the host device to each cache memory of the master and the redundant controller,
Thereafter, the cache processing means of the master controller and redundant controller may release the exclusion of the area of the cache memory.

  In the present invention, the cache processing means of the controller locks cache configuration information for managing configuration information of the cache memory area immediately before the cache search, and after exclusion of the cache memory area, The cache configuration information is unlocked. In the present invention, the cache processing means of the controller locks the cache configuration information for managing the configuration information of the cache memory area before releasing the exclusion of the cache memory area, After releasing the exclusion of the area, the cache configuration information is unlocked.

In the method according to another aspect of the present invention, each of a plurality of cache memories each including a cache memory that is connected to a corresponding host device and is connected to each other for communication and holds a part of data of the corresponding storage device A method for controlling cache memory of a storage system including a controller, comprising:
Each of the plurality of controllers stores and holds device configuration information that defines a correspondence relationship between a logical address area from the host device and a master controller assigned to the area, and the device configuration information is The controller having the same contents in the plurality of controllers and receiving the access request from the host device refers to the device configuration information in the controller and stores data corresponding to the address of the access request Determine the master controller for the area,
The master controller performs an exclusion process on the data storage destination area of the cache memory of the master controller (in this case, confirms whether or not the area is exclusive, and the area is already exclusive). Cache memory that waits for the exclusion of the exclusion of the area, and performs exclusion when the area is not exclusive), and stores the data in a redundant manner The above-described steps are included, in which, when there is a redundant destination controller having the above, the cache memory exclusive processing in the master controller is performed prior to the cache memory exclusive processing in the redundant destination controller.

In a program according to another aspect of the present invention,
Each of them includes a plurality of controllers that are connected to a corresponding host device and that are connected to each other for communication and hold a part of the data in the corresponding storage device and a processor.
Each of the plurality of controllers stores and holds device configuration information that defines a correspondence relationship between a logical address area from the host device and a master controller assigned to the area, and the device configuration information is The plurality of controllers have the same content,
In the processor of the controller,
When receiving a write request from the host device, referring to the device configuration information in the controller, a process for determining a master controller for the data of the address of the write request;
If the controller is not the master, processing to instruct the master controller to perform cache memory exclusion;
After the exclusion process of the cache memory area in the master controller, the process of exclusiveizing the cache memory area in the controller;
The program comprises a program for writing the write request data from the device to a cache memory area in the controller and transferring the write request data to the master controller.

  According to the present invention, each of the plurality of controllers includes a cache processing unit, and each cache processing unit individually manages the exclusion and area reservation of the cache memory, so that any area on the same cache memory can be managed. , Write data, write redundancy data, and read data can be arranged, and the cache memory can be used effectively.

  According to the present invention, in common with the system, the master controller and the redundant controller are defined, and when the write data is made redundant, first, the master controller area is exclusively processed, By ensuring data consistency and then writing the data to the redundant controller, triple or more redundancy can be achieved.

  According to the present invention, the cache search and the cache area are excluded by the master, the cache search and the cache area are excluded by the redundant controller or the like, and the write data is written to the cache area. The information transferred between redundant controllers is made more efficient.

The above-described present invention will be described in further detail. A storage system according to one aspect of the present invention is a storage system that includes a plurality of controllers that are connected to a host device, each of which includes a storage device and is connected to each other for communication, and each of the plurality of controllers Includes cache processing means including a cache memory, a processor (210a and 210b in FIG. 2), and the like.
A process for determining a controller (referred to as “master controller”) that performs exclusive processing of a partial area (for example, a page) of a cache memory,
・ Exclusion processing of a partial area of the cache memory provided in each controller, and what data requested by the host computer is searched, and if the requested data does not exist, it is newly Processing to secure the area,
-If the area is already excluded, a process of performing control to wait until the exclusion of the area is released,
A process for determining which controller the area is made redundant when performing redundancy of data stored in the cache memory;
The above processes are executed.

  In the present invention, it is preferable that information indicating which controller is a master controller in a partial area of a cache memory (209a and 209b in FIG. 2) determined by a request from a host computer that is a host device of the controller (FIG. 2) 211a, 211b) and the information (208a, 208b in FIG. 2) indicating which controller in which the area of the cache memory is made redundant, the cache processing means of each controller refers to the same contents. It can be configured.

  When the access request from the host computer is a write, a cache processing unit is used to determine a master controller for performing exclusive processing of the corresponding area on the cache memory for storing write request data.

  Thereafter, the cache processing unit requests the cache processing unit of the master controller to perform exclusive processing of the area.

  Upon receiving this, the cache processing means of the master controller checks whether or not the designated area is already excluded by another access request if it exists in its own cache memory.

  As a result of confirmation, if the area is excluded by another access request, the process waits until the exclusion ends. On the other hand, if the area is not excluded by another access request, an exclusion process is performed.

  If the designated area is not prepared and should be newly secured, a new area is secured and exclusive processing is performed.

  Then, the controller that has received the write request from the host notifies the controller that the exclusion process in the master controller has been completed.

  The controller having received the write request determines a controller having a cache memory to be made redundant by the write request by the cache processing means, and performs redundancy for the cache processing means of each controller by the write request. Request exclusive processing of.

  The cache processing means of each controller performs an exclusion process after waiting until the area is released if the area is excluded by others, and performs an exclusion process if the area is not excluded by others.

  If the area is new, it is newly secured and exclusive processing is performed. The cache processing means of each controller notifies the completion of the exclusion process and the completion of the exclusion process to the cache processing means of the controller that first receives a write request from the host computer.

  The cache processing means of the controller that has received the write request from the host computer waits for an exclusive completion response (report) from the controller that has issued a request for exclusive processing of the area for redundancy.

  After the exclusive processing of all areas is completed, write data received from the host computer is written to the cache memory areas of the master controller and the redundant controller, so that multiple controllers for the write data are written. Realize redundancy.

  Even when a write request to the same controller from a plurality of host computers is received, the master controller first performs exclusion so that other write requests to the same controller By waiting for the cache processing means and not writing to the same area for other redundant controllers, the consistency of the redundant data is guaranteed.

  Further, when the request from the host computer is a read, the cache processing means of the controller that has received the read request determines which controller performs the area for storing the read data of the read request.

  Upon receiving the read request, the cache processing means of the controller first determines whether its own controller is a master or a redundant controller for the area.

  When its own controller is a master or redundant controller, the cache processing means of the controller that has received the read request checks whether or not the data storage area of the cache memory exists.

  As a result, when it is confirmed that the data storage area exists, the cache processing means of the controller that has received the read request checks whether or not the area of the cache memory is exclusive.

  When the area of the cache memory is excluded by another request, the cache processing means of the controller that has received the read request waits until the area is released, and then excludes the area, as in the case of the write request. If the area is not excluded by another request, the exclusion is performed as it is. Thereafter, the cache processing means of the controller that has received the read request transmits the data in the area to the host computer, and finishes the processing for the read request.

  If the requested data area does not exist in the cache memory, the cache processing means of the controller that has received the read request secures a new area, performs exclusion, and reads the data from the disk. The data is stored in the area, and then data is transmitted to the host computer, and the read request processing is completed.

  When the read request is received, if the own controller is not the master or redundant destination controller for the area, the cache processing means of the controller that has received the read request is the master or redundant destination controller. One of them is requested to perform exclusive processing of the area.

  Similarly, the cache processing means of the controller that has received the exclusive processing checks whether there is a storage area for the read request data.

  The cache processing means of the controller that has received the exclusion process confirms whether or not the storage area for the read request data exists, as a result of the confirmation. As a result of the confirmation, if the request is excluded by another request, the cache processing means of the controller that has received the exclusion process performs the exclusion after waiting until the area is released, as in the case of the write request. If it is not excluded by the request, the area is excluded.

  Thereafter, the cache processing unit of the controller that has received the exclusion process notifies the controller that has received the read request of completion of exclusion of the area, and the cache processing unit of the controller Data in the area on the memory is read and transmitted to the host computer, and the read request processing is completed.

  In addition, the controller cache processing means that has received the exclusion request allocates a new area when the requested data does not exist in the cache memory, and after exchanging the newly allocated area, The data is read from and stored in the area.

  Thereafter, the cache processing means of the controller that has received the exclusion request notifies the controller that has received the read request of completion of exclusion of the area, and the cache processing means of the controller Data in the area on the memory is read, the data is transmitted to the host computer, and the read request processing is completed.

  According to the present invention, each controller includes a cache processing unit, and each cache processing unit individually manages the exclusion of the cache memory and secures the area so that write data can be written to an arbitrary area on the same cache memory. In addition, since redundant write data and read data can be arranged, the cache memory can be used effectively, and the object of the present invention can be achieved.

  Also, for redundant write data redundancy, a master controller and redundant controller are set in common for the system. When making write data redundant, the master controller area is first excluded. By doing so, data consistency is guaranteed and triple or more redundancy is achieved. Hereinafter, a detailed description will be given in accordance with examples.

  FIG. 1 is a diagram showing the configuration of the first exemplary embodiment of the present invention. FIG. 1 shows the configuration of one controller 101 constituting the storage.

  Referring to FIG. 1, a controller 101 is connected to a processor 110 and a host computer (not shown), and is connected to a host interface 102 for exchanging commands and data. A command processing unit 103 that exchanges notifications to the processor 110 at the time of reception and data in the cache memory 109 with the host computer via the host interface 102 and a plurality of controllers 101 are connected to each other, and cache data and The connection interface 104, which is an interface for communication, and the data and commands to be communicated are controlled through the connection interface 104, and the command from the host computer is sent to the processor 110. A communication control unit 105 that performs notification of a region, a disk interface 106 that interconnects a magnetic disk device (not shown) and a controller, data writing to the magnetic disk device via the disk interface 106, and a magnetic disk device Disk controller 107 that performs control such as reading data from the disk and requesting a desired access to the magnetic disk device, and temporarily storing the data read from the magnetic disk device and the write data received from the host computer Stored cache memory 109, cache configuration information 108 for searching whether the corresponding data exists in the cache memory 109 in response to a request from the host computer, and correspondence between the area information and the master controller Includes device configuration information 111 To have.

  The processor 110 receives the notification of the command received from the host computer by the command processing unit 103, and searches the cache configuration information 108 when it is a read according to the contents of the command.

  If there is data in the cache memory 109 as a result of the search, the data in the cache memory 109 is transmitted to the host computer via the command processing unit 103, and the data in the cache memory 109 is found as a result of the search of the cache configuration information 108. If not, the disk control unit 107 is instructed to read data existing in the magnetic disk device, the read data from the magnetic disk is stored in the cache memory 109, and the read data is transmitted to the host computer via the command processing unit 103. To do.

  Further, when the result of the command received from the host computer by the command processing unit 103 is a write, the processor 110 searches the logical address and the table on the device configuration information 111 indicated by the write command received from the host computer, and The master of the write data specified by the logical address of the command, that is, the controller to retrieve the cache configuration information 108 is first determined which controller in the system.

  Here, when the own controller is the master, the cache configuration information 108 of the own controller is searched to determine whether the data exists in the cache memory 109.

  As a result, if it exists, the area on the cache memory is exclusive.

  If the data does not exist on the cache memory 109, a new area is secured on the cache memory 109 and the area is exclusive.

  After that, the other controller that is redundant is instructed to search the cache configuration information 108 through the communication control unit 105.

  After the search from the other controller performing redundancy is completed and the exclusion of the data area is completed and the notification of the address on the cache memory to be written is received, the write data is transferred via the command processing unit 103. , Writing to the cache memory 109 in the own controller and the cache memory of the other controller is completed.

  FIG. 3 is a diagram showing one configuration of the device configuration information 111 shown in FIG. Referring to FIG. 3, the device configuration information 111 includes information indicating which controller should become the master and search first from the logical address designated by the host computer when searching the cache configuration information. . The device configuration information 111 includes a correspondence (pair) between the area information 301 and the master controller number 302 in a table format, and compares the logical address specified by the host computer with the area information 301 of the device configuration information 111. If the logical address is included in the range of the area information 301, the master controller number 302 corresponding to the area information 301 becomes the number of the controller to be searched first.

  FIG. 4 is a diagram showing an example of the contents of the cache configuration information 108 of FIG. Referring to FIG. 4, the cache configuration information 108 is configured by a link structure from the hash table 401 and the hash table 401 in order to increase the processing speed when searching for the cache configuration information (determination of cache hit / miss hit). A page tag 402 is provided.

Each page tag 402
A pointer 403 for configuring a link structure between page tags 402;
A page identifier 404 indicating which area on the cache memory indicated by the page tag 402 (hereinafter referred to as “page”) is designated by the host computer;
A page address 406 of address information indicating which page exists in the cache memory (cache memory 109 in FIG. 1);
Page information 405 indicating pages having write data not saved on the magnetic disk device. The page information 405 includes information indicating an empty page and the like, exclusive information (flag) for exclusive control of the page, and the like (not shown).

  FIG. 2 is a diagram schematically illustrating the overall configuration of the system according to the first embodiment of this invention. In FIG. 2, for the sake of simplicity, a system including two controllers 101 in FIG. 1 is illustrated. However, in the present invention, the number of controllers is of course not limited to two.

  The controller 0 (201a) and the controller 1 (201b) include the same elements as those shown in FIG.

  The host interfaces 202a and 202b correspond to the host interface 102 in FIG. 1, and the connection interface 204 corresponds to the connection interface 104 in FIG. The disk interfaces 206a, 206b, 213a, and 213b correspond to the disk interface 106 in FIG.

  The controller 201a and the controller 201b are connected by a connection interface 204, and perform communication such as cache data between the controllers.

  The controller 201a is connected to the magnetic disk device 212a via the disk interface 206a and the magnetic disk device 212b via the disk interface 213a. The controller 201b is connected to the magnetic disk device 212b and the disk interface 213b via the disk interface 206b. It is connected to the magnetic disk device 212a. That is, the disk control unit of the controller can access not only the magnetic disk device of its own controller but also the magnetic disk device of another controller via the disk interface.

  By doing so, the controller 201a and the controller 201b can mutually access the magnetic disk device 212a and the magnetic disk device 212b, and even when one of the controllers becomes unusable, both controllers are made redundant. Data can be written to the magnetic disk device.

  In addition, the same information is written in the device configuration information 211a and 211b on the controllers 201a and 201b in advance, and each controller can refer to the controllers 210a and 210b of the controllers 201a and 201b without inquiring other controllers. Is possible. The device configuration information 211a of the controller 201a and the device configuration information 211b of the controller 201b only need to have the same content, and the writing (updating) form and the like are arbitrary.

  Next, an example of the operation of this embodiment will be specifically described with reference to the flowcharts of FIGS. 5 to 7 and FIGS. 2 to 4. FIG. 5 is a flowchart showing the entire operation of the system, and FIGS. 6 and 7 are flowcharts showing details of the search of the own controller in steps S5 and S11 of FIG. 5 and the search of other controllers in steps S6 and S10.

  When the host interface 202a in FIG. 2 receives a command from the host computer by the command processing unit 203a, the command processing unit 203a notifies the processor 210a that the command has been received (step S1 in FIG. 5).

  The processor 210a determines the process indicated by the command from the contents of the command received by the command processing unit 203a (step S2 in FIG. 5).

  If the received command is a write operation, the processor 210a refers to the device configuration information 211a (step S3 in FIG. 5), and which controller is the master of the logical address data indicated by the command received from the host computer. That is, it is first determined whether the cache configuration information should be retrieved (step S4 in FIG. 5).

  Here, if the logical address designated by the host computer is a write command of 10, the processor 210a searches for the device configuration information 211a (step S5 in FIG. 5). As the device configuration information 211a, the same device configuration information 211b as that of the controller 201b is prepared.

  In the following description, it is assumed that the contents of the device configuration information 211a and 211b are the contents shown in FIG. In FIG. 3, the controller number 302 of the master indicates the number of the controller that becomes the master, and the number 0 is the controller 201a and the number 1 is the controller 201b.

  The processor 210a compares the logical address 10 with the item of the area information 301 of the device configuration information 211a. Since the logical address 10 is in the range of 0 to 99, the value of the controller number 302 of the master corresponding to the area information of 0 to 99 is read. Since the controller number of the master is 0, it can be determined that the logical address specified by the command is the controller 201a (step S101 in FIG. 6).

  Since it is determined that the master of the write command is the controller 201a, the processor 210a searches the cache configuration information 208a of the master controller 201a, and the page specified by the corresponding write command exists in the cache memory 209a. Is determined (step S102 in FIG. 6). A cache page search is performed after exclusive processing (LOCK) of the cache configuration information 208a of the master controller 201a. When the cache configuration information 208a and the cache memory 209a are updated by another request or the like, the process waits until the exclusion of the cache configuration information 208a is released (unlocked). Normally, the exclusion of the exclusion of the cache configuration information 208a is performed when the corresponding page of the cache memory is hit or when the corresponding page is newly reserved in the state where the corresponding page is secured and read / write is performed. After the cancellation, the exclusion of the corresponding page is performed.

  If it is determined in step S102 that the page specified by the write command does not exist on the cache memory 209a, the processor 210a refers to the cache configuration information 208a and searches for a page on the cache memory 209a that can be newly secured. Then, the page address is registered in the page address 406 of the cache configuration information 208a as a page to be newly stored, and exclusive processing of the page is performed. This exclusive processing is for preventing data corruption due to reading from another command or page from another controller, and preventing consistency from being lost due to writing to redundant write data.

  This exclusive processing is realized by the processor 210a writing exclusive information indicating that the page is being used by the command being executed in the page information 405 of FIG. 4 in the cache configuration information 208a (FIG. 6). Step S103).

  When the page specified by the write command exists in the cache memory 209a, the processor 210a checks whether the other command or another controller is using the exclusive.

  More specifically, the processor 210a refers to the exclusive information in the page information 405 (see FIG. 4) of the cache configuration information 208a and confirms the exclusive state (step S104 in FIG. 6).

  If the page is not in the exclusive state, the processor 210a acquires the page address 406 of the cache configuration information 208a, performs the exclusive process on the page, and proceeds to the next step (step S106 in FIG. 6).

  When the page is in the exclusive state, the processing of the write command enters a waiting state until the exclusion of the page due to execution of another command or another controller is cancelled. If the exclusion is released, an exclusion process is performed so that other commands and other controllers cannot be used, and the process proceeds to the next step (step S105 in FIG. 6). In the self controller search process of FIG. 6, after the cache memory page exclusion process, the exclusion of the cache configuration information is released (UNLOCK).

  Next, the cache configuration information 208b is searched for the redundant controller 201b (step S6 in FIG. 5).

  First, the processor 210a instructs the communication control unit 205a to search for cache control information with respect to the master controller 201b.

  The communication control unit 205a transmits a command cache search information search instruction to the communication control unit 205b of the controller 201b through the connection interface 204 (step S201 in FIG. 7).

  The communication control unit 205b transmits the received search instruction to the processor 210b, and the processor 210b searches its own cache configuration information 208b (step S202 in FIG. 7).

  As a result of the search, if there is no page in the area indicated by the write command (No branch in step S203 in FIG. 7), a new page is secured on the cache memory 209b, the page is exclusive, and the page Is registered in the page address 406 of the cache configuration information 208b (step S204 in FIG. 7).

  If the page specified by the write command is present in the cache memory 209b (Yes branch in step S203 in FIG. 7), it is confirmed whether or not it is being used by another command or another controller. More specifically, the exclusive information in the page information 405 of the cache configuration information 208b is referred to and it is confirmed whether or not it is already in the exclusive state (step S206 in FIG. 7).

  If the page is not in the exclusive state (No branch in step S206 in FIG. 7), the page address 406 (see FIG. 4) of the cache configuration information 208b is acquired, the page is excluded, and the process proceeds to the next step. (Step S208 in FIG. 7).

  If the page is in an exclusive state (Yes branch in step S206 in FIG. 7), the write command processing is in a wait state until the exclusion of the page due to execution of another command or other controller processing is released. enter. If the exclusion is released, an exclusion process is performed so that other commands and other controllers cannot be used, and the process proceeds to the next step (step S207 in FIG. 7).

  Next, the processor 210b transmits the acquired page address 406 to the communication control unit 205b, and notifies the communication control unit 205a of the controller 201a that the page has been secured through the connection interface 204 (step S205 in FIG. 7).

  When the communication control unit 205a receives the notification that the controller 201b has secured the page from the processor 210a, the communication control unit 205a sends the write data from the host computer through the command processing unit 203a to the page address 406 (see FIG. 4) is written to the page on the cache memory 209a at the address. At the same time, data is written to the cache memory 209b of the controller 201b through the communication control unit 205a, the connection interface 204, and the communication control unit 205b to the page address of the cache memory 209b of the controller 201b that has already been received. The write data is written to the cache and made redundant, and the end of the write command is notified to the host computer through the command processing unit 203a (step S7 in FIG. 5).

  Thereafter, the processor 210a instructs the controller 201b to cancel the exclusion of the page through the communication control unit 205a.

  The processor 210b receives the instruction through the connection interface 204 and the communication control unit 205b.

  Then, the processor 210b releases the exclusion of the page information of the cache configuration information 208b of the controller 201b.

  When the exclusion of the exclusion (UNLOCK) is completed, the processor 210b notifies the controller 201a of the completion of the exclusion of the page through the communication control unit 205b (step S8 in FIG. 5).

  When the processor 210a receives the notification of the exclusion release from the controller 201b, the processor 210a releases the exclusion of the page information 405 of the cache configuration information 208a of the controller 201a and completes the processing for the write command (step of FIG. 5). S9).

  Further, when the logical address of the write command is “150”, the controller 201b becomes the master, and therefore the processor 210a instructs the communication control unit 205a to search for the cache control information with respect to the master controller 201b. This is performed (step S10 in FIG. 5).

  The communication control unit 205a transmits a command cache search information search instruction to the communication control unit 205b of the controller 201b through the connection interface 204 (step S201 in FIG. 7).

  The communication control unit 205b transmits the received search instruction to the processor 210b, and the processor 210b searches its own cache configuration information 208b (step S202 in FIG. 7). As a result, the page of the area indicated by the write command Is not present (No in step S203 in FIG. 7), a new page is secured on the cache memory 209b, the page is exclusive, and the page address is registered in the page address 406 on the cache configuration information 208b. (Step S204 in FIG. 7).

  If the page specified by the write command is present in the cache memory 209b (Yes in step S203 in FIG. 7), the exclusion is checked to see if it is used by another command or another controller. More specifically, the exclusive information in the page information 405 of the cache configuration information 208b is referred to and the exclusive state is confirmed (step S206 in FIG. 7).

  If the page is not in the exclusive state (No in step S206 in FIG. 7), the page address 406 of the cache configuration information 208b is acquired, the page is excluded, and the process proceeds to the next step (step S208 in FIG. 7). ).

  If the page is in an exclusive state (Yes in step S206 in FIG. 7), the write command processing enters a wait state until the exclusion of the page due to execution of another command or other controller processing is released. . When the exclusion of the page is released, an exclusion process is performed so that other commands and other controllers cannot be used, and the process proceeds to the next step (step S207 in FIG. 7).

  Next, the processor 210b transmits the acquired page address 406 to the communication control unit 205b, and notifies the communication control unit 205a of the controller 201a through the connection interface 204 that the page has been secured (step S205 in FIG. 7).

  The communication control unit 205a of the controller 201a notifies the processor 210a of page reservation.

  Next, the cache configuration information 208a of the controller 201a is searched (step S101 in FIG. 6), and it is determined whether or not the page specified by the corresponding write command exists in the cache memory 209a (step S102 in FIG. 6). .

  As a result, if it is determined that the page specified by the write command is not in the cache memory 209a, the processor 210a refers to the cache configuration information 208a, searches for a page on the cache memory 209a that can be newly secured, The page address is registered at the page address 406 of the cache configuration information 208a as a page to be newly stored, and exclusive processing is performed (step S103 in FIG. 6).

  When the page specified by the write command exists in the cache memory 209a, the exclusion is checked to determine whether it is used by another command or another controller. More specifically, the exclusive information in the page information 405 of the cache configuration information 208a is referred to and the exclusive state is confirmed (step S104 in FIG. 6).

  If the page is not in the exclusive state (No in step S104 in FIG. 6), the page address 406 of the cache configuration information 208a is acquired, the page is excluded, and the process proceeds to the next step (step S106 in FIG. 6). .

  If the page is in an exclusive state (Yes in step S104 in FIG. 6), the write command processing enters a wait state until the exclusion of the page due to execution of another command or another controller is cancelled. If the exclusion of the page is released, an exclusion process is performed so that other commands and other controllers cannot be used, and the process proceeds to the next step (step S105 in FIG. 6).

  Next, the processor 210a writes write data from the host computer to the page at the page address 406 indicated by the cache configuration information 208a of the controller 201a through the command processing unit 203a, and at the same time, writes it to the cache memory 209b of the controller 201b. Through the communication control unit 205a, the connection interface 204, and the communication control unit 205b, the host computer is notified of data write to the page address of the cache memory 209b of the controller 201b that has already been received and the end of the write command (FIG. 5). Step S12).

  Furthermore, the processor 210a cancels the exclusion of the page of the cache configuration information 208a (step S13 in FIG. 5).

  Thereafter, the processor 210a instructs the controller 201b to release the page (page UNLOCK) through the communication control unit 205a.

  The processor 210b receives the instruction through the connection interface 204 and the communication control unit 205b, and releases the exclusion of the page information of the cache configuration information 208b of the controller 201b (step S14 in FIG. 5).

  When the exclusion of the exclusion is completed, the processor 210b notifies the controller 201a of the exclusion of the page through the communication control unit 205b.

  When the processor 210a receives the notification of exclusion release from the controller 201b, the processing for the write command is completed.

  In any case, the data written in the cache memory is appropriately written in the magnetic disk device, and the cache memory and the magnetic disk device are matched.

  If the command received from the host computer in the determination in step S2 is read (No in step S2 in FIG. 5), the processor 210a determines that the cache configuration information 208a is independent of the information indicating the master controller in the device configuration information 211a. Is searched (step S15 in FIG. 5).

  It is determined whether or not the read command data exists on the cache memory 209a (step S16 in FIG. 5).

  As a result of the determination, if a page corresponding to the data of the read command exists on the cache memory 209a (Yes in step S16 in FIG. 5), it is confirmed whether or not it is not used by another command or another controller. I do. Specifically, the exclusive information in the page information 405 of the cache configuration information 208a is referred to and the exclusive state is confirmed (step S21 in FIG. 5).

  As a result of the confirmation, if the page is not in the exclusive state (No in step S21 in FIG. 5), the page address 406 of the cache configuration information 208a is acquired, the page is excluded, and the process proceeds to the next step (FIG. 5). 5 step S23).

  As a result of the confirmation, if the page is in an exclusive state (Yes in step S21 in FIG. 5), the read command processing waits until the exclusion of the page due to execution of another command or other controller processing is released. Enter the state. If the exclusion is released, the exclusion information is written in the page information 405 of the cache configuration information 208a, and the exclusion process for the page is performed (step S22 in FIG. 5).

  Next, the data of the page indicated by the address of the page address 406 obtained as a result of the search is read from the cache memory 209a and transferred to the host computer through the command processing unit 203a (step S19 in FIG. 5).

  Thereafter, the end of the read command is reported to the host computer, and at the same time, the exclusion of the page information 405 of the cache configuration information 208a is canceled to complete the processing for the read command (step S20 in FIG. 5).

  When the page corresponding to the read command data does not exist in the cache memory 209a (No in step S16 in FIG. 5), the processor 210a searches for a page on the cache memory 209a that can be newly secured, As a new page to be stored, the page address is registered at the page address 406 of the cache configuration information 208a, and exclusive information is written into the page information 405 to perform exclusion processing (step S17 in FIG. 5).

  Thereafter, the processor 210a instructs the disk control unit 207a to read data on the magnetic disk device, and the disk control unit 207a operates on the magnetic disk device 212a or the magnetic disk device 212b via the disk interface 206a or 213a. Data is read and written to a page on the cache memory 209a (step S18 in FIG. 5).

  When the writing to the cache memory 209a is completed, the processor 210a transfers the data on the cache memory 209a to the host computer through the command processing unit 203a and the host interface 202a (step S19 in FIG. 5).

  Thereafter, the processor 210a reports the end of the read command to the host computer, and at the same time, releases the exclusion of the page information 405 of the cache configuration information 208a, and completes the processing for the read command (step S20 in FIG. 5).

  Next, the function and effect of this embodiment will be described.

  As a procedure for accessing a page on the cache memory, if it is read / write of the same logical address, it is always determined whether or not exclusion is performed if it is an existing page in the master controller. The exclusive page control is performed, and thereafter, the page on the cache memory of the controller that has been made redundant is accessed.

  With this configuration, subsequent commands that read / write to the same page wait for cancellation of exclusion of the corresponding page, and consistency with the data of the corresponding page is guaranteed.

  In addition, each controller performs cache memory management, that is, page management based on the cache configuration information, and the read data can be cached only by the cache memory of each individual controller. High memory utilization efficiency.

  Furthermore, since exclusive processing for performing read or write is only a minimum unit called a page as compared to a method of performing exclusive processing on all or part of cache configuration information, read / write by other commands and other controllers There is little competition of read / write, and performance improvement is facilitated.

  INDUSTRIAL APPLICABILITY According to the present invention, the present invention can be applied to a countermeasure against failure due to the use of a storage that accumulates information from a host computer and the redundancy of a cache device connected between the host computer and the storage via a network. Further, the function of the present invention is built in a host computer, and the present invention can also be applied to uses such as data redundancy in cluster connection between host computers.

  The operation procedure described with reference to FIGS. 5 to 7 is preferably realized by a computer program executed on the processor of the controller.

  FIG. 8 illustrates a system (four-node system) including four controllers according to the present invention. The controllers 0-3 (501a-501d) have the same elements as those of the embodiment shown in FIG.

  The host interface 502 corresponds to the host interface 102 in FIG. 1, and the interconnection network 504 corresponds to the connection interface 104 in FIG. The disk control unit 507 corresponds to the disk control unit 107 in FIG. The controllers 0 and 1 correspond to the two-node configuration of FIG. 2, and the disk control unit of the controller 0 is accessible to the magnetic disk devices 512a and 512b via the corresponding disk interface. Are accessible to the magnetic disk devices 512b and 512a via the corresponding disk interfaces. The controllers 2 and 3 correspond to the two-node configuration of FIG. 2, and the disk control unit of the controller 2 is accessible to the magnetic disk devices 512c and 512d via the corresponding disk interface. Are accessible to the magnetic disk devices 512d and 512c via the corresponding disk interfaces.

  The controllers 0-3 are connected to each other via a communication control unit in each controller and the interconnection network 504, and transfer cache data and the like between the controllers. The controllers 0 and 1 communicate with the controller 2 or 3 via the interconnection network 504 and can access the magnetic disk devices 512c and 512d via the disk control unit. The controllers 2 and 3 communicate with the interconnection network 504. , And communicates with the controller 0 or 1 through the disk control unit to make the magnetic disk devices 512a and 512b accessible, and each of the four controllers 0-3 can access the magnetic disk devices 512a to 512d. It is said. With this configuration, for example, even when the controller 0 becomes unusable, the redundant data can be written to the magnetic disk device via the controller 1. For example, even when the controller 2 becomes unusable, the redundant data can be written to the magnetic disk device via the controller 3. The connection form of the disk control unit of each controller and the magnetic disk devices 512a to 512d is not limited to the configuration shown in FIG. 8, and the disk control unit of each controller is connected to the magnetic disk device via a bus. Of course, it may be configured to be connected to 512a to 512d.

  Further, the same information is written in advance in each device configuration information 511 of the controller 0-3, and each controller can refer to the controller without querying another controller.

  FIG. 9 is a sequence diagram showing an example of write access control when four controllers that do not have the configuration of the present invention are provided as a comparative example of the present invention. In the case of the comparative example in FIG. 9, there is no master controller that manages the cache page. The controller 0-3 in FIG. 9 is configured such that each controller does not hold the device configuration information 511 in the controller 0-3 in FIG. In the comparative example of FIG. 9, the controllers 0, 1, and 3 form a triple redundant set in which write data from the host device is redundantly written to the respective cache memories. For example, in the Write command to the controller 0, On the other hand, write data is written to the cache memories of the controllers 0, 1, and 3.

  Referring to FIG. 9, when the command processing unit of the controller 0 receives a write command from the host (not shown) via the host interface, the command processing unit transmits to the other controllers 1 and 3 constituting the triple redundant set. The cache configuration information exclusion process (LOCK) is instructed. The controller 0 and the controllers 1 and 3 that have received an instruction from the controller 0 (cache configuration information exclusion instruction) lock (LOCK) their respective cache configuration information (see FIG. 4). Note that these exclusive processing and communication processing in each controller are performed through the processor, communication control unit, mutual communication network, and the like of each controller.

  Upon receiving notification of the completion of the lock of the cache configuration information in the controller 0 and the controllers 1 and 3, the controller 0 instructs the other controllers 1 and 3 to perform cache search and page lock, and performs cache search in its own controller. And lock the page. Upon receiving a cache search and page lock instruction from the controller 0, the controllers 1 and 3 also perform cache search and cache page lock. As described above, when the controller 0, 1, 3 determines that the page specified by the write command does not exist in the cache memory in the cache search, the processor refers to the cache configuration information, and newly A page of the cache memory that can be secured is searched, and the page address is registered in the page address of the cache configuration information as a page for newly storing the page. Then, the exclusion process for the page is performed. The page exclusion process is performed by setting a lock on the page information exclusion information of the cache configuration information.

  Subsequently, the controller 0 waits for the completion of the cache search and the page lock in the controllers 0, 1 and 3, and instructs the controllers 1 and 3 to unlock (UNLOCK) the cache configuration information. Upon receiving the UNLOCK instruction for the cache configuration information from the controller 0, the controllers 1 and 3 unlock the respective cache configuration information.

  The command processing unit of the controller 0 receives the write data from the host interface, transfers the write data to the controllers 1 and 3, and waits for a write completion response to the cache page of the write data in the controllers 0, 1 and 3.

  When the writing of the write data of the controller 0, 1, 3 to the corresponding page in the cache memory is completed, the controller 0 returns the write state (Write State) to the host via the host interface as a response to the Write command.

  Next, the controller 0 instructs the controllers 1 and 3 to perform cache configuration information exclusion processing (LOCK), and the controllers 0, 1 and 3 lock their cache configuration information (see FIG. 4) ( LOCK).

  When the cache configuration information is locked in each of the controllers 0, 1, 3, the controller 0 performs cache search and page unlock, and the controllers 1, 3 also receive the unlock instruction from the controller 0. Unlock the cache page.

  After unlocking the cache configuration information in the controllers 0, 1, 3, the controllers 0, 1, 3 unlock the cache configuration information (UNLOCK).

  FIG. 10 is a sequence diagram illustrating an example of write access control when the controller 0-3 includes the controller 0-3 of the present embodiment illustrated in FIG. In each controller, device configuration information (511 in FIG. 8) indicating which controller is the master controller of the partial area of the cache memory, and which controller is used to make the area of the cache memory redundant. Regarding the cache configuration information shown (508 in FIG. 8), each controller is configured to be able to refer to the same content. In the present embodiment shown in FIG. 10, the controllers 0, 1 and 3 constitute a triple redundant set. For example, in response to a write command to the controller 0, the cache memory of the controllers 0, 1 and 3 is transferred. Redundant data writing is performed.

  The command processing unit of the controller 0 receives the write command from the host computer, and excludes the corresponding area on the cache memory for storing the write data of the write command from the device configuration information (511 in FIG. 8). Determine the master controller for processing. In this case, it becomes clear that the master of the corresponding page on the cache memory is the controller 1.

  The controller 0 transmits a cache search instruction to the master controller 1, and transmits a request for exclusive processing of the page. Upon receiving this request, the processor of the controller 1 first locks (LOCK) the cache configuration information, performs cache search and page lock, and then unlocks (UNLOCK) the cache configuration information. At this time, in the cache search, if the designated page area already exists in the cache memory of the master controller 1, it is confirmed whether or not the page area is excluded by another access request. If the page area is not excluded by another access request, an exclusion process is performed. Further, in the master controller 1, when the designated page area is not prepared in the cache memory (miss hit) and should be newly reserved, a page area is newly reserved and the page is locked. The configuration information is unlocked (UNLOCK), and the controller 1 that is the master of the page area notifies the controller 0 that the cache search is completed. Note that these exclusive processing and communication processing in each controller are performed through the processor, communication control unit, mutual communication network, and the like of each controller.

  Next, the controller 0 determines the redundant destination controllers 0 and 3 having the cache memory to be made redundant by the write request, and in this case, the area for making the redundant controller 3 redundant by the write request. A request for exclusive processing (cache search instruction) is transmitted.

  Each controller 0, 1, 3 once performs an exclusive process (lock) on the cache configuration information. In this case, if the page area is exclusive, the exclusive process is performed after the page area is released. If the page area is not exclusive, the page area is locked and the cache configuration information is unlocked. If the page area is new, the page area is newly secured and exclusive processing is performed. The controllers 1 and 3 notify the controller 0 that the cache search, page lock, and cache configuration information unlock (UNLOCK) have been completed.

  The controller 0 waits for a completion response (report) from the destination controller 3 of the request for exclusive processing of the area for redundancy. That is, even if the exclusive process of the area for redundancy in the controller 0 is completed, the process does not proceed until a response (report) of the exclusive process from the other controller 3 in the redundancy destination is received.

  When receiving a completion response from the other redundant controller 3, the controller 0 writes the write data received from the host into the corresponding page area of the cache memory of the controller 0. Further, the controller 0 transfers the write data received from the host to the controllers 1 and 3 via the communication control unit 505 and the interconnection network 504, and transfers the write data from the host to the corresponding page area of the cache memory of the controllers 1 and 3. Write the received write data. Redundancy for multiple controllers for write data is realized. Redundancy is not limited to triple, and may be duplex.

  When writing of the write data of the controllers 0, 1 and 3 is completed, the controller 0 returns a write result (Write State) to the host, and each of the controllers 0, 1 and 3 also locks (LOCK) the cache configuration information. After unlocking the cache page (UNLOCK), the cache configuration information is unlocked. Note that the write data written to the cache memory of each controller is appropriately written to the corresponding disk device (storage) by, for example, a write back method.

  According to this embodiment, the master controller performs exclusive control of the cache page, and then accesses the page in the cache memory of the redundant controller, so that the same page is read / written. Subsequent commands wait for cancellation of exclusion of the corresponding page, and the consistency of the data of the corresponding page is guaranteed. On the other hand, in the case of the sequence diagram of FIG. 9 of the comparative example, such control is not performed.

  Further, as can be seen from the sequence diagram of FIG. 10 and the sequence diagram of FIG. 9 of the comparative example, according to the present invention, the exchange of instructions (commands) and responses (reports) between the controllers is greatly reduced. .

  In the above-described embodiment, an example in which the management unit area of the cache memory is managed in units of pages has been described, but the present invention is of course not limited to such a configuration.

  The present invention has been described with reference to the above-described embodiments. However, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, it includes deformation and correction.

It is a block diagram which shows the structure of the controller of one Example of this invention. It is a figure which shows the system configuration | structure (2 controllers) of one Example of this invention. It is a figure which shows the content of the apparatus structure information in one Example of this invention. It is a figure which shows the cache structure information in one Example of this invention. It is a flowchart for demonstrating operation | movement of one Example of this invention. It is a flowchart for demonstrating the search process of a self-controller in one Example of this invention. It is a flowchart for demonstrating the search process of another controller in one Example of this invention. It is a figure which shows the system configuration | structure (4 controllers) of the other Example of this invention. It is a sequence diagram explaining an example of operation | movement of a comparative example. It is a sequence diagram explaining an example of operation | movement of the other Example of this invention.

Explanation of symbols

101 controller 102 host interface 103 command processing unit 104 connection interface 105 communication control unit 106 disk interface 107 disk control unit 108 cache configuration information 109 cache memory 110 processor 111 device configuration information 201a, 201b, 501a, 501b, 501c, 501d controller 202a, 202b, 502 Host interface 203a, 203b, 503 Command processing unit 204 Connection interface 205a, 205b, 505 Communication control unit 206a, 206b, 506 Disk interface 207a, 207b, 507 Disk control unit 208a, 208b, 508 Cache configuration information 209a, 209b 509 Cache memory 210 a, 210b, 510 Processor 211a, 211b, 511 Device configuration information 212a, 212b, 512a, 512b, 512c, 512d Magnetic disk device 213a, 213b Disk interface 301 Area information 302 Master controller number 401 Hash table 402 Page tag 403 Pointer 404 Page identifier 405 Page information 406 Page address 504 Interconnection network

Claims (16)

Each of the storage systems includes a plurality of controllers that are connected to a corresponding host device and are connected to each other to communicate with each other to make the corresponding storage device accessible.
Each of the plurality of controllers is
A cache memory for storing a part of the data of the storage device;
Cache processing means for controlling access to the cache memory;
With
Each of the plurality of controllers further includes:
Storing and holding device configuration information that defines the correspondence between the logical address area from the host device and the master controller assigned to the area;
The device configuration information is the same content among the plurality of controllers,
In the controller that has received an access request from the host device, the cache processing means refers to the device configuration information in the controller and serves as a master for an area for storing data corresponding to the address of the access request Decide
The cache processing means of the master controller before the cache memory exclusive processing is performed in the redundant controller when there is a redundant controller having a cache memory for storing the data in a redundant manner In addition, the cache system of the master controller performs exclusive processing. In the controller that has received the write request from the host device, the cache processing means refers to the device configuration information in the controller and determines a controller as a master with respect to an area for storing write data.
The cache processing means of the master controller checks whether or not the write data storage destination area of the cache memory of the master controller is already exclusive, and if the area is exclusive , Wait until the exclusion of the area is released and then perform the exclusion, and if the area is not exclusive, perform the exclusion of the area,
When there is a redundant controller having a cache memory to store the write data in a redundant manner, the cache in the master controller is prior to the cache memory exclusive processing in the redundant controller. 2. The storage system according to claim 1, wherein a memory exclusive process is performed. When the redundancy destination controller exists for the write data, the cache processing means of the redundancy destination controller is configured to execute the exclusion processing of the cache memory area in the master controller. Exclude the write data storage area of the cache memory of the controller,
The write data is written to a cache memory of the master controller and a cache memory of the redundant controller based on completion of the exclusion process in the redundant controller. 2. The storage system according to 2. In response to a write request from the host device, the cache processing means of the controller performs cache search on the master controller when the master controller is not its own controller with respect to the area for storing write data. Instruct
When a cache search completion is received from the master controller, the cache processing means of the controller that has received a write request from the host device, and when there is another redundant destination controller, the redundancy destination 3. The storage system according to claim 1, wherein cache search is performed by the cache processing means of another controller, and write data is written to a corresponding area of the cache memory of each controller. Each of the plurality of controllers includes cache configuration information for managing configuration information of the cache memory area,
The storage system according to claim 1 or 2, wherein the plurality of controllers are configured to refer to the same contents with respect to the cache configuration information. The cache processing means of the controller that has received the write request from the higher-level device refers to the device configuration information based on the logical address of the write request, and stores the write request data on the cache memory. Decide the master controller for exclusion of the corresponding area, request the cache processing means of the determined master controller to exclude the area,
The cache processing means of the master controller is
If the specified area already exists in its own cache memory, check whether it is exclusive by another access request,
If the area is exclusive by another access request, wait until the exclusive processing of the area ends,
If the area is not excluded by another access request, the area is excluded,
On the other hand, if the specified area is not on the cache memory and should be newly secured, after securing a new area on the cache memory, the newly secured area is exclusive,
The storage system according to claim 1, wherein the controller that has received the write request from the higher-level device notifies the controller that the exclusion process in the master controller has been completed. The cache processing means of the controller that has received the write request,
Determining at least one redundant controller having a cache memory to be made redundant with respect to the write request;
Request the exclusive processing of the area for redundancy by a write request to the cache processing means of the redundant destination controller,
The cache processing means of the redundant controller is:
If the area for performing redundancy is excluded by another, exclusion is performed after waiting for the exclusion to be canceled, and if not exclusive by other, the area for performing redundancy is excluded. ,
If the area for performing the redundancy is new, the area for performing the redundancy is newly secured and exclusive,
The cache processing means of the redundant controller is:
Notifying that the exclusive processing is completed to the cache processing means of the controller that has received the write request from the host device,
The cache processing means of the controller that has received the write request from the host device,
Wait for the exclusion completion response from the controller that issued the request for exclusive processing of the area for redundancy, and after completing the exclusive processing of the corresponding area of the cache memory in each controller, the master controller and the redundant controller The storage system according to claim 1, wherein write data received from the host device is written in a corresponding area of the cache memory to realize redundancy for a plurality of controllers with respect to the write data.   When the plurality of controllers receive a write request to the same area, the master controller first performs exclusion of the area storing the write data in the cache memory, so that other write requests for the same area 2. The storage system according to claim 1, wherein the controller waits at the cache processing means of the controller and controls so as not to write to the same area for the other redundant controllers. The cache processing means of the controller that has received the read request from the higher-level device determines whether the own controller is the master of the area or the redundant destination controller for the area storing the data of the read request. Make a decision,
If the own controller is a master or redundant controller, check whether there is a storage area for the read request data in the cache memory;
If there is an area storing the data in the cache memory, check whether the area is exclusive;
If the area is exclusive by another request, do the exclusion after waiting until the area is released,
If the area is not excluded by another request, after the exclusion of the area, the data of the area of the cache memory is transmitted to the host device,
If the data area of the read request does not exist in the cache memory, a new area is secured in the cache memory, and after the newly secured area is excluded, the data is read from the storage device. The storage system according to claim 1, wherein the storage system stores data in the newly secured area and then transmits data to the higher-level device. The cache processing means of the controller that has received the read request from the host device, if its own controller is not the master or redundant destination controller for the area storing the read request data, the master or redundant destination for the area. Requesting exclusive processing of the area to any one of the controllers
The cache processing means of the controller that has received the exclusive processing request includes:
Check whether there is an area for storing read request data on the cache memory of the controller,
If there is an area for storing the read request data on the cache memory, check whether the area is exclusive;
If the area is exclusive by another request, do the exclusion after waiting until the area is released,
If the area is not excluded by another request, the area is excluded, the completion of the exclusion of the area is notified to the controller that received the read request from the host device,
The storage system according to claim 9, wherein the cache processing unit of the controller reads data in an area on the cache memory of the controller for which exclusion is performed, and transmits the data to the host device. In the controller that has received the exclusion request, if the data of the read request does not exist in the cache memory, a new area is secured on the cache memory,
After exclusion of the newly secured area, data is read from the storage device and stored in the newly secured area, and a read request is issued from the host device to complete the exclusion of the newly secured area. Notify the received controller,
11. The storage system according to claim 10, wherein the cache processing means of the controller reads data in an area on the cache memory of the controller where exclusion is performed, and transmits the data to the host device. The cache processing means of the controller that has received a write request from the host device,
Referring to the device configuration information in the controller, the controller that determines the master of the cache memory area corresponding to the write data of the write request is determined, and the controller that received the write request from the host device is the master controller. If there is, perform the cache search and the exclusion of the area to store the write data in the cache memory,
If the controller that received the access request from the host device is not the master, send a cache search instruction to the master controller,
The master controller performs a cache search and an exclusive area for storing write data in the cache memory,
Subsequently, when there is a redundant destination controller, the cache processing means of the redundant destination controller performs an exclusion of an area for storing write data in the cache search and the cache memory,
Subsequently, write data is written from the host device to each cache memory of the master and the redundant controller,
2. The storage system according to claim 1, wherein the cache processing means of the master controller and the redundant controller releases the exclusion of the area of the cache memory.   The cache processing means of the controller locks cache configuration information for managing configuration information of the cache memory area immediately before the cache search, and after the exclusion of the area of the cache memory, the cache configuration information The storage system according to claim 12, wherein the storage system is unlocked.   The cache processing means of the controller locks cache configuration information for managing configuration information of the area of the cache memory immediately before releasing the exclusion of the area of the cache memory, and excludes the area of the cache memory. 14. The storage system according to claim 13, wherein the cache configuration information is unlocked after release. Each is a cache redundancy method for a storage system that includes a plurality of controllers that are connected to a corresponding host device and are connected to each other for communication and hold a part of the data of the corresponding storage device. And
Each of the plurality of controllers stores and holds device configuration information that defines a correspondence relationship between a logical address area from the host device and a master controller assigned to the area, and the device configuration information is The plurality of controllers have the same content,
The controller that has received the access request from the higher-level device refers to the device configuration information in the controller, determines a controller to be a master with respect to an area for storing data corresponding to the address of the access request,
The master controller performs exclusive processing of the data storage destination area of the cache memory of the master controller, and there is a redundant destination controller having a cache memory for storing the data in a redundant manner In addition, prior to the cache memory exclusion process in the redundant controller, the cache memory exclusion process in the master controller is performed. Each of them includes a plurality of controllers that are connected to a corresponding host device and that are connected to each other for communication and hold a part of the data in the corresponding storage device and a processor.
Each of the plurality of controllers stores and holds device configuration information that defines a correspondence relationship between a logical address area from the host device and a master controller assigned to the area, and the device configuration information is , The same content in the plurality of controllers,
In the processor of the controller,
When receiving a write request from the host device, referring to the device configuration information in the controller, a process for determining a master controller for the data of the address of the write request;
If the controller is not the master, processing to instruct the master controller to perform cache memory exclusion;
After the exclusion process of the cache memory area in the master controller, the process of exclusiveizing the cache memory area in the controller;
Write the write request data from the device to the cache memory area in the controller, and transfer the write request data to the master controller;
A program that executes

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