JP2008046275A - Display device, drive unit of display device, television receiver, and television receiving system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a display device that can significantly reduce power consumption in a driving circuit by efficiently carrying out charge share. <P>SOLUTION: The display device is equipped with: a display section 100 where pixel electrodes 140 are formed via pixel TFTs 130 at intersections of gate signal lines 111 and source signal lines 121; a source driving circuit 200 that supplies a signal voltage corresponding to a video signal to the source signal lines 121; and a gate driving circuit 300 that supplies a high-level signal voltage to turn on the pixel TFT 130 during one horizontal scanning period to the gate signal lines 111. When the gate driving circuit 300 supplies a high level signal voltage to the gate signal lines 111 in one horizontal scanning period, the driving circuit also supplies a high level signal voltage in a first period of the one horizontal scanning period to a gate signal line 11 to be the scanning object next to the current gate signal line 111. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device that performs charge sharing in order to reduce power consumption in a drive circuit that drives the display device.

  In recent liquid crystal display devices, the temperature rise of the liquid crystal module tends to increase due to an increase in load accompanying an increase in the size of the liquid crystal module and an increase in operating frequency accompanying an increase in resolution.

  This is because if the liquid crystal module is increased in size, the load on the panel increases and the power for driving the panel increases, resulting in an increase in the amount of heat generated in the source drive circuit.

  In addition, a change in the signal voltage supplied to the source signal line is performed for each gate signal line. For this reason, if the line frequency increases as the resolution of the liquid crystal panel increases, it is necessary to quickly switch the signal voltage supplied to the source signal line. That is, the power consumption increases as the line frequency increases, and the heat generation amount of the source drive circuit is increased.

In order to solve these problems, for example, Patent Documents 1 and 2 disclose a technique of performing charge sharing by short-circuiting adjacent source signal lines to reduce power consumption in the source driving circuit. .
JP-A-9-212137 (released on August 15, 1997) JP 2000-39870 A (published February 8, 2000)

  However, in the conventional technique, charge sharing is performed between adjacent source signal lines, so that the movement of charges between the source signal lines is always performed via the source driver. For this reason, since the movement distance of the charge becomes long, the time until charge sharing is completed becomes long. As a result, there arises a problem that charge sharing cannot be performed efficiently.

  In this way, if charge sharing cannot be performed efficiently, a voltage whose polarity is inverted while imperfect charge sharing is applied is applied to the pixel electrode, so that the power necessary for charge charging of the pixel electrode is sufficiently consumed. The problem that it cannot be suppressed to occurs.

  The present invention has been made in view of the above problems, and an object of the present invention is to realize a display device capable of significantly reducing power consumption in a drive circuit by efficiently performing charge sharing.

  In order to solve the above problems, a display device according to the present invention includes a plurality of rows of gate signal lines and a plurality of columns of source signal lines arranged in a matrix, and pixel electrodes at intersections of the gate signal lines and the source signal lines. For the display section formed through the switching elements, the source driving circuit for supplying a signal voltage corresponding to the video signal to the plurality of columns of source signal lines, and the plurality of rows of gate signal lines, A gate driving circuit for supplying a high level signal voltage for turning on the switching element in one horizontal scanning period, and a predetermined period from the beginning of the one horizontal scanning period in the source driving circuit and each source signal line Is a first period in which the gate driving circuit is in an insulated state, and the remaining period is a second period in which a signal voltage is supplied from the source driving circuit to the source signal lines. When a high level signal voltage is supplied to the gate signal line in one horizontal scanning period, at least one of the gate signal lines to be scanned after the gate signal line is A high level signal voltage is supplied in the first period of the one horizontal scanning period.

  According to the above configuration, when a high level signal voltage is supplied to an arbitrary gate signal line in one horizontal scanning period, the gate signal line to be scanned after the gate signal line is By supplying a high level signal voltage in the first period of the one horizontal scanning period, that is, the period in which the source driving circuit and each source signal line are in an insulated state, the gate signal line to be scanned and the next and subsequent scanning objects The switching elements provided in at least one of the gate signal lines to be turned on can be simultaneously turned on.

  As a result, in the first period, charges are transferred between the pixel electrodes connected to the switching elements provided in at least two gate signal lines, so that the potentials of these pixel electrodes are substantially the same. It becomes possible to.

  Accordingly, the voltage for writing to the pixel electrode, that is, the signal voltage supplied to the source signal line can be lowered by the change in the potential of the pixel electrode, so that power consumption in the source driver circuit can be reduced.

  In addition, since the gate signal lines connected to the switching elements that are in the ON state in the first period are short-circuited by the source signal lines connected to the switching elements, the gate signal lines are connected to the respective switching elements. In the pixel electrodes, charge transfer is performed through the gate signal line and the source signal line.

  As a result, the distance of charge movement is shorter than in the case where charge movement is performed via a driver (such as a source driving circuit) as in the prior art, so the resistance value in the charge movement path is reduced, and as a result, the pixel It is possible to efficiently change the potential due to charge transfer in the electrode. That is, charge sharing can be performed efficiently.

  Accordingly, since the time until charge sharing is completed in each pixel electrode can be shortened, it is possible to apply a voltage whose polarity is reversed to the pixel electrode in a state where charge transfer due to charge sharing is sufficient. Less power is required for charging. That is, power consumption in the source drive circuit can be sufficiently reduced.

  When the gate driving circuit supplies a high-level signal voltage to an arbitrary gate signal line in one horizontal scanning period, the gate driving circuit performs the above-described 1 for the next scanning target gate signal line adjacent to the gate signal line. A high level signal voltage may be supplied in the first period of the horizontal scanning period.

  In this case, since charge transfer is performed between adjacent gate signal lines, the transfer distance of charge from one pixel electrode to the other pixel electrode can be minimized. This further reduces the resistance, and as a result, the potential change in the pixel electrode can be performed efficiently.

  The gate driving circuit includes a gate signal generation circuit that generates a gate signal that becomes a high level every horizontal scanning period corresponding to a plurality of gate signal lines, and a current scan generated by the gate signal generation circuit. The gate signal corresponding to the target gate signal line is changed from the gate signal corresponding to the gate signal line that was the target of previous scanning of the gate signal line to a signal voltage that becomes high level in the first period of the one horizontal scanning period. And a signal conversion circuit for conversion.

  In this case, the gate signal generated corresponding to a plurality of gate signal lines and having a high level for each horizontal scanning period is a gate signal when charge sharing is not performed. The gate signal generation circuit can be used.

  In a circuit that generates a signal voltage for charge sharing, that is, a signal conversion circuit, a gate signal corresponding to a gate signal line to be scanned generated by an existing gate signal generation circuit is supplied to the gate signal line. Since the gate signal corresponding to the gate signal line to be pre-scanned is converted into a signal voltage that becomes high level in the first period of the one horizontal scanning period, it is inexpensive and efficient. Charge sharing is possible.

  The source driving circuit may supply a signal voltage whose polarity is inverted every n horizontal scanning periods (n is a natural number) around the reference voltage to the plurality of columns of source signal lines.

  According to the above configuration, since the signal voltage whose polarity is inverted every n horizontal scanning periods around the reference voltage is supplied to the source signal lines in a plurality of columns, the adjacent gate signal lines are connected via the switch elements. Since the connected pixel electrodes have opposite polarities, charge sharing can be performed efficiently. In this case, if a high level signal is applied to the gate signal line every n-1 lines, the polarity is inverted every n horizontal scanning periods with the reference voltage as the center with respect to the source signal lines in a plurality of columns. A signal voltage can be supplied.

  In other words, in the case where the polarity of the pixel electrode is reversed for each row of the display portion, the charge is canceled between the pixel electrodes adjacent in the row direction in the first period. It can be done efficiently.

  Therefore, the present invention can be applied to both dot inversion driving and line inversion driving.

  In order to solve the above-described problem, the display device driving device of the present invention includes a plurality of rows of gate signal lines and a plurality of columns of source signal lines arranged in a matrix, and an intersection of the gate signal lines and the source signal lines. A drive device for a display device comprising a display unit in which pixel electrodes are formed via switching elements, wherein the source drive circuit supplies a signal voltage corresponding to a video signal to the plurality of source signal lines. And a gate driving circuit for supplying a high level signal voltage for turning on the switching element in one horizontal scanning period to the plurality of rows of gate signal lines, and a predetermined level from the beginning of the one horizontal scanning period. The period is a first period in which the source driver circuit and each source signal line are insulated, and the remaining period is a second period in which a signal voltage is supplied from the source driver circuit to each source signal line. When the gate driving circuit supplies a high level signal voltage to an arbitrary gate signal line in one horizontal scanning period, the gate signal line to be scanned after the gate signal line is A high-level signal voltage is supplied to at least one of the gate signal lines in the first period of the one horizontal scanning period.

  Accordingly, it is possible to provide a drive device that can efficiently perform charge sharing and consume less power.

  The television receiver of the present invention is a television receiver including a tuner unit that receives a television broadcast and a display device that displays the television broadcast received by the tuner unit. It is characterized by using a display device.

  In this case, it is possible to provide a television receiver that suppresses power consumption associated with an increase in screen size and resolution.

  Note that the above-described television receiver may be separately provided with a driving device for the display device.

  In the display device according to the present invention, as described above, a predetermined period from the beginning of one horizontal scanning period is a first period in which the source driving circuit and each source signal line are insulated, and the remaining period is In the second period in which a signal voltage is supplied from the source driving circuit to each source signal line, the gate driving circuit supplies a high level signal voltage to an arbitrary gate signal line in one horizontal scanning period. In this case, a high level signal voltage is supplied to at least one of the gate signal lines to be scanned after the gate signal line in the first period of the one horizontal scanning period. Therefore, since the distance of charge transfer is shorter than that in the conventional case where charge transfer is performed via a driver, the resistance value in the charge transfer path is reduced, and as a result, the charge transfer in the pixel electrode is reduced. It can be carried out efficiently potential change due. Therefore, since the time until charge sharing is completed in each pixel electrode can be shortened, it is possible to apply a polarity-inverted voltage to the pixel electrode in a state where charge transfer due to the charge share is sufficient, which is necessary for charge charging. Less power. That is, there is an effect that the power consumption in the source drive circuit can be sufficiently reduced.

  An embodiment of the present invention will be described as follows. Note that in this embodiment, an active matrix liquid crystal display device is described as a display device.

  In the display device according to the present invention, a plurality of rows of gate signal lines and a plurality of columns of source signal lines are wired in a matrix, and pixel electrodes are formed at intersections of the gate signal lines and the source signal lines via switching elements. A display driver; a source driver circuit that supplies a signal voltage corresponding to a video signal to the source signal lines in the plurality of columns; and the switching element in one horizontal scanning period for the gate signal lines in the plurality of rows. And a gate drive circuit for supplying a high level signal voltage for turning on the signal, and a first period in which the source drive circuit and each source signal line are insulated from each other for a predetermined period from the beginning of the one horizontal scanning period. And when the remaining period is a second period in which a signal voltage is supplied from the source driving circuit to the source signal lines, the gate driving circuit is connected to any gate signal line. When a high-level signal voltage is supplied in one horizontal scanning period, at least one gate signal line to be scanned after the gate signal line is applied to the one horizontal scanning period. A high-level signal voltage is supplied in the first period.

  That is, the active matrix liquid crystal display device according to this embodiment includes a display unit 100, a source driving circuit 200 and a gate driving circuit 300 for driving the display unit 100, and these driving circuits as shown in FIG. And a control circuit 400 that controls driving.

  That is, in the active matrix liquid crystal display device having the above structure, a plurality of rows of gate signal lines 111 and a plurality of columns of source signal lines 121 are wired in a matrix, and a pixel is formed at the intersection of the gate signal lines 111 and the source signal lines 121. The display unit 100 in which the electrode 140 is formed through the pixel TFT 130 as a switching element, the source driving circuit 200 that supplies a signal voltage corresponding to the video signal DATA to the source signal lines 121 in the plurality of columns, and the above A gate driving circuit 300 is provided for supplying a high level signal voltage for turning on the pixel TFT 130 in one horizontal scanning period to a plurality of gate signal lines 111.

  That is, in the display unit 100, a source signal line group 120 composed of a plurality of source signal lines 121 and a gate signal line group 110 composed of a plurality of gate signal lines 111 are wired in a matrix, and an intersection of each signal line. In this configuration, a plurality of pixel TFTs 130 are provided.

  The pixel TFT 130 is disposed at each intersection of the source signal line group 120 and the gate signal line group 110, the gate terminal 131 is the gate signal line 111, the source terminal 132 is the source signal line 121, and the drain terminal 133 is the pixel. Each is connected to the electrode 140. The pixel TFT 130 functions as a switching element for electrically connecting the pixel electrode 140 connected to the drain terminal 133 to the source signal line 121 by the potential of the gate signal line 111.

  A video signal DATA for displaying a desired video on the display unit 100 is supplied from the control circuit 400 to the source driving circuit 200.

  The source driving circuit 200 converts the video signal DATA supplied from the control circuit 400 into source signals S1, S2,. . . As (the number of source signal lines), it is supplied to each source signal line 121 of the display unit 100. Here, the source driving circuit 200 supplies each source signal to the source signal line 121 in synchronization with the rise or fall of the source clock signal SCK supplied from the control circuit 400.

  The writing of each source signal to the pixel electrode 140 is controlled by a gate signal supplied from the gate driving circuit 300.

  The gate drive circuit 300 includes a gate signal generation circuit 310 and a signal conversion circuit 320.

  Based on the gate clock signal GSK supplied from the control circuit 400, the gate signal generation circuit 310 generates gate signals G1, G2,. . . (The number of gate signal lines) is supplied to the signal conversion circuit 320 at the subsequent stage. Here, the gate signal generation circuit 310 corresponds to the source signal S-OUT output from the source driving circuit 200 as shown in FIG. 3A, and each gate signal falls on the falling edge of the gate clock signal GSK. The signal conversion circuit 320 is supplied in synchronization with the signal. However, in practice, as shown in FIG. 3B, the source signal S-OUT is in an insulated state between the source drive circuit 200 and the source signal line 121 during charge sharing described later. A period indicating the open state (shaded portion in the figure: first period) is included.

  The signal conversion circuit 320 includes the gate signals G1, G2,. . . Is converted into a waveform (gate signals G1 ′, G2 ′...) For charge sharing and supplied to each gate signal line 111 of the display unit 100. Here, as shown in FIG. 3B, the signal conversion circuit 320 has an adjacent gate corresponding to the open period (shaded portion in the figure) of the source signal S-OUT output from the source drive circuit 200. In the signal line, a gate signal provided with a period of high level simultaneously, that is, a charge share period is supplied to the gate signal line 111.

  That is, in the gate signal generation circuit 310, the source driving circuit 200 and the source signal lines 121 are insulated from each other for a predetermined period from the beginning of one cycle (one horizontal scanning period) of the gate clock signal GCK. When one period (the shaded portion shown in FIG. 3B) is set and the remaining period is a second period for supplying a signal voltage to each of the source signal lines 121, for example, a high level is set in one horizontal scanning period. When supplying the signal voltage to the gate signal line, a high level signal voltage is supplied to the gate signal line to be scanned after the gate signal line in the first period of the one horizontal scanning period. It has become.

  The signal conversion circuit 320 can be realized by a logic circuit as shown in FIG. That is, the signal conversion circuit 320 includes an OR gate 321, an AND gate 322, and a delay circuit 323. In the signal conversion circuit 320, the gate signal G (n) ′ output to the n-th gate signal line 111 is used as the gate corresponding to the n−1-th gate signal line 111 supplied from the gate signal generation circuit 310. It is generated from the signal G (n−1) and the gate signal G (n) corresponding to the n-th gate signal line 111. Here, the delay time in the delay circuit 323, that is, the delay time becomes the pulse width of the charge share (charge share section (FIG. 3B)).

  Therefore, in the logic circuit configured as described above, the charge share interval can be freely adjusted by adjusting the delay time in the delay circuit 323.

  Here, the charge share will be described below.

  In this description, the case where the display unit 100 performs dot inversion driving will be described. In the dot inversion driving, the polarity of each row in the display unit 100 is opposite between adjacent pixel electrodes as shown in FIG.

  For example, if a signal voltage having a waveform as shown in FIG. 3B is supplied to the (n−1) th gate signal line and the nth gate signal line adjacent to the gate signal line, the charge is generated. The switching element connected to each gate signal line is turned on in the share period (first period). In this charge share section, as shown in FIG. 3B, the source drive circuit 200 and each source signal line 121 are in an insulated state, so that the pixel electrode connected to the switching element in the on state. The charge moves through the source signal line 121 between them. At this time, as shown in FIG. 4, since the polarities of the adjacent pixel electrodes are reversed, the charges in each pixel electrode are canceled and the absolute value of the potential of each pixel electrode becomes substantially the same.

  Thereby, during the next scanning, the signal voltage for charging the pixel electrode may be low, so that the power consumption in the source driving circuit 200 can be greatly reduced.

  In addition, since charge sharing is performed between the gate signal lines, the charge transfer path becomes the gate signal line 111, the source signal line 121, and the gate signal line 111, and passes through the gate driving circuit 300 or the source driving circuit 200. I don't have to. As a result, the resistance value in the path of charge transfer can be reduced, so that charge transfer is performed quickly. That is, charge sharing is performed efficiently.

  Thereby, after the charge share is sufficiently performed and the potential is sufficiently changed, a signal voltage having a reverse polarity is supplied, so that writing to the pixel electrode can be performed with a low voltage.

  Furthermore, generally, as shown in FIG. 5, if the charge share time is long, the amount of heat generation tends to be small. Here, the charge sharing time is an execution time for charge sharing. In order to increase the execution time, it is only necessary to increase the number of lines opened simultaneously, that is, the number of gate signal lines targeted for charge sharing.

  The gate driving circuit 300 generates a gate signal that becomes a high level every horizontal scanning period corresponding to the gate signal lines 111 in a plurality of rows, and the gate signal generation circuit 310 generates the gate signal. The gate signal G (n) corresponding to the gate signal line 111 to be scanned is changed from the gate signal G (n−1) corresponding to the gate signal line 111 to be scanned before the gate signal line 111, A signal conversion circuit 320 that converts the signal voltage G (n) ′ to a high level in the first period of the one horizontal scanning period.

  In this case, since the generated gate signal corresponding to a plurality of rows of gate signal lines becomes a high level for each horizontal scanning period is a gate signal when charge sharing is not performed, an existing gate signal generation circuit is used. A gate signal generation circuit can be used.

  In a circuit that generates a signal voltage for charge sharing, that is, a signal conversion circuit, a gate signal corresponding to a gate signal line to be scanned generated by an existing gate signal generation circuit is supplied to the gate signal line. Since the gate signal corresponding to the gate signal line to be pre-scanned is converted into a signal voltage that becomes high level in the first period of the one horizontal scanning period, it is inexpensive and efficient. Charge sharing is possible.

  The source driving circuit may supply a signal voltage whose polarity is inverted every n horizontal scanning periods (n is a natural number) around the reference voltage to the plurality of columns of source signal lines.

  According to the above configuration, since the signal voltage whose polarity is inverted every n horizontal scanning periods around the reference voltage is supplied to the source signal lines in a plurality of columns, the adjacent gate signal lines are connected via the switch elements. Since the connected pixel electrodes have opposite polarities, charge sharing can be performed efficiently. In this case, if a high level signal is applied to the gate signal line every n-1 lines, the polarity is inverted every n horizontal scanning periods with the reference voltage as the center with respect to the source signal lines in a plurality of columns. A signal voltage can be supplied.

  In other words, in the case where the polarity of the pixel electrode is reversed for each row of the display portion, the charge is canceled between the pixel electrodes adjacent in the row direction in the first period. It can be done efficiently.

  Therefore, the present invention can be applied to line inversion driving in addition to dot inversion driving as shown in FIG.

  Further, the display device having the above structure can be used for a display portion of a television receiver.

  A television receiver to which the display device of the present invention is applied will be described below with reference to FIGS.

  FIG. 6 shows a circuit block of a liquid crystal display device 601 for a television receiver.

As shown in FIG. 6, the liquid crystal display device 601 includes a Y / C separation circuit 500, a video chroma circuit 501, an A / D converter 502, a liquid crystal controller 503, a liquid crystal panel 504, a backlight drive circuit 505, a backlight 506, a microcomputer. 507 and a gradation circuit 508 are provided.

  As the liquid crystal display device 601 having the above structure, the active matrix liquid crystal display device described in the above embodiment is used.

  In the liquid crystal display device 601 having the above configuration, first, an input video signal of a television signal is input to the Y / C separation circuit 500 and separated into a luminance signal and a color signal. The luminance signal and the color signal are converted into R, G, and B which are the three primary colors of light by the video chroma circuit 501, and the analog RGB signal is converted into a digital RGB signal by the A / D converter 502, and the liquid crystal Input to the controller 503.

  In the liquid crystal panel 504, RGB signals from the liquid crystal controller 503 are input at a predetermined timing, and RGB gradation voltages from the gradation circuit 508 are supplied to display an image. The microcomputer 507 controls the entire system including these processes.

  Video signals are displayed based on various video signals such as video signals based on television broadcasts, video signals captured by cameras, video signals supplied via the Internet, video signals recorded on DVDs, etc. Is possible.

  Furthermore, the tuner unit 600 shown in FIG. 7 receives a television broadcast and outputs a video signal, and the liquid crystal display device 601 displays an image (video) based on the video signal output from the tuner unit 600.

  When the liquid crystal display device having the above configuration is a television receiver, for example, as shown in FIG. 8, the liquid crystal display device 601 is sandwiched between a first housing 1301 and a second housing 1306. It has a configuration.

  The first housing 1301 has an opening 1301a through which an image displayed on the liquid crystal display device 601 is transmitted.

  The second housing 1306 covers the back side of the liquid crystal display device 601. An operation circuit 1305 for operating the liquid crystal display device 601 is provided, and a support member 1308 is attached below. ing.

  As described above, by using the display device of the present invention for the liquid crystal display device 601, it is possible to provide a television receiver that suppresses an increase in power consumption associated with an increase in screen size and resolution.

  Note that the above-described television receiver may be separately provided with a driving device for the display device.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  Since the display device of the present invention can perform charge sharing efficiently, it is suitable for a large-screen, high-resolution display device in which an increase in power consumption is a problem.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a liquid crystal display device. FIG. FIG. 2 is a logic circuit diagram of a signal conversion circuit provided in the liquid crystal display device shown in FIG. 1. (A) is a waveform diagram of a gate signal generated by a gate signal generation circuit provided in the liquid crystal display device shown in FIG. 1, and (b) is a signal conversion circuit provided in the liquid crystal display device shown in FIG. It is a wave form diagram of the generated gate signal. It is a figure which shows the polarity of the pixel electrode of a display part. It is a graph which shows the relationship between charge share time and the emitted-heat amount. It is a schematic block diagram of the television receiver provided with the liquid crystal display device of this invention. It is a block diagram which shows the relationship between the tuner part and liquid crystal display device in the television receiver shown in FIG. It is a disassembled perspective view of the television receiver shown in FIG.

Explanation of symbols

100 Display Unit 110 Gate Signal Line Group 111 Gate Signal Line 120 Source Signal Line Group 121 Source Signal Line 1301 First Housing 1301a Opening 1305 Operation Circuit 1306 Second Housing 1308 Support Member 131 Gate Terminal 132 Source Terminal 133 Drain Terminal 140 Pixel electrode 200 Source drive circuit 300 Gate drive circuit 310 Gate signal generation circuit 320 Signal conversion circuit 321 OR gate 322 AND gate 323 Delay circuit 400 Control circuit 500 Y / C separation circuit 501 Video chroma circuit 502 A / D converter 503 Liquid crystal Controller 504 Liquid crystal panel 505 Crite drive circuit 506 Backlight 507 Microcomputer 508 Gradation circuit 600 Tuner unit 601 Liquid crystal display device

Claims (7)

A display unit in which a plurality of rows of gate signal lines and a plurality of columns of source signal lines are wired in a matrix, and a pixel electrode is formed via a switching element at an intersection of the gate signal line and the source signal line;
A source driving circuit for supplying a signal voltage corresponding to a video signal to the plurality of source signal lines;
A gate driving circuit for supplying a high level signal voltage for turning on the switching element in one horizontal scanning period with respect to the plurality of gate signal lines;
A predetermined period from the beginning of the one horizontal scanning period is a first period in which the source driving circuit and each source signal line are insulated, and the remaining period is a signal from the source driving circuit to each source signal line. When the second period for supplying voltage is set,
The gate drive circuit is
When a high level signal voltage is supplied to an arbitrary gate signal line in one horizontal scanning period, at least one gate signal line among the gate signal lines to be scanned after the gate signal line A high-level signal voltage is supplied during the first period of the one horizontal scanning period. The gate drive circuit is
When a high level signal voltage is supplied to an arbitrary gate signal line in one horizontal scanning period, the first scanning signal in the first horizontal scanning period is applied to the gate signal line to be next scanned adjacent to the gate signal line. 2. The display device according to claim 1, wherein a high-level signal voltage is supplied during a period. The gate drive circuit is
A gate signal generation circuit that generates a gate signal that becomes a high level every horizontal scanning period in correspondence with a plurality of gate signal lines;
The gate signal corresponding to the gate signal line that is the current scanning target generated by the gate signal generation circuit is changed from the gate signal corresponding to the gate signal line that was the previous scanning target of the gate signal line to the one horizontal scanning period. The display device according to claim 2, further comprising: a signal conversion circuit that converts the signal voltage to a high level during the first period. The source drive circuit is
4. A signal voltage whose polarity is inverted every n horizontal scanning periods (n is a natural number) with a reference voltage as a center is supplied to the plurality of columns of source signal lines. The display device according to item. A display device comprising a display unit in which a plurality of rows of gate signal lines and a plurality of columns of source signal lines are wired in a matrix, and pixel electrodes are formed at intersections of the gate signal lines and the source signal lines via switching elements. Drive device
A source driving circuit for supplying a signal voltage corresponding to a video signal to the plurality of columns of source signal lines;
A gate driving circuit for supplying a high level signal voltage for turning on the switching element in one horizontal scanning period with respect to the plurality of gate signal lines;
A predetermined period from the beginning of the one horizontal scanning period is a first period in which the source driving circuit and each source signal line are insulated, and the remaining period is a signal from the source driving circuit to each source signal line. When the second period for supplying voltage is set,
The gate drive circuit is
When a high level signal voltage is supplied to an arbitrary gate signal line in one horizontal scanning period, the gate signal line to be scanned after the gate signal line is applied to at least one of the gate signal lines. A high-level signal voltage is supplied during the first period of the one horizontal scanning period.   The television receiver provided with the tuner part which receives a television broadcast, and the display apparatus of any one of Claims 1-4 which displays the television broadcast received by this tuner part. A television receiver according to claim 6;
A television receiving system having a driving device for driving a display device of the television receiver,
The television receiving system according to claim 5, wherein the driving device is a driving device for a display device according to claim 5.

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