JP2008042372A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with small noise sensitivity capable of suppressing a sampling dependent period of a sampling/hold error to a small value and realizing a highly accurate and stable sampling/hold. <P>SOLUTION: At a sample/hold circuit 9, resistors 10 and 11 are connected to both assistant joints of a transistor 12, respectively, and a capacitor 13 is connected between a joint of another side of the resistor 11 and standard potential VSS. Since the resistors 10 and 11 are connected to both joints of the transistor 12 respectively as described, both of an input signal Vin side and a capacitor 13 side have a time constant of (Cg(: back gate capacity of the transistor 12)/2×R) during extraction and insertion of electron charge when the transistor 12 is turned on, and a hold offset voltage ΔVhoff is set to qg/2Csh. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analog signal sample / hold technique, and more particularly to a technique effective for highly accurate sample / hold processing in an optical disc apparatus.

  2. Description of the Related Art An optical disc device exemplified by a DVD (Digital Versatile Disc) drive is provided with a semiconductor integrated circuit device for front-end processing.

  This type of semiconductor integrated circuit device extracts a signal read from an optical disc by analog signal processing. In this front-end processing, various sample / hold circuits that sample and hold an input signal in an RF (Radio Frequency) band are widely used.

  In recent years, with the widespread use of optical disk devices, it has become essential to support playback and recording at high speeds. To realize these high speed playback and recording, a high-speed and high-precision sample-and-hold circuit is required. Necessary.

  In general, the sample / hold circuit is composed of a MOS (Metal Oxide Semiconductor) transistor that functions as a switch and a capacitance element, or a configuration in which a resistance is added to the MOS transistor and the capacitance element. and so on.

  In the case of the MOS transistor and the capacitive element, one connection portion of the MOS transistor is connected so that an input signal read from the optical pickup is inputted. A capacitance element is connected between the other connection portion of the MOS transistor and the reference potential VSS, and the other connection portion of the MOS transistor becomes an output portion of a sampling signal of the sample / hold circuit.

  In the case of a sample / hold circuit in which a resistance is added to the MOS transistor and the capacitive element, an input portion to which an input signal read from the optical pickup is inputted and one connection portion of the MOS transistor And a configuration in which a resistor is connected while the other connection portion of the MOS transistor and one connection portion of the capacitance element are connected. Yes.

  However, the present inventor has found that the circuit configuration using the sample / hold circuit as described above has the following problems.

  In the case of a sample / hold circuit composed of a MOS transistor and a capacitance element, there is a problem that a sampling / hold error due to noise increases because of high noise sensitivity during sampling.

  In addition, in the sample / hold circuit with a resistance added to the MOS transistor and the capacitance element, the hold state output voltage and the sampling start that are generated when the MOS transistor is switched from OFF (hold state) to ON (sampling start). The difference between the sampling offset voltage, which is the difference (offset) from the output voltage, and the difference between the sampling state output voltage and the hold start output voltage that occurs when the MOS transistor switches from ON (sampling state) to OFF (hold start) Since the hold offset voltage which is (offset) is not the same, there is a problem that the sampling / hold error increases when the sampling period is shortened.

  An object of the present invention is to provide a technique capable of realizing highly accurate and stable sampling / holding by suppressing the sampling dependency period of the sampling / holding error to a low level with low noise sensitivity.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a transistor that performs a switching operation, a capacitance element that is a sample capacitor, and an offset voltage limiter that substantially equalizes the hold offset voltage and the sampling offset voltage regardless of the sampling period. It has a sample / hold circuit provided.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device according to the present invention, the offset voltage limiting unit has a first resistor in which an input signal is input to one connection unit, and one connection unit of the transistor is connected to the other connection unit, A second connection portion in which the other connection portion of the transistor is connected to one connection portion, the other connection portion serves as an output portion of the sample / hold circuit, and a capacitance element is connected between the other connection portion and the reference potential. It consists of resistance.

  In the semiconductor integrated circuit device according to the present invention, the sample / hold circuit is used for analog front-end processing of an optical disk device.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The sampling-dependent period of the sampling / hold error can be greatly reduced, and the sampling / hold variation can be greatly suppressed.

  (2) According to the above (1), by using a semiconductor integrated circuit device configured using a sample / hold circuit for an optical disk device, recording and reproduction can be stably performed at a high speed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration of a sample / hold circuit provided in the semiconductor integrated circuit device of FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing the relationship between the sampling period and the sampling offset voltage / hold offset voltage in the sample / hold circuit of FIG. 2, and FIG. 4 shows the sampling period and the sampling offset voltage / hold offset voltage in the sample / hold circuit examined by the present inventors. FIG. 5 is an explanatory diagram showing another example of the relationship between the sampling period and the sampling offset voltage / hold offset voltage in the sample / hold circuit studied by the present inventors.

  In the present embodiment, the semiconductor integrated circuit device 1 is an analog front that generates various signals necessary for drive control such as a reproduction signal and a servo signal from a signal read from an optical disk in an optical disk device exemplified by a DVD drive. Used for end processing.

  As shown in FIG. 1, the semiconductor integrated circuit device 1 includes an interface 2, an RF (Radio Frequency) system circuit 3, a wobble / various detection circuit 4, a servo system circuit 5, and an APC (Auto Laser Power Control) circuit 6. Has been.

  The interface 2 is an interface with the pickup 7 and receives a signal read from the pickup 7 provided in the optical disc apparatus. The pickup 7 irradiates an optical disk such as a DVD disk that is rotationally driven with laser light, receives the reflected light by a light receiving unit made of a photodiode, optically converts it, and reads information stored on the optical disk.

  An RF system circuit 3, a wobble / various detection circuit 4, a servo system circuit 5, and an APC circuit 6 are connected to the interface 2, respectively. Further, a DSP (Digital Signal Processor) 8 for performing digital signal processing provided in the subsequent stage is connected to the RF system circuit 3, the wobble / various detection circuit 4, the servo system circuit 5, and the APC circuit 6.

  The RF system circuit 3 generates a reproduction signal from the RF band signal and outputs the reproduction signal to the DSP 8. The wobble / various detection circuit 4 detects wobbles, disc scratches and defects, recorded / unrecorded portions, etc., and outputs the detection results to the DSP 8.

  The servo system circuit 5 performs various calculations for controlling the positions of the pickup 7 and the lens, and outputs the calculation results to the DSP 8. The APC circuit 6 detects the reproduction / recording laser power and feeds it back to the pickup 7 or outputs it to the DSP 8.

  FIG. 2 is a circuit diagram showing a configuration example of the sample / hold circuit 9 provided in the servo system circuit 5 and the APC circuit 6.

  As shown in the figure, the sample / hold circuit 9 includes resistors 10 and 11, a transistor 12, and a capacitance element 13 serving as a sample capacitor.

  The input signal Vin is input to one connection portion of the resistor 10, and one connection portion of the MOS transistor 12 is connected to the other connection portion of the resistor 10. One connection portion of the resistor 11 is connected to the other connection portion of the transistor 12, and one connection portion of the capacitance element 13 is connected to the other connection portion of the resistor 11.

  Further, the reference potential VSS is connected to the other connection portion of the capacitance element 13, and the other connection portion of the resistor 11 to which one connection portion of the capacitance element 13 is connected is a sample / hold. It becomes an output part from which the output signal Vout of the circuit 9 is output.

  The output signal Vout output from the sample / hold circuit 9 is input to a servo arithmetic circuit or the like connected to the subsequent stage in the servo system circuit 5, and the GPC (Gain Control) that performs gain adjustment connected to the subsequent stage in the APC circuit 6. Amp) and the like.

  Next, the operation of the sample / hold circuit 9 in the present embodiment will be described.

  First, the dependency of the sampling / hold error in the sample / hold circuit 9 on the sampling period will be described.

  The sampling period dependency of the sampling / hold error occurs when the sampling offset voltage and the hold offset voltage are not the same.

  When the transistor 12 is turned on (starts sampling) or turned off (starts hold), the sampling offset voltage and hold offset voltage are the same as the gate of the transistor 12 (vs. the back gate capacitance Cg, which is the parasitic capacitance of the gate of the transistor 12). It is generated by inserting / removing electric charge to / from the sample capacitor Csh of the capacitive element 13.

  Consider the case where the input signal Vin is DC and has a fixed potential. If the charge accumulated in the back gate capacitance Cg at the time of sampling (transistor 12 is ON) is qg, the gate generation is canceled when the transistor 12 is turned OFF. The charge insertion / extraction with respect to Csh is qg / 2 (the remaining qg / 2 is insertion / extraction with respect to the input signal Vin side).

As a result, the hold offset voltage ΔVhoff is
ΔVhoff = qg / 2Csh
It becomes.

On the other hand, when the transistor 12 is turned on, the insertion / extraction of charges to / from the back gate capacitance Cg is started simultaneously from the input signal Vin side and the capacitance element 13 side. Therefore, if the charge insertion / extraction to the back gate capacitance Cg is equal to qg / 2 on the input signal Vin side and the capacitance element 13 side, the sampling offset voltage ΔVsoff is
ΔVsoff = qg / 2Csh
Thus, the sampling offset voltage and the hold offset voltage are equal.

  In the sample / hold circuit 9, the resistors 10 and 11 are connected to both connection portions of the transistor 12. Therefore, when the transistor 12 is turned on, the input signal Vin and the capacitance element 13 side are connected. Both have a time constant of (Cg / 2 × R), and the hold offset voltage ΔVhoff = qg / 2Csh can be obtained as described above.

  Therefore, the hold offset voltage and the sampling offset voltage can be made equal regardless of the sampling period, and as shown in FIG. 3, it is possible to prevent the offset voltage from being accumulated even if the sampling / holding is repeated. it can.

  For example, as described in the background art, in a sample / hold circuit in which a resistor is provided only in one of the preceding stage and the succeeding stage of a transistor, the insertion / extraction of electric charges when the transistor is turned on causes the input signal Vin side ( Or on the sample capacitor side), it has a time constant constituted by the back gate capacitor Cg and the resistance, and the sampling offset voltage ΔVsoff = qg / 2Csh is not obtained, and the sampling offset voltage and the hold offset voltage are not equal. It will be.

  When the sampling offset voltage and the hold offset voltage are not equal, the offset difference ΔVhoff−ΔVsoff must be sampled with the time constant of the sampling period (Csh × R) after the hold, and when the sampling period is (Csh × R) If the constant is insufficient, the portion that cannot be sampled remains as an offset voltage, and as shown in FIGS. 4 and 5, the offset voltage is accumulated by repeating sampling / holding. .

  On the other hand, in the sample / hold circuit 9, as described above, the hold offset voltage and the sampling offset voltage can be made equal by setting the hold offset voltage ΔVhoff = qg / 2Csh.

  Thereby, according to the present embodiment, the sampling-dependent period of the sampling / hold error can be significantly reduced, so that the sampling / hold variation in the sample / hold circuit 9 can be greatly suppressed.

  In addition, recording and reproduction in the optical disc apparatus can be stably performed at a high speed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the sample / hold circuit is used in the semiconductor integrated circuit device for analog front end processing is described. However, the present invention is not limited to the semiconductor integrated circuit device for analog front end processing. The present invention can be applied to all semiconductor integrated circuit devices having a hold circuit.

  FIG. 6 is a block diagram showing a connection configuration example of the sample / hold circuit 9, and FIG. 7 shows an example of an A / D (Analog / Digital) converter 14 configured using the sample / hold circuit 9. FIG.

  In FIG. 6, a buffer B is connected to the subsequent stage of the sample / hold circuit 9, and an analog signal output from the sample / hold circuit 9 is output via the buffer B.

  In FIG. 7, an A / D converter ADC is connected to the subsequent stage of the sample / hold circuit 9, and an analog signal output from the sample / hold circuit 9 is input to the A / D converter ADC. It is converted into a digital signal by the converter ADC. The digital signal output from the A / D converter ADC becomes the output of the A / D converter 14.

  The present invention is suitable for a technique for reducing sampling period dependency and sampling / hold variation in a sample / hold circuit.

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a sample / hold circuit provided in the semiconductor integrated circuit device of FIG. 1. FIG. 3 is an explanatory diagram showing a relationship between a sampling period and a sampling offset voltage / hold offset voltage in the sample / hold circuit of FIG. 2. It is explanatory drawing which shows an example of the relationship between the sampling period and sampling offset voltage / hold offset voltage in the sample / hold circuit which this inventor examined. It is explanatory drawing which shows the other example of the relationship between the sampling period in the sample / hold circuit which this inventor examined, and the sampling offset voltage / hold offset voltage. It is the block diagram which showed the example of a connection of the sample / hold circuit by other embodiment of this invention. It is the block diagram which showed the structural example of the A / D converter comprised using the sample / hold circuit by other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Interface 3 RF system circuit 4 Wobble / various detection circuit 5 Servo system circuit 6 APC circuit 7 Pickup 8 DSP
9 Sample / Hold Circuits 10, 11 Resistor 12 Transistor 13 Capacitance Element 14 A / D Converter B Buffer

Claims (3)

A transistor that performs a switching operation;
A capacitance element that is a sample capacity;
What is claimed is: 1. A semiconductor integrated circuit device comprising a sample / hold circuit including an offset voltage limiter that makes a hold offset voltage and a sampling offset voltage substantially equal regardless of a sampling period. The semiconductor integrated circuit device according to claim 1.
The offset voltage limiter is
An input signal is input to one connection portion, and the first connection to which one connection portion of the transistor is connected to the other connection portion;
The other connection portion of the transistor is connected to one connection portion, the other connection portion is an output portion of the sample / hold circuit, and the capacitance element is connected between the other connection portion and a reference potential. A semiconductor integrated circuit device comprising the second resistor. The semiconductor integrated circuit device according to claim 1 or 2,
The sample / hold circuit includes:
A semiconductor integrated circuit device used for analog front-end processing of an optical disk device.

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