JP2008042179A - Light-emitting element, light-emitting device, and method of fabricating the light-emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting device which has ample luminance, high reliability, and low fabrication cost. <P>SOLUTION: The method of fabricating a semiconductor device includes the steps of forming a first electrode, a light-emitting layer containing zinc sulfide and manganese on the first electrode, and forming a second electrode on the light-emitting layer; and after the formation of the light-emitting layer, applying thermal treatment to the light-emitting layer. The manganese atoms in the zinc sulfide lattice is at a symmetric and nonequilibrium lattice position during the film formation, but has atomic positions which are stable in terms of energy, after undergoing thermal treatment. A light-emitting device, subjected to a thermal treatment, has luminance higher than that of a light-emitting device not subjected to a thermal treatment, and also can suppress the luminance deterioration. Furthermore, while a light-emitting device that is not subjected to the thermal treatment emits only a monochromatic light, a light-emitting device subjected to the thermal treatment can easily obtain color-mixed light. Thus, a light-emitting device with low production cost can be fabricated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a light-emitting material of a light-emitting element using electroluminescence. The present invention relates to a light-emitting element using electroluminescence. In addition, the present invention relates to a light-emitting device and an electronic device each having a light-emitting element.

  In recent years, research and development of light-emitting elements (hereinafter also referred to as “EL elements”) using electroluminescence have been actively conducted. The basic structure of the light-emitting element is that a light-emitting substance is sandwiched between a pair of electrodes, and light is emitted from the light-emitting substance by applying a voltage between both electrodes.

  Such a light-emitting element is self-luminous and has a wider viewing angle and better visibility than a liquid crystal display. In addition, the light-emitting element has a high response speed and can be reduced in thickness and weight. It has been broken.

  As light-emitting elements, organic EL elements using organic compounds and inorganic EL elements using inorganic compounds are known as light-emitting substances that exhibit electroluminescence.

  The organic EL element and the inorganic EL element differ not only in the light emitting material but also in the light emission mechanism.

  Inorganic EL elements are classified into a dispersion type and a thin film type according to the element configuration. The former has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the latter has a light-emitting layer made of a thin film of the light-emitting material. It is common in the point that requires. Note that the obtained light emission mechanism includes donor-acceptor recombination light emission using a donor level and an acceptor level, and localized light emission using inner-shell electron transition of a metal ion.

  Among these, as shown in FIG. 2, the thin-film inorganic EL element has an insulating film (a first insulating film 1502 and a second insulating film 1504) between a pair of electrodes (a first electrode 1501 and a second electrode 1505). ) Between the electrodes (the first electrode 1501 and the second electrode 1505), and the respective power sources (first power source 1506, second power source). Light emission is obtained by applying a voltage from 1507). The first insulating film 1502 and the second insulating film 1504 formed between the electrodes in the inorganic EL element are considered to be important elements. For example, in order to increase the light emission luminance of the inorganic EL element, a device for appropriately maintaining the capacitance ratio formed by the first insulating film and the second insulating film has been devised (see Patent Document 1).

In order to improve the reliability of the inorganic EL element, it is considered to devise a method for forming the first insulating film 1502 and the second insulating film 1504 used as dielectric films (see Patent Document 2). .
JP 2001-250691 A JP 2004-31422 A

  However, even if the insulating film sandwiched between the electrodes is improved, it has been difficult to obtain high reliability while maintaining practical light emission luminance. Therefore, an object of the present invention is to obtain a light-emitting element having sufficient luminance and high reliability and a light-emitting device using the light-emitting element.

  The present invention is a light emitting device having a light emitting layer containing zinc sulfide and manganese, wherein the light emitting layer has an emission spectrum in a wavelength range of 500 nm to 700 nm, and the emission spectrum is shorter than a wavelength of 580 nm. And a second peak on the longer wavelength side than the wavelength of 580 nm.

  The present invention also includes a light emitting layer containing zinc sulfide and manganese, the light emitting layer has an emission spectrum in a wavelength range of 500 nm to 700 nm, and the emission spectrum is a first wavelength shorter than a wavelength of 580 nm. And a driving circuit that controls light emission of the light-emitting element. The light-emitting device includes: a light-emitting element having a second peak at a wavelength longer than 580 nm;

  The present invention also includes a step of forming a light emitting layer containing zinc sulfide and manganese having an emission spectrum having a single emission peak in a wavelength range of 500 nm to 700 nm, and the emission spectrum having the one emission peak is converted to a wavelength of 580 nm. And a step of heat-treating the light-emitting layer so as to have a first peak on the shorter wavelength side and a second peak on the longer wavelength side than the wavelength of 580 nm. It is.

  The gist of the present invention is that the symmetry of the atomic arrangement of the impurity element added to the base light emitting material is changed after the light emitting layer is formed. In the manufacturing method of the present invention, after forming the light emitting layer by including the impurity element in the base light emitting material, in order to change the symmetry of the atomic arrangement of the impurity element, energy is applied to the light emitting layer to form an atomic structure. A process for inducing changes is performed.

  According to the present invention, it is possible to obtain a light-emitting element in which the luminance change with time is reduced while the emission luminance is increased. In particular, light emission characteristics in the visible light region can be stabilized. In addition, since the emission spectrum can be broadened and changed to mixed color emission, it can be applied to various applications.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  This embodiment will be described with reference to FIGS. 1, 3, 4, 5, and 10. FIG.

  The light-emitting element described in this embodiment includes a first electrode 101 and a second electrode 105 over a substrate 100 as illustrated in FIG. 4, and includes a first electrode 101 and a second electrode 105. A light emitting layer 103 is interposed therebetween, a first dielectric layer 102 is provided between the first electrode 101 and the light emitting layer 103, and a second dielectric is provided between the light emitting layer 103 and the second electrode 105. The body layer 104 is included.

  Note that the structure of the light-emitting element is not limited to that illustrated in FIG. 4, and the light-emitting element may have only one of the first dielectric layer 102 and the second dielectric layer 104. Note that in this embodiment, description is made below on the assumption that the first electrode 101 functions as an anode and the second electrode 105 functions as a cathode.

  The substrate 100 is used as a support for the light emitting element. As the substrate 100, for example, glass, quartz, or the like can be used. Note that other materials can be used as long as the light-emitting element functions as a support in the manufacturing process.

  For the first electrode 101 and the second electrode 105, a metal, an alloy, a conductive compound, a mixture thereof, or the like can be used. Specifically, for example, indium tin oxide (Indium Tin Oxide (ITO)), indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (also referred to as Indium Zinc Oxide (also referred to as IZO)), oxidation, and the like. Examples thereof include indium oxide containing tungsten and zinc oxide.

  These conductive metal oxide films are formed by a sputtering method, an ion plating method, or the like. For example, indium zinc oxide (IZO) can be formed by sputtering using a target in which 1 to 20 wt% of zinc oxide is added to indium oxide. Indium oxide containing tungsten oxide and zinc oxide can be formed by sputtering using a target containing 0.5 to 5 wt% tungsten oxide and 0.1 to 1 wt% zinc oxide with respect to indium oxide. In addition, aluminum (Al), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt ( Co), copper (Cu), palladium (Pd), or a nitride of a metal material (for example, titanium nitride) can be used.

  Note that in the case where the first electrode 101 or the second electrode 105 is a light-transmitting electrode, the thickness is about 1 nm to 50 nm, preferably about 5 nm to 20 nm, even if the material has low visible light transmittance. By forming the film, it can be used as a translucent electrode. In addition to sputtering, an electrode can also be produced using vacuum deposition, CVD, or a sol-gel method.

Note that light emission is extracted to the outside through the first electrode 101 or the second electrode 105; therefore, at least one of the first electrode 101 and the second electrode 105 is formed using a light-transmitting material. Need to be. The material is preferably selected so that the first electrode 101 has a higher work function than the second electrode 105.

  In the case where both the first electrode 101 and the second electrode 105 are formed using a light-transmitting material, the light-emitting device including the light-emitting element of this embodiment is a dual emission light-emitting device. In the case where either the first electrode 101 or the second electrode 105 is formed using a reflective material, the light-emitting device having the light-emitting element of this embodiment mode is a single-sided light-emitting device (top emission). Type light emitting device or bottom emission type light emitting device).

  In this embodiment, as the first electrode 101, an indium tin oxide film containing silicon oxide is formed by a sputtering method. As the second electrode 105, an aluminum film is formed by a sputtering method.

  The material forming the light-emitting layer 103 includes an inorganic material such as sulfide that is a base material of the light-emitting layer and an impurity element that serves as a light emission center.

  When zinc sulfide (ZnS) is used as the base material and manganese (Mn) is used as the impurity element, part of Zn in the base material, ZnS, is replaced with Mn, which is the emission center.

  In this embodiment, a ZnS target containing 0.5 wt% of Mn is used, and sputtering gas is argon (Ar), and ZnS containing Mn by sputtering (hereinafter also referred to as “ZnS: Mn”) is 500 nm thick. It will be formed.

The material forming the dielectric layer 102 and the dielectric layer 104 is an inorganic material such as nitride or oxide. In this embodiment, silicon nitride dielectric layers 102 and 104 having a thickness of 200 nm are formed by a sputtering method using silicon (Si) as a target and nitrogen (N ₂ ) as a sputtering gas.

After forming the dielectric layer 104, heat treatment is performed. Here, the dependency of the luminance of the ZnS: Mn EL element on the heat treatment time is described. The EL spectrum was measured while flowing nitrogen (N ₂ ) under conditions where the heat treatment time at 600 ° C. after forming the ZnS: Mn film was 5 minutes, 15 minutes, 30 minutes, and 240 minutes. FIG. 1 shows the EL spectrum heat treatment time dependency.

  From FIG. 1, one yellow (588 nm) peak is observed without heat treatment (heat treatment 0 minutes), but when the heat treatment is performed for 5 minutes, the yellow emission spectrum peaks are green and orange. It can be seen that it splits into two emission spectrum peaks near the (Orange) boundary. Furthermore, two emission spectrum peaks are observed in the same manner in a sample subjected to heat treatment for 240 minutes (4 hours).

  One possible cause of the splitting of the emission spectrum peak due to heat treatment is that the symmetry of the atomic arrangement of Mn atoms entering the ZnS lattice changes.

The crystal structure of ZnS includes a zinc zinc structure (cubic crystal) and a wurtzite structure (hexagonal crystal), and generally has a zinc zinc structure. The ionic bond is strong, and Zn atoms in the ZnS lattice are ion-bonded as Zn ²⁺ and S atoms as S ²⁻ .

Both outermost electrons of Zn atoms and Mn atoms are 4S ² , and when Mn is added to ZnS, the Mn atoms are substituted with Zn in the ZnS lattice and become ionic as Mn ²⁺ .

The ionization energy of Mn atoms (171 kcal / mol) is smaller than the ionization energy of Zn atoms (216 kcal / mol), and tends to be positive ions. Therefore, the binding force with S ²⁻ ions is larger in Mn ²⁺ than in Zn ²⁺ . Furthermore, since the atomic radius of Mn atoms (0.117 nm) is smaller than the atomic radius of Zn atoms (0.125 nm), it can be displaced from the normal lattice position.

  From the above, the Mn atom substituted with the Zn atom in the ZnS lattice is displaced from the normal lattice position so as to approach the S atom while being separated from the Zn atom in order to stabilize in energy. At the time of sputtering film formation, as shown in FIG. 3A, the Mn atoms in the ZnS lattice are in non-equilibrium symmetrical lattice positions. Thus, the symmetry is deteriorated and the crystal lattice is distorted.

  When Mn atoms receive energy (deformation potential) resulting from distortion of the crystal lattice, the degeneracy of atomic orbital energy of Mn atoms is dissolved and split.

  As a result, as shown in FIG. 5, there are two paths of electronic excitation and relaxation, transition A and transition B, so the peak of the emission spectrum is considered to be split into two.

  The fact that the emission spectrum has two peaks in this manner means that yellow (Yellow) monochromatic light before the emission spectrum peak split, but green (Green) and orange (Orange) after heat treatment. ). According to the present embodiment, monochromatic light can be easily mixed color light. For this reason, white light can be easily produced.

In addition, the luminance of a light-emitting element including a light-emitting layer that was not subjected to heat treatment and a light-emitting element including a light-emitting layer that was subjected to heat treatment were compared (see Table 1). As a result, the luminance of the light-emitting element including the light-emitting layer that was not subjected to heat treatment was 800 cd / m ² , whereas the luminance of the light-emitting element including the light-emitting layer that was subjected to heat treatment increased to 1600 cd / m ² . .

  FIG. 10 shows luminance deterioration of a light-emitting element including a light-emitting layer subjected to heat treatment. As shown in FIG. 10, it can be seen that the luminance degradation of the light emitting element of the present invention is very small.

  As described above, a light-emitting element in which a change in luminance with time is reduced can be obtained in a state where the luminance is increased. In particular, light emission characteristics in the visible light region can be stabilized. In addition, since the emission spectrum can be broadened and changed to mixed color emission, it can be applied to various applications. Accordingly, a light-emitting device with high reliability and low cost can be manufactured.

(Embodiment 2)
In this embodiment mode, a light-emitting device including the light-emitting element of the present invention will be described with reference to FIGS.

  The light-emitting device described in this embodiment is a passive matrix light-emitting device that drives a light-emitting element without providing a driving element such as a transistor over the same substrate as the light-emitting element. 6A is a perspective view of a passive matrix light-emitting device manufactured by applying the present invention, and FIG. 6B is a partial cross-sectional view taken along line XY in FIG. 6A. Indicates.

  6A and 6B, a layer 955 is provided over the substrate 951 between the electrode 952 and the electrode 956. Note that the layer 955 includes a light-emitting layer using ZnS as the base material described in Embodiment 1 and a light-emitting material using Mn as a light emission center.

  An end portion of the electrode 952 is covered with an insulating layer 953. A partition layer 954 is provided over the insulating layer 953. The side wall of the partition wall layer 954 has an inclination such that the distance between one side wall and the other side wall becomes narrower as it approaches the substrate surface. That is, the cross section in the short side direction of the partition wall layer 954 has a trapezoidal shape, and the bottom side (the side facing the insulating layer 953 in the same direction as the surface direction of the insulating layer 953) is the top side (the surface of the insulating layer 953). The direction is the same as the direction and is shorter than the side not in contact with the insulating layer 953. In this manner, by providing the partition layer 954, defects in the light-emitting element due to static electricity or the like can be prevented. A passive matrix light-emitting device can also be driven with low power consumption by providing the light-emitting element of the present invention that operates at a low drive voltage. In addition, the partition layer 954 having a shape as illustrated in FIGS. 6A and 6B is provided, whereby the layer 955 and the second electrode 956 can be formed in a self-aligning manner.

  Although the structure of one light-emitting element is described in this embodiment mode, the dielectric layer is formed on the electrode without being bound by the structure, and the layer including the light-emitting layer is a stacked layer of a p-type semiconductor and an n-type semiconductor. It may be structured. Furthermore, a layer in contact with the layer including the light emitting layer as well as the light emitting layer can be provided as in the function separation type light emitting element of the organic EL element. As a layer in contact with the layer including the light emitting layer, it functions as a carrier injection layer or a carrier transport layer, improving the orientation of the light emitting layer.

  According to the present embodiment, it is possible to obtain a light emitting element in which the luminance change with time is reduced while the emission luminance is increased as in the first embodiment. In particular, light emission characteristics in the visible light region can be stabilized. In addition, since the emission spectrum can be broadened and changed to mixed color emission, it can be applied to various applications.

  In addition, since the light emitting device of the present invention can easily generate mixed color light, it is easy to obtain white light. In addition, since luminance degradation is small, a highly reliable light-emitting device can be obtained.

(Embodiment 3)
In this embodiment, a light-emitting device having a light-emitting element and a manufacturing method thereof are described with reference to FIGS. 7A to 7B, FIGS. 11A to 11D, and FIGS. (C), FIG. 13 (A) to FIG. 13 (B), FIG. 14 and FIG. 15 (A) to FIG. 15 (B) will be described in detail below.

  7A and 7B are diagrams illustrating one embodiment of a light-emitting device of the present invention. 7A is a top view of the light-emitting device of the present invention, and FIG. 7B is a cross-sectional view. 7A illustrates a region where the FPC 694 and the thin film transistor wiring are electrically connected (hereinafter referred to as an external terminal connection region 702a). 7A illustrates a region where the FPC 694 and the first electrode layer of the light-emitting element are electrically connected (hereinafter, referred to as an external terminal connection region 702b).

  7A is a cross-sectional view taken along line AB in FIG. 7A, and FIGS. 15A and 15B are cross-sectional views taken along line CD in FIG. 7A. 7B, FIGS. 11A to 11D, FIGS. 12A to 12C, and FIGS. 13A to 13B are manufactured. This will be described with reference to FIG.

  Note that a thin film transistor (TFT) includes a semiconductor layer, a gate insulating layer, and a gate electrode layer as main components, and a wiring layer connected to a source region and a drain region formed in the semiconductor layer. Accompanying it. Structurally, the top gate type in which the semiconductor layer, the gate insulating layer and the gate electrode layer are arranged from the substrate side, and the bottom gate type in which the gate electrode layer, the gate insulating layer and the semiconductor layer are arranged from the substrate side are representative. In the present invention, any of those structures may be used.

  As the substrate 600, a glass substrate, a quartz substrate, a silicon substrate, or a metal substrate (for example, a stainless steel substrate) on which an insulating film is formed may be used. When light emitted from the light-emitting element is extracted through the substrate, a light-transmitting substrate such as a glass substrate or a quartz substrate is desirable. Since the glass substrate is deformed when the temperature is higher than 800 ° C., it is preferable to use a quartz substrate or a sapphire substrate when the temperature for heat treatment of the light emitting layer is higher.

  In addition, when light emitted from the light emitting element is not extracted through the substrate and light is extracted to the TFT element side to be formed in a later step, a substrate that does not transmit light can be used. Specifically, alumina, silicon nitride And ceramic substrates such as silicon carbide.

  In addition, when a light emitting element having a TFT element is formed on a substrate provided with a release layer and then the light emitting element is peeled from the substrate and used, there is no particular limitation on the light transmittance of the substrate. Examples thereof include glass, quartz, alumina, silicon nitride, silicon carbide, and a ceramic substrate.

  As a base film over the substrate 600 having an insulating surface, oxygen is included by sputtering, PVD (Physical Vapor Deposition), low pressure CVD (LPCVD), or CVD (Chemical Vapor Deposition) such as plasma CVD. A base film 601a is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm) using a silicon nitride film (also referred to as SiNO), and a base film 601b is formed to a thickness of 50 to 200 nm (also referred to as SiON) using a silicon oxide film containing nitrogen (also referred to as SiON). Preferably 100 to 150 nm).

  In this embodiment, the base film 601a and the base film 601b are formed by a plasma CVD method.

As the base film, silicon oxide, silicon nitride, silicon oxide containing nitrogen, silicon nitride containing oxygen, or the like can be used, and a single layer or a laminated structure of two layers or three layers may be used. Note that in this specification, silicon oxide containing nitrogen is a substance in which the composition ratio of oxygen is larger than the composition ratio of nitrogen. Similarly, silicon nitride containing oxygen is a substance in which the composition ratio of nitrogen is larger than the composition ratio of oxygen. In this embodiment mode, a silicon nitride film containing oxygen is formed on a substrate using SiH ₄ , NH ₃ , N ₂ O, N _2, and H ₂ as reaction gases to a thickness of 50 nm, and SiH ₄ and N ₂ O are used as reaction gases. A silicon oxide film containing nitrogen is formed with a thickness of 100 nm. The thickness of the silicon nitride film containing oxygen may be 140 nm, and the thickness of the silicon oxide film containing nitrogen to be stacked may be 100 nm.

  Next, a first electrode layer 802 is formed. As the first electrode layer 802, in the case where light emitted from the light-emitting element is extracted to the substrate side, a transparent conductive film made of a light-transmitting conductive material may be used. Indium tin oxide (ITO) Indium Zinc Oxide (IZO), indium oxide containing tungsten oxide and zinc oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like can be used.

The first electrode layer 802 can be formed by an evaporation method, a sputtering method, or the like. In the case of using a sputtering method, moisture (water vapor (H ₂ O)) or a gas containing H ₂ may be used as a gas. In this embodiment, as the first electrode layer 802, an indium zinc oxide target containing tungsten oxide to which silicon oxide is added is used, and moisture (H ₂ O) or a gas containing H ₂ is used. An indium zinc oxide film containing silicon oxide and tungsten oxide is formed by a sputtering method.

  In this embodiment, 10 wt% of silicon oxide is added to indium zinc oxide containing tungsten oxide. The first electrode layer 802 is preferably used with a total thickness of 100 nm to 800 nm, and in this embodiment mode, has a thickness of 185 nm.

In this embodiment, argon (Ar) is formed using a gas having a flow rate of 50 sccm, oxygen (O ₂ ) is 1.0 sccm, and H ₂ O gas is 0.2 sccm. The gas containing moisture (water vapor (H ₂ O)) used in the present invention does not contain a slight amount of moisture depending on the production method, storage method, etc., but actively contains moisture as one of the main components. Gas. The H ₂ O gas is preferably 0.5 sccm or less. The indium zinc oxide film containing silicon oxide and tungsten oxide formed in this embodiment mode has favorable workability and can be etched without residue by wet etching with a weak acid. When such a film is used for a pixel electrode of a display device, a light-emitting element can have high light extraction efficiency, and a highly reliable display device in which defects due to electrode etching defects or the like are suppressed can be manufactured.

  In the case where light is extracted only to the TFT element side, the first electrode layer 802 can be a multi-layer or single-layer reflective electrode made of a metal film having excellent heat resistance.

  The first electrode layer 802 may be formed by stacking a first conductive film with a thickness of 20 to 100 nm and a second conductive film with a thickness of 100 to 400 nm.

  The conductive film has an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), copper (Cu), chromium (Cr), and neodymium (Nd), or the element as a main component. It may be formed of an alloy material or a compound material.

  Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used.

  Moreover, it is not limited to a single layer structure, It is good also as a 2 layer structure and a 3 layer structure.

  Next, a resist mask may be formed using a photolithography method, and the first electrode layer 802 may be processed into a desired shape (see FIG. 15A).

ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to substrate-side electrode layer, substrate-side electrode temperature, etc.) By appropriately adjusting, etching can be performed to have a desired taper shape. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , CF ₅ , SF ₆ or NF _3, or O _{2 is used.} Can be used as appropriate.

  Next, after forming the first dielectric layer, the light emitting layer 804 is formed. The method for forming the first dielectric layer and the light emitting layer 804 is the same as that described in the first and second embodiments.

  The material forming the light-emitting layer 804 includes an inorganic material such as sulfide, which is a base material of the light-emitting layer, and an impurity element serving as a light emission center.

  When zinc sulfide (ZnS) is used as the base material and manganese (Mn) is used as the impurity element, part of Zn in the base material, ZnS, is replaced with Mn, which is the emission center.

  Further, the light-emitting layer 804 does not have to be a single layer of a base material layer containing an impurity element serving as a light emission center, and may have a stacked structure with a layer functioning as a carrier transport layer, for example. Specifically, a p-type semiconductor layer or an n-type semiconductor layer may be stacked.

  As a method for finely processing the light-emitting layer 804 into a desired shape, a conventional photolithography method or lift-off method in which a pattern is formed with a photoresist and unnecessary portions are removed by etching can be used.

  After the light emitting layer 804 is laminated on the first electrode layer 802 in this way, a second dielectric layer is formed, and then heated at 500 ° C. to 800 ° C., for example, 600 ° C. As a result, the emission spectrum of the light emitting layer 804 was a light emitting layer in which only one yellow (588 nm) peak was observed without heating, but because of the heat treatment, a shorter wavelength side than the wavelength of 580 nm. And a second peak on the longer wavelength side than the wavelength of 580 nm, that is, two peaks in the vicinity of the boundary between green and orange. That is, the emission spectrum after the heat treatment is distributed within a wavelength range of 500 nm to 700 nm, and has a first peak on the shorter wavelength side than the wavelength 580 nm and a second peak on the longer wavelength side than the wavelength 580 nm. Yes. Note that if the light emitting layer 804 is heated to a high temperature, for example, 900 ° C. or higher, light emission is not observed. This is considered to be because zinc sulfide is oxidized. Therefore, the temperature of the heat treatment may be, for example, 600 ° C., preferably 500 ° C. to 800 ° C.

  Next, an insulating layer 803 functioning as a partition is formed over the light-emitting layer. As the insulating layer 803 functioning as a partition wall, silicon oxide, silicon nitride, silicon oxide containing nitrogen, silicon nitride containing oxygen, aluminum nitride (AlN), aluminum oxide containing nitrogen whose oxygen content is higher than the nitrogen content (AlON) ), Aluminum nitride (AlNO) or aluminum oxide containing oxygen with a nitrogen content higher than the oxygen content, diamond-like carbon (DLC), carbon film containing nitrogen (CN), PSG (phosphorus glass), BPSG (phosphorus boron) Glass), alumina film, and other materials including inorganic insulating materials.

  As a method for forming the insulating layer 803 functioning as a partition wall, dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like can be employed. The insulating layer 803 functioning as a partition wall may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. In addition, a method that can transfer or depict a pattern, such as a droplet discharge method, for example, a printing method (a method of forming a pattern such as screen printing or offset printing) can be used.

  Next, as illustrated in FIGS. 7B and 11A, an opening is formed in the insulating layer 803 functioning as a partition wall. The insulating layer 803 functioning as a partition wall is etched in the pixel portion. Further, as shown in FIGS. 7B, 15A, and 15B, the external electrode connection regions 702a and 702b in which the first electrode layer 802 is connected to the connection terminals are etched over a wide area. There is a need to.

  For the etching, a parallel plate RIE apparatus or an ICP etching apparatus can be used. Note that the etching time is preferably set such that the wiring layer and the first electrode are over-etched. When the over-etching is performed as described above, it is possible to reduce the film thickness variation in the substrate and the etching rate variation. In this way, openings are formed in the external terminal connection regions 702a and 702b, respectively.

  In this embodiment mode, the case where the insulating layer 803 functioning as a partition wall is etched using a mask in which predetermined openings are provided in the external terminal connection regions 702a and 702b and the pixel region 706 has been described. It is not limited. For example, since the opening of the connection region has a large area, the etching amount is large. Such a wide-area opening may be etched a plurality of times. Further, in the case where a deep opening is formed as compared with other openings, etching may be performed a plurality of times in the same manner.

  Next, a second electrode layer 805 is formed over the light emitting layer 804. The second electrode layer 805 is in contact with a source electrode or a drain electrode of a TFT to be formed later.

  A conductive film used as the second electrode layer 805 (also referred to as a pixel electrode layer) over the light-emitting layer 804 is tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper ( An element selected from Cu), chromium (Cr), neodymium (Nd), or an alloy material or compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used.

  The second electrode layer 805 is not limited to a single layer structure, and may have a two-layer structure or a three-layer structure.

  In the case where the second electrode layer 805 is formed using a reflective conductive film, light emitted from the light-emitting element is extracted to the substrate side. In the case where the second electrode layer 805 is formed using a transparent conductive film, light emitted from the light-emitting element is extracted to the substrate side and the sealing substrate side, that is, both surfaces.

  In this embodiment mode, tungsten (W) is formed to a thickness of 370 nm as the conductive film. Next, a resist mask is formed by photolithography, so that the second electrode layer 805 is formed (see FIG. 11A).

ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to substrate-side electrode layer, substrate-side electrode temperature, etc.) By appropriately adjusting the thickness, the second electrode layer 805 can be formed by etching the conductive film so as to have a desired tapered shape. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , CF ₅ , SF ₆ or NF _3, or O _{2 is used.} Can be used as appropriate.

  Next, a first interlayer insulating layer 806 is formed. As the first interlayer insulating layer 806, silicon oxide, silicon nitride, silicon oxide containing nitrogen, silicon nitride containing oxygen, aluminum nitride (AlN), aluminum oxide containing nitrogen whose oxygen content is higher than the nitrogen content (AlON) ), Aluminum nitride (AlNO) or aluminum oxide containing oxygen with a nitrogen content higher than the oxygen content, diamond-like carbon (DLC), carbon film containing nitrogen (CN), PSG (phosphorus glass), BPSG (phosphorus boron) Glass), alumina film, and other materials including inorganic insulating materials.

  As a method for manufacturing the first interlayer insulating layer 806, dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like can be employed. The first interlayer insulating layer 806 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. In addition, a method that can transfer or depict a pattern, such as a droplet discharge method, for example, a printing method (a method of forming a pattern such as screen printing or offset printing) can be used.

  Next, as illustrated in FIGS. 7B and 11B, an opening is formed in the first interlayer insulating layer 806. The first interlayer insulating layer 806 needs to be etched over a wide area in a connection region (not shown), a wiring region 703, an external terminal connection region 702a, and the like. However, in the pixel region 706, the opening area is very small and fine compared to the opening area of the connection region or the like. Therefore, by providing a photolithography process for forming an opening in the pixel region 706 and a photolithography process for forming an opening in the connection region, a margin for etching conditions can be further widened. As a result, the yield can be improved. Further, since the margin of the etching condition is widened, the contact hole formed in the pixel region 706 can be formed with high accuracy.

  Specifically, a wide-area opening is formed in the first interlayer insulating layer 806 provided in part of the connection region, the wiring region 703, the external terminal connection region 702a, and the peripheral driver circuit region 704. Therefore, a mask is formed so as to cover the pixel region 706, part of the connection region, and part of the insulating layer 806 in the peripheral driver circuit region 704. For the etching, a parallel plate RIE apparatus or an ICP etching apparatus can be used. Note that the etching time may be set so that the insulating layer functioning as the second electrode or the partition wall is over-etched. When the over-etching is performed as described above, it is possible to reduce the film thickness variation in the substrate and the etching rate variation. In this way, an opening is formed in the external terminal connection region 702a.

  Next, a semiconductor film is formed over the first interlayer insulating layer 806. The semiconductor film may be formed by means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). A material for forming a semiconductor film is an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane, and the amorphous material. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter also referred to as “SAS”) semiconductor can be used.

  SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain.

Here, as an impurity element mainly taken in at the time of film formation, impurities derived from atmospheric components such as oxygen, nitrogen, and carbon are preferably 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor film.

An example of the semi-amorphous semiconductor is semi-amorphous silicon. In semi-amorphous silicon, a crystal region of 0.5 to 20 nm can be observed at least in a part of the film, and when silicon is a main component, the Raman spectrum has a lower wave number than 520 cm ^−1. Shift to the side. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more.

Semi-amorphous silicon is formed by glow discharge decomposition (plasma CVD) of a gas containing silicon. As a gas containing silicon, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Further, F ₂ and GeF ₄ may be mixed. The gas containing silicon may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C.

  It is preferable to use a semiconductor film obtained by crystallizing an amorphous semiconductor film by laser crystallization.

In laser crystallization, a solid-state laser capable of continuous oscillation is used, and a crystal having a large grain size can be obtained by irradiating laser light of the second to fourth harmonics of the fundamental wave. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec).

  The laser beam shape is preferably linear. As a result, throughput can be improved. Further, the laser may be irradiated with an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor film. This is because laser interference can be prevented.

  Laser irradiation can be performed by relatively scanning such a laser and the semiconductor film. In laser irradiation, a marker can be formed in order to superimpose beams with high accuracy and to control the laser irradiation start position and laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor film.

As the laser, a continuous wave or pulsed gas laser, solid state laser, copper vapor laser, gold vapor laser, or the like can be used. Examples of the gas laser include an excimer laser, an Ar laser, a Kr laser, and a He—Cd laser, and the solid laser includes a YAG laser, a YVO ₄ laser, a YLF laser, a YAlO ₃ laser, a Y ₂ O ₃ laser, a glass laser, and a ruby laser. Alexandrite laser, Ti: sapphire laser, and the like.

  Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens of nanoseconds to several hundred nanoseconds. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction of the included crystal grains and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, a semiconductor film having almost no crystal grain boundary at least in the channel direction of the thin film transistor can be formed.

  Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Thus, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values of thin film transistors caused by variations in interface state density can be suppressed.

  Next, the crystalline semiconductor film 602 is processed into a desired shape using a mask. In this embodiment mode, after the oxide film formed over the crystalline semiconductor film 602 is removed, a new oxide film is formed. Then, a photomask is manufactured, and the semiconductor layer 603, the semiconductor layer 604, the semiconductor layer 605, and the semiconductor layer 606 are formed by etching treatment using a photolithography method.

The etching process may be either plasma etching (dry etching) or wet etching, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

  In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, a process for controlling wettability and adhesion may be performed on the formation region. In addition, a method capable of transferring or drawing a pattern, for example, a printing method (a method of forming a pattern such as screen printing or offset printing) can be used.

  In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. Also, benzocyclobutene, parylene, fluorinated arylene ether, organic materials such as permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers Etc. can also be used. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. In the case of using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are adjusted as appropriate by adjusting the concentration of the solvent or adding a surfactant or the like.

  The oxide film over the semiconductor layers 603 to 606 is removed, and the semiconductor layer 603, the semiconductor layer 604, the semiconductor layer 605, and the gate insulating layer 607 that covers the semiconductor layer 606 are formed. The gate insulating layer 607 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method, a sputtering method, or the like.

  The gate insulating layer 607 may be formed using a material such as silicon nitride, silicon oxide, silicon oxide containing nitrogen, or an oxide or nitride material of silicon typified by silicon nitride containing oxygen. But you can. The insulating layer may be a three-layer stack of a silicon nitride film, a silicon oxide film, and a silicon nitride film, a single layer of a silicon oxide film containing nitrogen, or a layer in which two layers of the above materials are stacked. A silicon nitride film having a dense film quality is preferably used. Further, a thin silicon oxide film with a thickness of 1 to 100 nm, preferably 1 to 10 nm, more preferably 2 to 5 nm may be formed between the semiconductor layer and the gate insulating layer. As a method for forming a thin silicon oxide film, a thin silicon oxide film can be formed by oxidizing the surface of the semiconductor region using a GRTA method, an LRTA method, or the like to form a thermal oxide film. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film. In this embodiment, a silicon oxide film containing nitrogen is formed as the gate insulating layer 607 with a thickness of 115 nm.

  Next, a first conductive film 608 with a thickness of 20 to 100 nm and a second conductive film 609 with a thickness of 100 to 400 nm used as a gate electrode layer are stacked over the gate insulating layer 607 (FIG. 11 ( B)). The first conductive film 608 and the second conductive film 609 can be formed by a method such as a sputtering method, an evaporation method, or a CVD method. The first conductive film 608 and the second conductive film 609 include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and neodymium. An element selected from (Nd) or an alloy material or compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film 608 and the second conductive film 609. The structure is not limited to a two-layer structure. For example, a tungsten film with a thickness of 50 nm is used as the first conductive film, an aluminum-silicon alloy (Al-Si) film with a thickness of 500 nm is used as the second conductive film, The conductive film may have a three-layer structure in which titanium nitride films with a thickness of 30 nm are sequentially stacked. In the case of a three-layer structure, a tungsten nitride film may be used instead of the tungsten film of the first conductive film, or an aluminum-silicon alloy (Al-Si) film of the second conductive film is used. An alloy film of aluminum and titanium (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient. In this embodiment, tantalum nitride is formed to a thickness of 30 nm as the first conductive film 608 and tungsten (W) is formed to a thickness of 370 nm as the second conductive film 609.

Next, a resist mask 610a, a mask 610b, a mask 610d, a mask 610e, and a mask 610f are formed by photolithography, and the first conductive film 608 and the second conductive film 609 are processed into desired shapes. The first gate electrode layer 621, the first gate electrode layer 622, the first gate electrode layer 624, the first gate electrode layer 625, the first gate electrode layer 626, the conductive layer 611, and the conductive layer 612, a conductive layer 614, a conductive layer 615, and a conductive layer 616 are formed (see FIG. 11C).

ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to substrate-side electrode layer, substrate-side electrode temperature, etc.) Is adjusted as appropriate so that the first gate electrode layer 621, the first gate electrode layer 622, the first gate electrode layer 624, the first gate electrode layer 625, the first gate electrode layer 626, and the conductive layer The layer 611, the conductive layer 612, the conductive layer 614, the conductive layer 615, and the conductive layer 616 can be etched to have a desired tapered shape. Further, the taper shape can be controlled in angle and the like by the shapes of the mask 610a, the mask 610b, the mask 610d, the mask 610e, and the mask 610f. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , CF ₅ , SF ₆ or NF _3, or O _{2 is used.} Can be used as appropriate. In this embodiment mode, the second conductive film 609 is etched using an etching gas composed of CF ₅ , Cl ₂ , and O ₂ , and then continuously etched using an etching gas composed of CF ₅ and Cl ₂ . One conductive film 608 is etched.

  Next, the conductive layer 611, the conductive layer 612, the conductive layer 614, the conductive layer 615, and the conductive layer 616 are processed into desired shapes using the mask 610a, the mask 610b, the mask 610d, the mask 610e, and the mask 610f. At this time, the conductive layer is etched under an etching condition with a high selection ratio between the second conductive film 609 that forms the conductive layer and the first conductive film 608 that forms the first gate electrode layer. By this etching, the conductive layer 611, the conductive layer 612, the conductive layer 614, the conductive layer 615, and the conductive layer 616 are etched, and the second gate electrode layer 631, the second gate electrode layer 632, and the second gate electrode layer are etched. 634, a second gate electrode layer 635, and a second gate electrode layer 636 are formed.

In this embodiment mode, the second gate electrode layer also has a tapered shape, and the taper angles thereof are the first gate electrode layer 621, the first gate electrode layer 622, and the first gate electrode layer 624. , Larger than the taper angle of the first gate electrode layer 625 and the first gate electrode layer 626. Note that the taper angle is an angle of a side surface of each of the first gate electrode layer and the second gate electrode layer with respect to the surface of the conductive layer. Therefore, when the taper angle is increased and the angle is 90 degrees, the conductive layer has a vertical side surface. In this embodiment mode, Cl ₂ , SF ₆ , and O ₂ are used as an etching gas for forming the second gate electrode layer.

  In this embodiment, since the first gate electrode layer, the conductive layer, and the second gate electrode layer are formed to have a tapered shape, both of the two gate electrode layers have a tapered shape. However, the present invention is not limited thereto, and only one gate electrode layer may have a tapered shape, and the other may have a vertical side surface by anisotropic etching. As in this embodiment, the taper angle may be different between the stacked gate electrode layers, or may be the same. By having a tapered shape, the coverage of a film stacked thereon is improved and defects are reduced, so that reliability is improved.

  Through the above steps, the peripheral driver circuit region 704 includes the gate electrode layer 617 including the first gate electrode layer 621 and the second gate electrode layer 631, the first gate electrode layer 622, and the second gate electrode layer 632. The gate electrode layer 618 includes a gate electrode layer 627 including a first gate electrode layer 624 and a second gate electrode layer 634, and a gate electrode including a first gate electrode layer 625 and a second gate electrode layer 635. A gate electrode layer 629 including the layer 628, the first gate electrode layer 626, and the second gate electrode layer 636 can be formed (see FIG. 11D). In this embodiment mode, the gate electrode layer is formed by dry etching, but may be wet etching.

  The gate insulating layer 607 may be slightly etched by an etching process when forming the gate electrode layer, and the film thickness may be reduced (so-called film reduction).

  When forming the gate electrode layer, a thin film transistor capable of high-speed operation can be formed by reducing the width of the gate electrode layer. Two methods for forming the gate electrode layer with a narrow width in the channel direction are described below.

  In the first method, after a mask for the gate electrode layer is formed, the mask is narrowed in the width direction by etching, ashing, or the like to form a mask with a narrower width. By using a mask formed in advance in a narrow shape, the gate electrode layer can also be formed in a narrow shape.

  Next, in the second method, a normal mask is formed, and a gate electrode layer is formed using the mask. Next, the obtained gate electrode layer is further thinned by side etching in the width direction. Therefore, a narrow gate electrode layer can be finally formed. Through the above steps, a thin film transistor with a short channel length can be formed later, and a thin film transistor capable of high-speed operation can be manufactured.

  Next, the mask 610a, the mask 610b, the mask 610d, the mask 610e, and the mask 610f are removed, and the gate electrode layer 617, the gate electrode layer 618, the gate electrode layer 627, the gate electrode layer 628, and the gate electrode layer 629 are used as masks. An impurity element 651 imparting n-type conductivity is added, and the first n-type impurity region 640a, the first n-type impurity region 640b, the first n-type impurity region 641a, the first n-type impurity region 641b, and the first N-type impurity region 642a, first n-type impurity region 642b, first n-type impurity region 642c, first n-type impurity region 643a, and first n-type impurity region 643b are formed (FIG. 12A). )reference).

In this embodiment, phosphine (PH ₃ ) (doping gas is PH ₃ diluted with hydrogen (H ₂ ), and the ratio of PH _{3 in} the gas is 5%) is used as a doping gas containing an impurity element. Doping is performed at a gas flow rate of 80 sccm, a beam current of 54 μA / cm, an acceleration voltage of 50 kV, and an added dose of 7.0 × 10 ¹³ ions / cm ² . Here, the first n-type impurity region 640a, the first n-type impurity region 640b, the first n-type impurity region 641a, the first n-type impurity region 641b, the first n-type impurity region 642a, the first In the n-type impurity region 642b, the first n-type impurity region 642c, the first n-type impurity region 643a, and the first n-type impurity region 643b, an impurity element imparting n-type conductivity is 1 × 10 ^{17 to} 5 ×. It is added so as to be contained at a concentration of about 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  In this embodiment mode, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is a Loff region. In FIG. 12, hatching and white background are shown in the impurity region, but this does not indicate that the impurity element is not added to the white background portion, but the concentration distribution of the impurity element in this region is mask or doping. This is because it is possible to intuitively understand that the conditions are reflected. This also applies to other drawings in this specification.

  Next, a mask 653a, a mask 653b, a mask 653c, and a mask 653d which cover the semiconductor layer 603, part of the semiconductor layer 605, and the semiconductor layer 606 are formed. An n-type impurity element 652 is added using the mask 653a, the mask 653b, the mask 653c, the mask 653d, and the second gate electrode layer 632 as a mask, and the second n-type impurity region 644a and the second n-type impurity region are added. 644b, a third n-type impurity region 645a, a third n-type impurity region 645b, a second n-type impurity region 647a, a second n-type impurity region 647b, a second n-type impurity region 647c, a third An n-type impurity region 648a, a third n-type impurity region 648b, a third n-type impurity region 648c, and a third n-type impurity region 648d are formed.

In this embodiment, PH ₃ (doping gas is PH ₃ diluted with hydrogen (H ₂ ) and the ratio of PH _{3 in} the gas is 5%) is used as a doping gas containing an impurity element, and the gas flow rate is 80 sccm. Doping is performed with a beam current of 540 μA / cm, an acceleration voltage of 70 kV, and a dose of 5.0 × 10 ¹⁵ ions / cm ² to be added. Here, the second n-type impurity region 644a and the second n-type impurity region 644b are added so that the impurity element imparting n-type is included at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. To do. The third n-type impurity region 645a and the third n-type impurity region 645b include a third n-type impurity region 648a, a third n-type impurity region 648b, a third n-type impurity region 648c, and a third n-type impurity region 648a. It is formed so as to contain an impurity element imparting n-type at a concentration similar to or slightly higher than that of the type impurity region 648d. In addition, a channel formation region 646 is formed in the semiconductor layer 604, and a channel formation region 649a and a channel formation region 649b are formed in the semiconductor layer 605.

  The second n-type impurity region 644a, the second n-type impurity region 644b, the second n-type impurity region 647a, the second n-type impurity region 647b, and the second n-type impurity region 647c are high-concentration n-type impurities. A region that functions as a source region or a drain. On the other hand, the third n-type impurity region 645a, the third n-type impurity region 645b, the third n-type impurity region 648a, the third n-type impurity region 648b, the third n-type impurity region 648c, and the third The n-type impurity region 648d is a low-concentration impurity region, and becomes an LDD (Lightly Doped Drain) region.

  The third n-type impurity region 645a and the third n-type impurity region 645b are Lov regions because they are covered with the first gate electrode layer 622 through the gate insulating layer 607, and the electric field in the vicinity of the drain is reduced. It is possible to relax and suppress deterioration of on-current due to hot carriers. As a result, a thin film transistor capable of high speed operation can be formed. On the other hand, the third n-type impurity region 648a, the third n-type impurity region 648b, the third n-type impurity region 648c, and the third n-type impurity region 648d are covered with the gate electrode layer 627 and the gate electrode layer 628. Since it is not a Loff region, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection and to reduce the off current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

  Next, the mask 653a, the mask 653b, the mask 653c, and the mask 653d are removed, and a mask 655a and a mask 655b that cover the semiconductor layer 604 and the semiconductor layer 605 are formed. An impurity element 654 imparting p-type conductivity is added using the mask 655a, the mask 655b, the gate electrode layer 617, and the gate electrode layer 629 as a mask, and the first p-type impurity region 660a, the first p-type impurity region 660b, and the first P-type impurity region 663a, first p-type impurity region 663b, second p-type impurity region 661a, second p-type impurity region 661b, second p-type impurity region 664a, second p-type impurity region 664b is formed.

In this embodiment, since boron (B) is used as the impurity element, diborane (B ₂ H ₆ ) (doping gas is obtained by diluting B ₂ H ₆ with hydrogen (H ₂ ) as a doping gas containing the impurity element. The ratio of B ₂ H ₆ in the gas is 15%), and doping is performed at a gas flow rate of 70 sccm, a beam current of 180 μA / cm, an acceleration voltage of 80 kV, and a dose of 2.0 × 10 ¹⁵ ions / cm ² to be added. Here, the first p-type impurity region 660a, the first p-type impurity region 660b, the first p-type impurity region 663a, the first p-type impurity region 663b, the second p-type impurity region 661a, the second The p-type impurity region 661b, the second p-type impurity region 664a, and the second p-type impurity region 664b contain an impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Add as required.

  In this embodiment, the second p-type impurity region 661a, the second p-type impurity region 661b, the second p-type impurity region 664a, and the second p-type impurity region 664b include the gate electrode layer 617 and the gate electrode. Reflecting the shape of the layer 629, the concentration is lower than that of the first p-type impurity region 660a, the first p-type impurity region 660b, the first p-type impurity region 663a, and the first p-type impurity region 663b in a self-aligned manner. It forms so that it becomes. In addition, a channel formation region 662 is formed in the semiconductor layer 603, and a channel formation region 665 is formed in the semiconductor layer 606.

  The first p-type impurity region 660a, the first p-type impurity region 660b, the first p-type impurity region 663a, and the first p-type impurity region 663b are high-concentration n-type impurity regions and serve as a source region or a drain. Function. On the other hand, the second p-type impurity region 661a, the second p-type impurity region 661b, the second p-type impurity region 664a, and the second p-type impurity region 664b are low-concentration impurity regions, and are LDD (Lightly Doped Drain). ) Area. The second p-type impurity region 661a, the second p-type impurity region 661b, the second p-type impurity region 664a, and the second p-type impurity region 664b are connected to the first gate electrode through the gate insulating layer 607. Since it is covered with the layer 621 and the first gate electrode layer 626, it is a Lov region, and an electric field in the vicinity of the drain can be relaxed and deterioration of on-current due to hot carriers can be suppressed.

The masks 655a and 655b are removed by O ₂ ashing or resist stripping solution, and the oxide film is also removed. After that, an insulating film, so-called sidewall, may be formed so as to cover the side surface of the gate electrode layer. The sidewall can be formed using an insulating film containing silicon by a plasma CVD method or a low pressure CVD (LPCVD) method.

  In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

  Next, an interlayer insulating layer is formed to cover the gate electrode layer and the gate insulating layer. In this embodiment, a stacked structure of the insulating film 667 and the insulating film 668 is employed (see FIG. 13A). A silicon nitride film containing oxygen is formed as the insulating film 667 with a thickness of 100 nm, and a silicon oxide film containing nitrogen is formed as the insulating film 668 with a thickness of 900 nm, so that a stacked structure is obtained. Further, a silicon oxide film containing nitrogen is formed to a thickness of 30 nm, a silicon nitride film containing oxygen is formed to a thickness of 140 nm, and a silicon oxide film containing nitrogen is formed to a thickness of 800 nm so as to cover the gate electrode layer and the gate insulating layer. And it is good also as a laminated structure of 3 layers.

  In this embodiment mode, the insulating film 667 and the insulating film 668 are continuously formed by a plasma CVD method as in the case of the base film. The insulating film 667 and the insulating film 668 are not limited to the above materials, and may be a silicon nitride film using sputtering or plasma CVD, a silicon nitride film containing oxygen, a silicon oxide film containing nitrogen, or a silicon oxide film. Other insulating films containing silicon may be used as a single layer or a stacked structure of three or more layers.

  In addition, as the insulating films 667 and 668, aluminum nitride (AlN), aluminum oxide containing nitrogen having an oxygen content higher than the nitrogen content (AlON), and nitriding containing oxygen having a nitrogen content higher than the oxygen content It can be formed of a material selected from aluminum (AlNO) or aluminum oxide, diamond-like carbon (DLC), a carbon film containing nitrogen (CN), and other substances including an inorganic insulating material.

  A siloxane resin may also be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon (aryl group)) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, or polysilazane can be used. A coating film formed by a coating method with good flatness may be used.

  Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 667 which is an interlayer insulating layer. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour.

  Next, a contact hole (opening) reaching the semiconductor layer to the insulating film 667, the insulating film 668, and the gate insulating layer 607 using a resist mask, the insulating film 667, the insulating film 668, the gate insulating layer 607, the first A contact hole (opening) reaching the second electrode layer 805 is formed in the interlayer insulating layer 806. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. In this embodiment mode, the insulating film 668 that is a silicon oxide film containing nitrogen, the insulating film 667 that is a silicon nitride film containing oxygen, the gate insulating layer 607, and the first interlayer insulating layer 806 can be selected under a condition that can be selected. First etching is performed to remove the insulating film 668.

  Next, the insulating film 667 and the gate insulating layer 607 are removed by second etching, and the first p-type impurity region 660a, the first p-type impurity region 660b, and the first p-type which are source regions or drain regions are removed. The impurity region 663a, the first p-type impurity region 663b, the second n-type impurity region 644a, the second n-type impurity region 644b, the second n-type impurity region 647a, and the second n-type impurity region 647b are reached. An opening is formed.

  Further, the insulating film 667 and the first interlayer insulating layer 806 are removed by second etching, and an opening reaching the electrode layer 805 is formed.

In this embodiment mode, the first etching is performed by wet etching, and the second etching is performed by dry etching. As an etchant for wet etching, a hydrofluoric acid-based solution such as a mixed solution containing ammonium hydrogen fluoride and ammonium fluoride may be used. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used.

  A conductive film is formed so as to cover the opening, and the conductive film is etched to be electrically connected to a part of each source region or drain region. An electrode layer 669a which is a source or drain electrode layer and a source electrode layer Alternatively, the electrode layer 669b which is a drain electrode layer, the electrode layer 670a which is a source electrode layer or a drain electrode layer, the electrode layer 670b which is a source electrode layer or a drain electrode layer, the electrode layer 671a which is a source electrode layer or a drain electrode layer, a source An electrode layer 671b which is an electrode layer or a drain electrode layer, an electrode layer 672a which is a source or drain electrode layer, and an electrode layer 672b which is a source or drain electrode layer are formed. Further, the electrode layer 672b which is a source electrode layer or a drain electrode layer is also electrically connected to the second electrode.

  The source electrode layer or the drain electrode layer can be formed by forming a conductive film by a PVD method, a CVD method, an evaporation method, or the like and then etching the conductive film into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electrolytic plating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the source electrode layer or the drain electrode layer is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba or other metals, And Si, Ge, an alloy thereof, or a nitride thereof. Moreover, it is good also as these laminated structures.

  In this embodiment, a titanium (Ti) film is formed to a thickness of 60 nm, a titanium nitride film is formed to a thickness of 40 nm, an aluminum film is formed to a thickness of 700 nm, and a titanium (Ti) film is formed to a thickness of 200 nm. A structure is formed and processed into a desired shape.

  Through the above process, a thin film transistor (TFT) is formed. An active matrix substrate having a p-channel thin film transistor 673 and an n-channel thin film transistor 674 in the peripheral driver circuit region 704 and a multi-channel n-channel thin film transistor 675 and a p-channel thin film transistor 676 in the pixel region 706 can be manufactured. Yes (see FIG. 13B).

  Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. The thin film transistor in the peripheral driver circuit region may have a single gate structure, a double gate structure, or a triple gate structure.

  Note that not only the method for manufacturing the thin film transistor described in this embodiment mode, but a top gate type (planar type), a bottom gate type (reverse stagger type), or a channel formation region is provided above and below the gate insulating film. The present invention can also be applied to a dual gate type or other structure having two gate electrode layers.

  Next, a protective film 819 that covers the pixel region 706 and the peripheral driver circuit region 704 is formed. In this embodiment mode, the protective film 819 may have a single-layer structure or a stacked structure. For example, a stacked structure of a silicon nitride oxide film with a thickness of 100 nm and an oxynitride insulating film with a thickness of 900 nm may be used. A three-layer structure may be used.

  In this embodiment mode, the protective film 819 is continuously formed using a plasma CVD method in the same manner as the base film. The protective film 819 is not limited to the above material, and may be a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, a silicon oxide film using a sputtering method or plasma CVD, or an insulating film containing other silicon. May be used as a single layer or a laminated structure of three or more layers.

  As the protective film 819, aluminum nitride (AlN), aluminum oxide containing nitrogen having an oxygen content higher than the nitrogen content (AlON), and aluminum nitride containing aluminum having a nitrogen content higher than the oxygen content (AlNO) Alternatively, it can be formed using a material selected from substances including aluminum oxide, diamond-like carbon (DLC), a carbon film containing nitrogen (CN), and other inorganic insulating materials.

  A siloxane resin may also be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, or polysilazane can be used. A coating film formed by a coating method with good flatness may be used.

  Next, the protective film 819 is etched using a resist mask provided with a predetermined opening in the external terminal connection region 702b (see FIG. 14).

  After that, the sealing material 692 is attached to the sealing substrate 695. The space 693 is filled with a filler. As the filler, an inert gas (nitrogen, argon, or the like) may be used, or a filler may be filled.

  Note that an epoxy-based resin is preferably used for the sealant 692. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate or a quartz substrate, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar (registered trademark), polyester, acrylic, or the like is used as a material for the sealing substrate 695. Can do.

  Through the above steps, a light-emitting device having the light-emitting element of the present invention can be manufactured.

  Note that a TFT can be provided so as to overlap with the first electrode layer 802 or the second electrode layer 805 in the thickness direction of the light-emitting element (see FIG. 15B). By arranging in this way, the area of the element can be reduced.

  Since the light-emitting device of the present invention includes a thin film transistor (TFT) and an inorganic EL element, it can be applied to an active matrix light-emitting device.

  In addition, since an increase in defects due to hydrogen desorption from amorphous silicon or polysilicon used for a thin film transistor does not occur, an active matrix inorganic EL display can be manufactured without impairing TFT characteristics.

  Even a material having a low melting point such as aluminum or an organic material having low heat resistance can be used for a TFT of an inorganic EL display. In other words, the choice of materials that can be used is expanded.

  According to the present embodiment, it is possible to obtain a light emitting element in which the luminance change with time is reduced while the emission luminance is increased as in the first embodiment. In particular, light emission characteristics in the visible light region can be stabilized. In addition, since the emission spectrum can be broadened and changed to mixed color emission, it can be applied to various applications. Moreover, light emission of mixed colors can be easily obtained, so that white light emission can be produced. In addition, since luminance degradation is small, a highly reliable light-emitting device can be obtained.

  Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
In this embodiment mode, a light-emitting device having a light-emitting element manufactured by applying the present invention will be described.

  In this embodiment, the display device is described as one embodiment of the light-emitting device with reference to FIGS. 16A to 16B, FIGS. 17, 18, 19, and 20 </ b> A to 20 </ b> B. To explain. FIG. 17 is a block diagram showing the main part of the display device.

  The substrate 410 is provided with a first electrode 416 and a second electrode 418 extending in a direction crossing the electrode. At least at a crossing portion between the first electrode 416 and the second electrode 418, a light-emitting layer manufactured by a method similar to that described in Embodiments 1 to 3 is provided, and the light-emitting element is formed. Forming. In the display device in FIG. 17, a plurality of first electrodes 416 and second electrodes 418 are arranged, light emitting elements to be pixels are arranged in a matrix, and a display portion 414 is formed. The display unit 414 can display moving images and still images by controlling the potentials of the first electrode 416 and the second electrode 418 to control light emission and non-light emission of each light emitting element.

  In this display device, a signal for displaying an image is applied to each of the first electrode 416 extending in one direction of the substrate 410 and the second electrode 418 intersecting with the first electrode 416 so that the light emitting element emits light and does not emit light. select. That is, the pixel is driven by a simple matrix display device which is exclusively driven by a signal supplied from an external circuit. Since such a display device has a simple configuration, it can be easily manufactured even when the area is increased.

  In the case where both the first electrode 416 and the second electrode 418 are formed using a transparent conductive film, the light-emitting device of this embodiment can be a dual emission light-emitting device. In the case where one of the first electrode 416 and the second electrode 418 is formed using a reflective conductive film, the light-emitting device of this embodiment is a single-sided emission type (a top-emission type light-emitting device or a Bottom emission type light emitting device).

  As such a transparent conductive film, indium tin oxide (Indium Tin Oxide (ITO)), indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (also referred to as Indium Zinc Oxide (also referred to as IZO)). Indium oxide containing tungsten oxide and zinc oxide can be used. As the reflective conductive film, aluminum (Al), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron ( Fe), cobalt (Co), copper (Cu), palladium (Pd), a nitride of a metal material (for example, titanium nitride), or the like can be used.

  Note that the counter substrate 412 may be provided as necessary, and may be used as a protective member by being provided in accordance with the position of the display portion 414. This can be substituted by applying a resin film or resin material without using a plate-like hard material. The first electrode 416 and the second electrode 418 are drawn out to an end portion of the substrate 410 to form a terminal connected to an external circuit. That is, the first electrode 416 and the second electrode 418 form contacts with the first and second flexible wiring substrates 420 and 422 at the end of the substrate 410. Examples of the external circuit include a power supply circuit, a tuner circuit, and the like in addition to a controller circuit that controls a video signal.

  FIG. 18 is a partially enlarged view showing the configuration of the display unit 414 in FIG. A partition layer 524 is formed on a side end portion of the first electrode 516 formed over the substrate 510. A light emitting layer (also referred to as an EL layer) 526 is formed at least on the exposed surface of the first electrode 516. The second electrode 518 is provided over the EL layer 526. Since the second electrode 518 intersects with the first electrode 516, the second electrode 518 extends over the partition layer 524. The partition layer 524 is formed using an insulating material so that a short circuit does not occur between the first electrode 516 and the second electrode 518. In a portion where the partition wall layer 524 covers the end portion of the first electrode 516, a side end portion of the partition wall layer 524 is provided with a gradient so that a step is not steep so as to have a so-called tapered shape. When the partition layer 524 has such a shape, the coverage with the first electrode 516 is improved, and defects such as cracks and tears can be eliminated.

FIG. 19 is a plan view of the display portion 414 in FIG. 17 and shows the arrangement of the first electrode 1116, the second electrode 1118, the partition wall layer 1124, and the EL layer 1126 over the substrate 1110. The auxiliary electrode 1128 is preferably provided in order to reduce resistance loss in the case where the second electrode 1118 is formed using a transparent conductive film such as indium tin oxide or zinc oxide. In this case, the auxiliary electrode 1128 is preferably formed using a high melting point metal such as titanium, tungsten, chromium, or tantalum, or a combination of a high melting point metal and a low resistance metal such as aluminum or silver.

  19, cross-sectional views taken along lines EF and GH are shown in FIGS. 20A and 20B. 20A is a cross-sectional view in which the first electrodes 416 in FIG. 17 are arranged, and FIG. 20B is a cross-sectional view in which the second electrodes 418 in FIG. 17 are arranged. An EL layer 1226 is formed at the intersection of the first electrode 1216 and the second electrode 1218 over the substrate 1210, and a light-emitting element is formed there. As shown in FIG. 20B, the auxiliary electrode 1228 is provided over the partition wall layer 1224 so as to be in contact with the second electrode 1218. By providing the auxiliary electrode 1228 over the partition layer 1224, a light-emitting element formed at the intersection of the first electrode 1216 and the second electrode 1218 is not shielded, so that the emitted light can be used effectively. Can do. In addition, the auxiliary electrode 1228 can be prevented from being short-circuited with the first electrode 1216.

  16A and 16B illustrate an example in which a color conversion layer 1230 is provided on the counter substrate 1212 of the light-emitting device illustrated in FIGS. 20A and 20B. The color conversion layer 1230 is for changing the wavelength of light emitted from the EL layer 1226 to change the emission color. In this case, light emitted from the EL layer 1226 is preferably blue or ultraviolet light with high energy. If the color conversion layer 1230 is arranged to convert red, green, and blue, a display device that performs RGB color display can be obtained. In addition, the color conversion layer 1230 can be replaced with a colored layer (color filter). In that case, the EL layer 1226 may be configured to emit white light. The filler 1232 fixes the substrate 1210 and the counter substrate 1212 and may be provided as appropriate.

  The light emitting device of the present invention can easily obtain light emission of mixed colors, and thereby can produce white light emission. In addition, since luminance degradation is small, a highly reliable light-emitting device can be obtained.

  Note that this embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 5)
In this embodiment, electronic devices of the present invention including the light-emitting device described in any of Embodiments 1 to 3 as part thereof will be described. An electronic device of the present invention includes the light-emitting element described in any of Embodiments 1 to 3. Therefore, since a driving voltage is reduced and a light-emitting element with high luminance is included, an electronic device with high luminance with reduced consumption electrodes can be provided.

  As an electronic device manufactured using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproducing device (car audio, audio component, etc.), a computer, a game device, a portable information terminal (mobile) Display device capable of playing back a recording medium such as a computer, a mobile phone, a portable game machine, or an electronic book) and a recording medium (specifically, a digital versatile disc (DVD)) and displaying the image And the like). Specific examples of these electronic devices are illustrated in FIGS.

  FIG. 8A illustrates a television device according to the present invention, which includes a housing 9101, a supporting base 9102, a display portion 9103, a speaker portion 9104, a video input terminal 9105, and the like. In this television device, the display portion 9103 is formed by arranging light-emitting elements similar to those described in Embodiments 1 to 3 in a matrix.

  The light-emitting element formed according to the present invention has characteristics that white light can be easily obtained and luminance deterioration is small. As a result, the display device of the present invention has the advantages of low cost and high reliability. Since the display portion 9103 including the light-emitting elements has similar features, the manufacturing cost of this television device is low and high reliability can be obtained.

  FIG. 8B illustrates a computer according to the present invention, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like. In this computer, the display portion 9203 includes light-emitting elements similar to those described in Embodiments 1 to 3, arranged in a matrix.

  The light-emitting element formed according to the present invention has characteristics that white light can be easily obtained and luminance deterioration is small. As a result, the display device of the present invention has the advantages of low cost and high reliability. Since the display portion 9203 which includes the light-emitting elements has similar features, the manufacturing cost of this computer is low and high reliability can be obtained.

  FIG. 8C illustrates a mobile phone according to the present invention, which includes a main body 9401, a housing 9402, a display portion 9403, an audio input portion 9404, an audio output portion 9405, operation keys 9406, an external connection port 9407, an antenna 9408, and the like. . In this cellular phone, the display portion 9403 is formed by arranging light-emitting elements similar to those described in Embodiments 1 to 3 in a matrix.

  The light-emitting element formed according to the present invention has characteristics that white light can be easily obtained and luminance deterioration is small. As a result, the display device of the present invention has the advantages of low cost and high reliability. Since the display portion 9403 including the light-emitting elements has similar features, the manufacturing cost of this mobile phone is low and high reliability can be obtained.

  FIG. 8D illustrates a camera according to the present invention, which includes a main body 9501, a display portion 9502, a housing 9503, an external connection port 9504, a remote control receiving portion 9505, an image receiving portion 9506, a battery 9507, an audio input portion 9508, and operation keys 9509. , An eyepiece 9510 and the like. In this camera, the display portion 9502 includes light-emitting elements similar to those described in Embodiments 1 to 3, arranged in a matrix.

  The light-emitting element formed according to the present invention has characteristics that white light can be easily obtained and luminance deterioration is small. As a result, the display device of the present invention has the advantages of low cost and high reliability. Since the display portion 9502 including the light-emitting elements has similar features, the manufacturing cost of this camera is low and high reliability can be obtained.

  As described above, the applicable range of the light-emitting device of the present invention is so wide that the light-emitting device can be applied to electronic devices in various fields. By using the light-emitting device of the present invention, an electronic device having a display portion with low manufacturing cost, low luminance deterioration, and high reliability can be provided.

  In addition, the light-emitting device of the present invention includes a light-emitting element with high emission efficiency, and can also be used as a lighting device. One mode in which the light-emitting element of the present invention is used as a lighting device is described with reference to FIGS.

  FIG. 9 illustrates an example of a liquid crystal display device using the light-emitting device of the present invention as a backlight. The liquid crystal display device illustrated in FIG. 9 includes a housing 501, a liquid crystal layer 502, a backlight 503, and a housing 504, and the liquid crystal layer 502 is connected to a driver IC 505. The backlight 503 uses the light emitting device of the present invention, and a current is supplied from a terminal 506.

  By using the light-emitting device of the present invention as a backlight of a liquid crystal display device, a backlight with low manufacturing cost, low luminance deterioration, and high reliability can be obtained. Further, the light-emitting device of the present invention is a surface-emitting illumination device and can have a large area, so that the backlight can have a large area and a liquid crystal display device can have a large area. Further, since the light-emitting device of the present invention is thin and has low power consumption, the display device can be thinned and the power consumption can be reduced.

FIG. 11 shows an EL spectrum of the light-emitting device of the present invention. The figure which shows the structure of the conventional light-emitting device. The figure which shows the crystal state of ZnS: Mn. FIG. 6 illustrates a structure of a light-emitting device of the present invention. The figure which shows the path | route of electronic excitation and relaxation. The perspective view and sectional drawing of the light-emitting device of this invention. 2A and 2B are a top view and a cross-sectional view of a light-emitting device of the present invention. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 9 shows luminance deterioration of a light-emitting element. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a light-emitting device of the present invention. 4A and 4B illustrate a light-emitting device of the present invention. 3A and 3B illustrate a light-emitting device of the present invention. 4A and 4B illustrate a light-emitting device of the present invention. 4A and 4B illustrate a light-emitting device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Substrate 101 Electrode 102 Dielectric layer 103 Light emitting layer 104 Dielectric layer 105 Electrode 410 Substrate 412 Counter substrate 414 Display unit 416 Electrode 418 Electrode 420 Flexible wiring substrate 422 Flexible wiring substrate 501 Housing 502 Liquid crystal layer 503 Backlight 504 Housing 505 Driver IC
506 Terminal 510 Substrate 516 Electrode 518 Electrode 524 Partition layer 526 EL layer 600 Substrate 601a Base film 601b Base film 602 Crystalline semiconductor film 603 Semiconductor layer 604 Semiconductor layer 605 Semiconductor layer 606 Semiconductor layer 607 Gate insulating layer 608 Conductive film 609 Conductive film 610a Mask 610b Mask 610d Mask 610e Mask 610f Mask 611 Conductive layer 612 Conductive layer 614 Conductive layer 615 Conductive layer 616 Conductive layer 617 Gate electrode layer 618 Gate electrode layer 621 Gate electrode layer 622 Gate electrode layer 624 Gate electrode layer 625 Gate electrode layer 626 Gate Electrode layer 627 Gate electrode layer 628 Gate electrode layer 629 Gate electrode layer 631 Gate electrode layer 632 Gate electrode layer 634 Gate electrode layer 635 Gate electrode layer 636 Gate electrode layer 640a Impurity region 640b Impurity region 641a Impurity region 641b Impurity region 642a Impurity region 642b Impurity region 642c Impurity region 643a Impurity region 643b Impurity region 644a Impurity region 644b Impurity region 645a Impurity region 646 Channel formation region 647a Impurity region 647b Impurity region 647c Impurity region 648b Impurity region 648c Impurity region 648d Impurity region 649a Channel formation region 649b Channel formation region 651 Impurity element 652 Impurity element 653a Mask 653b Mask 653c Mask 653d Mask 654 Impurity element 655a Mask 655b Mask 660a Impurity region 661b Impurity region 661b Impurity region 662 channel formation region 66 a impurity region 663b impurity region 664a impurity region 664b impurity region 665 channel formation region 667 insulating film 668 insulating film 669a electrode layer 669b electrode layer 670a electrode layer 670b electrode layer 671a electrode layer 671b electrode layer 672a electrode layer 672b electrode layer 673 thin film transistor 675 Thin film transistor 676 Thin film transistor 692 Sealing material 693 Space 694 FPC
695 Sealing substrate 702a External terminal connection region 702b External terminal connection region 703 Wiring region 704 Peripheral drive circuit region 706 Pixel region 802 Electrode layer 803 Insulating layer 804 Light emitting layer 805 Electrode layer 806 Interlayer insulating layer 819 Protective film 951 Substrate 952 Electrode 953 Insulating Layer 954 partition layer 955 layer 956 electrode 1110 substrate 1116 electrode 1118 electrode 1124 partition layer 1126 EL layer 1128 auxiliary electrode 1210 substrate 1212 counter substrate 1216 electrode 1218 electrode 1224 partition layer 1226 EL layer 1228 auxiliary electrode 1230 color conversion layer 1501 electrode 1502 insulating film 1503 Light emitting layer 1504 Insulating film 1505 Electrode 1506 Power source 1507 Power source 9101 Case 9102 Support base 9103 Display portion 9104 Speaker portion 9105 Video input terminal 9201 Main body 9202 Case Body 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9401 Main body 9402 Case 9403 Display unit 9404 Audio input unit 9405 Audio output unit 9406 Operation key 9407 External connection port 9408 Antenna 9501 Main unit 9502 Display unit 9503 Case 9504 External connection port 9505 Remote control receiving unit 9506 Image receiving unit 9507 Battery 9508 Audio input unit 9509 Operation key 9510 Eyepiece unit

Claims (3)

A light emitting device having a light emitting layer containing zinc sulfide and manganese,
The light emitting layer has an emission spectrum in a wavelength range of 500 nm to 700 nm;
The light emission element, wherein the emission spectrum has a first peak on a shorter wavelength side than a wavelength of 580 nm and a second peak on a longer wavelength side than a wavelength of 580 nm. Having a light emitting layer containing zinc sulfide and manganese;
The light emitting layer has an emission spectrum in a wavelength range of 500 nm to 700 nm;
A light-emitting element having an emission spectrum having a first peak on a shorter wavelength side than a wavelength of 580 nm and a second peak on a longer wavelength side than a wavelength of 580 nm;
A light emitting device comprising a drive circuit for controlling light emission of the light emitting element. Forming a light emitting layer containing zinc sulfide and manganese having an emission spectrum having one emission peak within a wavelength range of 500 nm to 700 nm;
Heat-treating the light emitting layer so that the emission spectrum having the one emission peak has a first peak on the shorter wavelength side than the wavelength of 580 nm and a second peak on the longer wavelength side than the wavelength of 580 nm. A method for manufacturing a light-emitting element, comprising:

Images