JP2008035297A - Power supply circuit device and electronic equipment with the power supply circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply circuit device which can make current values to be output to respective loads connected in parallel equivalent values and can stably operate even by a PWM (pulse width modulation) control signal of a wide frequency band. <P>SOLUTION: The power supply circuit device is provided with MOS transistors T1 and T2 connected serially to respective loads 3 and 4 to which voltage is fed from a stabilization power supply circuit 2, a switch 6 the one end of which is connected to gates of the MOS transistors T1 and T2, and a current setting circuit 5 connected to the other end of the switch 6. An internal circuit of the current setting circuit 5 and the MOS transistors T1 and T2 constitute a current mirror circuit, and the switch 6 performs on/off switching operation on the basis of the PWM control signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power supply circuit device that boosts or steps down an input voltage from a DC power supply and supplies the load to a load, and an electronic device including the power supply circuit device, and in particular, based on a PWM (Pulse Width Modulation) signal. The present invention relates to a power supply circuit device that adjusts power supplied to a load, and an electronic apparatus including the power supply circuit device.

  In recent years, a liquid crystal display (LCD) is often used in portable electronic devices such as mobile phones, PDAs (Personal Digital Assistants), digital cameras, car navigation systems, and AV (Audio Visual) systems. . As one of the illumination sources (backlights or frontlights) of this LCD, white light emitting diodes (white LEDs) that are excellent in terms of durability, luminous efficiency, occupied area, etc. tend to be used. .

  In addition, a power supply circuit device that supplies power to the white LED is installed as an LED driver. By adjusting the amount of light of the white LED with this LED driver, the recognizability of the white LED is adjusted and the power consumption is suppressed. Is made. Furthermore, as a method of dimming control by the power supply circuit that is an LED driver, there are a method realized by adjusting a direct current value flowing to the white LED, a time for supplying the maximum current to the white LED, and a time for not supplying the current. There is a method of adjusting the brightness perceived by human eyes by adjusting the ratio using a PWM signal (see Patent Document 1 and Patent Document 2).

  In these dimming controls, when adjusting the direct current value flowing through the white LED, there is a problem that the color tone of the white LED is also changed by the current value flowing through the white LED. On the other hand, when the dimming control is performed using the PWM signal, the current value that flows when the white LED is driven can be kept constant, so that no change in the color tone occurs. For these reasons, with the increase in size and image quality of LCDs equipped with illumination sources using white LEDs, the superiority of the dimming control method using the PWM signal over the color tone has attracted attention and tends to be adopted.

  FIGS. 24 and 25 show the configuration of an illuminating device provided with a power supply circuit device that employs the dimming control method using the PWM signal. The lighting device shown in FIG. 24 includes an input power supply 1, a stabilized power supply circuit 102 that boosts a voltage from the input power supply 1, white LEDs 103 and 104 to which a voltage output from the stabilized power supply circuit 102 is applied, and white And resistors 105 and 106 connected in series to the LEDs 103 and 104, respectively.

  In the illuminating device configured as described above, a voltage signal representing a current value flowing through the white LED 103 appears in the resistor 105 and is fed back to the stabilized power circuit 102. As a result, the output voltage applied by the stabilized power supply circuit 102 to the white LEDs 103 and 104 is controlled so that the current flowing through the white LED 103 is constant. Since the resistor 106 connected to the white LED 104 has the same resistance value as that of the resistor 105, a current having the same current value as that of the white LED 103 flows through the white LED 104.

  Similarly to the power supply circuit device in Patent Document 2, a PWM control signal is input to the stabilized power supply circuit 102, and the current flows through the white LEDs 103 and 104 by controlling the operation of the stabilized power supply circuit 102 on / off. And the time during which no current flows through the white LEDs 103 and 104 is adjusted. As a result, the brightness perceived by human eyes is adjusted by the white LEDs 103 and 104 based on the PWM control signal input to the stabilized power supply circuit 102.

  25 differs from the illumination device shown in FIG. 24 in that N-channel MOS transistors T10 and T11 are connected to the white LEDs 103 and 104, respectively, instead of the resistors 105 and 106. The PWM control signal is not input to the stabilized power supply circuit 102 but is input to the gates of the MOS transistors T10 and T11. Therefore, the lighting device shown in FIG. 25 is dimmed and controlled by the ON / OFF timing of the MOS transistors T10 and T11 connected to the white LEDs 103 and 104, as in the power supply circuit device in Patent Document 1.

With the configuration as shown in FIG. 25, a PWM control signal is given to the gates of the MOS transistors T10 and T11 whose drains are connected to the white LEDs 103 and 104, respectively, and the white LEDs 103 and 104 are driven by the duty ratio of the PWM control signal. The time during which current flows is adjusted. That is, when the PWM control signal is set to high, the MOS transistors T10 and T11 are turned on and current flows through the white LEDs 103 and 104, and when the PWM control signal is set to low, the MOS transistors T10 and T11 are turned off. Thus, the brightness perceived by human eyes by the white LEDs 103 and 104 is adjusted by adjusting the ratio with the time during which no current flows through the white LEDs 103 and 104.
JP 2004-147435 A JP 2005-051883 A

  In the case of the configuration shown in FIG. 24, the output voltage from the stabilized power supply circuit 102 is adjusted so that the current flowing through the white LED 103 is constant, so that the power supply efficiency is good. However, the current values flowing through the white LEDs 103 and 104 vary due to variations in the voltage between the anodes and the cathodes of the white LEDs 103 and 104 and the resistance values of the resistors 105 and 106.

  Further, when PWM control is performed in the stabilized power supply circuit 102, if the PWM control signal is a high frequency signal, the internal circuit of the stabilized power supply circuit 102 cannot follow the PWM control signal. Therefore, when the PWM control signal becomes a high frequency, the linearity between the duty ratio of the PWM control signal and the current value flowing through the white LEDs 103 and 104 is lost. As a result, the usable frequency of the PWM control signal is limited to about 5 kHz. However, since the human audible frequency region has an upper limit of about 20 kHz, there is a problem that audible noise occurs in the frequency band of the PWM control signal.

  On the other hand, in the case of the configuration shown in FIG. 25, dimming control is performed according to the ON / OFF duty ratio of the MOS transistors T10 and T11. At this time, the anode-cathode voltage of the white LEDs 103 and 104 is the MOS It is determined by the drain-source voltage of the transistors T10 and T11. Therefore, the current value of the white LEDs 103 and 104 determined by the anode-cathode voltage of the white LEDs 103 and 104 is determined by the drain-source voltage of the MOS transistors T10 and T11. Therefore, when dimming control is performed by applying a PWM control signal to the gates of the MOS transistors T10 and T11, if the drain-source voltage of the MOS transistors T10 and T11 varies, the current values of the white LEDs 103 and 104 also vary. There was a problem that it would occur.

  In order to control the current value flowing through the white LEDs 103 and 104, the current value flowing through the white LED can be converted into a voltage value and fed back. In this case, the MOS transistors T10 and T11 are repeatedly turned ON / OFF, whereby the current flowing through the white LED is repeatedly switched between the maximum current value and zero. Therefore, the feedback control operation of the current value of the white LED becomes unstable due to the transient response characteristic.

  In view of such a problem, the present invention can make the current value output to each of the loads connected in parallel to an equivalent value, and can operate stably even with a PWM control signal in a wide frequency band. It is an object of the present invention to provide a power supply circuit device that can be used.

  In order to achieve the above object, a power supply circuit device of the present invention includes a stabilized power supply circuit connected to a DC power supply, and supplies an output voltage from the stabilized power supply circuit to a plurality of loads connected in parallel. In the power supply circuit device, a plurality of transistors connected in series to each of the loads, a current setting circuit for setting a current value flowing through each of the plurality of transistors, and between each control electrode of the transistors and the current setting circuit A switch for performing electrical contact / separation according to PWM control when the switch is turned on and the current setting circuit and the plurality of transistors are electrically connected to each other. A current mirror circuit is formed between the transistors.

  In such a power supply circuit device, a detection circuit for detecting the state of the DC power supply and a switching control of the output voltage value from the stabilized power supply circuit in accordance with the state of the DC power supply detected by the detection circuit. 1 voltage switching circuit may be provided. At this time, since the output voltage value supplied to the load can be changed based on the input voltage from the DC power supply, the output voltage value can be changed according to the amount of power of the DC power supply. As a result, the amount of power that can supply a sufficient current to the load can be output from the stabilized power supply circuit, and the power supply efficiency can be improved.

  The voltage generated between the first electrode and the second electrode of the transistor is detected, and the stabilization is performed so that the detected voltage value between the first and second electrodes of the transistor falls within a predetermined voltage range. A second voltage switching circuit that performs switching control of the output voltage value from the power supply circuit may be provided. Accordingly, whether or not the amount of current flowing through the load is a desired amount of current is confirmed by a voltage generated between the first electrode and the second electrode of the transistor. It can be controlled to flow.

  The second voltage switching circuit may detect a voltage generated between the first electrode and the second electrode when the transistor is turned on in synchronization with the PWM control. In the second voltage switching circuit, a voltage generated between the first electrode and the second electrode of the transistor may be smoothed and detected. At this time, based on the minimum value and the maximum value of the voltage between the first and second electrodes of the plurality of transistors, whether the voltage between the first and second electrodes of all the transistors is within a predetermined voltage range. It is also possible to confirm whether or not. Further, based on the average value of the voltages between the first and second electrodes of the plurality of transistors, it is confirmed whether or not the voltages between the first and second electrodes of all the transistors are within a predetermined voltage range. It does n’t matter what you do.

  Further, when it is confirmed that the voltage generated between the first electrode and the second electrode of the transistor detected by the second voltage switching circuit is lower than a predetermined voltage value, the power supply to the load is performed. It doesn't matter if it stops. At this time, when it is confirmed that the voltage generated between the first electrode and the second electrode of the transistor is lower than the predetermined voltage value, an error signal may be output to the outside.

  Further, the timing of the PWM control for the respective transistors connected to the respective loads may be different. At this time, when there are three or more series circuits of the load and the transistor, it may be divided into groups of at least one abnormal series circuit, and the timing of the PWM control may be different for each group. Furthermore, a delay circuit that delays the timing of the PWM control may be provided.

  The stabilized power supply circuit may be a chopper type or a charge pump type.

  According to another aspect of the invention, there is provided an electronic apparatus comprising: a plurality of loads connected in parallel; and any one of the above-described power supply circuit devices that supplies power to the plurality of loads. At this time, if the load is a light emitting diode, the current flowing through the light emitting diode can be made constant by the transistor, and the color tone can be made constant.

  The load may be a series circuit of a plurality of light emitting diodes, and the light emitting diodes may be arranged in a matrix, and the light emitting diodes arranged in adjacent columns may be arranged in different rows. Absent.

  According to the present invention, the PWM control is performed on the switch that electrically connects and disconnects the current mirror circuit that supplies current to the transistor connected to the load. Therefore, the current value is constant when the transistor is turned on and the current is supplied to the load. Can do. Therefore, when a light emitting diode is used as a load, the brightness can be adjusted by changing the ON period by PWM control without changing the color tone. Furthermore, a wide frequency band signal can be used as a control signal for performing PWM control.

  In addition, by making it possible to control the output voltage from the stabilized power supply circuit, it is possible to supply the load with the output voltage necessary for flowing the current necessary for the load, and to obtain high power efficiency. be able to. Furthermore, by controlling based on the voltage between the first and second electrodes of the transistor, not only can the current applied to the load be made constant, but also high power efficiency can be obtained. And the range (dynamic range) of the duty ratio by PWM control can be expanded by detecting by smoothing the voltage between the 1st and 2nd electrodes of a transistor.

  In addition, since the operation protection can be performed based on the voltage between the first and second electrodes of the transistor detected to control the output voltage from the stabilized power supply circuit, the operation protection circuit and the output voltage A circuit portion common to the control circuit can be used. Therefore, it is possible to reduce the size of the apparatus while having a plurality of functions. Furthermore, the timing of PWM control for each transistor connected to each load is made different, so that the timing at which current flows through a plurality of loads can be made different. Therefore, fluctuations in the current flowing through the plurality of loads can be suppressed, and the voltage control loop of the stabilized power supply circuit can be stabilized.

<First Embodiment>
A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a power supply circuit device according to the present embodiment.

  The power supply circuit device shown in FIG. 1 includes an input power supply 1, a stabilized power supply circuit 2 that boosts the voltage from the input power supply 1 and applies an output voltage to one end of each of the loads 3 and 4 connected in parallel. N-channel MOS transistors T1 and T2 whose drains are connected to the other ends of the transistors 3 and 4 and whose sources are grounded, a current setting circuit 5 for setting a current amount of the MOS transistors T1 and T2, and a current setting circuit 5 And a switch 6 that electrically connects and disconnects the MOS transistors T1 and T2 and performs an ON / OFF operation by a PWM control signal p.

  When configured in this way, the input voltage input from the input power supply 1 is boosted by the stabilized power supply circuit 2 and applied to the loads 3 and 4. The MOS transistors T1 and T2 are set by the current setting circuit 5 by connecting the gates of the MOS transistors T1 and T2 and the current setting circuit 5 when the PWM control signal p is high and the switch 6 is turned ON. A drain current equivalent to the current value flows. As a result, the current set by the current setting circuit 5 flows to the loads 3 and 4. On the contrary, when the PWM control signal p becomes low and the switch 6 is turned off, the gates of the MOS transistors T1 and T2 and the current setting circuit 5 are disconnected, and the MOS transistors T1 and T2 are turned off. As a result, the current value flowing through the loads 3 and 4 becomes zero.

  When the switch 6 is turned on, the MOS transistors T1 and T2 are connected to the current setting circuit 5 by a current mirror circuit, as will be described later. Thus, when the switch 6 is turned on, a drain current having a current value set by the current setting circuit 5 flows through the MOS transistors T1 and T2. The current value of the drain current flowing through the MOS transistors T1 and T2 is held to be constant at the set current value by performing feedback control in the current setting circuit 5. That is, the current setting circuit 5 constitutes a current control loop for holding the current flowing through the loads 3 and 4 at a set value. Therefore, the current control loop is not affected by the circuit constituted by the loads 3 and 4 and the MOS transistors T1 and T2 whose currents fluctuate due to the PWM control signal p, and stable current control can be performed.

  An example of the configuration of each of the stabilized power supply circuit 2 and the current setting circuit 5 in such a power supply circuit device is shown in FIG. In FIG. 2, it is assumed that the stabilized power supply circuit 2 is constituted by a boost chopper regulator. As shown in FIG. 2, the stabilized power supply circuit 2 has one end connected to a connection node between the capacitor C1 connected in parallel with the input power supply 1 and the positive terminal (power supply potential side) of the input power supply 1 of the capacitor C1. The coil L1, the diode D1 serving as a rectifier having an anode connected to the other end of the coil L1, the capacitor C2 connected to the cathode of the diode D1, and the connection between the other end of the coil L1 and the anode of the diode D1. And a power transistor PT composed of an N-channel MOS transistor having a drain connected to the node.

  The stabilized power circuit 2 further includes a resistor R1 having one end connected to a connection node between the cathode of the diode D1 and one end of the capacitor C2, and a resistor R2 having one end connected to the other end of the resistor R1. An output voltage appearing at the cathode of the diode D1 is divided by the resistors R1 and R2 and input to the inverting input terminal, and the reference voltage Vref1 is input to the non-inverting input terminal; a sawtooth wave signal; An oscillation circuit 22 that outputs an oscillation signal, and a comparator 23 in which the output from the differential amplifier circuit 21 is input to the non-inverting input terminal and the oscillation signal from the oscillation circuit 22 is input to the inverting input terminal. . The negative side of the input power source 1, the other ends of the capacitors C2 and C3, the other end of the resistor R2, and the source of the power transistor PT are grounded. The output from the comparator 23 is input to the gate of the power transistor PT.

  In the stabilized power supply circuit 2 configured in this way, when the oscillation signal from the oscillation circuit 22 has a value smaller than the output from the differential amplifier circuit 21, the comparator 23 outputs an output that becomes high. Therefore, the power transistor PT is turned on, the current from the input power supply 1 flows through the coil L1, and energy is stored in the coil L1. Conversely, when the oscillation signal from the oscillation circuit 22 has a value greater than the output from the differential amplifier circuit 21, the comparator 23 outputs an output that is low. Therefore, the power transistor PT is turned off and the energy accumulated in the coil L1 is released, thereby generating a counter electromotive force in the coil L1. The back electromotive force generated in the coil L1 is added to the input voltage supplied from the input power supply 1, and charges the capacitor C2 via the diode D1. That is, the voltage generated on the diode D1 side of the coil L1 is smoothed by the diode D1 and the capacitor C2.

  By repeating such a series of operations, a boosting operation is performed, an output voltage is generated across the capacitor C2, and an output current due to this output voltage flows to the loads 3 and 4. At this time, the duty ratio during the ON / OFF period of the power transistor PT is determined by the relationship between the oscillation signal from the oscillation circuit 22 and the output from the differential amplifier circuit 21. As the ON period of the power transistor PT is longer, the output voltage to the loads 3 and 4 is higher. When white LEDs are used as the loads 3 and 4, an output current flows through the white LEDs to emit light.

  Since the output voltage applied to the loads 3 and 4 is also applied to the series circuit of the resistors R1 and R2, the voltage obtained by dividing the output voltage by the resistors R1 and R2 is differentially amplified as a feedback signal. The signal is input to the inverting input terminal of the circuit 21. In this differential amplifier circuit 21, the difference between the reference voltage Vref 1 and the divided voltage by the resistors R 1 and R 2 as feedback signals is obtained, and an output signal corresponding to this difference is output to the non-inverting input terminal of the comparator 23.

  The comparator 23 compares the oscillation signal from the oscillation circuit 22 and the output signal from the differential amplifier circuit 21 to output a high and low signal as described above. As described above, by operating the differential amplifier circuit 21 and the comparator 23, the output voltage output to the loads 3 and 4 is controlled to be constant. That is, when the output voltage is lowered, feedback control is performed so that the output voltage is increased by outputting a high from the comparator 23 and the power transistor PT is turned on for a longer period. Conversely, when the output voltage is increased, the comparator Feedback control is performed so that the output voltage is lowered by shortening the period in which the power transistor PT is turned on by outputting high from 23.

  Further, as shown in FIG. 2, the current setting circuit 5 includes an N-channel MOS transistor T4 whose gate and drain are connected to the gates of the MOS transistors T1 and T2 via an N-channel MOS transistor T3 corresponding to the switch 6. A P-channel MOS transistor T5 having a drain connected to the drain and gate of the MOS transistor T4; a P-channel MOS transistor T6 having a drain and gate connected to the gate of the MOS transistor T5; An N-channel MOS transistor T7 having a drain connected to the gate, a resistor R3 having one end connected to the source of the MOS transistor T7, and an inverting input terminal connected to a connection node between the source of the MOS transistor T7 and one end of the resistor R3 Differential amplification It includes a road 51.

  The source of the MOS transistor T4 and the other end of the resistor R3 are grounded, the sources of the MOS transistors T5 and T6 are connected to the cathode of the diode D1, and the output voltage from the stabilized power supply circuit 2 is applied to the MOS transistor T5. Applied to T6. Furthermore, a current setting signal representing a current value flowing through the loads 3 and 4 is input to the non-inverting input terminal of the differential amplifier circuit 51. In such a configuration, the differential amplifier circuit 51 provides an output corresponding to the difference between the value of the current setting signal and the feedback voltage generated in the resistor R3 to the gate of the MOS transistor T7. Thus, the value of the drain current of the MOS transistor T7 is held by the negative feedback circuit using the differential amplifier circuit 51 and the resistor R3 so that the current value set by the current setting signal flows through the loads 3 and 4.

  Since the current mirror circuit is constituted by the MOS transistors T5 and T6, the current flowing through the MOS transistor T7 flows into the MOS transistor T6, so that the drain current having the same value as the drain current of the MOS transistor T6 flows through the MOS transistor T5. It will be. Therefore, a drain current having the same value as the current flowing through the MOS transistor T7 flows through the MOS transistor T4 connected to the MOS transistor T5.

  By making the ratio W / L of the gate width W and the gate length L of the MOS transistors T5 and T6 different, the amplified current of the drain current flowing through the MOS transistor T7 flows through the MOS transistor T5 as the drain current. It does n’t matter. At this time, when the ratio W / L of the gate width W to the gate length L of each of the MOS transistors T5 and T6 is A and B, and the current flowing through the MOS transistor T7 is Id, the MOS transistor T6 has A × Id / A current of B flows. That is, a drain current having a current value obtained by amplifying the drain current flowing through the MOS transistor T7 by A / B times flows through the MOS transistor T4.

  The MOS transistor T3 serving as the switch 6 has a drain connected to the gate and drain of the MOS transistor T4, a source connected to the gates of the MOS transistors T1 and T2, and a PWM control signal p inputted to the gate. Therefore, when the PWM control signal p becomes high, the MOS transistor T3 is turned on, and a current mirror circuit is configured by the MOS transistors T1, T2, and T4. As a result, a drain current having the same value as the drain current flowing through the MOS transistor T4 flows through the MOS transistors T1 and T2. That is, a current corresponding to the current setting signal input to the differential amplifier circuit 51 flows through the loads 3 and 4.

  Here, the ratio W / L of the gate width W and the gate length L of the MOS transistors T1 and T2 is different from the ratio W / L of the gate width W and the gate length L of the T4, whereby the MOS transistor T4 is made different. A current obtained by amplifying the flowing drain current may flow through the MOS transistors T1 and T2 as the drain current. A current obtained by amplifying the drain current of the MOS transistor T4 by increasing the ratio W / L of the gate width W and the gate length L of the MOS transistors T1 and T2 and the ratio W / L of the gate width W and the gate length L of the T4. Flows through loads 3 and 4.

  On the contrary, when the PWM control signal p becomes low, the MOS transistor T3 is turned OFF, and the electrical connection between the gates of the MOS transistors T1 and T2 and the gate and drain of the MOS transistor T4 is disconnected. Therefore, the MOS transistors T1 and T2 are turned off, and no current flows through the loads 3 and 4. However, the MOS transistors T4 to T7 are in operation based on the output voltage from the stabilized power supply circuit 2, and a current corresponding to the current setting signal flows through the MOS transistors T4 to T7. Therefore, the current control loop configured in the current setting circuit 5 is affected by the circuit configured by the loads 3 and 4 and the MOS transistors T1 and T2 in which the current varies according to the PWM control signal p. Can be prevented.

  As described above, when the MOS transistor T3 is turned ON / OFF according to the PWM control signal p, the ratio of the time during which the current flows through the loads 3 and 4 and the time during which the current does not flow through the loads 3 and 4 is determined as the duty of the PWM control signal p. Can be adjusted by ratio. Further, since the ON / OFF of the MOS transistors T1 and T2 is controlled by the ON / OFF of the MOS transistor T3, the PWM control signal p can be made to respond even if the frequency band is several tens to several hundreds of Hz. The switch 6 is an N-channel MOS transistor T3. However, the switch 6 may be a P-channel MOS transistor or may be a transistor switch having another configuration.

  Since the MOS transistors T1 and T2 constitute an internal circuit of the current setting circuit 5 and a current mirror circuit so that a constant current flows when the switch 6 is turned on by the PWM control signal p, the load 3 , 4 are a plurality of white LEDs connected in series, the color tone does not change. Then, the brightness perceived by human eyes is adjusted by adjusting the ratio of the time during which the current flows through the white LED and the time during which no current flows through the white LED according to the duty ratio of the PWM control signal p.

  Furthermore, although the case where two loads of the loads 3 and 4 are connected in parallel has been described as an example, three or more loads may be connected in parallel. At this time, n MOS transistors are connected in series to each of the n loads connected in parallel, and the gates of the n MOS transistors are connected to the switch 6 so that the switch 6 is ON. Sometimes an internal circuit of the current setting circuit 5 and a current mirror circuit are formed.

<Second Embodiment>
A second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of the power supply circuit device according to this embodiment. In the power supply circuit device shown in FIG. 3, portions used for the same purpose as those of the power supply circuit device shown in FIG.

  The power supply circuit device shown in FIG. 3 has an input voltage measuring circuit 7 that measures the input voltage from the input power supply 1 instead of the stabilized power supply circuit 2 of the power supply circuit device shown in FIG. A power supply circuit 2a and a voltage switching circuit 8 for instructing switching of the output voltage from the stabilized power supply circuit 2a based on the input voltage measured by the input voltage measurement circuit 7 are provided. Since other configurations are the same as those of the power supply circuit device of FIG. 1, detailed description thereof is omitted.

  As shown in FIG. 4, the stabilized power circuit 2a is different from the stabilized power circuit 2 having the configuration of FIG. 2 in that the reference voltage applied to the non-inverting input terminal of the differential amplifier circuit 21 is variable. A voltage switching circuit 24 is installed. The reference voltage switching circuit 24 switches the value of the reference voltage applied to the non-inverting input terminal of the differential amplifier circuit 21 based on the switching instruction signal from the voltage switching circuit 8. In the configuration example of FIG. 4 as well, as in the second configuration example, it is assumed that the stabilized power supply circuit 2a is configured by a boost chopper regulator.

  In such a configuration, when the input voltage from the input power source measured by the input voltage measuring circuit 7 decreases, the voltage switching circuit 8 outputs a switching instruction signal for decreasing the output voltage from the stabilized power circuit 2a. . By supplying this switching instruction signal to the reference voltage switching circuit 24 in the stabilized power supply circuit 2a, the reference voltage input to the non-inverting input terminal of the differential amplifier circuit 21 is lowered. Therefore, the output voltage output from the stabilized power supply circuit 2a can be reduced according to the decrease in the input voltage from the input power supply 1.

At this time, the output voltage from the stabilized power supply circuit 2a may change stepwise while the input voltage from the input power supply 1 changes continuously. Hereinafter, an example in which the voltage value of the output voltage from the stabilized power supply circuit 2a changes in three stages with respect to the input voltage from the input power supply 1 that continuously decreases with time will be described. At this time, as shown in FIG. 5, the reference voltage output from the reference voltage switching circuit 24 changes in three stages with respect to the input voltage from the input power supply 1 that continuously decreases with time. That is, the relationship between the input voltage Vi from the input power supply 1 and the reference voltage Vref output from the reference voltage switching circuit 24 is as follows. The relationship between the voltage values V1 and V2 at the input voltage Vi is V1> V2, and the relationship between the voltage values Vref1 to Vref3 at the reference voltage Vref is Vref1>Vref2> Vref3.
(1) When Vi> V1 Vref = Vref1
(2) When V2 <Vi ≦ V1, Vref = Vref2
(3) When Vi ≦ V2, Vref = Vref3

  FIG. 6 shows a configuration example of the reference voltage switching circuit 24 when the output voltage from the stabilized power supply circuit 2a is changed in this way. The reference voltage switching circuit 24 shown in FIG. 6 includes three resistors Ra to Rc connected in series, and switches Sa to Sc having one end connected in parallel to the non-inverting input terminal of the differential amplifier circuit 21. . The DC voltage Vref1 is applied to one end of the resistor Ra and the other end of the switch Sa is connected. The other end of the switch Sb is connected to a connection node between the other end of the resistor Ra and one end of the resistor Rb. The other end of the switch Sc is connected to a connection node between the other end of the resistor and one end of the resistor Rc, and the other end of the resistor Rc is grounded.

  In the reference voltage circuit 24 configured in this way, the switches Sa to Sc are switched ON / OFF by a switching instruction signal. That is, when the input voltage Vi is larger than V1, the switch Sa is turned on and the switches Sb and Sc are turned off, and the DC voltage Vref1 is applied to the non-inverting input terminal of the differential amplifier circuit 21. When the input voltage Vi becomes equal to or lower than V1, when the input voltage Vi is larger than V2, the switch Sb is turned on and the switches Sa and Sc are turned off to generate a direct current generated at the connection node of the resistors Ra and Rb. The voltage Vref2 is applied to the non-inverting input terminal of the differential amplifier circuit 21. Further, when the input voltage Vi becomes V2 or less, the switch Sc is turned on and the switches Sa and Sb are turned off, so that the DC voltage Vref3 generated at the connection node of the resistors Rb and Rc is not applied to the differential amplifier circuit 21. It is given to the inverting input terminal.

  As in the configuration of FIG. 6, the reference voltage circuit 24 has n resistors connected in series and n−1 switches and one end connected to each of the resistor connection nodes. By connecting the other end of one switch to which Vref1 is applied to one end to the non-inverting input terminal of the differential amplifier circuit 21, the DC voltage applied to the non-inverting input terminal of the differential amplifier circuit 21 is divided into n. be able to. As a result, the output voltage from the stabilized power supply circuit 2 a can be changed in n stages according to the input voltage of the input power supply 1. Further, the DC voltage applied to the non-inverting input terminal of the differential amplifier circuit 21 may be continuously changed using a variable resistor.

  Thus, by making the output voltage from the stabilized power supply circuit 2a change according to the input voltage from the input power supply 1, the loads 3 and 4 are connected to the anode-cathode voltage of the white LED and the stabilized power supply circuit 2a. The difference from the output voltage can be reduced. Thereby, compared with the case where output voltage is fixed like the stabilized power supply circuit 2, the power supply efficiency can be improved.

<Third Embodiment>
A third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing the configuration of the power supply circuit device according to this embodiment. In the power supply circuit device shown in FIG. 7, parts used for the same purpose as those of the power supply circuit device shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The power supply circuit device of FIG. 7 outputs the output of the stabilized power supply circuit 2a based on the drain-source voltages of the MOS transistors T1 and T2 instead of the input voltage measuring circuit 7 and the voltage switching circuit 8 of the power supply circuit device of FIG. A voltage switching circuit 8a that outputs a switching instruction signal for switching the voltage is provided. Since the other configuration is the same as that of the power supply circuit device of FIG. 3, detailed description thereof is omitted. Further, as shown in FIG. 4, the stabilized power supply circuit 2 a is provided with a reference voltage switching circuit 24 that makes the reference voltage applied to the non-inverting input terminal of the differential amplifier circuit 21 variable.

  According to the power supply circuit device configured as described above, the drain-source voltages of the MOS transistors T1 and T2 are detected by connecting the drains of the MOS transistors T1 and T2 to the voltage switching circuit 8a. Then, in the voltage switching circuit 8a, based on the comparison between the detected drain-source voltage of the MOS transistors T1 and T2 and the voltage value Vds serving as the reference value, the voltage from the reference voltage switching circuit 24 in the stabilized power supply circuit 2a. Change the reference voltage value. The voltage value Vds is the lowest value when the MOS transistors T1 and T2 operate so that a constant current flows through the loads 3 and 4.

  A configuration example of the voltage switching circuit 8a will be described with reference to a block diagram of FIG. The voltage switching circuit 8a in FIG. 8 compares the drain voltages of the MOS transistors T1 and T2 and detects the drain-source voltage Vdmin that is the minimum value, and the drain voltage of the MOS transistors T1 and T2. A maximum value detector 82 that detects the drain-source voltage Vdmax that is the maximum value by comparison, a comparator 83 that compares the minimum value voltage Vdmin from the minimum value detector 81 and the reference value Vds, and a maximum value detector And a comparator 84 that compares a maximum value voltage Vdmax from 82 and a voltage value Vds + ΔV (ΔV is a positive value) larger than a reference value.

  In the voltage switching circuit 8a, the minimum value detector 81 and the maximum value detector 82 receive the PWM control signal p, and the minimum value detector 81 and the maximum value detector 82 operate in synchronization with the PWM control signal p. To do. That is, by operating the minimum value detector 81 and the maximum value detector 82 in synchronization with the PWM control signal p, the minimum value is determined based on the drain-source voltage that appears when the MOS transistors T1 and T2 are turned on. The voltage Vdmin and the maximum value voltage Vdmax can be detected. The minimum value voltage Vdmin and the maximum value voltage Vdmax detected by the minimum value detection unit 81 and the maximum value detection unit 82, respectively, are held until the MOS transistors T1 and T2 are turned on next time.

  When the voltage switching circuit 8a is configured in this way, when the minimum value voltage Vdmin becomes equal to or higher than the reference value Vds, the comparator 83 outputs a switching instruction signal that goes high, and when the maximum value voltage Vdmax becomes equal to or lower than the voltage value Vds + ΔV. The comparator 84 outputs a switching instruction signal that goes high. Switching instruction signals output from the comparators 83 and 84 are input to the reference voltage switching circuit 24.

  When the switching instruction signals output from the comparators 83 and 84 are both high, the reference voltage is not switched by the reference voltage switching circuit 24 and is currently input to the non-inverting input terminal of the differential amplifier circuit 21. It is held at the reference voltage. Further, when the switching instruction signal output from the comparator 83 becomes low, the reference voltage by the reference voltage switching circuit 24 is switched, and the reference voltage currently input to the non-inverting input terminal of the differential amplifier circuit 21 becomes high. It changes to become. Further, when the switching instruction signal output from the comparator 83 is high and the switching instruction signal output from the comparator 84 is low, the reference voltage is switched by the reference voltage switching circuit 24 and the current differential amplifier circuit is switched. The reference voltage input to the non-inverting input terminal 21 changes so as to be low.

  By operating in this way, the drain-source voltage Vd of the MOS transistors T1 and T2 satisfies the condition of Vds ≦ Vd ≦ Vds + ΔV, and flows through the loads 3 and 4 when the MOS transistors T1 and T2 are turned on. The current is set to be constant. Therefore, since the minimum output voltage required for the set current to be output to the loads 3 and 4 can be detected and set with high accuracy, higher power supply efficiency can be realized.

  The reference voltage Vds for setting the drain-source voltage of the MOS transistors T1, T2 may be changed according to the value of the current flowing through the loads 3, 4 set by the current setting circuit 5.

  In the present embodiment, the reference voltage is switched by the reference voltage switching circuit 24 based on the binary switching instruction signals from the comparators 83 and 84. Further, the minimum voltage value Vdmin and the reference voltage Vds The difference value (Vdmin−Vds) and the difference value (Vdmax− (Vds + ΔV)) between the maximum voltage value Vdmax and the voltage value Vds + ΔV may be given to the reference voltage switching circuit 24. At this time, when the minimum voltage value Vdmin is lower than the reference voltage Vds, the reference voltage value from the reference voltage switching circuit 24 is switched according to the difference value (Vdmin−Vds). When the minimum voltage value Vdmin is higher than the reference voltage Vds and the maximum voltage value Vdmax is higher than the voltage value Vds + ΔV, the reference voltage value from the reference voltage switching circuit 24 is set according to the difference value (Vdmax− (Vds + ΔV)). Can be switched.

  Further, in this embodiment, the maximum value and the minimum value of the drain-source voltage of the MOS transistors T1 and T2 are detected and the reference voltage output from the reference voltage switching circuit 24 is switched. The reference voltage output from the reference voltage switching circuit 24 may be switched based on the average value of the drain-source voltages of the transistors T1 and T2. That is, an average value calculation unit 80 that operates in synchronization with the PWM control signal p is provided instead of the minimum value detection unit 81 and the maximum value detection unit 82 as in the voltage switching circuit 8b shown in FIG.

  As a result, the average value calculation unit 80 calculates the average value Vav of the drain-source voltages of the MOS transistors T1 and T2 generated when the MOS transistors T1 and T2 are turned on, and inputs them to the comparators 83 and 84. . Thus, the comparator 83 compares the average value Vav with the reference voltage Vds, and the comparator 84 compares the average value Vav with the voltage value Vds + ΔV. Then, the switching instruction signal obtained from the comparison result of the comparators 83 and 84 is output to the reference voltage switching circuit 24, whereby the reference voltage from the reference voltage switching circuit 24 is set and the output voltage from the stabilized power supply circuit 2a. Value is set.

<Fourth Embodiment>
A fourth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of the power supply circuit device according to this embodiment. In the power supply circuit device shown in FIG. 10, parts used for the same purpose as those of the power supply circuit device shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The power supply circuit device of FIG. 10 detects whether or not the loads 3 and 4 are open based on the drain-source voltages of the MOS transistors T1 and T2 in the configuration of the power supply circuit device of FIG. And a device protection circuit 9 for outputting a protection signal. Further, instead of the stabilized power supply circuit 2a, a stabilized power supply circuit 2b whose driving and stopping are controlled based on a protection signal output from the device protection circuit 9 is provided. Since the other configuration is the same as that of the power supply circuit device of FIG. 7, detailed description thereof is omitted.

  Further, as shown in FIG. 11, the stabilized power supply circuit 2b includes an AND gate 25 having two inputs and one output, the output side of which is connected to the power transistor PT and the output from the comparator 23 is input to one input. A protection signal output from the device protection circuit 9 is input to the other input of the AND gate 25. At this time, when the protection signal from the device protection circuit 9 is high, since the output from the comparator 23 is input to the power transistor PT, the stabilized power circuit 2b is driven to supply the output voltage to the loads 3 and 4. To do. On the contrary, when the protection signal from the device protection circuit 9 is low, the output from the comparator 23 is prohibited from being input to the power transistor PT, so that the stabilized power supply circuit 2b stops and loads the output voltage. Supply stops at 3 and 4.

  At this time, as shown in FIG. 12, the device protection circuit 9 includes a minimum voltage Vdmin from the minimum value detector 81 and a reference voltage Vrefx for detecting that any of the loads 3 and 4 is open. The comparator 91 is configured to compare (Vrefx <Vds). At this time, the comparator 91 that is the device protection circuit 9 outputs a protection signal that becomes high when the minimum value voltage Vdmin from the minimum value detector 81 is equal to or higher than the reference voltage Vrefx, and the minimum value from the minimum value detector 81. When the voltage Vdmin is lower than the reference voltage Vrefx, a protection signal that is low is output.

  With this configuration, it is detected that the minimum voltage among the drain-source voltages of the MOS transistors T1 and T2 connected to the loads 3 and 4 is lower than the reference voltage Vrefx and close to zero. Then, it is detected that one of the loads 3 and 4 is open. Then, the protection signal that becomes low is input to the AND gate 25 of the stabilized power supply circuit 2b, whereby the power transistor PT is turned off, and the output voltage is supplied from the stabilized power supply circuit 2b to the loads 3 and 4. Stops.

  Therefore, according to the present embodiment, the voltage switching circuit 8a and the device protection circuit 9 detect not only the drain-source voltage of each of the MOS transistors T1 and T2, but also the switching of the output voltage of the stabilized power circuit 2b. The output of the stabilized power supply circuit 2b can also be stopped by detecting the opening of the loads 3 and 4. That is, a protection circuit against load opening can be added to the power supply circuit device of the third embodiment by adding a small circuit configuration.

  In the present embodiment, the device protection circuit 9 may be configured such that the PWM control signal p is input and the protection signal is switched between high and low based on the switching instruction signal output from the comparator 83. At this time, according to the period of the input PWM control signal p, it is confirmed whether or not the switching instruction signal output from the comparator 83 is low, and the switching instruction signal from the comparator 83 is continuously provided for a plurality of periods. When detecting that is low, the protection signal may be low in order to turn off the stabilized power supply circuit 2b.

  In this embodiment, the drive of the stabilized power supply circuit 2b is stopped by the protection signal from the device protection circuit 9. However, as the drive of the stabilized power supply circuit 2b is stopped, the stabilized power supply circuit 2b and the load are stopped. 3 and 4 may also be disconnected, or the input power supply 1 and the stabilized power supply circuit 2b may be disconnected to prohibit input from the input power supply 1. Further, the operation of the current setting circuit 5 is stopped by a protection signal from the device protection circuit 9, thereby prohibiting current from flowing through the MOS transistors T1 and T2 connected by the current mirror circuit, and to the loads 3 and 4. The current supply may be prohibited. At this time, for example, in the case of the current setting circuit 5 configured as shown in FIG. 2, the current supply to the MOS transistors T1 and T2 can be prohibited by forcibly stopping the operation of the MOS transistor T7.

  Further, an error signal may be output to the outside of the power supply circuit device based on the protection signal output from the device protection circuit 9. That is, when the protection signal output from the device protection circuit 9 becomes low, an error signal indicating that the loads 3 and 4 are detected to be open is output to the outside of the power supply circuit device. Accordingly, by inputting the error signal to another circuit device outside the power supply circuit device, another operation such as error display can be performed in the electronic device including the power supply circuit device.

<Fifth Embodiment>
A fifth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing the configuration of the power supply circuit device according to this embodiment. In the power supply circuit device shown in FIG. 13, parts used for the same purpose as those of the power supply circuit device shown in FIG.

  The power supply circuit device of FIG. 13 includes a voltage switching circuit 8c for smoothing and detecting the drain-source voltages of the MOS transistors T1 and T2 instead of the voltage switching circuit 8a of the power supply circuit device of FIG. Since other configurations are the same as those of the power supply circuit device of FIG. 10, detailed description thereof is omitted. Unlike the voltage switching circuit 8a, the voltage switching circuit 8c smoothes the voltage applied from the drains of the MOS transistors T1 and T2, and therefore does not need to be synchronized with the PWM control signal p. Therefore, it is not necessary to input the PWM control signal p to the voltage switching circuit 8c unlike the voltage switching circuit 8a.

  Further, as shown in FIG. 14, the voltage switching circuit 8c includes voltage smoothing portions 85a and 85b for smoothing voltages appearing at the drains of the MOS transistors T1 and T2, and smoothing is performed by the voltage smoothing portions 85a and 85b. The obtained voltage is supplied to the minimum value detector 81 and the maximum value detector 82. The minimum value detection unit 81 and the maximum value detection unit 82 receive the smoothed drain-source voltages of the MOS transistors T1 and T2, respectively. Therefore, unlike the minimum value detection unit 81 and the maximum value detection unit 82 in the voltage switching circuit 8a in the power supply circuit devices of the third and fourth embodiments, it is not necessary to operate in synchronization with the PWM control signal p.

  For example, as shown in FIG. 15, the voltage smoothing sections 85a and 85b include a diode D having an anode connected to the drains of the MOS transistors T1 and T2, and one end connected to the cathode of the diode D and the other end grounded. It may be configured by the capacitor C formed. In this way, the switch 6 is turned on by the PWM control signal p, and the drain voltage generated when the MOS transistors T1 and T2 are turned on is applied to the capacitor C via the diode D. C performs a power storage operation. When the switch 6 is turned off by the PWM control signal p and the MOS transistors T1 and T2 are turned off, the drain voltage becomes zero, so that the capacitor C performs a discharging operation.

  Therefore, the voltage appearing at the drains of the MOS transistors T1 and T2 is smoothed by the storage operation and the discharge operation of the capacitor C, and is supplied to the minimum value detection unit 81 and the maximum value detection unit 82. That is, as shown in FIG. 16A, the drain-source voltages of the MOS transistors T1 and T2 that change every period of the PWM control signal p are PWMed by the voltage smoothing units 85a and 85b as shown in FIG. The signal is smoothed for each cycle of the control signal p and is supplied to the minimum value detection unit 81 and the maximum value detection unit 82.

  Then, the minimum value detection unit 81, the maximum value detection unit 82, and the comparators 83 and 84 perform the same operation as in the third and fourth embodiments, so that the switching instruction signal is output from the comparators 83 and 84. . Similarly to the fourth embodiment, the minimum voltage value Vmin detected by the minimum value detector 81 is given to the device protection circuit 9 and compared with the reference voltage Vrefx, so that the protection signal is sent from the device protection circuit 9. Is output.

  With this configuration, unlike the third and fourth embodiments, it is not necessary to detect the drain-source voltages of the MOS transistors T1 and T2 in synchronization with the PWM control signal p. Therefore, even when the time during which the MOS transistors T1 and T2 are turned on by the PWM control signal p is short, the drain-source voltage can be detected stably. Therefore, the frequency of the PWM control signal p can be increased and the controllable duty range (dynamic range) can be expanded.

  In the present embodiment, as in the third embodiment, as a power supply circuit device including the stabilized power supply circuit 2a, the output of the stabilized power supply circuit 2a is detected by detecting the drain-source voltages of the MOS transistors T1 and T2. It does not matter if the voltage is only switched. Instead of the voltage switching circuit 8c, the reference voltage output from the reference voltage switching circuit 24 is switched based on the average value of the drain-source voltages of the MOS transistors T1 and T2 as in the voltage switching circuit 8b. It does not matter. That is, as in the voltage switching circuit 8d shown in FIG. 17, an average value calculation unit 80 may be provided instead of the minimum value detection unit 81 and the maximum value detection unit 82.

  In the third to fifth embodiments, as in the second embodiment, the input voltage measurement circuit 7 is provided, so that the reference voltage output from the reference voltage switching circuit 24 even when the input voltage changes is provided. Can be switched. In the second to fifth embodiments, the output voltage from the stabilized power supply circuit is switched using another means for switching the duty ratio according to ON / OFF of the power transistor PT in addition to the reference voltage switching circuit 24. It doesn't matter. Furthermore, stabilization is based on the detected value of the output voltage from the stabilized power supply circuit, the instruction from the external CPU, and the signal from the illuminance sensor that detects the illuminance when the loads 3 and 4 are white LEDs. The output voltage from the power supply circuit may be switched.

  In the first to fifth embodiments, the output voltage from the stabilized power supply circuit is supplied to the two loads 3 and 4 connected in parallel. Regarding the load to which the voltage is supplied, three or more loads may be connected in parallel. At this time, a MOS transistor connected in series is connected to each load, and when the gate of each MOS transistor is connected to the switch 6 and the switch 6 is turned on, the internal circuit of the current setting circuit 5 and the current mirror circuit are connected. Constitute.

<Sixth Embodiment>
A sixth embodiment of the present invention will be described with reference to the drawings. FIG. 18 is a block diagram showing the configuration of the power supply circuit device according to this embodiment. In the power supply circuit device shown in FIG. 18, parts used for the same purpose as those of the power supply circuit device shown in FIG.

  The power supply circuit device of FIG. 18 includes switches 6a and 6b connected to the gates of the MOS transistors T1 and T2 instead of the switch 6 of the power supply circuit device of FIG. 1 and a delay circuit 10 that delays the PWM control signal p. The configuration is That is, the other end of the switch 6a having one end connected to the gate of the MOS transistor T1 and the other end of the switch 6b having one end connected to the gate of the MOS transistor T2 are connected, and the switches 6a and 6b are connected in parallel. To do. A connection node at the other end of the switches 6 a and 6 b is connected to the current setting circuit 5.

  Also, the PWM control signal p is directly given to the switch 6a to perform ON / OFF control, and the PWM control signal pa delayed by the delay circuit 10 is given to the switch 6b to perform ON / OFF control. . That is, as shown in FIG. 19, the timing at which the switch 6a is switched ON / OFF is shifted from the timing at which the switch 6b is switched ON / OFF. As a result, the period during which the drain current flows through the MOS transistor T1 and the period during which the drain current flows through the MOS transistor T2 become different in time.

  Note that the delay time for delaying the PWM control signal p in order to generate the PWM control signal pa in the delay circuit 10 is shorter than the time of one cycle of the PWM control signal p. Further, the delay circuit 10 is operated in synchronization with the oscillation signal from the oscillation circuit 22 in the stabilized power supply circuit 2, for example, to delay the rising or falling edge of the input PWM control signal p as a trigger, The delayed PWM control signal pa can be output.

  With this configuration, in the loads 3 and 4, the period in which the current flows and the period in which no current flows do not become the same period. That is, the timing at which the current flowing through each of the loads 3 and 4 switches between the maximum value and zero is not simultaneous. As a result, as compared with the case where the MOS transistors T1 and T2 are switched ON / OFF at the same timing as in the first embodiment, fluctuations in the current flowing to the parallel circuit of the loads 3 and 4 are suppressed. can do. Therefore, the abnormal oscillation in the stabilized power supply circuit 2 can be suppressed and the voltage feedback control operation can be performed stably, and the input / output ripple voltage is reduced, so the burden on the input power supply 1 is reduced. Further, when the loads 3 and 4 are white LEDs, flickering of the white LEDs can be reduced.

  In the present embodiment, the output voltage from the stabilized power supply circuit may be switched according to the input voltage of the input power supply 1 as in the second embodiment. Similarly to the third to fifth embodiments, the drain-source voltage of the MOS transistors T1 and T2 may be detected to switch or stop the output voltage from the stabilized power supply circuit. As in the third and fourth embodiments, when the drain-source voltage of the MOS transistors T1, T2 is detected in synchronization with the PWM control signal, the detection of the drain-source voltage of the MOS transistor T1 is directly performed. In addition to the input PWM control signal p, the detection of the drain-source voltage of the MOS transistor T2 is performed by the PWM control signal pa delayed by the delay circuit 10.

  When the PWM control signals p and pa having different timings are given to the MOS transistors T1 and T2 as in the present embodiment, current fluctuations in the loads 3 and 4 are suppressed as described above. Therefore, as shown in FIG. 20, instead of the stabilized power supply circuit 2, a stabilized power supply circuit 2c including a timing control unit 26 that outputs the PWM control signals p and pa to the gates of the MOS transistors T1 and T2 at different timings is provided. By providing the current setting circuit 5, the current setting circuit 5 can be omitted.

  When configured in this way, the stabilized power supply circuit 2c receives two PWM control signals p and pa that switch between high and low at different timings when the PWM control signal p input from the outside is supplied to the timing control unit 26. Are output to the gates of the MOS transistors T1 and T2, respectively. Therefore, the dimming control when the loads 3 and 4 are white LEDs can be performed by changing the duty ratio of the PWM control signals p and pa and changing the ON / OFF period of the MOS transistors T1 and T2. it can.

  Further, in FIGS. 18 and 20, the MOS transistor is generated by the PWM control signals p and pa having the same two duty ratios by shifting the high / low switching timing by delaying one input PWM control signal p. Although ON / OFF control of T1 and T2 is performed, two PWM control signals having different duty ratios may be input from the outside to perform ON / OFF control of the MOS transistors T1 and T2. That is, as shown in FIG. 21, instead of omitting the delay circuit 10 in FIG. 18, the switches 6a and 6b are ON / OFF controlled by PWM control signals p1 and p2 having different duty ratios. Further, the PWM control signals p1 and p2 are signals whose periods are shifted, and are set so that the switching timing of high / low is shifted.

  Furthermore, in this embodiment, power is supplied to the two loads 3 and 4 connected in parallel. However, power may be supplied to three or more loads connected in parallel. At this time, PWM control signals having different high / low switching timings may be given to the gates of the MOS transistors connected in series to the respective loads. Also, PWM control signals having different high / low switching timings may be given for each group of one or more loads. FIG. 22 shows a configuration example in which two PWM control signals are given to two groups as a configuration example in which PWM control signals having different switching timings are given to each group.

  The power supply circuit device shown in FIG. 22 has a configuration in which n loads 3-1 to 3-n and m loads 4-1 to 4-m constituting two groups are connected in parallel. MOS transistors T1-1 to T1-n and T2-1 to T2-m are connected in series to the loads 3-1 to 3-n and 4-1 to 4-m, respectively. One end of a switch 6a that is ON / OFF controlled by the PWM control signal p is connected to the gates of the MOS transistors T1-1 to T1-n, and the gates of the MOS transistors T2-1 to T2-m are connected to the gates by the PWM control signal pa. One end of the switch 6b that is ON / OFF controlled is connected.

  Similarly to the configuration of FIG. 21, the PWM control signals p1 and p2 that are different from the outside are given to the switches 6a and 6b. The period during which current is supplied to each of -1 to 4-m can be different. Accordingly, when configuring white LEDs in which the loads 3-1 to 3-n and 4-1 to 4-m are connected in series, the brightness of the white LEDs corresponding to the loads 3-1 to 3-n, The brightness of the white LEDs corresponding to the loads 4-1 to 4-m can be different. Thereby, when it comprises as an illumination source of a liquid crystal display device, a brightness can be changed with an area | region by making the duty ratio of the PWM control signal given to each group differ.

<Example when the load is a white LED>
In the first to sixth embodiments, each load to which the output voltage from the stabilized power supply circuit is applied may be a white LED connected in series. A plurality of white LEDs can be arranged in a matrix by connecting a plurality of loads in parallel by the white LEDs connected in series. The white LEDs connected in parallel are alternately arranged in adjacent columns. In this way, an illumination source using a white LED as a load is used as a backlight of a liquid crystal display device.

  At this time, as in the sixth embodiment, by applying PWM control signals having different switching timings to the gates of the MOS transistors connected to different loads, the timing at which the adjacent white LED emits light is different. can do. Thereby, brightness unevenness due to the white LEDs can be reduced, and flickering due to the multiple rows of white LEDs can also be reduced.

  FIG. 23 shows the arrangement relationship of the plurality of white LEDs constituting this load. In FIG. 23, three white LEDs a1 to a3, b1 to b3, and c1 to c3 are connected in series, and three series circuits are connected in parallel. At this time, the white LEDs b1 to b3 are arranged in a row adjacent to the white LEDs a1 to a3 arranged in the same row, and the white LEDs c1 to c3 are arranged in a row adjacent to the white LEDs b1 to b3. The white LED bx is arranged in a row between the row in which the white LEDs ax and cx (x = 1, 2) are arranged and the row in which the white LEDs a (x + 1) and b (x + 1) are arranged.

  At this time, the load of the white LEDs a1 to a3 connected in series and the load of the white LEDs c1 to c3 connected in series are grouped together, and the load of the white LEDs b1 to b3 connected in series is another one. A group. When configured as in the sixth embodiment, the switch 6a controlled by the PWM control signal p is connected to the gates of the MOS transistors Ta and Tc whose drains are connected to the white LEDs a3 and c3, respectively, and the white LED b3 The switch 6b controlled by the PWM control signal pa is connected to the gate of the MOS transistor Tb to which the drain is connected.

  Further, in each of the above-described embodiments, the step-up DC voltage chopper circuit is used. However, a step-down chopper circuit may be used, and a combination of a switch and a capacitor, and a charge pump type that performs step-up or step-down by the electric difference of the capacitor. It may be a stabilized power circuit.

  The present invention can be applied to a power supply circuit device including a DC voltage chopper circuit for boosting or stepping down an output voltage and a charge pump type stabilized power supply circuit. Moreover, it is applicable to the power supply circuit apparatus which can perform the light control of LED by using LED as the load which outputs voltage. Further, when the load is an LED, the LED can be used as a white LED and as an illumination source for a liquid crystal display device.

These are block diagrams which show the internal structure of the power supply circuit device of 1st Embodiment. FIG. 2 is a block diagram showing a configuration example of a stabilized power supply circuit and a current setting circuit in the power supply circuit device of FIG. 1. These are block diagrams which show the internal structure of the power supply circuit device of 2nd Embodiment. FIG. 4 is a block diagram showing a configuration example of a stabilized power supply circuit in the power supply circuit device of FIG. 3. These are figures which show the example of a reference voltage switching operation | movement of the reference voltage switching circuit in the stabilization power supply circuit of FIG. FIG. 5 is a block diagram showing a configuration example of a reference voltage switching circuit in the stabilized power supply circuit of FIG. 4. These are block diagrams which show the internal structure of the power supply circuit device of 3rd Embodiment. These are block diagrams which show the structure of the voltage switching circuit in the power supply circuit apparatus of FIG. These are block diagrams which show another structure of the voltage switching circuit in the power supply circuit apparatus of FIG. These are block diagrams which show the internal structure of the power supply circuit device of 4th Embodiment. FIG. 11 is a block diagram showing a configuration of a stabilized power supply circuit in the power supply circuit device of FIG. 10. FIG. 12 is a block diagram showing a configuration of a device protection circuit in the power supply circuit device of FIG. 11. These are block diagrams which show the internal structure of the power supply circuit device of 5th Embodiment. FIG. 14 is a block diagram showing a configuration of a voltage switching circuit in the power supply circuit device of FIG. 13. These are block diagrams which show the structural example of the voltage smoothing part in the voltage switching circuit of FIG. These are figures which show the relationship between the smoothing operation of the voltage smoothing part of FIG. 15, and a PWM control signal. FIG. 14 is a block diagram showing another configuration of the voltage switching circuit in the power supply circuit device of FIG. 13. These are block diagrams which show the internal structure of the power supply circuit device of 6th Embodiment. These are timing charts showing the ON / OFF switching timing of the switches 6a and 6b. These are block diagrams which show the internal structure of the power supply circuit device used as another structural example in 6th Embodiment. These are block diagrams which show the internal structure of the power supply circuit device used as another structural example in 6th Embodiment. These are block diagrams which show the internal structure of the power supply circuit device used as another structural example in 6th Embodiment. These are figures which show the arrangement | positioning relationship when load is made into white LED. These are block diagrams which show the internal structure of the conventional power supply circuit device. These are block diagrams which show the internal structure of the conventional power supply circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input power supply 2 Stabilized power supply circuit 3, 4 Load 5 Current setting circuit 6, 6a, 6b Switch 7 Input voltage measuring circuit 8, 8a-8d Voltage switching circuit 9 Device protection circuit 10 Delay circuit T1-T7 MOS transistor

Claims (13)

In a power supply circuit device comprising a stabilized power supply circuit connected to a direct current power supply and supplying an output voltage from the stabilized power supply circuit to a plurality of loads connected in parallel,
A plurality of transistors connected in series to each of the loads;
A current setting circuit for setting a current value flowing through each of the plurality of transistors;
A switch for performing electrical contact and separation between the control electrode of each of the transistors and the current setting circuit according to PWM control;
With
When the switch is turned on and the current setting circuit and the plurality of transistors are electrically connected, a current mirror circuit is configured between the current setting circuit and the plurality of transistors. Power supply circuit device. A detection circuit for detecting a state of the DC power supply;
A first voltage switching circuit that performs switching control of an output voltage value from the stabilized power supply circuit according to the state of the DC power supply detected by the detection circuit;
The power supply circuit device according to claim 1, further comprising:   The stabilized power supply circuit detects a voltage generated between the first electrode and the second electrode of the transistor, and the detected voltage value between the first and second electrodes of the transistor falls within a predetermined voltage range. The power supply circuit device according to claim 1, further comprising a second voltage switching circuit that performs switching control of an output voltage value from the power supply circuit.   The voltage generated between the first electrode and the second electrode is detected when the transistor is turned on in synchronization with the PWM control in the second voltage switching circuit. Power circuit equipment.   4. The power supply circuit device according to claim 3, wherein in the second voltage switching circuit, a voltage generated between a first electrode and a second electrode of the transistor is smoothed and detected. 5.   When it is confirmed that the voltage generated between the first electrode and the second electrode of the transistor detected by the second voltage switching circuit is lower than a predetermined voltage value, the power supply to the load is stopped. The power supply circuit device according to any one of claims 3 to 5, wherein   The error signal is output to the outside when it is confirmed that a voltage generated between the first electrode and the second electrode of the transistor is lower than the predetermined voltage value. Power supply circuit device.   The power supply circuit device according to any one of claims 1 to 7, wherein timing of the PWM control for each of the transistors connected to each of the loads is different.   9. The system according to claim 8, wherein when there are three or more series circuits of the load and the transistor, the load is divided into groups of at least one abnormal series circuit, and the timing of the PWM control is different for each group. The power supply circuit device described.   The power supply circuit device according to claim 8, further comprising a delay circuit that delays the timing of the PWM control. Multiple loads connected in parallel;
The power supply circuit device according to any one of claims 1 to 9, wherein power is supplied to the plurality of loads.
An electronic device comprising:   The electronic device according to claim 11, wherein the load is a light emitting diode. The load is a series circuit of a plurality of light emitting diodes;
The electronic device according to claim 11, wherein the light emitting diodes are arranged in a matrix and the light emitting diodes arranged in adjacent columns are arranged in different rows.

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