JP2008035186A - Clock signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal generation circuit capable of efficiently generating clock signals even when using weak radio waves as in radio broadcasting. <P>SOLUTION: The clock signal generation circuit comprises: an antenna for receiving radio waves supplied from the outside and converting them to electric signals; a resonance circuit including a variable capacitance capacitor and a coil, for extracting AC signals having a desired frequency by performing a tuning operation to the electric signals outputted from the antenna; a rectifying and smoothing circuit including a diode having a forward voltage lower than that of a silicon diode and a capacitor, for rectifying and smoothing the AC signals extracted by the resonance circuit and generating a power supply voltage; and a logic circuit constituted of a plurality of transistors formed on a silicon substrate, for converting the AC signals extracted by the resonance circuit to the clock signals when the power supply voltage generated by the rectifying and smoothing circuit is supplied. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock signal generation circuit for generating a clock signal from a signal such as a radio wave received from the outside.

  RFID (Radio Frequency Identification) is known as one of techniques for driving a circuit based on a signal received from the outside. The RFID operates by receiving a radio frequency (RF) magnetic field or electromagnetic field supplied from the outside, and performs wireless communication with the outside. An IC tag (passive tag) that stores an identification code and various types of information is known as an RFID tag, and is used in various industries. The passive tag does not have a built-in power supply, and power is generated in the passive tag by a magnetic field or electromagnetic field supplied from the outside, and information processing or the like is performed by the power.

As a related technique, the following Patent Document 1 discloses that a stable clock signal and power are generated from a received wave in an electromagnetic coupling type transmission / reception circuit (ID tag) that transmits and receives a signal by one coil. Yes. This ID tag includes a resonance circuit that transmits and receives signals to and from an information reader, a modulation transistor that modulates the output of the resonance circuit by grounding the output terminal of the resonance circuit, and response data read from the memory. Accordingly, a modulation circuit is provided that generates a modulation control signal for turning on the modulation transistor for every half cycle during modulation. According to this ID tag, it is possible to generate a stable clock signal by performing modulation without changing the frequency of the output of the resonance circuit, and because modulation is performed so that a part of the output is thinned out. Stable power can be taken out with small ripple. However, Patent Document 1 does not disclose the generation of a clock signal using weak radio waves such as radio broadcasting.
JP-A-7-218626 (first page, FIG. 1)

  Therefore, in view of the above points, an object of the present invention is to provide a clock signal generation circuit capable of efficiently generating a clock signal even if weak radio waves such as radio broadcasting are used.

  In order to solve the above problems, a clock signal generation circuit according to a first aspect of the present invention includes an antenna that receives a radio wave supplied from the outside and converts it into an electrical signal, a variable capacitor, and a coil. A resonant circuit that extracts an AC signal having a desired frequency by performing a tuning operation on the output electrical signal, and a diode and a capacitor that have a forward voltage lower than that of a silicon diode, are extracted by the resonant circuit. A rectifying / smoothing circuit that rectifies and smoothes an alternating current signal to generate a power supply voltage and a plurality of transistors formed on the silicon substrate, and when a power supply voltage generated by the rectifying / smoothing circuit is supplied, the resonance circuit And a logic circuit for converting the alternating current signal extracted by the method into a clock signal.

  The clock signal generation circuit according to the second aspect of the present invention includes a plurality of antennas that receive radio waves supplied from the outside and convert them into electrical signals, a plurality of sets of variable capacitors and coils, A plurality of resonance circuits that respectively extract a plurality of AC signals having a desired frequency by performing a tuning operation on an electric signal output from an antenna, a plurality of diodes having a forward voltage lower than that of a silicon diode, and at least A rectifying / smoothing circuit that rectifies and smoothes a plurality of AC signals respectively extracted by a plurality of resonance circuits and generates a power supply voltage, and a plurality of transistors formed on a silicon substrate, When the power supply voltage generated by the smoothing circuit is supplied, it is extracted by one of the resonance circuits. An AC signal; and a logic circuit for converting the clock signal.

  Furthermore, the clock signal generation circuit according to the third aspect of the present invention has a primary side winding and a secondary side winding, and is AC-connected to a circuit of another device to which the primary side winding is connected. A transformer that outputs an AC signal from the combined secondary winding, a diode having a forward voltage lower than that of a silicon diode, and a capacitor, and rectifies and smoothes the AC signal output from the secondary winding of the transformer. Output from the secondary winding of the transformer when the power supply voltage generated by the rectifying and smoothing circuit is supplied. And a logic circuit for converting the AC signal to be converted into a clock signal.

  In the clock signal generation circuit according to the third aspect of the present invention, the rectifying and smoothing circuit further includes at least one diode having a forward voltage lower than that of the silicon diode, and is output from the secondary winding of the transformer. The signal may be full-wave rectified.

  In the above, the logic circuit may include an inverter that inverts and amplifies the AC signal, or a D flip-flop that inverts the level of the output signal in synchronization with the AC signal, or by dividing the clock signal. A frequency dividing circuit that generates a second clock signal having a frequency lower than that of the AC signal, and a time measuring circuit that performs a time measuring operation based on the second clock signal generated by the frequency dividing circuit may be included.

  According to the present invention, by using a logic circuit including a plurality of transistors formed on a silicon substrate and a rectifying / smoothing circuit including a diode having a forward voltage lower than that of a silicon diode, a radio broadcast It is possible to provide a clock signal generation circuit capable of efficiently generating a clock signal even if a weak radio wave is used.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a circuit diagram showing a clock signal generation circuit according to the first embodiment of the present invention. As shown in FIG. 1, the clock signal generation circuit includes an antenna 10, a capacitor C <b> 10, a resonance circuit 20, a rectifying / smoothing circuit 30, and a logic circuit 40.

  In the present embodiment, the logic circuit 40 is formed in a semiconductor integrated circuit (IC) using a silicon substrate. This IC is mounted on a controller of a general household device, and the controller stores a time measuring unit for measuring time, an input unit for inputting setting information, and setting information. And a liquid crystal display panel for displaying time, setting information, and the like. The IC includes a clock unit, a storage unit, and a control unit. Alternatively, a liquid crystal driver or the like can be incorporated. The storage unit and the control unit may be configured by a microcomputer.

  As the antenna 10, for example, a loop antenna or a bar antenna may be used, or an AC100V power supply line may be used. The antenna 10 receives radio waves such as AM radio broadcasts supplied from the outside, and converts the received radio waves into electrical signals. A capacitor C10 that allows a frequency component equal to or higher than a predetermined frequency to pass is connected between the antenna 10 and the resonance circuit 20.

  The resonance circuit 20 includes a variable capacitor C11 and a coil L11, and resonates at a specific frequency. The resonance frequency can be adjusted by changing the capacitance value of the variable capacitor C11. In this way, by tuning the electric signal output from the antenna 10, a desired frequency component specified by the resonance frequency of the resonance circuit 20 among various frequency components output from the antenna 10. Are extracted and applied to node A as a tuning signal.

The rectifying / smoothing circuit 30 includes a diode D10 and an electric field capacitor C12. The anode of the diode D10 is connected to the node A, and the cathode of the diode D10 is connected to one end of the capacitor C12. The other end of the capacitor C12 is connected to the power supply potential V _SS (in this embodiment, the ground potential). The diode D10 rectifies the tuning signal applied to the node A by the resonance circuit 20, and the electric field capacitor C12 smoothes the pulsating signal output from the diode D10. The potential smoothed by the electric field capacitor C12 is used as the power supply potential V _DD of the logic circuit 40, and the power supply voltage (V _DD −V _SS ) is supplied to the logic circuit 40.

  In the present embodiment, a germanium diode having a forward voltage lower than that of a silicon diode is used as the diode D10. In general, the forward characteristics of a silicon diode and a germanium diode are different as shown in FIG. 2, and the threshold voltage of the silicon diode is about 0.7 V, while the threshold voltage of the silicon diode is about 0.7V. 1V, which is much lower than the threshold voltage of the silicon diode. Therefore, when a tuning signal having the same amplitude is rectified, a germanium diode can generate a higher power supply voltage than a silicon diode. Alternatively, a Schottky barrier diode having a threshold voltage (about 0.2 V) lower than that of the silicon diode may be used as the diode D10.

Logic circuit 40 includes diodes D11 and D12, and a P-channel MOS transistor QP11 and an N-channel MOS transistor QN11 that form an inverter. The source of the transistor QP11 is smoothed power supply potential _{V DD} by the rectifying and smoothing circuit 30 is supplied to the source of the transistor QN11 is the power supply potential _{V SS} is supplied.

  The tuning signal applied to the node A is input to the gates of the transistors QP11 and QN11 constituting the inverter. The transistors QP11 and QN11 invert and amplify the tuning signal input to the gate, thereby converting the tuning signal into a square wave clock signal and outputting it from the drain. The output clock signal is used in a subsequent logic circuit, timing unit, storage unit, control unit, or liquid crystal driver incorporated in the IC.

The diodes D11 and D12 are protective diodes formed in the IC. The anode of the diode D11 is connected to the power supply potential _{V SS,} the cathode of the diode D11 is connected to the gate of the transistor QP11 and QN11. The anode of the diode D12 is connected to the gates of the transistors QP11 and QN11, and the cathode of the diode D12 is connected to the power supply potential V _DD .

  When a high voltage is applied to the gate of the transistor due to static electricity or the like, the withstand voltage of the gate insulating film is low, so that the transistor may be destroyed. In such a case, when the protective diode D11 or D12 is turned on, the diode forms a bypass path and serves as a high voltage protection circuit. For example, in FIG. 1, when a positive high voltage is applied to the input terminal (node A) of the IC, the diode D12 forms a bypass path, and the gate insulating films of the transistors QP11 and QN11 are protected from the high voltage. Is done.

  On the other hand, the rectifying / smoothing circuit 30 outside the IC is provided with a germanium diode D10. Since the threshold voltage of the germanium diode is lower than the threshold voltage of the silicon diode, the tuning signal applied to the node A does not pass through the protective diode D11 or D12, but passes through the germanium diode D10.

  As shown in FIG. 2, the forward characteristics of the silicon diode and the germanium diode are different, and the resistance value of the germanium diode and the resistance value of the silicon diode are reversed around the forward voltage of about 0.7V. When the forward voltage is in the vicinity of 0 V to 0.7 V, almost no current flows through the silicon diode, so the resistance value of the silicon diode is large and the resistance value of the germanium diode is small. The operation of the clock signal generation circuit already described utilizes the difference in characteristics between such a silicon diode and a germanium diode.

  On the other hand, when the forward voltage exceeds about 0.7 V, a current starts to flow steeply through the silicon diode, so that the resistance value of the silicon diode is small and the resistance value of the germanium diode is large. For example, when a high voltage is applied to the input terminal due to static electricity or the like, the silicon diode D12 is turned on and the germanium diode D10 is not turned on due to the difference in characteristics between the germanium diode and the silicon diode. In general, germanium diodes are easily destroyed by a high voltage. However, as shown in FIG. 1, it is possible to prevent the germanium diode from being destroyed by a high voltage by using the germanium diode and the silicon diode in combination.

  A household device connected by wire to a controller on which this IC is mounted operates by being supplied with an AC 100V power supply, so that a DC power supply voltage obtained based on the AC 100V power supply is also supplied to the controller. Therefore, normally, the IC can be operated by a DC power supply voltage obtained based on an AC100V power supply. In that case, a DC power supply voltage obtained based on an AC 100V power supply may be supplied to the logic circuit 40 via a backflow prevention diode.

  Even when the AC 100V power supply is not supplied due to a disaster or the like, the power supply voltage generated by the rectifying and smoothing circuit 30 is supplied to the logic circuit 40 and / or other circuits built in the IC. As a result, the minimum operation of the IC can be maintained even when the AC 100 V power supply is cut off, so that the clocking operation can be continued, the setting information can be retained, or the time and other information can be displayed. It becomes possible.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing a clock signal generation circuit according to the second embodiment of the present invention. In the logic circuit 40 of the clock signal generation circuit according to the second embodiment, a D flip-flop FF1 is provided instead of the inverter shown in FIG. Other configurations are the same as those in the first embodiment.

  As shown in FIG. 3, the tuning signal applied to the node A by the resonance circuit 20 is input to the clock signal input terminal CK of the flip-flop FF1 in the logic circuit 40. A signal output from the inverting output terminal Q bar of the flip-flop FF1 is input to the data input terminal D, and a signal output from the non-inverting output terminal Q is used as a clock signal.

  The flip-flop FF1 outputs the signal input to the data input terminal D from the non-inverted output terminal Q and the input to the data input terminal D in synchronization with the tuning signal input to the clock signal input terminal CK. The output signal is inverted and output from the inverted output terminal Q bar. Since the signal output from the inverting output terminal Q is input again to the data input terminal D, each time the potential of the tuning signal changes from low level to high level, the non-inverting output terminal Q and the inverting output terminal Q The level of the signal output from the bar is inverted. In this way, the tuning signal input to the clock signal input terminal CK is converted into a square wave clock signal. At that time, the frequency of the clock signal is half the frequency of the tuning signal.

  Note that a control signal may be supplied to a set terminal or a reset terminal (not shown) of the flip-flop FF1 in order to determine an initial state of the clock signal output from the flip-flop FF1.

Next, a third embodiment of the present invention will be described.
FIG. 4 is a circuit diagram showing a clock signal generation circuit according to the third embodiment of the present invention. In the logic circuit 40 of the clock signal generation circuit according to the third embodiment, a frequency dividing circuit 50 and a time measuring circuit 60 are provided in addition to the inverter shown in FIG. Other configurations are the same as those in the first embodiment.

  In the present embodiment, the clock signal output from the inverter constituted by the transistors QP11 and QN11 is input to the frequency dividing circuit 50. For example, when the radio wave of AM radio broadcasting is received by the antenna 10 and the tuning signal has a frequency of 1 MHz, a clock signal having a frequency of 1 MHz output from the drains of the transistors QP11 and QN11 is supplied to the frequency dividing circuit 50. Entered.

  The frequency dividing circuit 50 is configured by, for example, connecting a plurality of flip-flops connected as shown in FIG. 3 in series, and has a frequency suitable for a time measuring operation by dividing the input clock signal. A second clock signal is generated. The second clock signal generated by the frequency dividing circuit 50 is supplied to the subsequent time measuring circuit 60. The timer circuit 60 can obtain the current time by incrementing the count value in synchronization with the second clock signal. The obtained current time is displayed on the liquid crystal display panel by a liquid crystal driver built in the IC.

  As shown in FIG. 4, the clock signal generated based on the radio wave received by the antenna 10 is supplied to the clock circuit 60 through the frequency divider circuit 50, so that the clock circuit 60 generates the clock signal. Costs can be reduced by eliminating the need for a device such as quartz.

Next, a fourth embodiment of the present invention will be described.
FIG. 5 is a circuit diagram showing a clock signal generation circuit according to the fourth embodiment of the present invention. In the fourth embodiment, a plurality of antennas to a plurality of resonance circuits are used. As an example, as shown in FIG. 5, the clock signal generation circuit includes two antennas 10 and 11, two capacitors C10 and C20, two resonance circuits 20 and 21, a rectifying / smoothing circuit 70, and a logic circuit. 40. The antenna 10, the capacitor C10, the resonance circuit 20, and the logic circuit 40 are the same as those in the first embodiment shown in FIG.

  The antenna 11 may be the same type as the antenna 10 or a different type. The resonance circuit 21 includes a variable capacitor C21 and a coil L21, and resonates at a specific frequency. The resonance frequency of the resonance circuit 21 may be adjusted to be the same frequency as the resonance frequency of the resonance circuit 20 or may be adjusted to be a different frequency.

  The rectifying / smoothing circuit 70 includes germanium diodes D10 and D20 and an electric field capacitor C12. The anode of the diode D20 is connected to the resonance circuit 21, and the cathode of the diode D20 is connected to one end of the capacitor C12 together with the cathode of the diode D10. The rectifying operation by these diodes D10 and D20 and the smoothing operation by the capacitor C12 are the same as described with reference to FIG.

  In the present embodiment, a signal obtained by adding the pulsating flow signal output from the germanium diode D10 and the pulsating flow signal output from the germanium diode D20 is smoothed by the capacitor C12. Therefore, the capacitor C12 can be charged more quickly and the clock signal can be output than the clock signal generation circuit shown in FIG. In the logic circuit 40, a flip-flop is used instead of the inverter as shown in FIG. 3, and a frequency divider circuit 50 and a time measuring circuit 60 are connected to the subsequent stage of the inverter as shown in FIG. It is good also as a structure.

Next, a fifth embodiment of the present invention will be described.
FIG. 6 is a circuit diagram showing a clock signal generation circuit according to the fifth embodiment of the present invention. As shown in FIG. 6, this clock signal generation circuit includes input terminals P1 and P2 connected to an external AC signal source, a transformer 80, a rectifying / smoothing circuit 90, and a logic circuit 40.

  The transformer 80 has a primary side winding 81 and a secondary side winding 82 wound around a core. The rectifying / smoothing circuit 90 includes diodes D31 to D34 and a capacitor C12. The diodes D31 to D34 constitute a diode bridge, and full-wave rectifies the AC signal generated in the secondary winding 82 of the transformer.

  In the present embodiment, the portion constituted by the antenna, the capacitor, and the resonance circuit in the first to fourth embodiments is constituted by the transformer 80. An external AC signal source is connected to the controller on which the IC is mounted, and an AC signal supplied from the AC signal source is input to the input terminals P1 and P2 of the clock signal generation circuit.

  In FIG. 6, the connection between the AC signal source and the rectifying / smoothing circuit 90 and the logic circuit 40 via the transformer 80 is a connection form generally referred to as non-contact power transmission. The smoothing circuit 30 is electromagnetically coupled, but is physically insulated.

  When an AC signal supplied from an AC signal source is applied to the primary winding 81 of the transformer, an AC voltage is induced in the secondary winding 82 of the transformer by electromagnetic coupling. The induced AC voltage is rectified and smoothed by the diodes D31 to D34 and the capacitor C12 and supplied to the logic circuit 40 as a power supply voltage.

  The AC signal source used in the present embodiment may be any AC signal source as long as it has sufficient frequency stability to generate a clock signal. For example, a carrier wave transmitted over a network cable used for computer network communication can be used. In that case, a pulse transformer generally used to insulate and protect the computer from noise applied to the cable at the interface between the computer and the network cable is used as the transformer 80 shown in FIG. May be.

  In FIG. 6, a rectifying / smoothing circuit 90 including diodes D31 to D34 is shown to perform full-wave rectification. However, as in the first embodiment shown in FIG. 1, one diode that performs half-wave rectification is shown. A rectifying / smoothing circuit including may be used.

1 is a circuit diagram showing a clock signal generation circuit according to a first embodiment of the present invention. The figure which shows the forward direction characteristic of a silicon diode and a germanium diode. The circuit diagram which shows the clock signal generation circuit which concerns on the 2nd Embodiment of this invention. The circuit diagram which shows the clock signal generation circuit which concerns on the 3rd Embodiment of this invention. The circuit diagram which shows the clock signal generation circuit which concerns on the 4th Embodiment of this invention. The circuit diagram which shows the clock signal generation circuit which concerns on the 5th Embodiment of this invention.

Explanation of symbols

  10, 11 Antenna, 20, 21 Resonant circuit, 30, 70, 90 Rectifier smoothing circuit, 40 Logic circuit, 50 Divider circuit, 60 Clock circuit, 80 Transformer, 81 Primary winding, 82 Secondary winding, C10 to C21 capacitor, L11, L21 coil, D10 to D34 diode, QN11 N channel MOS transistor, QP11 P channel MOS transistor, FF1 D flip-flop

Claims (6)

An antenna that receives radio waves supplied from outside and converts them into electrical signals;
A resonance circuit that includes a variable capacitor and a coil, and extracts an AC signal having a desired frequency by performing a tuning operation on the electric signal output from the antenna;
A rectifying / smoothing circuit including a diode having a forward voltage lower than that of a silicon diode and a capacitor, and rectifying and smoothing an AC signal extracted by the resonance circuit to generate a power supply voltage;
A logic circuit that includes a plurality of transistors formed on a silicon substrate and converts an AC signal extracted by the resonance circuit into a clock signal when a power supply voltage generated by the rectifying and smoothing circuit is supplied;
A clock signal generation circuit comprising: A plurality of antennas that receive radio waves supplied from outside and convert them into electrical signals;
A plurality of resonant circuits including a plurality of sets of variable capacitors and coils, respectively, for extracting a plurality of AC signals having desired frequencies by performing a tuning operation on the electrical signals output from the plurality of antennas;
A rectifying / smoothing circuit including a plurality of diodes having a forward voltage lower than that of a silicon diode and at least one capacitor, and rectifying and smoothing a plurality of AC signals respectively extracted by the plurality of resonance circuits to generate a power supply voltage When,
An AC signal extracted by one of the plurality of resonance circuits is used as a clock signal when a power supply voltage generated by the rectifying and smoothing circuit is supplied, which is composed of a plurality of transistors formed on a silicon substrate. Logic circuit to convert,
A clock signal generation circuit comprising: A transformer having a primary side winding and a secondary side winding and outputting an AC signal from a secondary side winding that is AC-coupled to a circuit of another device to which the primary side winding is connected;
A rectifying and smoothing circuit that includes a diode having a forward voltage lower than that of a silicon diode and a capacitor, rectifies and smoothes an AC signal output from the secondary side winding of the transformer, and generates a power supply voltage;
An AC signal output from the secondary winding of the transformer is converted into a clock signal when a power supply voltage generated by the rectifying and smoothing circuit is supplied, which is constituted by a plurality of transistors formed on a silicon substrate. Logic circuit;
A clock signal generation circuit comprising:   The clock according to claim 3, wherein the rectifying and smoothing circuit further includes at least one diode having a forward voltage lower than that of a silicon diode, and full-wave rectifies an AC signal output from the secondary winding of the transformer. Signal generation circuit.   5. The clock signal according to claim 1, wherein the logic circuit includes an inverter that inverts and amplifies the AC signal, or a D flip-flop that inverts the level of an output signal in synchronization with the AC signal. Generation circuit. The logic circuit divides the clock signal to generate a second clock signal having a frequency lower than that of the AC signal, and a second clock generated by the frequency divider circuit The clock signal generation circuit according to claim 1, further comprising a timing circuit that performs a timing operation based on the signal.

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