JP2008034767A - Storage medium and semiconductor integrated circuit for evaluation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it easy to detect short circuit and disconnection of an semiconductor integrated circuit, and evaluate the semiconductor manufacturing process in a short period of time, thus improving its yield. <P>SOLUTION: By using a redundant wiring cell RWLDc11 for evaluating disconnections in a long wiring pattern using evaluation redundant wiring design information 11 of an evaluation semiconductor integrated circuit 14_1, and a redundant wiring cell RWLSt1 for evaluating short circuit in an adjacent wiring pattern; sensitivity of wiring disconnection and short circuit is improved to easily evaluate a semiconductor manufacturing process. If the wiring cell RWLDc11 is disconnected, signal supplies to functional circuits Cell 11, 12 are terminated; and if the wiring cell RWLSt1 shortcircuits, signal levels of mutually independent circuit nodes N_11 and N_12 of the functional circuits Cell 11, 12 become approximately the same level. The wiring cell RWLDc11 has a meander shape, and the wiring cell RWLSt1 has a shape of two comb-like wiring pattern where teeth of combs are mutually intricate. If the redundant wiring cell is deleted, design information 10_1 for mass production is obtained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an evaluation semiconductor integrated circuit and a storage medium storing design information thereof, and more particularly to a technique suitable for an evaluation semiconductor integrated circuit used for evaluation of a semiconductor production line and yield improvement.

  Non-Patent Document 1 below describes a method of detecting short-circuit and disconnection defects in an LSI interconnection process. Electrical resistance measurement using a mechanical probing pad is performed for short-circuiting and disconnection detection, and voltage contrast measurement using a scanning electron microscope is performed for accurate position detection of short-circuiting and disconnection.

Yuichi Hamamura et al, “An Advanced Defect-Monitoring Structure Structure for Electrical Measurement and Defect Localization”, 2003 Int'l. 47-52

  Prior to the present invention, the present inventors engaged in trial development for mass production of highly integrated semiconductor integrated circuits utilizing a novel semiconductor manufacturing process.

  When developing this prototype, it is necessary to evaluate new semiconductor manufacturing processes, make necessary improvements, reach high manufacturing yields in a short time, and tune semiconductor integrated circuit designs to new semiconductor manufacturing processes in a short period of time. It was.

  The method for detecting defects in short-circuiting and disconnection of LSI wiring described in Non-Patent Document 1 is suitable for research and basic development of semiconductor integrated circuits because defects can be detected accurately. However, with this detection method, in trial development for mass production of a semiconductor integrated circuit that requires speed, the detection operation is complicated, and an expensive device called a scanning electron microscope is required.

  Accordingly, it is an object of the present invention to facilitate the detection of short circuits and disconnections of a semiconductor integrated circuit during development of the semiconductor integrated circuit, and to improve the yield by evaluating the semiconductor manufacturing process in a short period of time.

  Another object of the present invention is to tune the design of a semiconductor integrated circuit to a new semiconductor manufacturing process in a short period of time.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one aspect of the present invention, layout information of a plurality of functional circuits (Cell11... Cell22) constituting a core, layout information of disconnection evaluation redundant wiring cells (RWLDc11...), And short-circuit evaluation redundant wiring cells ( This is a storage medium (14) that stores evaluation semiconductor design information (14_1) including layout information of RWLSt1.

  In the layout of the semiconductor integrated circuit for evaluation based on the layout information of the semiconductor design information for evaluation (14_1), the plurality of functional circuits (Cell11 ... Cell22) each have a substantially rectangular shape and the plurality of functional circuits (Cell11). ... Cell 22) is arranged with at least a predetermined separation interval, and the disconnection evaluation redundant wiring cell (Cell 22) is arranged in a region between the plurality of functional circuits (Cell11 ... Cell22) arranged with the separation interval. RWLDc11... And the short-circuit evaluation redundant wiring cell (RWLSt1...) Are arranged.

  The disconnection evaluation redundant wiring cells (RWLDc11...) Transmit signals to two functional circuits (Cell11, Cell21...) Of the plurality of functional circuits, and the short circuit evaluation redundant wiring cells (RWLSt1...) The two functional circuits (Cell11, Cell12...) Of the plurality of functional circuits are connected to two independent circuit nodes (N_11, N_12...).

  The disconnection evaluation redundant wiring cell (RWLDc11...) Is longer than the separation distance between the plurality of functional circuits (Cell11... Cell22) and any side of the square of the plurality of functional circuits (Cell11... Cell22). It has a wiring pattern.

  The redundant wiring cell for short-circuit evaluation (RWLSt1...) Is longer than the separation distance between the plurality of functional circuits (Cell11... Cell22) and any one side of the square of the plurality of functional circuits (Cell11... Cell22). It has two wirings adjacent to each other having a long wiring pattern, and the adjacent distance between the two wirings of the redundant wiring cell for short-circuit evaluation (RWLSt1...) Is the plurality of functional circuits (Cell11... Cell22 ) And a distance shorter than any one of the square sides of the plurality of functional circuits (Cell11... Cell22) (see FIGS. 1 and 2).

  According to the means of the one embodiment, the disconnection evaluation redundant wiring cell (RWLDc11...) Having a long wiring pattern remarkably improves the disconnection sensitivity (disconnection probability) of the wiring due to the insulating foreign material and the short circuit evaluation. Two adjacent long wiring patterns of the redundant wiring cells (RWLSt1...) Can significantly improve the sensitivity (short circuit probability) of the wiring short circuit due to the conductive foreign matter, and can easily evaluate the semiconductor manufacturing line. When the disconnection evaluation redundant wiring cell (RWLDc11...) Is disconnected, the signal is not supplied to the two functional circuits (Cell11, Cell21) and the short circuit evaluation redundant wiring cell (RWLSt1...) Is short-circuited. The signal levels of the two circuit nodes (N_11, N12) independent of each other of the two functional circuits (Cell11, Cell12) are substantially the same level.

  In the storage medium (14) according to one preferred embodiment of the present invention, the long wiring pattern of the disconnection evaluation redundant wiring cell (RWLDc11...) Has a meandering shape, and the short circuit evaluation redundant wiring cell (RWLSt1...) It has two comb-shaped wiring pattern shapes in which comb teeth are intertwined with each other.

  According to the one preferred mode, the disconnection evaluation redundant wiring cell (RWLDc11...) And the short circuit evaluation redundant wiring cell (RWLSt1...) Are compactly formed on a semiconductor chip of the evaluation semiconductor integrated circuit. Can be arranged in.

  In the storage medium (14) according to one more preferable aspect of the present invention, each of the plurality of functional circuits (Cell11 ... Cell22) includes a storage element (Inv1_11, Inv2_11 ... Inv1_22, Inv2_22), and the plurality of functional circuits ( The two functional nodes (N_11, N12) of the two functional circuits (Cell11, Cell12) of the Cell11 ... Cell22) are information storage nodes of the storage elements (Inv1_11, Inv2_11 ... Inv1_12, Inv2_12).

  In the storage medium (14) according to one more preferable aspect of the present invention, each of the plurality of functional circuits (Cell11 ... Cell22) includes a storage element (Inv1_11, Inv2_11 ... Inv1_22, Inv2_22), a switch (SW_11, SW22), and Including a memory cell. The storage elements (Inv1_11, Inv2_11 ... Inv1_22, Inv2_22) of the memory cells of the plurality of functional circuits (Cell11 ... Cell22) are connected to a data line (DL31) via the switches (SW_11, SW22). The switches (SW_11, SW21) of the memory cells of the plurality of functional circuits (Cell11... Cell22) are driven by the address signal of the word line (WL21) via the disconnection evaluation redundant wiring cells (RWLDc11, RWLDc21...). Is done. The two independent circuit nodes (N_11, N12) of the two functional circuits (Cell11, Cell12) of the plurality of functional circuits (Cell11 ... Cell22) are information on the memory cells (Inv1_11, Inv2_11 ... Inv1_12, Inv2_12). It is a storage node.

  In the storage medium (14) according to one more preferable aspect of the present invention, a part of the wiring of the disconnection evaluation redundant wiring cell is constituted by a via wiring connecting a plurality of wiring layers.

  In the storage medium (14) according to one more preferable mode of the present invention, each of the plurality of functional circuits (CPU1, CPU2) further includes a logic circuit (ID & ALU1, ID & ALU2) (see FIG. 17).

  A semiconductor integrated circuit for evaluation according to another embodiment of the present invention includes a plurality of functional circuits (Cell11... Cell22) constituting a core, a redundant wiring cell for disconnection evaluation (RWLDc11...), And a redundant wiring cell for short circuit evaluation ( RWLSt1 ...) on the semiconductor chip.

  Each of the plurality of functional circuits (Cell11... Cell22) has a substantially quadrangular shape, and the plurality of functional circuits (Cell11... Cell22) are arranged with at least a predetermined separation interval and separated with the separation interval. The disconnection evaluation redundant wiring cell (RWLDc11...) And the short circuit evaluation redundant wiring cell (RWLSt1...) Are disposed in a region between the plurality of functional circuits (Cell11... Cell22).

  The disconnection evaluation redundant wiring cells (RWLDc11...) Transmit signals to two functional circuits (Cell11, Cell21...) Of the plurality of functional circuits, and the short circuit evaluation redundant wiring cells (RWLSt1...) The two functional circuits (Cell11, Cell12...) Of the plurality of functional circuits are connected to two independent circuit nodes (N_11, N_12...).

  The disconnection evaluation redundant wiring cell (RWLDc11...) Is longer than the separation distance between the plurality of functional circuits (Cell11... Cell22) and any side of the square of the plurality of functional circuits (Cell11... Cell22). It has a wiring pattern.

  The redundant wiring cell for short-circuit evaluation (RWLSt1...) Is longer than the separation distance between the plurality of functional circuits (Cell11... Cell22) and any one side of the square of the plurality of functional circuits (Cell11... Cell22). It has two wirings adjacent to each other having a long wiring pattern, and the adjacent distance between the two wirings of the redundant wiring cell for short-circuit evaluation (RWLSt1...) Is the plurality of functional circuits (Cell11... Cell22 ) And a distance shorter than any one of the square sides of the plurality of functional circuits (Cell11... Cell22) (see FIGS. 1 and 2).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, when developing a semiconductor integrated circuit, it is possible to easily detect a short circuit and disconnection of the semiconductor integrated circuit, and to evaluate the semiconductor manufacturing process in a short period of time and improve the yield.

  Further, according to the present invention, the design of the semiconductor integrated circuit can be tuned to a new semiconductor manufacturing process in a short period of time.

≪Storage media used for design of semiconductor integrated circuit for evaluation≫
FIG. 1 is a diagram showing a computer system for designing an evaluation semiconductor integrated circuit according to an embodiment of the present invention.

  As shown in the figure, basic core design information 10_1 of a semiconductor integrated circuit as a developed product is stored in the first storage medium 10, and a semiconductor manufacturing line of a semiconductor integrated circuit as a developed product is stored in the second storage medium 11. Redundant wiring design information for evaluation 11_1 used for evaluation is stored.

  The basic core design information 10_1 stored in the first storage medium 10 includes, for example, a plurality of memory cells Cell11 ... Cell22, a plurality of word lines WL21 and WL22, and a plurality of data lines DL31 and DL32 constituting a memory core on a semiconductor wafer. It includes mask pattern data for manufacturing. The core as a functional block starts with a software module in which the function of the core as the first functional block is described in a description language such as HDL (Hardware Description Language). Next, from this description language, a netlist describing the electrical connections between a plurality of circuits is generated using an automatic logic synthesis tool. Thereafter, a VLSI pattern layout design is performed by an automatic wiring program using standard cells from the net list. In particular, in a place where high performance is required, a new macro cell based on a new handwritten design may be used instead of a standard cell. As described above, the basic core design information 10_1 is a hardware module or hardware IP (Intellectual Property) including the mask pattern data of the core as a functional block.

  As usual, in the basic core design information 10_1, the plurality of cells Cell11 ... Cell22 are formed in the lowest layer of the semiconductor chip, the plurality of word lines WL21, WL22 are formed in the intermediate layer, and the plurality of data lines DL31, DL32 are formed. Formed on the top layer. Further, as usual, in order to increase the integration density of the semiconductor integrated circuit, in the basic core design information 10_1, the inter-cell pitch of the plurality of cells Cell11. The pitch between the plurality of word lines WL21 and WL22 and the plurality of data lines DL31 and DL32 by the multilayer wiring is also minimized.

  The basic core design information 10_1 includes a mask pattern for forming a P well in a CMOS process, a mask pattern for forming an N well, a mask pattern for forming a gate insulating film for an N-channel or P-channel MOSFET, and a gate electrode for an N-channel or P-channel MOSFET. Mask pattern for forming, mask pattern for forming source / drain regions of N-channel and P-channel MOSFETs, P-well contact hole to first interlayer insulating film, N-well contact hole, gate contact hole, source-drain contact It includes information such as a mask pattern for forming an opening such as a hole, and a mask pattern for forming a pattern for the first layer wiring M1_Wire of the multilayer wiring.

  The evaluation redundant wiring design information 11_1 stored in the second storage medium 11 is characteristic design information of the present invention, and includes the disconnection evaluation redundant wiring cells RWLDc11... And the short circuit evaluation redundant wiring cells RWLSt1. Yes. This is because the manufacturing process that greatly affects the yield in the semiconductor manufacturing line is a wiring formation process of the semiconductor integrated circuit. In order to increase the integration density of semiconductor integrated circuits, the pitch between lines of the wiring is often minimized and the wiring width of the lower layer wiring is also minimized. Under such conditions, the wiring may be short-circuited or disconnected due to conductive foreign matter or insulating foreign matter in the wiring formation process, the previous interlayer insulating film forming process, or the contact hole opening process to the interlayer insulating film. .

  The disconnection evaluation redundant wiring cell RWLDc11 of the evaluation redundant wiring design information 11_1 has a wiring pattern of a wiring path that is much longer than the shortest path such as the inter-cell pitch of the plurality of cells Cell11. ing. This disconnection evaluation redundant wiring cell RWLDc11... Remarkably improves the disconnection sensitivity (disconnection probability) of the wiring due to the insulating foreign matter, and facilitates the evaluation of the semiconductor production line. As a more preferred embodiment of the present invention, the long wiring pattern of the disconnection evaluation redundant wiring cell RWLDc11 can be arranged in a compact size on the semiconductor chip by having a meandering shape.

  The redundant wiring cell RWLSt1 for short-circuit evaluation in the redundant wiring design information 11_1 for evaluation has two wirings adjacent to each other at an opposing wiring distance that is far longer than the longitudinal distance of the rectangular cell shape of the plurality of cells Cell11. is doing. The adjacent distance between the two wires is set to be shorter than the inter-cell pitch between the plurality of cells Cell11. This redundant wiring cell for short-circuit evaluation RWLSt1... Remarkably improves the short-circuit sensitivity (short-circuit probability) of the wiring due to the conductive foreign matter, thereby facilitating the evaluation of the semiconductor production line. As a more preferred embodiment of the present invention, the short-circuit evaluation redundant wiring cells RWLSt1... Are arranged in a compact size on a semiconductor chip by having two comb-shaped wiring pattern shapes in which comb teeth are intertwined with each other. Can.

  The disconnection evaluation redundant wiring cell RWLDc11 and the short circuit evaluation redundant wiring cell RWLSt1... Of the evaluation redundant wiring design information 11_1 are the second layer wiring M2_Wire, the third layer wiring M3_Wire,... Higher than the first layer wiring M1_Wire of the multilayer wiring. It is formed by either.

  As shown in FIG. 1, a processor 12_1 of a computer 12, such as an engineering workstation, has basic core design information 10_1 stored in a first storage medium 10 and a second storage medium 11 via a disk drive of an input circuit 12_3. Can be read from the evaluation redundant wiring design information 11_1. A main memory 12_2, an input circuit 12_3, an output circuit 12_4, and a hard disk driver 12_5 are connected to the processor 12_1 via a bus.

  A designer who designs a semiconductor integrated circuit for evaluation controls the computer 12 by operating the input device 13_1 such as a keyboard while viewing the screen of the display device 13_2. The designer looks at the screen of the display device 13_2 and has a basic core including a plurality of cells Cell11 ... Cell22, a plurality of word lines WL21 and WL22, and a plurality of data lines DL31 and DL32 integrated on a semiconductor chip at a high integration density. The disconnection evaluation redundant wiring cells RWLDc11... And the short circuit evaluation redundant wiring cells RWLSt1... Selected from the evaluation redundant wiring design information 11_1 are incorporated in the layout pattern of the design information 10_1. As a result, the disconnection evaluation redundant wiring cell RWLDc11 of the evaluation redundant wiring design information 11_1 and the short circuit evaluation redundant wiring cell RWLSt1... Are incorporated in the middle region of the plurality of cells Cell11... Cell22 of the basic core design information 10_1. Evaluation semiconductor design information 14_1 having a layout pattern is formed in the main memory 12_2 of the computer 12 or the hard disk driver 12_5. The designer copies the evaluation semiconductor design information 14_1 to the external storage device 13_3, whereby the third storage medium 14 storing the evaluation semiconductor design information 14_1 is created in the external storage device 13_3.

  By reading the third storage medium 14 with a mask pattern generator, it is possible to manufacture a mask pattern for trial manufacture of a semiconductor integrated circuit. By using this mask pattern in the production or trial production line, the trial production of the semiconductor integrated circuit, the evaluation of the semiconductor production line, and the yield improvement are performed. If necessary, feedback is made to the basic core design information 10_1, and the development of the semiconductor integrated circuit is advanced to complete the tuned basic core design information 10_1. A mask pattern for mass production of the semiconductor integrated circuit is manufactured from the completed basic core design information 10_1, and mass production of the semiconductor integrated circuit is started.

  It should be noted that the above-described trial manufacture, evaluation, and tuning by design change can be performed on the evaluation semiconductor design information 14_1 stored in the third storage medium 14. When tuning is completed, the basics tuned for mass production in which the disconnection evaluation redundant wiring cells RWLDc11... And the short circuit evaluation redundant wiring cells RWLD1... Of the evaluation redundant wiring design information 11_1 are deleted from the evaluation semiconductor design information 14_1. Core design information 10_1 can be obtained.

<Configuration of evaluation semiconductor integrated circuit>
FIG. 2 is a circuit layout diagram (evaluation semiconductor design information 14_1 under FIG. 1) showing a part of the evaluation semiconductor integrated circuit according to one embodiment of the present invention.

  As shown in the figure, each of the plurality of functional circuits Cell11... Cell22 has a substantially rectangular shape, and the plurality of functional circuits Cell11... Cell22 are arranged with at least a predetermined spacing. The disconnection evaluation redundant wiring cell RWLDc11... And the short circuit evaluation redundant wiring cell RWLSt1... Are arranged in a region between the plurality of functional circuits Cell11. The redundant wiring cell RWLDc11 for disconnection evaluation transmits signals to the two functional circuits Cell11 and Cell21 of the plurality of functional circuits, and the redundant wiring cell RWLSt1 for short circuit evaluation includes two functional circuits Cell11 of the plurality of functional circuits, The cell 12 is connected to two independent circuit nodes N_11 and N_12.

  The redundant wiring cell RWLDc11 for disconnection evaluation has a wiring pattern longer than the separation distance between the plurality of functional circuits Cell11... Cell22 and any side of the square of the plurality of functional circuits Cell11.

  Redundant wiring cells for short-circuit evaluation (RWLSt1...) Are two adjacent to each other having a wiring pattern longer than a separation distance between the plurality of functional circuits Cell11... Cell22 and a square side of the plurality of functional circuits Cell11. The adjacent distance between the two wirings of the short-circuit evaluation redundant wiring cell RWLSt1... Is set shorter than any one of the square sides of the plurality of functional circuits Cell11.

  As shown in the figure, a plurality of cells Cell11 ... Cell22 are flip-flops composed of two inverters Inv1_11, Inv2_12 ... Inv1_22, Inv2_22, a switch SW_11 ... SW_22, and an inverter Inv3_11 ... Inv3_22 connected in a cross direction. Are arranged in an array along the word lines WL21 and WL22 and the horizontal data lines DL31 and DL32. For example, the switch SW_11 is configured by parallel connection of an N-channel MOSFET and a P-channel MOSFET, the gate of the N-channel MOSFET is connected to the input of the inverter Inv3_11, and the output of the inverter Inv3_11 is connected to the gate of the P-channel MOSFET. When the gate of the N-channel MOSFET becomes high level and the N-channel MOSFET is turned on, the output of the inverter Inv3_11 becomes low level, the P-channel MOSFET is also turned on, and the switch SW_11 is turned on. One node of two inverters Inv1_11, Inv2_12... Inv1_22, Inv2_22 connected in a cross couple is an input / output terminal of a flip-flop connected to the data lines DL31, DL32 via the switch SW_11 ... SW_22, and the other node N_11 ... N_22 is an independent circuit node. The circuit nodes N_11... N_22 are driven only by the cross-coupled inverters Inv1_11, Inv2_12 ... Inv1_22, Inv2_22.

  By activating the word line WL21 to a high level, the switches SW_11 and SW21 of the memory cells Cell11 and Cell21 are turned on, so that the memory cells Cell11 and Cell21 can be read and written.

  At the time of reading, the data stored in the memory cells Cell11 and Cell21 is output to the data lines DL31 and DL32 by activating the word line WL21 to a high level, respectively. At the time of writing, by activating the word line WL21 to a high level, the levels of the data lines DL31 and DL32 become new storage data of the memory cells Cell11 and Cell21.

  In the evaluation semiconductor integrated circuit according to one embodiment of the present invention shown in FIG. 2, the disconnection evaluation redundant wiring RWLDc11... RWLDc22 and the short-circuit evaluation redundant wiring RWLSt1. ing.

  The signal of the vertical word line WL21 is supplied to the 2-bit memory cells Cell11 and Cell21 adjacent in the vertical direction via a series connection of two disconnection evaluation redundant wirings RWLDc11 and RWLDc21, and the other vertical word lines The signal of WL22 is supplied to the 2-bit memory cells Cell12 and Cell22 adjacent in the vertical direction via a series connection of two disconnection evaluation redundant wirings RWLDc12 and RWLDc21.

  The short circuit evaluation redundant wiring RWLSt1 is connected to the circuit nodes N_11 and N12 independent of each other. The short-circuit evaluation redundant wiring RWLSt1 is two comb-shaped wirings facing each other and adjacent to each other, one connected to the circuit node N_11 and the other connected to the circuit node N12. Similarly, the short-circuit evaluation redundant wiring RWLSt2 is connected to the circuit nodes N_21 and N22 independent of each other. The short-circuit evaluation redundant wiring RWLSt2 is two comb-shaped wirings that face each other and are adjacent to each other. One is connected to the circuit node N_21 and the other is connected to the circuit node N22. The independent circuit nodes N_21 and N22 function as information storage nodes for the memory cells Cell21 and Cell22.

  The four disconnection evaluation redundant wirings RWLDc11... RWLDc22 are formed in a wiring pattern meandering longer than the shortest path. As a result, when the degree of cleanliness of the semiconductor manufacturing line or the semiconductor manufacturing apparatus is insufficient, the signal wiring such as the word line, the data line, and the clock line is disconnected by the foreign matter. Four disconnection evaluation redundant wirings RWLDc11... RWLDc22 meandering longer than the shortest path remarkably improve the sensitivity of disconnection (disconnection probability) due to foreign matters due to insufficient cleanliness, and facilitate evaluation of the semiconductor manufacturing line.

  The two short-circuit evaluation redundant wirings RWLSt1 and RWLSt2 are composed of comb-shaped wirings facing each other in this way. As a result, when the degree of cleanliness of the semiconductor manufacturing line or the semiconductor manufacturing apparatus is insufficient, two adjacent signal lines such as a word line, a data line, and a clock line are short-circuited by the foreign matter. Two redundant wirings for short-circuit evaluation RWLSt1 and RWLSt2 composed of comb-shaped wirings facing each other remarkably improve the sensitivity of short-circuiting due to foreign matters due to insufficient cleanliness (short-circuit probability), and evaluate semiconductor manufacturing lines Make it easy.

  FIG. 3 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention.

  The difference between the circuit layout shown in FIG. 3 and the circuit layout shown in FIG. 2 will be described below.

  In the figure, the signal of the word line WL21 is connected via the inverter INV_1 and the four short-circuit evaluation redundant wirings RWLSt3, the disconnection evaluation redundant wiring RWLDc12, the short-circuit evaluation redundant wiring RWLD4, and the disconnection evaluation redundant wiring RWLDc11. Supplied to the 2-bit memory cells Cell11 and Cell21 adjacent in the vertical direction, the signals of the other word lines WL22 are the inverter INV_2, four short-circuit evaluation redundant wirings RWLSt3, the disconnection evaluation redundant wiring RWLDc13, and the short-circuit evaluation redundant wiring. RWSt4 is supplied to the 2-bit memory cells Cell12 and Cell22 adjacent in the vertical direction via the serial connection of the disconnection evaluation redundant wiring RWLDc14.

  In the serial connection of the four short-circuit evaluation redundant wirings RWSt3, the disconnection evaluation redundant wiring RWLDc12, the short-circuit evaluation redundant wiring RWLSt4, and the disconnection evaluation redundant wiring RWLDc11, the two short-circuit evaluation redundant wirings RWSt3 and RWSt4 are connected to the shortest path. The wiring pattern is meandering for a long time. Further, two disconnection evaluation redundant wirings RWLDc12 and RWLDc11 reciprocate between the 2-bit memory cells Cell11 and Cell21 adjacent in the vertical direction. As a result, when the degree of cleanliness of the semiconductor manufacturing line or the semiconductor manufacturing apparatus is insufficient, the signal wiring such as the word line, the data line, and the clock line is disconnected by the foreign matter. The two short-circuit evaluation redundant wirings RWLDc12 and RWLDc11 that reciprocate between the two short-circuit evaluation redundant wirings RWLSt3 and RWLSt4 meandering longer than the shortest path and the 2-bit memory cells Cell11 and Cell21 adjacent in the vertical direction The sensitivity (disconnection probability) of disconnection due to foreign matter due to shortage is remarkably improved, and the evaluation of the semiconductor production line is facilitated.

  Even when the four short-circuit evaluation redundant wirings RWSt3, the disconnection evaluation redundant wiring RWLDc13, the short-circuit evaluation redundant wiring RWLDc4, and the disconnection evaluation redundant wiring RWLDc14 are connected in series, the two short-circuit evaluation redundant wirings RWLSt3 and RWSt4 are connected through the shortest path. The wiring pattern is meandering for a long time. Further, the two disconnection evaluation redundant wirings RWLDc13 and RWLDc14 reciprocate between the 2-bit memory cells Cell12 and Cell22 adjacent in the vertical direction. As a result, when the degree of cleanliness of the semiconductor manufacturing line or the semiconductor manufacturing apparatus is insufficient, the signal wiring such as the word line, the data line, and the clock line is disconnected by the foreign matter. The two short-circuit evaluation redundant wirings RWLDc13 and RWLDc14 that reciprocate between the two short-circuit evaluation redundant wirings RWLSt3 and RWLSt4 and the 2-bit memory cells Cell12 and Cell22 vertically adjacent to each other longer than the shortest path The sensitivity (disconnection probability) of disconnection due to foreign matter due to shortage is remarkably improved, and the evaluation of the semiconductor production line is facilitated.

  Further, in the short circuit evaluation redundant wirings RWLSt3 and RWLSt4, the wiring connected to the output of the inverter INV_1 and the wiring connected to the output of the inverter INV_2 are arranged adjacent to each other. As a result, when the degree of cleanliness of the semiconductor manufacturing line or the semiconductor manufacturing apparatus is insufficient, two adjacent signal lines such as a word line, a data line, and a clock line are short-circuited by the foreign matter. The adjacent short-circuit evaluation redundant wirings RWLSt3 and RWLSt4 that are formed adjacent to each other remarkably improve the sensitivity (short-circuit probability) of a short circuit due to a foreign matter due to insufficient cleanliness, and facilitate the evaluation of the semiconductor production line.

  FIG. 4 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention.

  The layout of the circuit shown in FIG. 4 is different from the layout of the circuit shown in FIG. 3 in that the wiring connected to the output of the inverter INV_1 in the short circuit evaluation redundant wirings RWLSt3 and RWLSt4 meanders long as shown in FIG. Instead of a wiring pattern, it is branched into comb-shaped wirings.

  FIG. 5 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to still another embodiment of the present invention.

  In the figure, two memory cells Cell11 and Cell12 are respectively composed of flip-flops FF11 and FF12 and output buffers OB11 and OB12. The data inputs D of the flip-flops FF11 and FF12 are connected to the write data lines WDL31 and WDL32, the write sampling inputs T of the flip-flops FF11 and FF12 are connected to the write word line WWL21, and the data output Q of the flip-flops FF11 and FF12 is supplied. The read sampling inputs of the output buffers OB11 and OB12 are connected to the read word line RWL21.

  In FIG. 5, in particular, the write sampling input T of the flip-flop FF11 is connected to the write word line WWL21 via the disconnection evaluation redundant wiring RWLDc11, and the write sampling input T of the flip-flop FF12 is flip-flopped via the disconnection evaluation redundant wiring RWLDc12. The circuit node N_11 of the data output Q of the flip-flop FF11 and the circuit node N_12 of the data output Q of the flip-flop FF12 are connected to the write sampling input T of the flip-flop FF11, and are short-circuited composed of adjacent comb-shaped wirings. The redundant wiring for evaluation RWLSt1 is connected to one wiring and the other wiring. The disconnection evaluation redundant wirings RWLDc11 and RWLDc12 and the short circuit evaluation redundant wiring RWLSt1 significantly improve the sensitivity of disconnection (disconnection probability) due to foreign matter due to insufficient cleanliness and the sensitivity of short circuit (short circuit probability) to evaluate the semiconductor manufacturing line. Can be made easy.

  6, the same arrangement structure as the plurality of cells Cell11... Cell22, the disconnection evaluation redundant wiring RWLDc11... RWLDc22, and the short-circuit evaluation redundant wiring RWLSt1. It is a figure which shows 256-Kbit evaluation SRAM as a semiconductor integrated circuit for evaluation. Between the four memory arrays MA1... MA4, an X decoder X-DEC for driving a word line, a Y decoder Y-DEC for selecting a bit line, and a control circuit CC are arranged in a cross shape.

  FIG. 7 is a diagram showing a layout of one cell Cell11 of the plurality of cells Cell11... Cell22 shown in FIG.

  This figure shows the gate electrode Gate of a plurality of MOSFETs (the vertical thin lines in FIG. 7) and the lowermost first wiring layer M1_Wire (a plurality of wirings shown by the right-down diagonal lines in FIG. 7). ing. An N-type well NWELL in which a P-channel MOSFET is formed is formed on the line A-A ′, and a P-type well PWELL in which an N-channel MOSFET is formed is formed on the line A-A ′. 7 includes two inverters Inv1_11 and Inv2_12 that are cross-coupled to one cell Cell11. A switch SW_11 of one cell Cell11 is formed in the approximate center of FIG. 6, and the right side of FIG. An inverter Inv3_11 is formed. A contact hole N_11_CH for the circuit node N_11 is formed in the first interlayer insulating film formed on the first wiring layer in the two inverters Inv1_11 and Inv2_12 arranged on the left side of FIG. A contact hole DL31_CH for connection to the data line DL31 is formed in the switch SW_11 disposed substantially in the center in the first interlayer insulating film, and the inverter Inv3_11 disposed on the right side of FIG. 7 is connected to the word line WL21. Contact hole WL21_CH is formed in the first interlayer insulating film. 7 includes two inverters Inv1_11 and Inv2_12, a switch SW_11, and a power supply voltage wiring for supplying a power supply voltage VDD to the source of the P-channel MOSFET of the inverter Inv3. The lower part of FIG. 6 includes two inverters Inv1_11 and Inv2_12. , A switch SW_11 and a ground wiring for supplying the ground voltage VSS to the source of the N-channel MOSFET of the inverter Inv3 are disposed.

  FIG. 8 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention.

  The arrangement of the circuit shown in FIG. 8 is different from the arrangement of the circuit shown in FIG. 2 in that the signal of the vertical word line WL21 is supplied to the memory cell Cell11 via the disconnection evaluation redundant wiring RWLDc11. The output signal of the redundant wiring RWLDc11 is further supplied to the memory cell Cell12 via the disconnection evaluation redundant wiring RWLDc12, and the other vertical word line WL22 signal is supplied to the memory cell Cell21 via the disconnection evaluation redundant wiring RWLDc21. Then, the output signal of the disconnection evaluation redundant wiring RWLDc21 is further supplied to the memory cell Cell22 via the disconnection evaluation redundant wiring RWLDc22, and one of the comb wirings adjacent to each other of the short-circuit evaluation redundant wiring RWLDc1 Are the circuit node N_11 of the memory cell Cell11 and the memory cell Cell21. One and the other of the comb-shaped wirings that are connected to the circuit node N_21 and are opposite to each other and adjacent to the short circuit evaluation redundant wiring RWLSt2 are connected to the circuit node N_12 of the memory cell Cell12 and the circuit node N_22 of the memory cell Cell22. It is that you are. Further, the memory cells Cell11 and Cell21 are connected to the data line DL31, and the memory cells Cell12 and Cell22 are connected to the data line DL32.

  FIG. 9 is a plan view on the chip of the semiconductor integrated circuit for evaluation based on the layout of the circuit shown in FIG.

  9, the memory cell Cell11 is arranged at the upper left, the memory cell Cell21 is arranged at the upper right, the memory cell Cell22 is arranged at the lower right, and the memory cell Cell21 is arranged at the lower left.

  The two word lines WL21 and WL22 are formed in the row direction by the second wiring layer M2_Wire. The word line WL21 is connected to the word line contact hole WL21_CH11 of the upper left memory cell Cell11 via a disconnection evaluation redundant wiring RWLDc11 having a meandering wiring pattern arranged from the upper right to the upper left of FIG. 8, and the word line contact hole WL21_CH11 is connected to the word line WL21. It is connected to the word line contact hole WL21_CH12 of the upper right memory cell Cell12 via a disconnection evaluation redundant wiring RWLDc12 having a straight wiring pattern in the right direction. The word line WL22 is connected to the word line contact hole WL21_CH21 of the lower left memory cell Cell21 via the disconnection evaluation redundant wiring RWLDc21 having the meandering wiring pattern arranged from the lower right to the lower left in FIG. 8, and the word line contact hole WL21_CH21. Is connected to the word line contact hole WL22_CH22 of the memory cell Cell22 at the lower right through a disconnection evaluation redundant wiring RWLDc22 having a straight wiring pattern in the right direction. Further, the disconnection evaluation redundant wirings RWLDc11 and RWLDc21 having the meandering wiring pattern and the disconnection evaluation redundant wirings RWLDc12 and RWLDc22 having the straight wiring pattern are formed by the second wiring layer M2_Wire.

  The two data lines DL31 and DL32 are formed in the column direction by the third wiring layer M3_Wire. The left data line DL31 is connected to the upper left memory cell Cell11 via the data line contact hole DL31_CH11 and is connected to the lower left memory cell Cell21 via the data line contact hole DL31_CH21, and the right data line DL32 is connected to the upper right memory cell. The cell Cell12 is connected via the data line contact hole DL31_CH12 and is connected to the lower right memory cell Cell22 via the data line contact hole DL31_CH22. Short circuit evaluation redundant wirings RWLSt1 and RWLSt2 configured by the third wiring layer M3_Wire are formed in the column direction at substantially the center between the two left and right data lines DL31 and DL32. One and the other of the adjacent comb-shaped wirings of the central left short circuit evaluation redundant wiring RWLSt1 are connected to the circuit node N_11 of the upper left memory cell Cell11 and the circuit node N_21 of the lower left memory cell Cell21, respectively. One and the other of the adjacent comb-shaped wirings of the right short circuit evaluation redundant wiring RWLSt2 are connected to the circuit node N_21 of the upper right memory cell Cell21 and the circuit node N_22 of the lower right memory cell Cell22. .

  FIG. 10 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention.

  The circuit layout shown in FIG. 10 is different from the circuit layout shown in FIG. 2 in that the signal of the vertical word line WL21 is supplied to the memory cell Cell21 via the disconnection evaluation redundant wiring RWLDc21. The output signal of the redundant wiring RWLDc21 is further supplied to the memory cell Cell11 via the disconnection evaluation redundant wiring RWLDc11, and the other vertical word line WL22 signal is supplied to the memory cell Cell22 via the disconnection evaluation redundant wiring RWLDc22. The output signal of the disconnection evaluation redundant wiring RWLDc22 is further supplied to the memory cell Cell12 via the disconnection evaluation redundant wiring RWLDc12, and one of the comb wirings adjacent to each other of the shorting evaluation redundant wiring RWLDc1 Is the circuit node N_11 of the memory cell Cell11 and the memory cell Cell1. One of the comb wirings facing each other and adjacent to the short circuit evaluation redundant wiring RWLSt2 is connected to the circuit node N_21 of the memory cell Cell21 and the circuit node N_22 of the memory cell Cell22. It is that. Further, the memory cells Cell11 and Cell12 are connected to the data line DL31, and the memory cells Cell21 and Cell22 are connected to the data line DL32.

  FIG. 11 is a diagram showing a plan view on the chip of the semiconductor integrated circuit for evaluation based on the layout of the circuit shown in FIG.

  In FIG. 11, the memory cell Cell11 is arranged at the upper left, the memory cell Cell21 is arranged at the upper right, the memory cell Cell22 is arranged at the lower right, and the memory cell Cell12 is arranged at the lower left.

  The two word lines WL21 and WL22 are formed in the row direction by the second wiring layer M2_Wire. Between the upper and lower two word lines WL21 and WL22, one of the comb wirings adjacent to each other of the short-circuit evaluation redundant wiring RWLSt2 formed by the second wiring layer M2_Wire is the upper right memory cell Cell21. Is connected to the circuit node N_21 of the lower right memory cell Cell22 via the contact hole RWLSt2_CH22 and the wiring LN_22 formed by the third wiring layer M3_Wire. Under the word line WL22, one of the comb wirings facing and adjacent to each other in the short-circuit evaluation redundant wiring RWLSt1 formed by the second wiring layer M2_Wire is connected to the circuit node N_12 of the upper left memory cell Cell12. The other is connected to the circuit node N_11 of the upper left memory cell Cell11 through the contact hole RWLSt2_CH11 and the wiring LN_11 formed by the third wiring layer M3_Wire.

  The word line WL21 formed by the second wiring layer M2_Wire is formed by the third wiring layer M3_Wire via the word line contact hole WL21_CH formed in the vicinity of the upper left memory cell Cell21 in FIG. One end of the disconnection evaluation redundant wiring RWLDc21 having the meandering wiring pattern is connected, and the other end of the disconnection evaluation redundant wiring RWLDc21 is connected to the upper right memory cell Cell21 via the word line contact hole WL21_CH21. The word line contact hole WL21_CH21 of the upper right memory cell Cell21 is connected to the upper left memory cell Cell11 via the disconnection evaluation redundant wiring RWLDc11 having the linear wiring pattern formed by the third wiring layer M3_Wire and the word line contact hole WL21_CH11. It is connected to the.

  Similarly, the word line WL22 formed by the second wiring layer M2_Wire is connected to the third wiring layer M3_Wire via the word line contact hole WL22_CH formed in the vicinity of the lower left memory cell Cell12 in FIG. One end of the disconnection evaluation redundant wiring RWLDc22 having the meandering wiring pattern formed is connected, and the other end of the disconnection evaluation redundant wiring RWLDc22 is connected to the lower right memory cell Cell22 via the word line contact hole WL22_CH22. The word line contact hole WL22_CH22 of the lower right memory cell Cell22 is connected to the lower left memory cell via the disconnection evaluation redundant wiring RWLDc22 having a linear wiring pattern formed by the third wiring layer M3_Wire and the word line contact hole WL21_CH22. It is connected to Cell22.

  The two data lines DL31 and DL32 are formed in the column direction by the third wiring layer M3_Wire. The left data line DL31 is connected to the upper left memory cell Cell11 via the data line contact hole DL31_CH11 and is connected to the lower left memory cell Cell12 via the data line contact hole DL31_CH12, and the right data line DL32 is connected to the upper right memory cell. It is connected to the cell Cell21 via the data line contact hole DL31_CH21 and is connected to the lower right memory cell Cell22 via the data line contact hole DL31_CH22. In the approximate center between the two left and right data lines DL31 and DL32, the disconnection evaluation redundant wirings RWLDc21 and RWLDc22 having a meandering wiring pattern constituted by the third wiring layer M3_Wire and the disconnection having a straight wiring pattern Redundant wirings for evaluation RWLDc11 and RWLDc12 and wirings LN_11 and LN_22 are formed.

  Redundant lines for short-circuit evaluation RWLSt1 and RWLSt2 are formed in the column direction. One and the other of the adjacent comb-shaped wirings of the central left short circuit evaluation redundant wiring RWLSt1 are connected to the circuit node N_11 of the upper left memory cell Cell11 and the circuit node N_21 of the lower left memory cell Cell21, respectively. One and the other of the adjacent comb-shaped wirings of the right short circuit evaluation redundant wiring RWLSt2 are connected to the circuit node N_21 of the upper right memory cell Cell21 and the circuit node N_22 of the lower right memory cell Cell22. .

  FIG. 12 shows an algorithm for evaluating a fail bit of a 256 Kbit SRAM in which a plurality of memory cells of the evaluation semiconductor device according to each embodiment of the present invention described above are arranged in the X direction and 512 in the Y direction, respectively. It is a figure explaining.

  In the figure, after starting in step S01, in step S02, initial values Xi and Yi of the X direction address and Y direction address are set and an initial value Di (data of “0” bit) of the write data D is set. Via step S03, the non-inverted data D of the initial value Di is written in the memory cell in step S04. In step S05, the Y-direction address is incremented by +1 and the inverted data / D of the initial value Di is written to the memory cell. In step S06, it is determined whether or not the Y-direction address is the final Y-direction address Yf (512). If not, the process returns to step S03. When step S04 and step S06 are repeated until the Y-direction address is determined to be the final Y-direction address Yf (512) in step S06, initial values from the initial Y-direction address Yi in the lower left of FIG. 12 to the final Y-direction address Yf are obtained. “0” -bit data and “1” -bit data are alternately written in 512 memory cells of the X-direction address Xi. If it is determined in step S06 that the Y-direction address is the final Y-direction address Yf (512), the X-direction address is incremented by 1 in step S07 and the inverted data / D is written to the memory cell. In step S08, it is determined whether or not the X-direction address is the final X-direction address Xf (512). If not, the process returns to step S03. Until the X-direction address is determined to be the final X-direction address Xf (512) in step S08, when the processing from step S04 to step S07 is repeated, a 256-Kbit SRAM in which 512 in the X direction and 512 in the Y direction are arranged. Data is written to all of the memory cells.

  In step S09, the X-direction address and the Y-direction address are returned to the initial values Xi and Yi, the data in the memory cell is read in step S11 via step S10, and the read data from the memory cell is stored in the memory cell in step S12. It is determined whether or not the data to be written matches, and if they do not match, the error direction E is output as error E, and the X-direction address and Y-direction address of the defective memory cell are output in step S17. If no error E occurs in step S12, the Y-direction address is incremented by 1 in step S13, and it is determined in step S14 whether the Y-direction address is the final Y-direction address Yf (512). Return to. When the processing from step S10 to step S13 is repeated until the Y-direction address is determined to be the final Y-direction address Yf (512) in step S14, the initial Y-direction address Yi at the lower left in FIG. 12 to the final Y-direction address Yf. Data is read from 512 memory cells at the initial X direction address Xi. If it is determined in step S14 that the Y direction address is the final Y direction address Yf (512), the Y direction address is returned to the initial value Yi in step S15, and the X direction address is incremented by +1. In step S16, it is determined whether or not the X direction address is the final X direction address Xf (512). If not, the process returns to step S10. Until the X-direction address is determined to be the final X-direction address Xf (512) in step S16, when the processing from step S10 to step S15 is repeated, a 256-Kbit SRAM in which 512 in the X direction and 512 in the Y direction are arranged. The presence or absence of all errors E in the memory cell can be confirmed.

  The first process at the lower right in FIG. 12 is a process of writing data into the memory cell as described above and confirming whether or not there is an error E in the read data. In the second process, the address opposite to the first write is performed. Data is written so that the bits adjacent to each other in the X direction and the Y direction in the order are inverted. In the second processing, after all bits are written, data is read in the same order as the writing, and if the read data is different from the data written to the same bits, an error is assumed. If an error occurs in either of the above two writes, the memory cell of that bit is determined to be defective.

  FIG. 13 is a diagram for explaining a procedure for detecting a short circuit failure due to conductive foreign matter using the evaluation semiconductor integrated circuit shown in FIG.

  A conductive foreign object FM electrically connects one wiring of the comb wiring and the other wiring of the redundant wiring RWLSt2 for short-circuit evaluation adjacent to each other in the short circuit evaluation redundant wiring RWLSt2 connected to the circuit nodes N_21 and N_22 of the memory cells Cell21 and Cell22. Is short-circuited. When the first data is written by the same algorithm as the fail bit evaluation algorithm shown in FIG. 12, “1” bit is written in the left memory cell Cell21 in the first write, but the short-circuit evaluation redundant wiring RWLSt2 When the “0” bit is written in the right memory cell Cell22 because the comb wiring is short-circuited, the “0” bit is also written in the left memory cell Cell21 due to the influence. Next, when data is written for the second time by the same algorithm as the fail bit evaluation algorithm shown in FIG. 11, the order of writing is reversed, so that the “1” bit is written to the right memory cell Cell22. However, when a “0” bit is written in the left memory cell Cell21, a “0” bit is also written in the right memory cell Cell22 because the comb wiring of the short-circuit evaluation redundant wiring RWLSt2 is short-circuited. Therefore, when the results of the two readings are combined, a short circuit of the comb wiring of the short circuit evaluation redundant wiring RWLSt2 is detected as a pair bit failure of the adjacent two memory cells Cell21 and Cell22.

  FIG. 14 is a diagram for explaining a procedure for detecting a short-circuit failure caused by an insulating foreign material using the evaluation semiconductor integrated circuit shown in FIG.

  Since the insulating foreign substance FM forms a disconnection (electrical outage) in the disconnection evaluation redundant wiring RWLDc21 between the two memory cells Cell11 and Cell21, the signal of the left word line WL21 is transmitted to the two memory cells Cell11. , Is not transmitted to Cell21.

  When the first data is written by the same algorithm as in FIG. 12, in the first writing, “1” bit is written to the lower memory cell Cell 21 and “0” bit is written to the upper memory cell Cell 11. Since the signal of the word line WL21 does not reach the two memory cells Cell11 and Cell21, writing to the two memory cells cannot be performed. Next, when the second data is written by the same algorithm as in FIG. 11, the order of writing is reversed, so that the upper memory cell Cell11 has “1” bits and the lower memory cell Cell21 has “0” bits. However, since the signal of the word line WL21 does not reach the two memory cells Cell11 and Cell21, the two memory cells cannot be written. The write data is inverted between the first and second times, and the expected values of the two memory cells Cell11 and Cell21 are both “1” bits and “0” bits. The disconnection of the evaluation redundant wiring RWLDc21 is detected as a pair bit defect of the two memory cells Cell11 and Cell21.

  FIG. 15 is a circuit layout diagram showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention.

  As shown in the figure, the address signal of the word line WL21 is supplied to the four memory cells Cell11, Cell21, Cell31, and Cell41 through the serial connection of the four disconnection evaluation redundant wirings RWLDc11, RWLDc21, RWLDc31, and RWLDc41. The address signal of the word line WL22 is supplied to the four memory cells Cell12, Cell22, Cell32, and Cell42 via the serial connection of the four disconnection evaluation redundant wirings RWLDc12, RWLDc22, RWLDc32, and RWLDc42. Therefore, if the four disconnection evaluation redundant wirings RWLDc11, RWLDc21, RWLDc31, and RWLDc41 are connected in series or the four disconnection evaluation redundant wirings RWLDc12, RWLDc22, RWLDc32, and RWLDc42 are disconnected in series, the four memory cells Cell11, Cell 21, Cell 31, Cell 41, or four memory cells Cell 12, Cell 22, Cell 32, and Cell 42 can be observed as continuous defects of 4 bits.

  FIG. 16 is a circuit layout diagram showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention.

  As shown in the figure, each of the four memory cells includes a dynamic random access memory (DRAM) memory cell including a switch MOS transistor and a capacitor. The address signal of the word line WL21 is supplied to the gates of the switch MOS transistors of the DRAM cells Cell11 and Cell21 via the disconnection evaluation redundant wiring RWLDc11, and the address signal of the word line WL22 is supplied to the DRAM cell Cell12 via the disconnection evaluation redundant wiring RWLDc12. , Is supplied to the gate of the switch MOS transistor of Cell22. The information storage node N_11 at one end of the capacity of the DRAM cell Cell11 and the information storage node N_12 at one end of the capacity of the DRAM cell Cell12 are connected to one and the other of the two short-circuit evaluation redundant wirings RWLSt1, and the capacity of the DRAM cell Cell21. The information storage node N_21 at one end and the information storage node N_22 at one end of the capacity of the DRAM cell Cell22 are connected to one and the other of the two short-circuit evaluation redundant wirings RWLSt2.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, as the plurality of memory cells, flash type nonvolatile memory cells can be used in addition to SRAM type and DRAM type memory cells.

  Further, a part of the wiring of the disconnection evaluation redundant wiring cell may be constituted by a via wiring connecting a plurality of wiring layers. As a result, the redundant wiring cell for disconnection evaluation has a structure such as a so-called via chain or contact chain constituted by more wiring layers than the minimum necessary wiring layers.

  FIG. 17 is a layout diagram of a microprocessor unit MPU which is a semiconductor integrated circuit for evaluation according to another embodiment of the present invention.

  As shown in the figure, the semiconductor chip of the microprocessor unit MPU includes two central processing units CPU1, CPU2, a read only memory ROM, a random access memory RAM, a bus control unit BSC, an input / output port I / O_Port, and peripherals. Device PD. The instruction decoder / arithmetic logic units ID & ALU1 and ID & ALU2 in the two central processing units CPU1 and CPU2 and the register files Reg_F1 and Reg_F2 are connected to the disconnection evaluation redundant wirings RWLDc1 and RWLDc2, and the Reg_F1 and Reg_F2 The information storage nodes of one flip-flop FF1 are connected to the short-circuit evaluation redundant wiring RWLSt1, the information storage nodes of the second flip-flop FF2 are connected to the short-circuit evaluation redundant wiring RWLSt2, and the N-th flip-flops FFN are connected to each other. The information storage nodes are connected to the short-circuit evaluation redundant wiring RWLStN. The central processing unit CPU1 is connected to the first CPU bus CPU_Bus1 via the disconnection evaluation redundant wiring RWLDc3, and the central processing unit CPU2 is connected to the second CPU bus CPU_Bus2 via the disconnection evaluation redundant wiring RWLDc4.

  The first CPU bus CPU_Bus1 and the second CPU bus CPU_Bus2 include a read-only memory ROM that stores programs executed by the two central processing units CPU1 and CPU2, and random data that stores work data of the two central processing units CPU1 and CPU2. An access memory RAM is connected. Similar to FIG. 2, the random access memory RAM includes a plurality of disconnection evaluation redundant wirings and a plurality of short circuit evaluation redundant wirings.

  Using the semiconductor chip of the evaluation semiconductor integrated circuit of the microprocessor unit MPU shown in FIG. 17, the semiconductor manufacturing line is evaluated and the yield is improved, tuning is performed, and the process development and trial production are completed. Thereafter, the computer system shown in FIG. 1 is used to delete the disconnection evaluation redundant wiring cell and the short circuit evaluation redundant wiring cell of the evaluation redundant wiring design information 11_1 from the evaluation semiconductor design information 14_1. Basic core design information 10_1 tuned for mass production of the processor unit MPU can be obtained.

FIG. 1 is a diagram showing a computer system for designing an evaluation semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to one embodiment of the present invention. FIG. 3 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention. FIG. 4 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention. FIG. 5 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to still another embodiment of the present invention. FIG. 6 shows a 256-Kbit evaluation SRAM as an evaluation semiconductor integrated circuit in which the same arrangement structure as the plurality of cells, the disconnection evaluation redundant wiring, and the short-circuit evaluation redundant wiring shown in FIG. 2 is arranged in four memory arrays. FIG. FIG. 7 is a diagram showing a layout of one of the plurality of cells shown in FIG. FIG. 8 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention. FIG. 9 is a plan view on the chip of the semiconductor integrated circuit for evaluation based on the layout of the circuit shown in FIG. FIG. 10 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention. FIG. 11 is a diagram showing a plan view on the chip of the semiconductor integrated circuit for evaluation based on the layout of the circuit shown in FIG. FIG. 12 shows an algorithm for evaluating a fail bit of a 256 Kbit SRAM in which a plurality of memory cells of the evaluation semiconductor device according to each embodiment of the present invention described above are arranged in the X direction and 512 in the Y direction, respectively. It is a figure explaining. FIG. 13 is a diagram for explaining a procedure for detecting a short circuit failure due to conductive foreign matter using the evaluation semiconductor integrated circuit shown in FIG. FIG. 14 is a diagram for explaining a procedure for detecting a short-circuit failure caused by an insulating foreign material using the evaluation semiconductor integrated circuit shown in FIG. FIG. 15 is a circuit layout showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention. FIG. 16 is a circuit layout diagram showing a part of an evaluation semiconductor integrated circuit according to another embodiment of the present invention. FIG. 17 is a layout view of a microprocessor unit which is a semiconductor integrated circuit for evaluation according to another embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Basic core design information 11 Redundant wiring design information for evaluation 12 Computer 14 Semiconductor design information for evaluation Cell11 ... Cell22 Multiple functional circuits RWLDc11 ... Redundant wiring cell for disconnection evaluation RWLSt1 ... Redundant wiring cell for short circuit evaluation

Claims (14)

Memory in which evaluation semiconductor design information including layout information of a plurality of functional circuits constituting the core, layout information of redundant wiring cells for disconnection evaluation, and layout information of redundant wiring cells for short-circuit evaluation is stored so as to be readable by a computer A medium,
In the layout of the semiconductor integrated circuit for evaluation based on the layout information of the semiconductor design information for evaluation, each of the plurality of functional circuits has a substantially quadrangular shape, and the plurality of functional circuits are arranged with at least a predetermined separation interval. The disconnection evaluation redundant wiring cell and the short circuit evaluation redundant wiring cell are disposed in a region between the plurality of functional circuits that are spaced apart with the separation interval,
The disconnection evaluation redundant wiring cell transmits a signal to two functional circuits of the plurality of functional circuits, and the short circuit evaluation redundant wiring cell is an independent 2 of the two functional circuits of the plurality of functional circuits. Connected to one circuit node,
The disconnection evaluation redundant wiring cell has a wiring pattern longer than the separation distance between the plurality of functional circuits and any one side of the square of the plurality of functional circuits,
The redundant wiring cell for short circuit evaluation has two wirings adjacent to each other having a wiring pattern longer than the separation distance between the plurality of functional circuits and the one side of the square of the plurality of functional circuits. The adjacent distance between the two wirings of the redundant wiring cell for short-circuit evaluation is determined based on the separation distance between the plurality of functional circuits and one of the sides of the square of the plurality of functional circuits. Also a short storage medium.   The storage medium according to claim 1, wherein the long wiring pattern of the disconnection evaluation redundant wiring cell has a meandering shape, and the short circuit evaluation redundant wiring cell has two comb-shaped wiring pattern shapes in which comb teeth are intertwined with each other. .   One end and the other end of the long wiring pattern of the redundant wiring cell for disconnection evaluation are respectively connected to a main line and the two functional circuits to which the signals of the plurality of functional circuits are transmitted. The storage medium according to claim 2, wherein the signal of the line is transmitted to the two functional circuits through the long wiring pattern of the disconnection evaluation redundant wiring cell. Each of the plurality of functional circuits includes a storage element,
4. The storage medium according to claim 1, wherein the two circuit nodes independent of each other of the two functional circuits of the plurality of functional circuits are information storage nodes of the storage element. 5. Each of the plurality of functional circuits includes a memory cell including a storage element and a switch,
The storage element of the memory cell of the plurality of functional circuits is connected to a data line through the switch;
The switches of the memory cells of the plurality of functional circuits are driven by an address signal of a word line via the disconnection evaluation redundant wiring cell,
4. The storage medium according to claim 1, wherein the two circuit nodes independent of each other of the two functional circuits of the plurality of functional circuits are information storage nodes of the memory cells. 5.   The storage medium according to any one of claims 1 to 6, wherein a part of the wiring of the disconnection evaluation redundant wiring cell is configured by a via wiring that connects a plurality of wiring layers.   The storage medium according to claim 4, wherein each of the plurality of functional circuits further includes a logic circuit. A plurality of functional circuits constituting a core, a redundant wiring cell for disconnection evaluation, and a redundant wiring cell for short circuit evaluation are provided on a semiconductor chip,
Each of the plurality of functional circuits has a substantially quadrangular shape, and the plurality of functional circuits are arranged with at least a predetermined separation interval, and the plurality of functional circuits are arranged with separation with the separation interval. The redundant wiring cell for disconnection evaluation and the redundant wiring cell for short circuit evaluation are arranged in a region between
The disconnection evaluation redundant wiring cell transmits a signal to two functional circuits of the plurality of functional circuits, and the short circuit evaluation redundant wiring cell is an independent 2 of the two functional circuits of the plurality of functional circuits. Connected to one circuit node,
The disconnection evaluation redundant wiring cell has a wiring pattern longer than the separation distance between the plurality of functional circuits and any one side of the square of the plurality of functional circuits,
The redundant wiring cell for short circuit evaluation has two wirings adjacent to each other having a wiring pattern longer than the separation distance between the plurality of functional circuits and the one side of the square of the plurality of functional circuits. The adjacent distance between the two wirings of the redundant wiring cell for short-circuit evaluation is determined based on the separation distance between the plurality of functional circuits and one of the sides of the square of the plurality of functional circuits. A semiconductor integrated circuit for evaluation that is set to be shorter.   9. The evaluation according to claim 8, wherein the long wiring pattern of the redundant wiring cell for disconnection evaluation has a meandering shape, and the redundant wiring cell for short circuit evaluation has a shape of two comb-shaped wiring patterns in which comb teeth are entangled with each other. Semiconductor integrated circuit.   One end and the other end of the long wiring pattern of the redundant wiring cell for disconnection evaluation are respectively connected to a main line and the two functional circuits to which the signals of the plurality of functional circuits are transmitted. 10. The evaluation semiconductor integrated circuit according to claim 9, wherein the signal of the line is transmitted to the two functional circuits via the long wiring pattern of the disconnection evaluation redundant wiring cell. Each of the plurality of functional circuits includes a storage element,
11. The evaluation semiconductor integrated circuit according to claim 8, wherein the two circuit nodes independent of each other of the two functional circuits of the plurality of functional circuits are information storage nodes of the storage element. Each of the plurality of functional circuits includes a memory cell including a storage element and a switch,
The storage element of the memory cell of the plurality of functional circuits is connected to a data line through the switch;
The switches of the memory cells of the plurality of functional circuits are driven by an address signal of a word line via the disconnection evaluation redundant wiring cell,
11. The evaluation semiconductor integrated circuit according to claim 8, wherein the two circuit nodes independent of each other of the two functional circuits of the plurality of functional circuits are information storage nodes of the memory cells.   14. The evaluation semiconductor integrated circuit according to claim 8, wherein a part of the wiring of the disconnection evaluation redundant wiring cell is configured by a via wiring connecting a plurality of wiring layers.   The evaluation semiconductor integrated circuit according to claim 11, wherein each of the plurality of functional circuits further includes a logic circuit.

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