JP2008027522A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve both of an efficiency of write operation and a reduction of write disturb in a nonvolatile memory. <P>SOLUTION: The nonvolatile memory includes a memory array and a parallel write restriction circuit. The memory array has nonvolatile memory cells, in which a write voltage is applied from a write selection word line according to an address signal in the write operation and also a write current is supplied from a transistor (TR6) switching controlled by a write selection bit line and the parallel write restriction circuit according to logical values of write data. The parallel write restriction circuit restricts the bit lines to which the write current flows in parallel, according to difference in write unit. A sequencer applies the write voltage while successively changing over the range of the plurality of bit lines by reducing the range in several times when the write unit is large and also applies the write voltage in the frequency smaller than the above steps by increasing the range of the plurality of bit lines when the write unit is small. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an improvement in write operation efficiency and write disturb in an electrically erasable and writable nonvolatile memory, for example, a technique effective when applied to a microcomputer in which the nonvolatile memory and a central processing unit are on-chip. .

  In an electrically erasable and writable nonvolatile memory, in a write operation to a nonvolatile memory having a charge storage region, a write voltage is applied to a word line and a write current is supplied to a write selection bit line to generate hot electrons. The threshold voltage can be increased by injecting electrons accelerated thereby into the charge storage region. At this time, the write voltage is applied to the nonvolatile memory cell of the write unselected bit line that shares the write selected word line with the nonvolatile memory cell of the write selected bit line. Due to the high electric field, the threshold voltage may fluctuate undesirably. In order to suppress such word disturb, it is possible to limit the range in which the write voltage is applied by separating the word lines in the middle of the write operation. Patent Document 1 describes such a countermeasure against disturbance.

Japanese Unexamined Patent Publication No. 2000-149581

  If the range of a plurality of bit lines through which the write current can flow in parallel increases in the hot electron write, the write current supplied to the write selection bit line requires a large write current supply capability accordingly. For example, when 1024 (128 bytes) bit lines cross a word line, which is a unit for applying a write voltage, hot electron writing is performed in a state where a write current can flow through all the bit lines in accordance with 1024-bit write data. For this reason, it is uneconomical because a power supply circuit having a large current supply capacity is required. Therefore, also in the word line batch writing, the unit in which the write current can flow in parallel with respect to the 1024 bit lines is set to 128 bit lines, for example, and the unit is sequentially switched 8 times to all the bit lines. On the other hand, a writing procedure for enabling writing can be adopted. The unit of the 128 bit lines, which is a unit capable of flowing a write current in parallel, is determined by the relationship with the current supply capability of the power supply circuit. However, in such a word line batch write procedure, even when 1 byte of data is rewritten, a write voltage is repeatedly applied to the word line to be written eight times, resulting in a decrease in write efficiency. In addition, the nonvolatile memory cells of the write unselected bit line are subjected to excessive word disturb.

  On the other hand, when a write operation that restricts the write data of the write operation to a small number of bits is employed, writing of the required number of bits can be completed by applying a single write voltage, improving the write efficiency, It is possible to minimize the influence of disturbance. At this time, it is convenient to limit the number of data bits targeted for one write operation to the number of parallel interface data bits with the outside in consideration of usability. However, when the number of data bits to be subjected to one write operation is less than 128 bits, writing to a non-volatile memory cell for one word line using such a write operation results in the write operation. The number of repetitions increases, and the adverse effect of word disturb increases compared to the case where word line batch writing is adopted, and the writing efficiency also decreases.

  An object of the present invention is to provide a semiconductor device capable of improving both the write operation efficiency and the write disturb reduction in a nonvolatile memory.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor device according to the present invention includes an electrically erasable and writable nonvolatile memory. The nonvolatile memory has a memory array and a parallel write limiting circuit. In the memory array, a write voltage is applied from a word line (MGL) selected for writing according to an address signal in a write operation, and writing is performed via a bit line (BL) selected for writing according to a logical value of write data. It has a plurality of nonvolatile memory cells to which current is supplied. The parallel write limiting circuit (the whole of FIG. 9) limits the range of a plurality of bit lines through which a write current flows in parallel according to the difference in write unit. When the write unit is large, the sequencer (10) applies the write voltage while reducing the range of the multiple bit lines and switching the range of the multiple bit lines in several steps, and when the write unit is small. Increases the range of the plurality of bit lines and applies the write voltage fewer times than the above. As a result, both the write operation efficiency and the write disturb reduction in the nonvolatile memory can be improved depending on whether the write unit is large or small.

  As one specific form of the present invention, a data latch (DLAT) that latches write data for each bit line and a column that can selectively connect a data line and a data latch assigned to each of a plurality of data latches. A first switch transistor (TR5) for selectively opening and closing a write current path of a corresponding bit line according to a logic value of a storage node of the data latch; and a second switch transistor arranged in series with the first switch transistor (TR6). At this time, the parallel write limiting circuit includes a first operation (128-byte write mode) for sequentially switching a range of a plurality of bit lines for turning on the second switch transistors in parallel, and the second switch for all the bit lines. The second operation (8-byte write mode) for turning on the transistors in parallel can be selected. Thereby, it is possible to simplify the circuit configuration for limiting the range in which the write current can flow depending on whether the write unit is large or small. In particular, when the write unit is large, the configuration is suitable for the case where the first operation is performed by storing the write data in the data latch in advance within that range.

  As a more specific form of the present invention, the sequencer selects the first operation or the second operation in response to the type of the write command. Instruction from the outside becomes easy.

  As a more specific mode of the present invention, the sequencer clears all the data latches to a write non-selected logic value in a write operation in response to a write command, and then starts a write data latch operation. When the write unit is small, it is easy to prevent the undesired write current from flowing in the write unselected bit line in the operation of applying the write voltage with a small number of times by increasing the range of the multiple bit lines. can do.

  As a more specific form of the present invention, the sequencer determines the maximum number (first number) of the data latches in which write data can be latched in the second operation, and the second switch transistor in the first operation. The number is smaller than the number (second number) of the plurality of bit lines that are turned on in parallel. The second number is determined, for example, by the relationship with the current supply capability of the power supply circuit. The first number is limited to, for example, the number of parallel interface data bits with the outside.

  As a more specific form of the present invention, a third switch transistor connected in series to the first switch transistor and the second switch transistor is provided. The sequencer sets the mutual conductance of the third switch transistor to be larger in the second operation than in the first operation, and increases the write current. As a result, even when the second operation is repeated and writing is performed at the same scale as the first operation, the amount of data to be written once is small in the second operation, so that the current supply of the first operation is not exceeded. .

  [2] A semiconductor device according to the present invention includes an electrically erasable and writable nonvolatile memory. The non-volatile memory includes a memory array, a parallel write limiting circuit, a write current limiting circuit, and a sequencer. The memory array is supplied with a write voltage from a word line selected for writing according to an address signal in a write operation and supplied with a write current via a bit line selected for writing according to a logical value of write data. Non-volatile memory cells. The parallel write limiting circuit (the whole of FIG. 9) limits the range of a plurality of bit lines through which a write current flows in parallel according to the size of the write unit. The write current limiting circuit (31, 38) limits the write current according to the size of the write unit. The sequencer (10) increases the write current by the current limiting circuit per bit line when a small write unit is designated, compared to when a large write unit is designated. As described above, when writing is repeatedly performed in a small writing unit in the same range as the large writing unit, the writing current per bit line by the current limiting circuit is increased, and the writing is repeated several times. The application time for each word line voltage can be shortened. Therefore, writing efficiency can be improved even when writing in small writing units is repeated.

  As one specific form of the present invention, when the write unit is large, the sequencer applies a write voltage while switching the range of the plurality of bit lines in order by decreasing the range of the plurality of bit lines and dividing the range several times. When the write unit is small, the range of the plurality of bit lines is enlarged and the write voltage is applied less than the above. As a result, both the write operation efficiency and the write disturb reduction in the nonvolatile memory can be improved depending on whether the write unit is large or small.

  As one specific form of the present invention, a central processing unit capable of accessing the nonvolatile memory cell is provided, and the central processing unit issues the write command.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, both the write operation efficiency and the write disturb reduction in the nonvolatile memory can be improved.

  FIG. 2 shows a microcomputer (MCU) 1 which is an example of a semiconductor device according to the present invention. The microcomputer 1 is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique or the like. The microcomputer 1 includes a central processing unit (CPU) 2, a RAM 3 as a volatile memory, a flash memory (FLASH) 4 as a nonvolatile memory, a direct memory access controller (DMAC) 5, an input / output port (PRT) ) 6, 7, timer (TMR) 8, clock generator (CPG) 9, etc., and these circuit modules are connected to the internal bus BUS. The internal bus BUS includes bus signal lines for address, data, and control signals. The CPU 2 includes an instruction control unit and an execution unit, decodes the fetched instruction, and performs arithmetic processing according to the decoding result. The flash memory 4 stores an operation program and data for the CPU 2. The RAM 3 is a work area or a data temporary storage area of the CPU 2. A clock pulse generator 9 inputs a clock or system clock generated by an oscillation operation in accordance with the resonance frequency of an external crystal resonator, generates an internal clock that is phase-synchronized with the system clock by a PLL circuit, and the microcomputer 1 It is operated in synchronization with the clock and its divided clock. Access to the flash memory 4 is controlled by the CPU 2, and operation modes such as erasing and writing are controlled based on commands issued by the CPU 2 to the sequencer (SQUEC) 10.

  FIG. 3 illustrates the device structure of the nonvolatile memory cell of the flash memory 4 and the basic structure of the memory array. The nonvolatile memory cell MC includes a p-type well region 12 provided on a silicon substrate, a memory MOS transistor portion TRm used for information storage, and a selection MOS transistor portion that selectively connects the memory transistor portion TRm to the bit line BL. TRs. The memory MOS transistor portion TRm has an n-type diffusion layer (n-type impurity region) 13 serving as a source line electrode connected to the source line, and the selection MOS transistor portion TRs is n serving as a bit line electrode connected to the bit line BL. A type diffusion layer (n-type impurity region) 14 is provided. A region between the source line electrode 13 and the bit line electrode 14 is a channel formation region, and a charge storage region (for example, a silicon nitride film) 15 and a memory gate electrode (for example, an n-type polycrystal) are disposed near the memory MOS transistor portion TRm thereon. A silicon layer 16 is stacked via a gate insulating film, and a control gate electrode (for example, an n-type polysilicon layer) 17 is disposed near the selection MOS transistor TRs via a gate insulating film.

  The memory gate electrode 16 is connected to the corresponding memory gate control line MGL, and the control electrode 17 is connected to the control gate control line CGL.

  In a write operation in which a relatively high threshold voltage is set in the memory MOS transistor portion TRm of the nonvolatile memory cell MC, for example, a memory gate voltage Vmg = 11 V is applied as a write voltage to the memory gate electrode. Further, a source line voltage Vs = 6, a control gate voltage Vcg of 1.0 V, a write selection bit line BL of 0.8 V (circuit ground potential), a write non-selection bit line of 1.5 V, and a memory cell The MC selection MOS transistor TRs is turned on, and a write current is caused to flow from the source line electrode to the bit line electrode in the write selection bit line. Hot electrons are generated by this write current, and electrons accelerated by a high electric field between the memory gate electrode are injected into the charge storage region. In the erase operation in which a relatively low threshold voltage is set in the memory MOS transistor portion TRm of the nonvolatile memory cell MC, for example, the memory gate voltage Vmg = −6.0V, Vd = 0V, Vs = 0V and the charge storage region 15 The held electrons are emitted to the memory gate electrode.

  FIG. 4 shows an example of the flash memory 4. The flash memory 4 has a memory array (MARY) 21 in which a plurality of nonvolatile memory cells MC are arranged in a matrix. Although not particularly limited, it is assumed here that the nonvolatile memory cell MC has the MONOS (metal oxide nitride oxide semiconductor) type split gate structure described in FIG. The row selector (RSEL) 22 includes a row address buffer, a row address decoder, and a driver, and decodes a row address signal input from the address bus ADR to the address buffer. The memory gate control line MGL, the control gate control line CGL, and the source line SL are driven according to the decoding result. The driving mode is determined according to the operation (reading, erasing, writing, etc.) of the flash memory.

  The write latch circuit (WRL) 23 has a write data latch for latching write data for each bit line BL. Whether or not a write current is supplied to the bit line is controlled by the logical value of the write data held by the write data latch. Input of write data or output of read data is selected for the bit line BL via a column selector (CSEL) 24. The column selector 24 includes a column switch circuit and a column decoder, and selects a bit line to be connected to a data line based on a column address signal input from the address bus ADR. Each data line is connected to an input / output circuit (EXIO) 26 via a sense amplifier (AMP) 25. The input / output circuit 26 inputs / outputs data DAT to / from the bus BUS.

  The memory power supply circuit (MPS) 27 generates a write voltage and an erase voltage as a high voltage required for erasing and writing of the nonvolatile memory cell MC and supplies the generated voltages to the respective units. The memory power circuit 27 boosts the external voltage and supplies operation power used for erase and write operations. The write power line circuit (MPS) 27 also outputs the write bit line current. A sequencer (SQUEC) 10 performs a control sequence of read, erase, erase verify, write, and write verify and operation power supply voltage switching control in accordance with control information CNT such as a command given from the CPU 2 via the bus BUS. The write latch circuit 23 in FIG. 4 schematically shows a current source for supplying a write current to the write selection bit line. The address ADR, data DAT, and control signal CNT are given from the CPU 2 or the like via the bus BUS.

  FIG. 5 shows a connection relationship between the memory array 21, the write latch circuit 23, and the column selector 24. Here, in the memory array 21, 2048 nonvolatile memory cells share one memory gate control line MGL and one control gate control line CGL. The write latch circuit 23 has 1024 data latches in one-to-one correspondence with the bit lines BL. The column selector 24 assigns 1 bit to 16 bit lines for 64 bits of I / O63 to I / O0, and the connection is determined by an address signal.

  FIG. 6 illustrates the configuration of the unit circuit CSWi of the column selector 24. Sixteen bit lines BLi-0 to BLi-15 are assigned to 1-bit I / Oi, and their connections are alternatively selected by address signals ywa0 to ywa3 and ywb0 to ywb3. The configuration of FIG. 6 is repeated for 64 bits of I / O63 to I / O0.

  FIG. 1 illustrates a write path per bit line. In FIG. 1, the bit line BL is a main bit line, and a sub bit line SBL can be connected to the bit line BL via a selection MOS transistor TR1. In a write or read operation, the sub bit line SBL selected by one selection signal SBLS is connected to the bit line BL. The sub bit line SBL is connected to the power supply terminal via the compensation MOS transistor TR2 in order to compensate for the leak current from the diffusion layer, and compensates for the leak current in the write operation. This is to prevent an undesired leak current from being erroneously regarded as a write current in the write unselected bit line. SBLC is a selection signal for the compensation MOS transistor TR2. TR3 typically represents one column selection MOS transistor included in the column selector 24. DLAT represents a data latch provided for each bit line BL in the write latch circuit 23 as a representative. The data latch DLAT has a static latch, and one storage node of the static latch is connected to the bit line BL via the selection MOS transistor TR4. PS1 means a latch path for write data. LTC is the selection signal. Between the bit line BL and the ground terminal GND of the circuit, a first switch MOS transistor TR5, a second switch MOS transistor TR6, and a third switch MOS transistor TR7 that receive the other storage node of the static latch at the gate are connected in series. Be placed. PS2 means a write current path. The second switch MOS transistor TR6 is switch-controlled by a write pulse control signal WRPLS which is a gate control signal in accordance with a write operation. The third switch MOS transistor TR7 has a mutual conductance controlled by a write current control signal WRCC which is a gate control signal in accordance with a write operation. A series circuit of first to third MOS transistors is arranged for each data latch (for each bit line).

  A write mode with control of the switch MOS transistors TR6 and TR7 will be described. The write modes are a 128-byte write mode (first write mode) and an 8-byte write mode (second write mode). In the first write mode, as shown in FIG. 7, the write data is latched in the write data latch DLAT for 1024 bits, and then the second switch MOS transistor TR6 is turned on every 128 bit lines. This is an operation of writing 128 bytes (1024 bits) of data (a write operation with a large write unit) by sequentially switching the above and applying the write voltage every 8 times. In the second write mode, the latch data of all the 64-byte data latches DLAT are cleared to the write non-selective value, and then the write of 8 bytes of I / O63 to I / O0 is performed as illustrated in FIG. Data is latched in the write data latch DLAT, and then all the second switch MOS transistors TR6 are turned on and the write voltage is applied only once, thereby writing 8 bytes (64 bits) of data. Operation (write operation with a small write unit).

  FIG. 9 illustrates the generation logic of the control signal WRPLU (WRPLS1 to WRPLS8) corresponding to the operation mode. The circuit block LGR1 is a general term for data latches DLAT and MOS transistors TR5 to TR7 of 64 bit lines BL corresponding to I / O63 to I / O60. The circuit blocks LGR2 to LGR16 are also generally referred to as similar configurations corresponding to I / O59 to I / O56,... I / O3 to I / O0 sequentially. The write current control signal WRCC of the MOS transistor TR7 is shared among the circuit blocks LGR1 to LGR16. The write pulse control signal WRPLS of the MOS transistor TR6 is commonly used between the two sequential circuit blocks LGR1 to LGR16 to be WRPLS1 to WRPLS8. Write pulse control signals WRPLS1 to WRPLS8 are output from the bits STB1 to STB8 in the 8-bit shift register (SFTR) 30, respectively. A write start signal WRSTR is supplied to the first stage of the shift register 30, and this signal WRSTR is sequentially transmitted to the subsequent stage in synchronization with the cycle of the write clock signal WRCK. . The shift register 30 performs the shift operation when the mode signal MOD is a logical value “0”. When the mode signal MOD is a logical value “1”, each of the bits STB1 to STB8 transmits the start signal WRSTR to the subsequent stage through. In the 128-byte write mode, the mode signal MOD is set to a logical value “0”, and in the 8-byte write mode, the mode signal MOD is set to a logical value “1”.

  According to the configuration of FIG. 9, in the 128-byte write mode, the MOS transistor TR7 is turned on every two circuit blocks of the circuit blocks LGR1 to LGR16 sequentially as illustrated in FIG. A write current corresponding to the write data of the data latch DLAT is supplied for each range of the bit lines, and the write operation for 1024 bits can be completed in 8 steps. FIG. 12 shows the waveforms of the write pulse control signals WRPLS1 to WRPLS8 in the 128-byte write mode. In the 8-byte write mode, even if all the MOS transistors TR7 of the circuit blocks LGR1 to LGR16 are turned on, all of the circuit blocks LGR1 to LGR16 are in a non-write state except for the 1-byte write data latch DLAT. Since it is cleared, as illustrated in FIG. 11, only writing of 8 bytes can be performed by applying the write voltage once. FIG. 13 shows waveforms of the write pulse control signals WRPLS1 to WRPLS8 in the 8-byte write mode.

  FIG. 14 shows a write current control circuit. The write current control circuit 31 generates a write current control signal WRCC corresponding to the logic value of the mode signal MOD. The write current control circuit 31 includes a current mirror circuit 32 in which the current mirror ratio of the MOS transistor M1 and the MOS transistor M2 is 1: 1, and a current mirror circuit 33 in which the current mirror ratio of the MOS transistor M3 and the MOS transistor M4 is 1: 2. The same current as that of the constant current source 34 flows through the MOS transistor M1 and the MOS transistor M3. When mode signal MOD is logical “0” (128-byte write mode), the gate voltage of MOS transistor M5 is set to the level of write current control signal WRCC, whereby write current control signal WRCC is received at the gate. The mutual conductance of the MOS transistor TR7 (see FIG. 1) is made relatively small, and the current flowing through the constant current source 34 is attempted to flow as a write current. On the other hand, when the mode signal MOD is the logical value “1” (8-byte write mode), the gate voltage of the MOS transistor M6 is set to the level of the write current control signal WRCC, thereby the write current control signal WRCC. The transconductance of the MOS transistor TR7 receiving at the gate is made relatively large, and the write current (the same current as the current flowing through the constant current source 34) that is twice as much as the above is attempted to flow.

  As is apparent from the above description, the maximum number of bit lines through which a write current flows in one write voltage application cycle in the 128-byte write mode is 128, and half of that in the 8-byte write mode. There are 64. Focusing on this difference, the current consumption due to the write current in the 8-byte write mode is doubled in the 128-byte write mode. This current control is based on the premise that one write voltage application cycle time is made equal in both the 128-byte write mode and the 8-byte write mode. That is, in FIG. 9, the frequency of the write clock signal WRCK is equal in both the 128-byte write mode and the 8-byte write mode.

  FIG. 15 generally shows the configuration for the write pulse control and write current control described above. The write start signal WRSTR is generated at a predetermined timing by the write pulse generation circuit 36 in response to a write operation instruction. The write clock signal WRCK is generated using the clock signal CLK selected by the reference clock control circuit 37. The reference clock control circuit 37 is a clock signal synchronized with the reference clock signal CK generated by the CPG 9.

  FIG. 16 illustrates a flash control command issued from the CPU 2 to the sequencer 10. When the CPU 2 fetches a program from the flash memory 4 and accesses the flash memory 4 according to the fetched program, the CPU 2 issues a flash control command such as erasing or writing according to the type of the access. The sequencer 10 generates a control signal for controlling the internal operation of the flash memory 4 according to a predetermined procedure in accordance with the flash control command.

  FIG. 17 generally shows a configuration for realizing different control of write pulse control and write current control. The first difference from FIG. 15 is that the reference clock control circuit 37A receives the mode signal MOD, and controls the frequency of CLK to be the same as the frequency of CK when MOD = 0 (128-byte write mode), and MOD = 1. In (8-byte write mode), the frequency of CLK is controlled to be twice the frequency of CK. In short, in the 8-byte write mode, the write current per bit line is increased and the write voltage application time is shortened compared to the 128-byte write mode. The second difference is that the input of the current selection control terminal (the input terminal of MOD in FIG. 14) of the write current control circuit 31 is converted into a logical product signal of MOD and CB by the logical product gate 38. The control bit CB is one bit of the control register and can be initialized by the CPU 2. When the control bit CB is set to the logical value “0”, the same write current is supplied in both the 128-byte write mode and the 8-byte write mode. The write current is doubled in response to the frequency of the write clock WRCK being doubled in the 8-byte write mode and the write voltage application time being halved, thereby compensating for the required write capability. It is. There are 64 bit lines to be written in one write voltage application cycle in the 8-byte write mode, and 128 bit lines to be written in one write voltage application cycle in the 128-byte write mode. However, the former one write voltage application cycle is shortened to half of the latter one write voltage application cycle, and the write efficiency per bit can be made equal in both operation modes. FIG. 18 illustrates a timing chart of 16 consecutive write operations when the write current and frequency are not doubled, and FIG. 19 illustrates 16 consecutive write operations when both the write current and frequency are doubled. An operation timing chart is illustrated. In the latter case, the same 128-byte write data as the former can be completed at about twice the speed by using the 8-byte write mode.

  FIG. 20 shows a difference from an EEPROM in which well region division is performed for each erase unit, and writing is possible in units of 8 bytes, which is the number of data bits per well in the word line direction, for example. In the case of this EEPROM, writing in units of 8 bytes cannot be performed unless well region separation is performed. On the other hand, the flash memory described so far can perform writing in units of 8 bytes without performing well region separation.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor device is not limited to a microcomputer including a CPU, and may be a semiconductor device having a volatile memory such as a flash memory. The memory cell structure of the flash memory is not limited to the split gate structure, and may be a stack type MONOS structure or a structure having a floating gate. Further, the large writing unit is not limited to 1024 bits. The write unit is the size of write data specified by the write command. In addition, when the write unit is large, the multiple bit lines are limited to 128 bits each time the write voltage is applied while switching the multiple bit line range in several steps by reducing the multiple bit line range. In addition, when the write unit is small, the write unit when the range of the plurality of bit lines is increased and the write voltage is applied less than the above is not limited to 64 bits.

  In the above description, the first switch transistor and the second switch transistor have a third switch transistor connected in series, and the sequencer sets the mutual conductance of the third switch transistor to the second operation rather than the first operation. In the above description, the write voltage application time is made equal in the first operation and the second operation (corresponding to claim 6), but the present invention is not limited to this. In short, the sequencer may set the mutual conductance of the third switch transistor to be smaller in the second operation than in the first operation, and make the application time of the write voltage equal in the first operation and the second operation. . In that case, in FIG. 14, the mutual conductance of the MOS transistor TR7 (see FIG. 1) receiving the write current control signal WRCC at its gate is made relatively large, and an attempt is made to flow a write current twice as large as the current flowing through the constant current source 34. To do. On the other hand, when the mode signal MOD is a logical value “0” (8-byte write mode), the gate voltage of the MOS transistor M6 is set to the level of the write current control signal WRCC, thereby the write current control signal WRCC. The transconductance of the MOS transistor TR7 receiving at the gate thereof is made relatively small, so that half the write current (the same current as the current flowing through the constant current source 34) is made to flow. In FIG. 17, when MOD = 1 (128 byte write mode), the CLK frequency is controlled to be the same as the CK frequency, and when MOD = 0 (8 byte write mode), the CLK frequency is controlled to be twice the CK frequency. Then, the input of the current selection control terminal (the input terminal of MOD in FIG. 14) of the write current control circuit 31 may be converted into a logical sum signal of MOD and CB by the logical sum gate (38).

FIG. 6 is a circuit diagram illustrating a write path per bit line. 1 is a block diagram of a microcomputer as an example of a semiconductor device according to the present invention. It is explanatory drawing which illustrates the device structure of the non-volatile memory cell of flash memory, and the basic structure of a memory array. It is a block diagram which shows an example of flash memory. FIG. 3 is a block diagram showing a connection relationship among a memory array, a write latch circuit, and a column selector. It is a circuit diagram which illustrates the composition of unit circuit CSWi of a column selector. It is explanatory drawing which illustrates the latch operation | movement of the write data by 128 byte write mode (1st write mode). It is explanatory drawing which illustrates the latch operation of the write data by 8 byte write mode (2nd write mode). It is a circuit diagram illustrating the generation logic of the control signal WRPLU (WRPLS1 to WRPLS8) according to the operation mode. It is explanatory drawing which shows typically the application form of the write-control pulse in 128 byte write mode. It is explanatory drawing which shows typically the application form of the write-control pulse in 8-byte write mode. It is a wave form diagram which shows the waveform of the write pulse control signals WRPLS1 to WRPLS8 in the 128-byte write mode. FIG. 13 is a waveform diagram showing waveforms of the write pulse control signals WRPLS1 to WRPLS8 in the 8-byte write mode. It is a circuit diagram of a write current control circuit. It is a block diagram which shows the structure for write pulse control and write current control as a whole. It is explanatory drawing which illustrates the flash control command issued to a sequencer from CPU. It is a block diagram which shows entirely the structure for implement | achieving another control of write pulse control and write current control. 6 is a timing chart of 16 consecutive write operations when CB = 0 and MOD = 0. FIG. 19 is a timing chart of 16 consecutive write operations when CB = 1 and MOD = 0. It is explanatory drawing which illustrates the difference with EEPROM by which well area | region division is performed for every erasing unit.

Explanation of symbols

1 Microcomputer (MCU)
2 Central processing unit (CPU)
3 RAM
4 Flash memory (FLASH) 4
5 Direct memory access controller (DMAC)
6,7 I / O port (PRT)
8 Timer (TMR)
9 Clock generator (CPG)
10 Sequencer (SQUEC)
MGL memory gate line (word line)
CGL Control gate line SL Source line BL Bit line MC Non-volatile memory cell 21 Memory array (MARY)
23 Write latch circuit (WRL)
24 Column selector (CSEL)
DLAT data latch 30 shift register WRCC write current control signal WRSTR write start signal WRCK write clock signal MOD mode signal indicating 128-byte write mode or 8-byte write mode CB control bit TR5 first switch MOS transistor TR6 second switch MOS transistor TR7 Third switch MOS transistor 31 Write current control circuit 36 Write pulse generation circuit 37, 37A Reference clock control circuit

Claims (14)

A semiconductor device comprising a nonvolatile memory that is electrically erasable and writable,
The nonvolatile memory includes a memory array, a parallel write limiting circuit, and a sequencer,
The memory array is supplied with a write voltage from a word line selected for writing according to an address signal in a write operation and supplied with a write current via a bit line selected for writing according to a logical value of write data. A non-volatile memory cell,
The parallel write limiting circuit limits a range of a plurality of bit lines through which a write current flows in parallel according to a difference in write units,
The sequencer applies a write voltage while switching the range of the plurality of bit lines in order by decreasing the range of the plurality of bit lines when the write unit is large, and when the write unit is small A semiconductor device in which a range of bit lines is enlarged and a write voltage is applied fewer times than the above. Data latch that latches write data for each bit line, column selection circuit that enables selective connection of data lines and data latches assigned to a plurality of data latches, and correspondence according to the logical value of the storage node of the data latch A first switch transistor for selectively opening and closing a write current path of the bit line to be connected, and a second switch transistor arranged in series with the first switch transistor,
The parallel write limiting circuit includes a first operation for sequentially switching a range of a plurality of bit lines for turning on the first switch transistors in parallel, and a first operation for turning on the second switch transistors of all bit lines in parallel. The semiconductor device according to claim 1, wherein two operations can be selected.   The semiconductor device according to claim 2, wherein the sequencer selects the first operation or the second operation in response to a type of a write command.   4. The semiconductor device according to claim 3, wherein the sequencer clears all the data latches to a write non-selected logic value in a write operation in response to a write command, and then starts a write data latch operation.   The sequencer makes the maximum number of the data latches in which write data can be latched in the second operation smaller than the number of the plurality of bit lines in which the second switch transistors are turned on in parallel in the first operation. The semiconductor device according to claim 4. A third switch transistor connected in series to the first switch transistor and the second switch transistor;
6. The semiconductor device according to claim 5, wherein the sequencer sets the mutual conductance of the third switch transistor to be larger in the second operation than in the first operation, and makes the application time of the write voltage equal in the first operation and the second operation. . A semiconductor device comprising a nonvolatile memory that is electrically erasable and writable,
The nonvolatile memory includes a memory array, a parallel write limit circuit, a write current limit circuit, and a sequencer,
The memory array is supplied with a write voltage from a word line selected for writing according to an address signal in a write operation and supplied with a write current via a bit line selected for writing according to a logical value of write data. A non-volatile memory cell,
The parallel write limiting circuit limits a range of a plurality of bit lines through which a write current flows in parallel according to the size of a write unit,
The write current limiting circuit limits the write current according to the size of the write unit,
The sequencer increases the write current by the current limiting circuit per bit line when a small write unit is specified, compared to when a large write unit is specified.   The sequencer applies a write voltage while switching the range of the plurality of bit lines in order by decreasing the range of the plurality of bit lines when the write unit is large, and when the write unit is small The semiconductor device according to claim 7, wherein the range of the bit line is enlarged and the write voltage is applied fewer times than the above. Data latch that latches write data for each bit line, column selection circuit that enables selective connection of data lines and data latches assigned to a plurality of data latches, and correspondence according to the logical value of the storage node of the data latch A first switch transistor for selectively opening and closing a write current path of the bit line to be connected, and a second switch transistor arranged in series with the first switch transistor,
The parallel write restriction circuit sequentially switches a range of a plurality of bit lines that turn on the second switch transistors in parallel when the write unit is large, and the second operation of all the bit lines when the write unit is small. 9. The semiconductor device according to claim 8, wherein the second operation for turning on the switch transistors in parallel can be selected.   The semiconductor device according to claim 9, wherein the sequencer selects the first operation or the second operation in response to a type of a write command.   11. The semiconductor device according to claim 10, wherein the sequencer clears all the data latches to a write non-selected logic value in a write operation in response to a write command, and then starts a write data latch operation.   The sequencer makes the maximum number of the data latches in which write data can be latched in the second operation smaller than the number of the plurality of bit lines in which the second switch transistors are turned on in parallel in the first operation. The semiconductor device according to claim 11. A third switch transistor connected in series to the first switch transistor and the second switch transistor;
The sequencer causes the mutual conductance of the third switch transistor in the second operation to be equal to or greater than the mutual conductance of the third switch transistor in the first operation via the current control circuit, and applies the write voltage in the second operation. The semiconductor device according to claim 12, which is shorter than the first operation.   The semiconductor device according to claim 3, further comprising a central processing unit capable of accessing the nonvolatile memory cell, wherein the central processing unit issues the write command.

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