JP2008021881A - Electrical device, its manufacturing method, and display unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain the miniaturization of a whole device by making the area of a wiring layer around the opening of a contact hole as small as possible. <P>SOLUTION: The electrical device includes an electrode layer 23; an interlayer insulation film 25 covering the electrode layer 23; a contact hole 27 formed in the interlayer insulation film 25 so as to expose a part of the electrode layer 23; and a wiring layer 31 formed in the surface of the interlayer insulation film 25, and at the same time, connected to the electrode layer 23 through the contact hole 27. The contact hole 27 is formed to be a tapered shape in its cross section whose inner diameter becomes small toward the electrode layer 23 side from the surface of the interlayer insulation film 25, and the taper angle of the contact hole 27 is 30° or more and 80° or less. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electric element, a method for manufacturing the electric element, and a display device including the electric element.

  For example, many active elements such as thin film transistors (TFTs) are formed in an active matrix display device (see, for example, Patent Document 1). In particular, demand for liquid crystal display devices has been increasing in recent years, and improvement in display quality and reduction in cost are required.

  The liquid crystal display device has a display area that contributes to display and a frame area that is provided around the display area and does not contribute to display. In the display area, a plurality of pixels are arranged in a matrix, and a TFT is arranged in each pixel. On the other hand, a driver circuit unit for driving each pixel is provided in the frame region. A plurality of TFTs are also formed in this driver circuit portion.

As shown in FIG. 16 which is an enlarged plan view, the TFT 100 includes an active region 101 which is a silicon layer, and a gate electrode 102 which is stacked on the active region 101 via a gate insulating film (not shown). . The active region 101 and the gate electrode 102 are covered with an interlayer insulating film (not shown). In the interlayer insulating film, contact holes 103 are formed at positions above the active region 101 (front side in FIG. 16) and above the gate electrode 102 so as to open upward. A wiring layer 104 is patterned by photolithography inside each contact hole 103 and around the opening. As a result, the gate electrode 102 and the active region 101 are connected to an external wiring, element, or the like through the contact hole 103 and the wiring layer 104, respectively.
JP-A-11-218787

  However, since the TFT has a fine structure, a slight misalignment of the mask in photolithography may cause poor connection between the gate electrode and the active region and the wiring layer. Therefore, the wiring layer is usually formed in a relatively large area as a margin region around the opening of the contact hole.

  However, since the margin area of the wiring layer is large, there is a problem that it is difficult to reduce the size of the entire device. For example, in the case of a TFT in a display region of a display device, it is difficult to improve the aperture ratio of the pixel because the TFT itself is difficult to be formed small. In the case of TFTs in the frame region, it is difficult to narrow the frame region for the same reason, and it is difficult to reduce the area ratio of the frame region to the display region.

  The present invention has been made in view of the above points, and an object of the present invention is to reduce the area of the wiring layer around the opening of the contact hole as much as possible and to reduce the size of the entire apparatus. It is in.

  In order to achieve the above object, an electric element according to the present invention is formed on an electrode layer, an interlayer insulating film covering the electrode layer, and the interlayer insulating film so that a part of the electrode layer is exposed. An electrical element comprising a contact hole and a wiring layer formed on the surface of the interlayer insulating film and connected to the electrode layer through the contact hole, wherein the contact hole is formed of the interlayer insulating film A taper angle of the contact hole is not less than 30 ° and not more than 80 °.

  The thickness of the interlayer insulating film is preferably 0.3 μm or more and 1.0 μm or less.

  The inner diameter at the open end of the contact hole is preferably 1.5 μm or more and 8 μm or less.

  The electrical element according to the present invention includes an electrode layer, an interlayer insulating film covering the electrode layer, a contact hole formed in the interlayer insulating film so that a part of the electrode layer is exposed, and the interlayer insulation An electrical element formed on the surface of the film and connected to the electrode layer through the contact hole, wherein the wiring layer is at least a part of an inner peripheral surface of the contact hole And the entire surface of the electrode layer constituting the bottom of the contact hole, and so as not to surround at least a part of the opening end of the contact hole. And

  The wiring layer may be formed over the entire inner peripheral surface of the contact hole.

  The wiring layer is preferably formed in a film shape along the surface of the electrode layer and the inner peripheral surface of the contact hole.

  The method for manufacturing an electrical element according to the present invention includes a contact hole forming step of forming a contact hole in an interlayer insulating film covering the electrode layer to expose the electrode layer, a surface of the interlayer insulating film, and a contact hole A conductive material layer forming step for forming a conductive material layer therein; and a part of the conductive material layer is removed by photolithography to be formed on the surface of the interlayer insulating film; and the electrode layer via the contact hole A wiring layer forming step of forming a wiring layer connected to the substrate, wherein the contact hole forming step includes forming the taper angle of the contact hole to be 30 ° or more and 80 ° or less. Features.

  The thickness of the interlayer insulating film is preferably 0.3 μm or more and 1.0 μm or less.

  In the contact hole forming step, it is preferable to form an inner diameter of the contact hole at an opening end of 1.5 μm or more and 8 μm or less.

  The method for manufacturing an electrical element according to the present invention includes a contact hole forming step of forming a contact hole in an interlayer insulating film covering the electrode layer to expose the electrode layer, a surface of the interlayer insulating film, and a contact hole A conductive material layer forming step for forming a conductive material layer therein; and a part of the conductive material layer is removed by photolithography to be formed on the surface of the interlayer insulating film; and the electrode layer via the contact hole A wiring layer forming step of forming a wiring layer connected to the wiring layer, wherein in the wiring layer forming step, the wiring layer includes at least a part of an inner peripheral surface of the contact hole; The electrode layer is formed so as to cover the entire surface of the electrode layer constituting the bottom of the contact hole, and at least one of the opening ends of the contact hole. And forming so as not enclose.

  The wiring layer may be formed over the entire inner peripheral surface of the contact hole.

  The wiring layer is preferably formed in a film shape along the surface of the electrode layer and the inner peripheral surface of the contact hole.

  The display device according to the present invention includes an element substrate on which a plurality of the electric elements are formed, a counter substrate disposed to face the element substrate, and a display provided between the counter substrate and the element substrate. And a medium layer.

-Action-
Next, the operation of the present invention will be described.

  The wiring layer is formed on the surface of the interlayer insulating film and is connected to the electrode layer constituting the bottom of the contact hole through the contact hole formed in the interlayer insulating film. Accordingly, current is input / output to / from the electrode layer via the wiring layer.

  When manufacturing the electrical element according to the present invention, first, in the contact formation step, a contact hole is formed in an interlayer insulating film covering the electrode layer to expose the electrode layer. Next, in the conductive material layer forming step, a conductive material layer is formed on the surface of the interlayer insulating film and inside the contact hole. Thereafter, in the wiring layer forming step, a part of the conductive material layer is removed by photolithography to form a wiring layer formed on the surface of the interlayer insulating film and connected to the electrode layer through the contact hole. The electric element can be formed on an element substrate constituting a display device, for example.

  If the taper angle of the contact hole is larger than 80 °, it is difficult to reliably form the wiring layer on the inner peripheral wall surface of the contact hole, for example, by sputtering. It is assumed that the taper angle is 0 ° when the inner diameter is constant in the length direction of the contact hole. If the taper angle is less than 30 °, the resist formed inside the contact hole is exposed to the bottom of the contact hole, so that at least a part of the conductive material layer covering the electrode layer is removed. End up. That is, connection failure between the electrode layer and the wiring layer and an increase in connection resistance are caused.

  On the other hand, in the present invention, since the contact hole has a taper angle of 30 ° or more and 80 ° or less, a wiring layer can be reliably formed on the inner peripheral wall surface of the contact hole. Connection failure and increase in connection resistance can be suppressed.

  Further, if the thickness of the interlayer insulating film is less than 0.3 μm, it becomes difficult to planarize the interlayer insulating film. On the other hand, if the thickness of the interlayer insulating film is larger than 1.0 μm, it becomes difficult to form the contact hole by etching.

  Therefore, in the present invention, since the thickness of the interlayer insulating film is set to 0.3 μm or more and 1.0 μm or less, the contact hole can be penetrated by photolithography while the interlayer insulating film can be flattened.

  If the inner diameter of the contact hole is less than 1.5 μm, it is difficult to reliably form the contact hole by photolithography sufficiently. On the other hand, if the inner diameter at the opening end of the contact hole is larger than 8 μm, the size of the contact hole with respect to the entire electric element becomes too large, and it is difficult to reduce the size of the electric element.

  In contrast, in the present invention, since the inner diameter of the contact hole at the opening end is formed to be 1.5 μm or more and 8 μm or less, it is possible to reliably form the contact hole and to reduce the size of the electric element. .

  Thus, the manufactured electrical element is formed so that the wiring layer does not surround at least a part of the opening end of the contact hole, but the wiring layer is in contact with at least a part of the inner peripheral surface of the contact hole. It is formed so as to cover the entire surface of the electrode layer constituting the bottom of the hole. That is, since the wiring layer covers the entire electrode layer at the bottom of the contact hole, connection failure with the electrode layer and increase in connection resistance are suppressed. In addition, since it is not necessary to cover the entire area around the opening of the contact hole, it is possible to reduce the size of the entire device by reducing the area of the margin area of the wiring layer in consideration of misalignment.

  According to the present invention, the entire surface of the electrode layer constituting the bottom of the contact hole can be covered with the wiring layer while forming the wiring layer so as not to surround at least a part of the opening end of the contact hole. . As a result, the area of the margin area of the wiring layer considering misalignment can be greatly reduced, and the overall device can be reduced in size, and the connection failure between the wiring layer and the electrode layer and the increase in connection resistance can be suppressed. can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

Embodiment 1 of the Invention
1 to 7 show Embodiment 1 of an electric element and a display device according to the present invention. In the present embodiment, a liquid crystal display device having a thin film transistor (hereinafter abbreviated as TFT) which is an active element as an example of an electric element will be described.

  As shown in FIG. 6, which is a plan view, the liquid crystal display device 10 includes a TFT substrate 11 that is an element substrate, a counter substrate 12 that is disposed to face the TFT substrate 11, and a space between the counter substrate 12 and the TFT substrate 11. And a liquid crystal layer (not shown), which is a display medium layer. On the counter substrate 12, a color filter, a common electrode, a black matrix, and the like (not shown) are formed.

  On the other hand, the TFT substrate 11 is configured as a so-called active matrix substrate. The TFT substrate 11 has a display area 13 that contributes to display and a frame area 14 that is formed around the display area 13 and does not contribute to display. In the display area 13, a plurality of pixels (not shown) are arranged in a matrix. Although not shown, each pixel is provided with a pixel electrode for driving the liquid crystal layer and a TFT for switching driving the pixel electrode.

  For example, the TFT substrate 11 and the counter substrate 12 are each formed in a rectangular shape, and the counter substrate 12 is formed to be slightly smaller than the TFT substrate 11. The display area 13 is formed in a rectangular shape in an area where the TFT substrate 11 and the counter substrate 12 overlap each other. A gate driver portion 15 is formed in a region along one side of the counter substrate 12 in the frame region 14. A source driver unit 16 is formed in the frame region 14 along the other side of the counter substrate 12. In the gate driver unit 15 and the source driver unit 16, a driving circuit which is a logic circuit is formed and connected to the TFT of each pixel through a wiring.

  As shown in FIG. 7 which is an enlarged cross-sectional view of the TFT substrate 11, the TFT 1 formed in the pixel or the drive circuit includes a semiconductor layer 19 which is an electrode layer formed on a substrate 18 such as a glass substrate or a plastic substrate, A gate insulating film 20 that covers the semiconductor layer 19 and a gate electrode 21 that is an electrode layer disposed to face the semiconductor layer 19 with the gate insulating film 20 interposed therebetween are provided.

  In the semiconductor layer 19, a region facing the gate electrode 21 is formed in the channel region 22, one region adjacent to the side of the channel region 22 is formed in the source region 23, and the other region is formed in the drain region 24. Is formed.

  Further, the TFT 1 has an interlayer insulating film 25 formed on the substrate 18 so as to cover the gate insulating film 20 and the gate electrode 21. In the interlayer insulating film 25, a contact hole 26 formed so that a part of the gate electrode 21 is exposed, a contact hole 27 formed so that a part of the source region 23 is exposed, and a drain region 24 And a contact hole 28 formed so that the portion is exposed.

  The TFT 1 has a plurality of wiring layers 30, 31, 32 formed on the surface of the interlayer insulating film 25. The wiring layer 30 is electrically connected to the gate electrode 21 through the contact hole 26. The wiring layer 31 is electrically connected to the source region 23 through the contact hole 27. The wiring layer 32 is electrically connected to the drain region 24 through the contact hole 28.

  The main feature of the present invention is the structure of the contact holes 26, 27, 28 and the wiring layers 30, 31, 32 formed in the interlayer insulating film 25. Here, since the contact holes 26, 27, and 28 and the wiring layers 30, 31, and 32 have the same configuration, the source region 23, the contact hole 27, and the wiring layer 31 are given as representative examples. Description will be made with reference to FIG. 1 which is a schematic enlarged plan view and FIG. 2 which is a schematic enlarged sectional view.

  As shown in FIG. 2, the contact hole 27 is formed in a tapered shape having a smaller inner diameter from the surface of the interlayer insulating film 25 toward the source region 23. The taper angle θ of the contact hole 27 is not less than 30 ° and not more than 80 ° (first condition). The taper angle θ is preferably 35 ° to 70 °, and more preferably 40 ° to 60 °. It is assumed that the taper angle θ is 0 ° when the inner diameter is constant in the length direction of the contact hole.

  The thickness of the interlayer insulating film 25 is 0.3 μm or more and 1.0 μm or less (second condition). The thickness of the interlayer insulating film 25 is preferably 0.4 μm or more and 0.9 μm or less, and more preferably 0.5 μm or more and 0.8 μm or less.

  The inner diameter at the opening end 27a of the contact hole 27 is 1.5 μm or more and 8 μm or less (third condition). Furthermore, the inner diameter of the open end 27a is preferably 2 μm or more and 5 μm or less. In addition, it is preferable to satisfy at least one of the first to third conditions.

  As a result, the wiring layer 31 is formed so as to cover at least a part of the inner peripheral surface of the contact hole 27 and the entire surface of the source region 23 constituting the bottom of the contact hole 27, and the contact hole. 27 is formed so as not to surround at least a part of the opening end 27a.

  In particular, the wiring layer 31 is formed over the entire inner peripheral surface of the contact hole 27 as shown in FIG. Further, as shown in FIG. 2, the wiring layer 31 is formed in a film shape along the surface of the source region 23 and the inner peripheral surface of the contact hole 27. That is, the cross section of the wiring layer 31 is formed in a concave shape inside the contact hole 27.

  That is, the wiring layer 31 is formed inside the contact hole 27 and electrically connected to the source region 23, and from the part of the opening end 27a of the contact hole 27 to the side (left in FIG. 1). A second connection portion 31c extending on the surface of the interlayer insulating film 25 in the direction) and a wiring portion 31b extending further on the surface of the interlayer insulating film 25 laterally (to the left in FIG. 1) from the second connection portion 31c. Have.

  The second connection portion 31c is a part of the wiring layer 31 formed aiming to be formed at the position of the first connection portion 31a, and is formed by misalignment. As shown in FIG. 1, the outer shape of the second connection portion 31 c is configured by a part of a circle having substantially the same diameter as the opening end 27 a of the contact hole 27. That is, the diameter of the second connection portion 31 c in the direction orthogonal to the direction in which the wiring layer 31 extends (the vertical direction in FIG. 1) is substantially the same as the inner diameter of the opening end 27 a of the contact hole 27.

  The width of the wiring portion 31b in the direction perpendicular to the direction in which the wiring layer 31 extends (the vertical direction in FIG. 1) is narrower than the diameter of the first connection portion 31a and the second connection portion 31c. The wiring layer 31 is not formed around the opening end 27a of the contact hole 27 except for the region where the second connection portion 31c is formed.

  With such a configuration, the wiring layers 30, 31, and 32 are electrically connected to the entire gate electrode 21, source region 23, and drain region 24 that are electrode layers constituting the bottoms of the contact holes 26, 27, and 28, respectively. Has been.

-Manufacturing method-
Next, a manufacturing method of the TFT 1 and the liquid crystal display device 10 which are the electric elements will be described.

  The liquid crystal display device 10 is manufactured by forming the TFT substrate 11 and the counter substrate 12, and then bonding the TFT substrate 11 and the counter substrate 12 to each other via a seal member and a liquid crystal layer.

  Although the illustration of the counter substrate 12 is omitted, for example, a transparent common electrode is uniformly formed of ITO or the like on a transparent substrate such as a glass substrate or a plastic substrate, and a color filter or a light-shielding film is formed in a predetermined shape by photolithography or the like. To form. Thereafter, an alignment film (not shown) is formed so as to cover the common electrode and the like.

  The TFT substrate 11 is, for example, a substrate 18 such as a glass substrate or a plastic substrate, TFT1, a pixel electrode connected to the TFT1 (not shown), a source wiring (not shown) connected to the TFT1, and a gate wiring (not shown). Etc. Thereafter, an alignment film (not shown) is formed so as to cover these TFTs 1 and the like.

  When the TFT 1 is manufactured, as shown in FIG. 7, a semiconductor layer 19 is formed in a predetermined shape on the substrate 18 by photolithography or the like. Subsequently, after forming the gate insulating film 20 covering the semiconductor layer 19, the gate electrode 21 is patterned on the gate insulating film 20. Further, after ion implantation of impurity ions into the semiconductor layer 19, the impurity ions are activated by heat treatment. Thus, in the semiconductor layer 19, a region overlapping with the gate electrode 21 is formed as the channel region 22, and regions not overlapping with the gate electrode 21 are formed as the source region 23 and the drain region 24.

  Subsequently, an interlayer insulating film 25 is formed on the substrate 18 by CVD or the like so as to cover the gate insulating film 20 and the gate electrode 21. Thereafter, a contact hole 26 is formed above the gate electrode 21 and a contact hole 27 is formed above the source region 23 in the interlayer insulating film 25. Further, a contact hole 28 is formed above the drain region 24.

  Thereafter, a conductive material layer is deposited and formed on the surface of the interlayer insulating film 25 and in each contact hole 26, 27, 28, and the conductive material layer is patterned by photolithography or the like to form wiring layers 30, 31, 32. Form.

  Each wiring layer 30, 31, 32 has the same configuration. Therefore, as a representative, the formation process of the wiring layer 31 will be described in detail. 2 to 5 are schematic enlarged sectional views showing steps of forming the wiring layer 31. FIG.

  First, as shown in FIG. 3, an interlayer insulating film is formed to 0.3 μm or more and 1.0 μm or less on the substrate 18. Subsequently, a contact hole forming step is performed by photolithography or the like, a contact hole 27 is formed in the interlayer insulating film 25 and the gate insulating film 20 covering the source region 23, and a part of the source region 23 is exposed. At this time, the contact hole 27 is formed in a tapered shape with a smaller inner diameter toward the substrate 18 side, and the taper angle θ is defined to be 30 ° or more and 80 ° or less.

  Thereafter, a conductive material layer forming step is performed to uniformly form the conductive material layer 40 on the surface of the interlayer insulating film 25 inside the contact hole 27 and around the opening end 27a. The conductive material layer 40 is formed in a thin film shape along the inner peripheral surface of the contact hole 27 and the surface of the source region 23.

  Next, a wiring layer forming step is performed, a part of the conductive material layer 40 is removed by photolithography, and the wiring layer 31 is formed. First, a photosensitive resist 41 is formed so as to cover the surface of the conductive material layer 40. The resist 41 is formed with a substantially uniform film thickness on the surface of the interlayer insulating film 25, while the film thickness in the region where the contact hole 27 is formed is larger than the surrounding area.

  Thereafter, as shown in FIG. 4, the resist 41 is exposed by irradiating light through a mask 42. The mask 42 has a light shielding portion 43 having substantially the same shape as the opening end 27a of the contact hole 27 in plan view. Then, the mask 42 is aligned with the aim of the light shielding portion 43 being disposed immediately above the contact hole 27. In the present embodiment, due to misalignment, the position of the mask 42 is shifted from the position of the contact hole 27 to the left in FIG.

  Since the thickness of the resist 41 is relatively thin around the opening of the contact hole 27, the light transmitted through the mask 42 sufficiently exposes the resist 41 in the entire thickness direction. On the other hand, since the thickness of the resist suddenly increases inside the contact hole 27, the light transmitted through the mask 42 cannot be sufficiently transmitted through the resist 41 in the entire thickness direction. As shown in FIG. 4, the exposure can be sufficiently performed only to the same depth as the thickness of the resist 41 around the opening of the contact hole 27.

  Then, as shown in FIG. 5, the exposed resist 41 is developed and removed. Since a part of the resist 41 is not exposed inside the contact hole 27, the resist 41 can be left without being removed. Subsequently, using the resist 41 as a mask, the conductive material layer 40 exposed without being covered with the resist 41 is removed by etching or the like. Thereafter, the resist 41 is removed.

  In this way, the wiring part 31b and the second connection part 31c formed on the surface of the interlayer insulating film 25, and the wiring part 31b and the second connection part 31c are connected to the source region 23 through the contact hole 27. A wiring layer 31 including the first connection portion 31a thus formed is formed.

  In the wiring layer forming step, as shown in FIGS. 1 and 2, the wiring layer 31 is formed on the surface of the source region 23 that forms at least a part of the inner peripheral surface of the contact hole 27 and the bottom of the contact hole 27. Each of the contact holes 27 is formed so as to cover each other, and at least a part of the opening end 27 a of the contact hole 27 is not surrounded by the wiring layer 31.

  Since the resist 41 is left inside the contact hole 27 without being removed, the wiring layer 31 is formed over the entire inner peripheral surface of the contact hole 27. Since the conductive material layer 40 is formed in a thin film shape, the wiring layer 31 is formed in a film shape along the surface of the source region 23 and the inner peripheral surface of the contact hole 27.

-Effect of Embodiment 1-
Therefore, according to the first embodiment, the taper angle θ of the contact holes 26, 27, and 28 is defined as 30 ° or more and 80 ° or less, and the thickness of the interlayer insulating film 25 is defined as 0.3 μm or more and 1.0 μm or less. Then, by defining the inner diameters at the open ends of the contact holes 26, 27, and 28 to be not less than 1.5 μm and not more than 8 μm, the wiring layer does not surround at least a part of the open ends of the contact holes 26, 27, and 28. While forming 30, 31, 32, the resist 41 was left inside the contact holes 26, 27, 28 and exposed at the bottoms of the contact holes 26, 27, 28, regardless of the misalignment of the mask 42. The entire conductive material layer 40 can be covered with the resist 41. As a result, the conductive material layer 40 is left on the entire bottoms of the contact holes 26, 27, and 28, and can be formed as the wiring layers 30, 31, 32. Therefore, the wiring layers 30, 31, 32 and the electrode layers (source regions) 23, the drain region 24 or the gate electrode 21) can be electrically connected reliably.

  That is, the area of the margin regions of the wiring layers 30, 31, and 32 in consideration of misalignment can be greatly reduced, and the entire device can be reduced in size, and the wiring layers 30, 31, 32 and the electrode layers (sources) can be reduced. The region 23, the drain region 24, or the gate electrode 21) can be reliably connected, and the connection failure and the increase in connection resistance can be suppressed. Further, the wiring layers 30, 31, 32 can be formed in a self-aligned manner with respect to the contact holes 26, 27, 28.

  In addition, according to the configuration of the present embodiment, even if there is an alignment misalignment of the same degree as the inner diameter at the open ends of the contact holes 26, 27, 28, the conductive material exposed at the bottoms of the contact holes 26, 27, 28. Since the entire material layer 40 can be covered with the resist 41, it is possible to ensure an electrical connection state between the wiring layers 30, 31, 32 and the electrode layer (source region 23, drain region 24 or gate electrode 21). it can.

  Here, if the taper angle of the contact holes 26, 27, 28 is less than 30 °, the wiring layers 30, 31, 32 are securely attached to the inner peripheral wall surfaces of the contact holes 26, 27, 28, for example, by sputtering. Difficult to form. On the other hand, if the taper angle is larger than 80 °, the resist 41 formed inside the contact holes 26, 27, 28 is exposed to the bottoms of the contact holes 26, 27, 28. At least a part of the conductive material layer 40 covering the source region 23, the drain region 24 or the gate electrode 21) is removed. That is, poor connection between the electrode layer (source region 23, drain region 24 or gate electrode 21) and the wiring layers 30, 31, 32, and increase in connection resistance are caused.

  On the other hand, in the present embodiment, since the taper angles of the contact holes 26, 27, 28 are 30 ° or more and 80 ° or less, the wiring layers 30, 31, 32 are formed on the inner peripheral wall surfaces of the contact holes 26, 27, 28. Can be reliably formed, and connection failure between the electrode layer (source region 23, drain region 24 or gate electrode 21) and the wiring layers 30, 31, 32 and an increase in connection resistance can be suppressed.

  Further, if the thickness of the interlayer insulating film 25 is less than 0.3 μm, it becomes difficult to planarize the interlayer insulating film 25. On the other hand, if the thickness of the interlayer insulating film 25 is larger than 1.0 μm, it is difficult to penetrate the contact holes 26, 27, and 28 by photolithography.

  Therefore, in this embodiment, since the thickness of the interlayer insulating film is set to 0.3 μm or more and 1.0 μm or less, the contact holes 26, 27, and 28 are formed by photolithography while allowing the interlayer insulating film to be flattened. can do.

  If the inner diameters at the open ends of the contact holes 26, 27, and 28 are less than 1.5 μm, it is difficult to reliably form the contact holes 26, 27, and 28 by sufficient exposure by photolithography. Become. On the other hand, if the inner diameters at the open ends of the contact holes 26, 27, 28 are larger than 8 μm, the size of the contact holes 26, 27, 28 with respect to the entire TFT 1 becomes too large, and it is difficult to reduce the size of the TFT 1. become.

  On the other hand, in the present invention, the inner diameters at the open ends of the contact holes 26, 27, and 28 are formed to be 3 μm or more and 5 μm or less, so that the contact holes 26, 27, and 28 are surely formed and the TFT 1 is downsized. Can be achieved. As a result, the aperture ratio in each pixel can be improved.

<< Embodiment 2 of the Invention >>
8 to 11 show Embodiment 2 of the present invention. In the following embodiments, the same portions as those in FIGS. 1 to 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the first embodiment, the case where alignment misalignment occurs in the alignment of the mask 42 when the wiring layers 30, 31, and 32 are formed by photolithography has been described. On the other hand, in the second embodiment, a case where the alignment deviation does not occur will be described.

  As shown in FIG. 8 which is an enlarged plan view and FIG. 9 which is an enlarged cross-sectional view, the wiring layer 31 includes a first connection portion 31a and a layer further laterally (leftward in FIG. 8) from the first connection portion 31a. And a wiring portion 31 b extending on the surface of the insulating film 25. That is, the wiring layer 31 does not have the second connection part 31c in the first embodiment.

  The outer shape of the first connection portion 31 a matches the opening end 27 a of the contact hole 27 when viewed from the normal direction of the surface of the substrate 18. On the other hand, the structure of the interlayer insulating film 25 and the contact hole 27 is the same as that of the first embodiment.

  The TFT 1 of the present embodiment is manufactured in the same manner as in the first embodiment. That is, in the wiring layer forming step, the light shielding portion 43 of the mask 42 is disposed immediately above the opening end 27a of the contact hole 27 as shown in FIG. Then, the resist 41 is exposed through the mask 42. Thereafter, as shown in FIG. 11 which is an enlarged sectional view, the exposed portion of the resist 41 is developed and removed. As a result, the wiring layer 31 is patterned as shown in FIGS. Also in the second embodiment, the same effect as in the first embodiment can be obtained.

《Comparative example》
Next, a comparative example will be described with reference to FIGS. FIG. 12 is an enlarged plan view schematically showing a contact hole 50 and a wiring layer 51 constituting an electric element such as a TFT. 13 to 15 are enlarged cross-sectional views schematically showing the formation process of the wiring layer 51.

  In the first embodiment, the taper angle θ of the contact hole 27 is set to 30 ° to 80 ° (first condition), and the thickness of the interlayer insulating film 25 is set to 0.3 μm to 1.0 μm (the second condition) Condition), the inner diameter of the opening end 27a of the contact hole 27 is set to 1.5 μm or more and 8 μm or less (third condition). In contrast, in this comparative example, the first to third conditions are not satisfied. Have.

  As shown in FIGS. 12 and 13, in this comparative example, the semiconductor layer 19 and the gate insulating film 20 are formed on the substrate 18 as in the first embodiment, but the taper angle of the contact hole 50 is relatively large. In addition, the interlayer insulating film 52 is made relatively thin, and the inner diameter at the opening end 50a of the contact hole 50 is made relatively large. Therefore, a part of the source region 23 inside the contact hole 50 is not covered with the wiring layer 51.

  The wiring layer 51 is formed inside the contact hole 50 and electrically connected to the source region 23, and from the part of the opening end 27a of the contact hole 50 to the side (leftward in FIG. 12). The second connecting portion 51c extending on the surface of the interlayer insulating film 52 and the wiring portion 51b extending further on the surface of the interlayer insulating film 52 laterally (leftward in FIG. 12) from the second connecting portion 51c. ing.

  The outer shape of the second connection portion 51 c is configured by a part of a circle having a diameter larger than the inner diameter of the opening end 50 a of the contact hole 50. The width of the wiring portion 51 b in the direction orthogonal to the direction in which the wiring layer 51 extends (the vertical direction in FIG. 12) is narrower than the inner diameter of the opening end 50 a of the contact hole 50. The first connection portion 51 a covers a part of the inner peripheral wall surface of the contact hole 50 and only a part of the source region 23 inside the contact hole 50 in a thin film shape.

  When manufacturing a TFT having the contact hole 50 and the wiring layer 51, an interlayer insulating film 52 is formed on the substrate 18 so as to cover the gate insulating film 20. Subsequently, after a contact hole 50 is formed in the interlayer insulating film 52 to form the conductive material layer 54, a resist 55 is formed so as to cover the conductive material layer 54. At this time, as shown in FIG. 14, since the surface of the resist 55 is greatly depressed, the thickness of the resist 55 inside and outside the contact hole 50 is formed to be approximately the same.

  Thereafter, the resist 55 is exposed by irradiating light through the mask 53. The mask 53 has a circular light shielding portion 56 that is larger than the opening end 27 a of the contact hole 27 in plan view. The resist 55 is sufficiently exposed even in the contact hole 50 in the thickness direction. Therefore, as shown in FIG. 15, the conductive material layer 54 in contact with the source region 23 at the bottom of the contact hole 50 is exposed without being covered with the resist 55. As a result, as shown in FIG. 13, a part of the source region 23 inside the contact hole 50 is not covered with the wiring layer 51.

  Therefore, in this comparative example, when the margin region of the wiring layer 51 is relatively small, the contact area between the source region 23 inside the contact hole 50 and the wiring layer 51 is reduced due to the misalignment of the mask 53. That is, this results in a connection failure between the wiring layer 51 and the source region 23 and an increase in connection resistance.

<< Other Embodiments >>
In each of the above embodiments, the TFT has been described as an example of the electric element. However, the present invention is not limited to this, and can be similarly applied to other electric elements such as active elements. In addition to the liquid crystal display device, the present invention can be applied to other display devices such as an organic EL display device.

  As described above, the present invention is useful for an electric element, a method for manufacturing the same, and a display device. In particular, the area of the wiring layer around the opening of the contact hole is made as small as possible to reduce the size of the entire device. Suitable when trying to

3 is a plan view schematically showing a wiring layer and contact holes of Embodiment 1. FIG. 3 is a cross-sectional view schematically showing a wiring layer and a contact hole of Embodiment 1. FIG. FIG. 6 is a cross-sectional view schematically showing a wiring layer forming process of the first embodiment. FIG. 6 is a cross-sectional view schematically showing a wiring layer forming process of the first embodiment. FIG. 6 is a cross-sectional view schematically showing a wiring layer forming process of the first embodiment. It is a top view which shows the external appearance of a liquid crystal display device. It is an expanded sectional view which shows the structure of TFT. FIG. 6 is a plan view schematically showing a wiring layer and a contact hole of Embodiment 2. FIG. 6 is a cross-sectional view schematically showing a wiring layer and a contact hole of Embodiment 2. 10 is a cross-sectional view schematically showing a wiring layer forming step of Embodiment 2. FIG. 10 is a cross-sectional view schematically showing a wiring layer forming step of Embodiment 2. FIG. It is a top view which shows typically the wiring layer and contact hole of a comparative example. It is sectional drawing which shows typically the wiring layer and contact hole of a comparative example. It is sectional drawing which shows typically the formation process of the wiring layer of a comparative example. It is sectional drawing which shows typically the formation process of the wiring layer of a comparative example. It is an enlarged plan view showing the structure of a conventional TFT.

Explanation of symbols

1 TFT (electric element)
10 Liquid crystal display device
11 TFT substrate
12 Counter substrate
18 Substrate
19 Semiconductor layer
20 Gate insulation film
21 Gate electrode
22 channel region
23 Source area
24 Drain region
25 Interlayer insulation film
26, 27, 28 Contact hole
27a Open end
30, 31, 32 Wiring layer
31a 1st connection part
31b Wiring part
31c 2nd connection part
40 Conductive material layer
41 resist
42 Mask
43 Shading part

Claims (13)

An electrode layer;
An interlayer insulating film covering the electrode layer;
A contact hole formed in the interlayer insulating film so that a part of the electrode layer is exposed;
An electrical element including a wiring layer formed on the surface of the interlayer insulating film and connected to the electrode layer through the contact hole;
The contact hole is formed in a tapered shape with a smaller inner diameter from the surface of the interlayer insulating film toward the electrode layer side,
The electrical angle of the contact hole is 30 ° or more and 80 ° or less. In claim 1,
The electrical element, wherein the interlayer insulating film has a thickness of 0.3 μm or more and 1.0 μm or less. In claim 1,
An electric element having an inner diameter at an opening end of the contact hole of 1.5 μm or more and 8 μm or less. An electrode layer;
An interlayer insulating film covering the electrode layer;
A contact hole formed in the interlayer insulating film so that a part of the electrode layer is exposed;
An electrical element including a wiring layer formed on the surface of the interlayer insulating film and connected to the electrode layer through the contact hole;
The wiring layer is formed so as to cover at least a part of the inner peripheral surface of the contact hole and the entire surface of the electrode layer constituting the bottom of the contact hole, and the opening end of the contact hole An electric element characterized in that it is formed so as not to surround at least a part thereof. In claim 4,
The electrical element, wherein the wiring layer is formed over the entire inner peripheral surface of the contact hole. In claim 1 or 4,
The electrical element, wherein the wiring layer is formed in a film shape along a surface of the electrode layer and an inner peripheral surface of the contact hole. Forming a contact hole in an interlayer insulating film covering the electrode layer to expose the electrode layer; and
A conductive material layer forming step of forming a conductive material layer on the surface of the interlayer insulating film and inside the contact hole;
A wiring layer forming step of removing a part of the conductive material layer by photolithography and forming a wiring layer formed on the surface of the interlayer insulating film and connected to the electrode layer through the contact hole; A method for manufacturing an electrical element comprising:
In the contact hole forming step, the taper angle of the contact hole is formed to be 30 ° or more and 80 ° or less. In claim 7,
The method for manufacturing an electrical element, wherein the thickness of the interlayer insulating film is 0.3 μm or more and 1.0 μm or less. In claim 7,
In the contact hole forming step, an inner diameter at an opening end of the contact hole is formed to be not less than 1.5 μm and not more than 8 μm. Forming a contact hole in an interlayer insulating film covering the electrode layer to expose the electrode layer; and
A conductive material layer forming step of forming a conductive material layer on the surface of the interlayer insulating film and inside the contact hole;
A wiring layer forming step of removing a part of the conductive material layer by photolithography and forming a wiring layer formed on the surface of the interlayer insulating film and connected to the electrode layer through the contact hole; A method for manufacturing an electrical element comprising:
In the wiring layer forming step, the wiring layer is formed so as to cover at least a part of the inner peripheral surface of the contact hole and the entire surface of the electrode layer constituting the bottom of the contact hole, and The method of manufacturing an electrical element, wherein the contact hole is formed so as not to surround at least a part of the opening end of the contact hole. In claim 9,
The method of manufacturing an electrical element, wherein the wiring layer is formed over the entire inner peripheral surface of the contact hole. In claim 7 or 10,
The method of manufacturing an electrical element, wherein the wiring layer is formed in a film shape along a surface of the electrode layer and an inner peripheral surface of the contact hole. An element substrate on which a plurality of electric elements according to claim 1 or 4 are formed,
A counter substrate disposed to face the element substrate;
A display device comprising: a display medium layer provided between the counter substrate and the element substrate.

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