JP2008021733A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor integrated circuit device in which three kinds of power supply voltages are used with optimized thickness of a gate oxide film of a transistor to be used for an input/output buffer. <P>SOLUTION: In the semiconductor integrated circuit device to which three kinds of power supply voltages are supplied, the thickness of the gate oxide film of all MOS transistors of an input/output buffer 7 operating with a power supply voltage VCC3 (approx. 1.8 V) is the same as that of a transistor suitable for use of a power supply voltage VCC 2 (approx. 3.2 V). The MOS transistor used in a pre-buffer 15, a three-state circuit 16, and part of circuits (operating with the VCC3) of level shifters 10, 12 and 13 is formed in a gate length Lg shorter than that of the MOS transistor used with the power supply voltage VCC2. By forming the gate length Lg to be short even if the gate oxide films of the MOS transistors are the same, the device can be operated sufficiently at a high speed with the power supply voltage VCC3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technology for reducing the manufacturing cost of a semiconductor integrated circuit device, and more particularly to a technology effective for reducing the manufacturing process of an input / output buffer in a semiconductor integrated circuit device operating with a plurality of power supply voltages.

  In recent years, in semiconductor integrated circuit devices, the operating voltage has been lowered with the miniaturization of semiconductor devices. In an internal logic such as a CPU, for example, an operation of an internal power supply voltage VDD of about 1.2V is performed. In a semiconductor memory such as an SDRAM (Synchronous Dynamic Random Access Memory), for example, a power supply voltage of about 1.8 V is operated.

  Generally, in the field of control of electronic systems, for example, a power supply voltage VCC of about 3.3 V is widely used, and a signal having the same voltage level as the power supply voltage VCC is used in the above-described semiconductor integrated circuit device operating at low voltage. Are input / output from an externally connected peripheral device.

  Therefore, this type of semiconductor integrated circuit device is provided with a level conversion circuit for exchanging signals having different voltage levels in an I / O (Input / Output) region. The power supply voltage will be used.

  For example, when a semiconductor memory that operates at a power supply voltage of about 1.8V and a semiconductor integrated circuit device that operates at a power supply voltage VCC of about 3.3V are externally connected, 1.2V, 1.8V, and A power supply voltage of 3.3V will be used.

  However, the present inventors have found that the semiconductor integrated circuit device using a plurality of power supply voltages as described above has the following problems.

  That is, three types of gate oxide film transistors are required in order for MOS (Metal Oxide Semiconductor) transistors in the I / O region to operate optimally in accordance with each power supply voltage. This increases the number of man-hours for the manufacturing process of the semiconductor integrated circuit device, which increases the manufacturing cost of the semiconductor integrated circuit device.

  In addition, as the number of manufacturing processes increases, the yield of the semiconductor integrated circuit device may decrease, which also increases the manufacturing cost of the semiconductor integrated circuit device.

  In order to avoid these problems, in a semiconductor integrated circuit device that uses three types of power supply voltages, it may be possible to manufacture transistors used in the I / O region using two types of gate oxide film thicknesses. In this case, a transistor manufactured with a gate oxide film thickness for 3.3V, which is a power supply voltage higher than that of the transistor used with a power supply voltage of 1.8V, is used.

  However, if a transistor manufactured with a gate oxide film thickness of 3.3V is used with a power supply voltage of 1.8V, the driving capability is lowered, and high-speed operation of the semiconductor integrated circuit device becomes difficult.

  In particular, a semiconductor memory such as an SDRAM requires a higher-speed operation in the I / O region than usual, and thus cannot satisfy the operation specifications, which is a fatal problem.

  An object of the present invention is to achieve a sufficiently high speed even at a low voltage by optimizing the gate oxide film thickness of a transistor used for an input / output buffer in a semiconductor integrated circuit device using three types of power supply voltages. It is to provide a technique that can be realized and can simplify the manufacturing process.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor integrated circuit device according to the present invention includes a first power supply region to which a first power supply voltage is supplied, and a second power supply to which a second power supply voltage having a voltage level higher than the first power supply voltage is supplied. And a third power supply region to which a third power supply voltage having a voltage level higher than the second power supply voltage is supplied. The MOS transistor formed in the second power supply region has a gate oxide film thickness. An arbitrary MOS transistor formed in the second power supply region is formed with the same thickness as the gate oxide film thickness of the MOS transistor formed in the third power supply region, and the gate length is formed in the third power supply region. The MOS transistor is formed shorter than the MOS transistor.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor integrated circuit device according to the present invention, the functional module formed in the second power supply region is composed of an input / output buffer unit.

  In the semiconductor integrated circuit device according to the present invention, a volatile semiconductor memory connected externally is connected to the input / output buffer section.

  Furthermore, in the semiconductor integrated circuit device according to the present invention, the input / output buffer unit temporarily stores an externally input signal and transfers the signal to the first power supply region, and the first power supply voltage is An output buffer for temporarily storing a signal output from a power supply region to be supplied and transferring the signal to an I / O pad, and the output buffer is output from the power supply region to which a first power supply voltage is supplied A MOS that includes a driver that amplifies and outputs a signal, a pre-buffer that drives the driver, and a driver control unit that controls driving of the driver, and a gate length of the output buffer formed in the third power supply region The MOS transistor formed shorter than the transistor includes a pre-buffer and a transistor constituting a driver control unit.

  In the semiconductor integrated circuit device according to the present invention, the input / output buffer unit temporarily stores an externally input signal and transfers the signal to the first power supply region; and the first power supply voltage is An output buffer for temporarily storing a signal output from a power supply region to be supplied and transferring the signal to an I / O pad, and the output buffer is output from the power supply region to which a first power supply voltage is supplied A driver that amplifies and outputs a signal, a pre-buffer that drives the driver, and a driver control unit that controls the driving of the driver. The gate lengths of all the MOS transistors constituting the output buffer and the input buffer are 3 is formed shorter than the MOS transistor formed in the power source region 3.

  Furthermore, in the semiconductor integrated circuit device according to the present invention, the input / output buffer unit temporarily stores an externally input signal and transfers the signal to the first power source region; An output buffer for temporarily storing the output signal and transferring the signal to the I / O pad; and a level shifter for level-converting a signal input / output from the first power supply region. A driver that amplifies and outputs a signal output from the power supply region, a pre-buffer that drives the driver, and a driver control unit that performs drive control of the driver, and has a gate length formed in the third power supply region The MOS transistor formed shorter than the MOS transistor is a transistor used in a pre-buffer, a driver control unit, and a partial circuit that operates with the second power supply voltage of the level shifter. It is made from registers.

  In the semiconductor integrated circuit device according to the present invention, the input / output buffer unit temporarily stores an externally input signal and transfers the signal to the first power source region; An output buffer for temporarily storing the output signal and transferring it to the I / O pad; and a level shifter for level-converting a signal inputted / outputted from the first power supply region, the output buffer having a first power supply A second power supply for an output buffer, an input buffer, and a level shifter, comprising: a driver that amplifies and outputs a signal output from the region; a prebuffer that drives the driver; and a driver control unit that controls the driver. The gate lengths of all the MOS transistors constituting a part of the circuit that operates with voltage are formed shorter than the MOS transistors formed in the third power supply region A.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The manufacturing process of the semiconductor integrated circuit device can be simplified.

  (2) According to the above (1), the yield of the semiconductor integrated circuit device can be improved, and the manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is an input provided in an I / O region operated by a power supply voltage VCC3 provided in the semiconductor integrated circuit device of FIG. It is explanatory drawing which shows the cell structure of an output buffer part.

  In the first embodiment, the semiconductor integrated circuit device 1 includes a plurality of power supply regions to which a plurality of power supply voltages having different voltage levels are supplied. As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a CPU 2, a built-in memory 3, and the like, and includes a core region 4 serving as a first power supply region and an I / O (Input / Output) region serving as a third power supply region. 5 and an I / O area 6 which is a second power supply area.

  The CPU 2 functions as a central processing unit and manages all the controls in the semiconductor integrated circuit device 1. The built-in memory 3 is composed of a volatile semiconductor memory such as a DRAM (Dynamic Random Access Memory), for example, and temporarily stores programs, data, and the like.

  Input / output buffers are provided in the I / O area 5 and the I / O area 6, respectively. An externally connected external device is connected to the I / O area 5, and an externally connected semiconductor memory M is connected to the I / O area 6. The semiconductor memory M is composed of, for example, a volatile semiconductor memory that performs high-speed operation such as SDRAM (Synchronous DRAM).

  The core region 4 is a power supply region that operates at a power supply voltage VCC1 of about 1.2 V, which is a first power supply voltage, for example. The I / O (Input / Output) region 5 is a power supply region that operates at a power supply voltage VCC2 of about 3.3 V, which is a third power supply voltage, for example. The I / O region 6 is a power supply region that operates at a power supply voltage VCC3 of about 1.8 V, which is the second power supply voltage, for example, as with the operating voltage of the semiconductor memory M.

  FIG. 2 is an explanatory diagram showing a cell configuration of the input / output buffer unit 7 provided in the I / O region 6 operated by the power supply voltage VCC3.

  The input / output buffer unit 7 includes an output buffer unit 7a, an input buffer 7b, and a level shifter unit 7c.

  The output buffer unit 7a includes an ESD (Electrostatic Discharge) protection circuit 8 and an output buffer. Further, the level shifter section 7c is composed of level shifters 10-13.

  The ESD protection circuit 8 is a circuit that absorbs overvoltage and prevents destruction of the device due to electrostatic discharge (ESD), and includes diodes D1 and D2 and a resistor R.

  The cathode of the diode D1 is connected to be supplied with the power supply voltage VCC3, and the anode of the diode D1 is connected to the I / O pad PAD of the semiconductor integrated circuit device 1. A semiconductor memory M is connected to the I / O pad PAD via an I / O terminal of the semiconductor integrated circuit device.

  The anode of the diode D1 is connected to the cathode of the diode D2 and one connection portion of the resistor R, and the cathode of the diode D2 is connected to the reference potential VSS.

  The output buffer 9 temporarily stores the output signal output from the core area 4 and transfers it to the I / O pad PAD. The input buffer unit 7 b temporarily stores an input signal input from the outside via the I / O pad PAD and transfers it to the core area 4.

  The output buffer 9 includes an output unit 14 that functions as a driver, a pre-buffer 15, and a three-state 16 that functions as a driver control unit.

  The output unit 14 includes transistors T1 and T2. The prebuffer 15 includes inverters Iv1 and Iv2, and the three-state 16 includes a NAND circuit NAND, a NOR circuit NOR, and inverters Iv3 to Iv5.

  The transistor T1 is a P-channel MOS (Metal Oxide Semiconductor), and the transistor T2 is an N-channel MOS.

  The transistors T1 and T2 are connected to be connected in series between the power supply voltage VCC3 and the reference potential VSS so as to have an inverter configuration. The other connection portion of the resistor R and one input portion of the input buffer portion 7b are connected to the connection portion between the transistor T1 and the transistor T2.

  The output portion of the inverter Iv1 is connected to the gate of the transistor T1, and the output portion of the inverter Iv2 is connected to the gate of the transistor T2. Output parts of inverters Iv3 and Iv4 are connected to input parts of inverters Iv1 and Iv2, respectively.

  The output part of the NAND circuit NAND is connected to the input part of the inverter Iv3, and the output part of the NOR circuit NOR is connected to the input part of the inverter Iv3. The output part of the level shifter 12 is connected to one input part of the NAND circuit NAND and the NOR circuit NOR.

  The other input of the NAND circuit NAND is connected to the output part of the inverter Iv4. The other input part of the NOR circuit NOR and the output part of the level shifter 13 are connected to the input part of the inverter Iv4. Each is connected.

  The other input part of the input buffer 7 b is connected so that the reference voltage VREF is inputted. The output part of the output buffer 10 is connected to the input part of the level shifter 10. Further, the output section of the level shifter 11 is connected to the control terminal of the input buffer 7b.

  The level shifter 10 converts the input signal CIN amplitude of the power supply voltage VCC3 output from the input buffer 7b into an input signal CIN of the power supply voltage VCC1 and outputs it. The level shifter 11 converts the input buffer enable signal IE for enabling the input buffer 7b output from the core region 4 from a power supply voltage VCC1 amplitude to a signal having the power supply voltage VCC3 amplitude, and outputs the converted signal.

  The level shifter 12 converts the output signal I having the power supply voltage VCC1 amplitude output from the core region 4 into an output signal having the power supply voltage VCC3 amplitude, and outputs the output signal to the output buffer unit 7a.

  The level shifter 13 converts the output buffer enable signal OEN having the power supply voltage VCC1 amplitude output from the core region 4 into an output signal having the power supply voltage VCC3 amplitude, and outputs the output signal to the output buffer 10. The output buffer enable signal OEN is a signal for enabling the output buffer 9.

  Next, a transistor constituting the input / output buffer unit 7 in the present embodiment will be described.

  In the input / output buffer unit 7 operated by the power supply voltage VCC3, the gate oxide film thicknesses of all the MOS transistors constituting the input / output buffer unit 7 are all formed with the gate oxide film thickness adapted to the use of the power supply voltage VCC2. Yes.

  In the area shown by the shaded area in FIG. 2, that is, in the pre-buffer 15, the three-state 16, and the MOS transistors used in the partial circuits of the level shifters 10, 12, and 13 operating at the power supply voltage VCC3, It is formed with a gate length Lg shorter than the gate length Lg of the MOS transistor designed in accordance with the voltage VCC2.

  As described above, even if the gate oxide film of the MOS transistor has the same film thickness, the MOS transistor used in the partial circuit of the level shifters 10, 12 and 13 operating at the power supply voltage VCC3 is used at the power supply voltage VCC2. By forming the MOS transistor so as to be shorter than the gate length Lg of the MOS transistor, it is possible to operate at a sufficiently high speed with the power supply voltage VCC3 which is a voltage lower than the power supply voltage VCC2.

  Here, the definition of the gate length Lg in the MOS transistor used in the input / output buffer unit 7 will be described.

  The minimum gate length Lg1 of the MOS transistor used at the power supply voltage VCC2 is obtained as follows.

Gate length LgC1 <Gate length Lg1
Gate length LgC2 <gate length Lg1
Gate length LgC3 <gate length Lg1
The maximum value of these gate lengths LgC1, LgC2, and LgC3 is assumed to be gate length LgC = max (C1, C2, C3).

Therefore, the minimum gate length Lg1 of the MOS transistor used at the power supply voltage VCC2 is
LgC <gate length Lg1
It becomes.

  Here, the gate length LgC1 is the minimum gate length that satisfies the arbitrary standard of the hot carrier lifetime in the MOS transistor when the power supply voltage VCC2 is used, and the gate length LgC2 is between the drain and the source in the MOS transistor when the power supply voltage VCC2 is used. The gate length LgC3 is a gate length that satisfies the lower limit of the arbitrary standard of the gate breakdown voltage in the MOS transistor when the power supply voltage VCC2 is used.

  Further, the minimum gate length Lg2 of the MOS transistor used at the power supply voltage VCC3 is obtained as follows.

Gate length LgA1 <Gate length Lg2
Gate length LgA2 <Gate length Lg2
Gate length LgA3 <Gate length Lg2
The maximum of these gate lengths LgA1, LgA2, and LgA3 is: gate length LgA = max (A1, A2, A3).

Therefore, the minimum gate length Lg2 of the MOS transistor used at the power supply voltage VCC3 is
Gate length LgA <gate length Lg2
It becomes.

  Here, the gate length LgA1 is the minimum gate length satisfying an arbitrary standard of the hot carrier lifetime in the MOS transistor used at the power supply voltage VCC3, and the gate length LgA2 is the drain-source in the MOS transistor when using the power supply voltage VCC3. The gate length LgA3 is a gate length that satisfies the lower limit of the arbitrary standard of the gate breakdown voltage in the MOS transistor when the power supply voltage VCC3 is used.

Therefore, from the above, the appropriate gate length Lg of the MOS transistor used in each of the power supply voltages VCC3 and VCC2 is
A <gate length Lg (power supply voltage VCC3) <B <C <gate length Lg (power supply voltage VCC2)
It becomes.

  Thereby, according to the first embodiment, the MOS transistor used in the semiconductor integrated circuit device 1 can be manufactured by using two types of gate oxide films, so that the manufacturing yield of the semiconductor integrated circuit device 1 can be improved. it can.

(Embodiment 2)
FIG. 3 is an explanatory diagram showing a cell configuration of the input / output buffer unit provided in the I / O region operated by the power supply voltage VCC3 provided in the semiconductor integrated circuit device according to the second embodiment of the present invention.

  In the second embodiment, as in FIG. 1 of the first embodiment, the semiconductor integrated circuit device 1 includes a core area 4 including a CPU 2 and a built-in memory 3, an I / O (Input / Output) area 5, and It consists of an I / O area 6.

  Also in this case, the core region 4 is, for example, a power supply region that operates at a power supply voltage VCC1 of about 1.2V, and the I / O (Input / Output) region 5 is, for example, at a power supply voltage VCC2 of about 3.3V. This is the power supply area that operates. The I / O region 6 is a power supply region that operates at a power supply voltage VCC3 of about 1.8 V, for example, like the operating voltage of the semiconductor memory M.

  The semiconductor integrated circuit device 1 is different from the first embodiment in the configuration of the input / output buffer unit 7 provided in the I / O region 6 operated by the power supply voltage VCC3.

  FIG. 3 is an explanatory diagram showing a cell configuration of the input / output buffer unit 7 provided in the I / O area 6.

  As shown in the figure, the input / output buffer unit 7 has a configuration similar to that of the first embodiment, which includes an output buffer unit 7a and an input buffer 7b, with a termination resistor unit 17, a termination resistor switching control unit 18, and a level shifter unit 7c. The level shifters 19 and 19a provided in the above are added.

  The termination resistor 17 prevents signal reflection when a signal is input via the I / O pad PAD. Terminating resistor 17 is composed of transistors T3 to T6 and resistors R1 to R4. Transistors T3 and T5 are composed of P-channel MOS, and transistors T4 and T6 are composed of N-channel MOS.

  Further, the termination resistance switching control unit 18 performs switching and operation control of the resistors R1 to R4 functioning as termination resistors in accordance with the input signal. The termination resistance switching control unit 18 includes a negative logical product circuit NAND1, a negative logical sum circuit NOR1, and inverters Iv6 to Iv8.

  The level shifter 19 converts the control signal ODTE having the amplitude of the power supply voltage VCC1 output from the core region 4 into a signal having the amplitude of the power supply voltage VCC3 and outputs the signal. The control signal ODTE is connected to be input to the termination resistance switching control unit 18 through the level shifter 19.

  The level shifter 19a is also connected so that the select signal TSEL output from the core region 4 is also input. The level shifter 19a converts the selection signal TSEL having the amplitude of the power supply voltage VCC1 output from the core region 4 into a signal having the amplitude of the power supply voltage VCC3 and outputs the signal. The termination resistance switching control unit 18 is connected so that the select signal TSEL output from the level shifter 19a is also input.

  The control signal ODTE activates the resistors R1 to R4 functioning as termination resistors by turning on the transistors T3 to T6 when an input signal is input. The select signal TSEL is a signal for selecting whether or not to operate the transistors T3 and T4 when the control signal ODTE is input, and thereby varies the termination resistance value.

  One of connection portions of the transistors T3 and T5 is connected to be supplied with the power supply voltage VCC3. One connection portion of the resistor R1 is connected to the other connection portion of the transistor T3, and one connection portion of the resistor R2 is connected to the other connection portion of the resistor R1.

  One connection portion of the transistor T4 is connected to the other connection portion of the resistor R2, and the reference potential VSS is connected to the other connection portion of the transistor T4. One connecting portion of the resistor R3 is connected to the other connecting portion of the transistor T5, and one connecting portion of the resistor R4 and connecting portions of the resistors R1 and R2 are connected to the other connecting portion of the transistor R3. Are connected to each other. Further, the other connection portion of the resistor R of the ESD protection circuit 8 is connected to the connection portion of the resistors R1 and R2.

  One connection portion of the transistor T6 is connected to the other connection portion of the resistor R4, and the reference potential VSS is connected to the other connection portion of the transistor T6.

  The output of the NAND circuit NAND1 is connected to the gate of the transistor T3, and the output of the NOR circuit NOR1 is connected to the gate of the transistor T4.

  The gate of the transistor T5 is connected to the output part of the inverter Iv6, the input part of the inverter Iv8, and one input part of the NOR circuit NOR1. The output part of the inverter Iv8 is connected to the gate of the transistor T6.

  The control signal ODTE output from the level shifter 19a is connected to one input portion of the NAND circuit NAND1 and the input portion of the inverter Iv6 so as to be input respectively. The other input part of the NAND circuit NAND1 and the input part of the inverter Iv7 are connected so that the select signal TSEL is input thereto.

  Also in the second embodiment, the input / output buffer unit 7 operated by the power supply voltage VCC3 has a gate oxide film thickness of all the MOS transistors constituting the input / output buffer unit 7 in accordance with the use of the power supply voltage VCC2. It is formed with an oxide film thickness.

  In the area shown by shading in FIG. 3, that is, in the pre-buffer 15, the three-state 16, and the MOS transistors used in the partial circuits of the level shifters 10, 12, and 13 operating at the power supply voltage VCC3, It is formed with a gate length Lg shorter than the gate length Lg of the MOS transistor designed in accordance with the voltage VCC2.

  Also in this case, the pre-buffer 15, the three-state 16, and the level shifters 10, 12, and 13 can be operated at a sufficiently high speed even when the operating voltage is the power supply voltage VCC3.

  Thereby, also in the second embodiment, since the MOS transistor used in the semiconductor integrated circuit device 1 can be manufactured with two types of gate oxide films, the manufacturing yield of the semiconductor integrated circuit device 1 can be improved. .

(Embodiment 3)
FIG. 4 is an explanatory diagram showing the cell configuration of the input / output buffer unit provided in the I / O region operated by the power supply voltage VCC3 provided in the semiconductor integrated circuit device according to the third embodiment of the present invention.

  Also in the third embodiment, the semiconductor integrated circuit device 1 includes the core area 4, the I / O area 5, and the I / O area including the CPU 2 and the built-in memory 3 as in FIG. 1 of the first embodiment. Here, the core region 4 is a power source region that operates at a power source voltage VCC1 of about 1.2V, and the I / O region 5 is a power source that operates at a power source voltage VCC2 of about 3.3V. The I / O region 6 is a power supply region that operates with a power supply voltage VCC3 of about 1.8V.

  The difference from the first and second embodiments is that when the input / output buffer unit 7 provided in the I / O area 6 outputs an output signal, a normal output signal and its inverted output signal are output. It has the structure which has the function to do.

  FIG. 4 is an explanatory diagram showing a cell configuration of the input / output buffer unit 7.

  In this case, the input / output buffer unit 7 has the same configuration as that of the first embodiment including the output buffer unit 7a, the input buffer 7b, and the level shifter unit 7c, and the output buffer unit 7a1, the input buffer unit 7b1, and the level shifter unit 7c. The level shifter 20 provided in is added.

  Since the output buffer unit 7a and the input buffer 7b have the same connection configuration as that of FIG.

  Similarly to the output buffer unit 7a, the output buffer unit 7a1 includes an ESD protection circuit 8a and an output buffer 9a. The ESD protection circuit 8a includes diodes D1a and D2a and a resistor Ra. The configuration of the output buffer 9a includes an output unit 14a, a pre-buffer 15a, and a three-state 16a.

  The output unit 14a includes transistors T1a and T2a. The pre-buffer 15a is composed of inverters Iv1a and Iv2a, and the three-state 16a is composed of a negative logical product circuit NANDa, a negative logical sum circuit NORa, and inverters Iv3a to Iv5a.

  The other input part of the NOR circuit NORa and the input part of the inverter Iv4a are connected to the output part of the level shifter 13, respectively. One input part of the NAND circuit NANDa and one of the NOR circuits NORa Are connected so that an inverted signal output from the level shifter 12 is input thereto.

  The input unit of the level shifter 20 is connected to the output unit of the input buffer 7b1. The level shifter 20 converts the input signal having the power supply voltage VCC3 amplitude output from the input buffer 7b1 into the input signal CIN1 having the power supply voltage VCC1 amplitude and outputs the converted signal.

  An I / O pad PADB of the semiconductor integrated circuit device 1 is connected to a connection portion between the diodes D1 and D2. Since other connection configurations are the same as those of the output buffer unit 7a, the input buffer 7b, and the level shifter unit 7c, the description thereof is omitted.

  Also in the third embodiment, in the input / output buffer unit 7 operating with the power supply voltage VCC3, the gate oxide film thicknesses of all the MOS transistors constituting the input / output buffer unit 7 are all adapted to the use of the power supply voltage VCC2. It is formed with a gate oxide film thickness.

  4 are used in the partial buffers of the level shifters 10, 12, 13, and 20 that operate with the pre-buffers 15 and 15a, the three-states 16 and 16a, and the power supply voltage VCC3, which are the shaded areas in FIG. The MOS transistor is formed with a gate length Lg shorter than the gate length Lg of the MOS transistor designed according to the power supply voltage VCC2.

  Also in this case, the pre-buffers 15 and 15a, the three-states 16 and 16a, and the level shifters 10, 12, and 13 can be operated at a sufficiently high speed even when the operating voltage is the power supply voltage VCC3.

  Thereby, also in the third embodiment, since the MOS transistor used in the semiconductor integrated circuit device 1 can be manufactured with two types of gate oxide films, the manufacturing yield of the semiconductor integrated circuit device 1 can be improved. .

(Embodiment 4)
FIG. 5 is an explanatory diagram showing a cell configuration of the input / output buffer unit provided in the I / O region operated by the power supply voltage VCC3 provided in the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

  Also in the fourth embodiment, the semiconductor integrated circuit device 1 includes the core area 4, the I / O area 5, and the I / O area 6 including the CPU 2 and the built-in memory 3 as in FIG. Here, the core area 4 is a power supply area that operates at a power supply voltage VCC1 of approximately 1.2V, and the I / O area 5 is a power supply area that operates at a power supply voltage VCC2 of approximately 3.3V. The I / O region 6 is a power supply region that operates at a power supply voltage VCC3 of about 1.8V.

  In this case, the input / output buffer unit 7 provided in the I / O area 6 has a configuration similar to that shown in FIG. 4 of the third embodiment including the output buffer units 7a and 7a1, the input buffer 7b, and the level shifter unit 7c. Resistors 17 and 17a, termination resistance switching controllers 18a and 18b, three-state controller 23, and level shifters 21 and 22 provided in the level shifter 7c are added.

  The connection configurations of the output buffer units 7a and 7a1, the input buffer 7b, the ESD protection circuits 8 and 8a, the termination resistor units 17 and 17a, and the level shifters 10 to 13 are the same as those in FIG. The termination resistance switching control unit 18a includes inverters Iv9 to Iv15 and NAND circuits NAND2 to NAND4. Similarly, the termination resistance switching control unit 18b includes inverters Iv18 to Iv20, NOR circuits NOR3 and NOR4, and NAND circuits NAND5 to NAND7. The three-state control unit 23 includes inverters Iv16 and Iv17 and a negative OR circuit NOR2.

  The termination resistance switching control unit 18a activates or pulls the I / O pad PAD based on the control operation of switching the resistors R1 to R4 functioning as termination resistors based on the input control signal ODTE and the control signal PUDN. Transition to one of up.

  The termination resistance switching control unit 18b controls the switching of the resistors R1 to R4 functioning as termination resistors based on the input control signal ODTE, and activates or pulls down the I / O pad PAD based on the control signal PUDN. The I / O pad PADB is set to either indefinite or active according to the transition to any one and the control signal DBL output via the three-state control unit 23.

  The three-state control unit 23 controls the control signal DBL input via the level shifter 22 and the control signal output to the termination resistance switching control unit 18b based on the signal states of the output buffer enable signal OEN input via the level shifter 13. ODTE output control is performed.

  The level shifter 21 converts the control signal PUDN having the power supply voltage VCC1 amplitude output from the core region 4 into an output signal having the power supply voltage VCC3 amplitude and outputs the output signal. The level shifter 22 converts the control signal DBL having the power supply voltage VCC1 amplitude output from the core region 4 into an output signal having the power supply voltage VCC3 amplitude, and outputs the output signal.

  Also in the fourth embodiment, in the input / output buffer unit 7 operated by the power supply voltage VCC3, the gate oxide film thicknesses of all the MOS transistors constituting the input / output buffer unit 7 are all adapted to the use of the power supply voltage VCC2. It is formed with a gate oxide film thickness.

  The MOS transistors used in the partial buffers of the level shifters 10, 12, and 13 operating with the pre-buffers 15 and 15a, the three-states 16 and 16a, and the power supply voltage VCC3, which are the shaded areas in FIG. In FIG. 2, the gate length Lg is shorter than the gate length Lg of the MOS transistor designed in accordance with the power supply voltage VCC2.

  As a result, the pre-buffers 15 and 15a, the three-states 16 and 16a, and the level shifters 10, 12, and 13 can be operated at a sufficiently high speed even when the operating voltage is the power supply voltage VCC3.

  Thereby, also in the fourth embodiment, since the MOS transistor used in the semiconductor integrated circuit device 1 can be manufactured with two types of gate oxide films, the manufacturing yield of the semiconductor integrated circuit device 1 can be improved. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fourth embodiments, the pre-buffers in the input / output buffer unit 7 (areas shown by hatching in FIGS. 2 to 5) and the three states (areas shown by hatching in FIGS. 2 to 5). ), And only the MOS transistors used in the partial circuits of the level shifters (areas shown by shading in FIGS. 2 to 5) operating at the power supply voltage VCC3 are the gates of the MOS transistors designed to match the power supply voltage VCC2. Although the gate length Lg is shorter than the length Lg, the gates of the MOS transistors are designed so that all the MOS transistors constituting the input / output buffer 7 shown in FIGS. 2 to 5 are designed to match the power supply voltage VCC2. The gate length Lg may be shorter than the length Lg.

  The present invention is suitable for a technique for manufacturing an I / O buffer unit in a semiconductor integrated circuit device to which a plurality of power supply voltages are supplied.

1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing a cell configuration of an input / output buffer unit provided in an I / O region operated by a power supply voltage VCC3 provided in the semiconductor integrated circuit device of FIG. 1; It is explanatory drawing which shows the cell structure of the input / output buffer part provided in the I / O area | region which operate | moves with the power supply voltage VCC3 provided in the semiconductor integrated circuit device by Embodiment 2 of this invention. It is explanatory drawing which shows the cell structure of the input / output buffer part provided in the I / O area | region which operate | moves with the power supply voltage VCC3 provided in the semiconductor integrated circuit device by Embodiment 3 of this invention. It is explanatory drawing which shows the cell structure of the input / output buffer part provided in the I / O area | region which operate | moves with the power supply voltage VCC3 provided in the semiconductor integrated circuit device by Embodiment 4 of this invention.

Explanation of symbols

1 Semiconductor Integrated Circuit Device 2 CPU
3 Internal Memory 4 Core Area 5 I / O Area 6 I / O Area 7 Input / Output Buffer Units 7a and 7a1 Output Buffer Unit 7b Input Buffer 7b1 Input Buffer 7c Level Shifter Unit 8 ESD Protection Circuit 8a ESD Protection Circuit 9 Output Buffer 10 Level Shifter 11 Level shifter 12 Level shifter 13 Level shifter 14 Output unit 14a Output unit 15 Pre-buffer 15a Pre-buffer 16 Three-state 16a Three-state 17 Termination resistor unit 17, 17a Termination resistor unit 18 Termination resistor switching control unit 18a, 18b Termination resistor switching control unit 19, 19a Level shifter 20 Level shifter 21, 22 Level shifter 21, 22 Level shifter 23 Three-state controller M Semiconductor memory D1, D2 Diode D1a, D2a Diode R Resistor Ra Resistor R1-R4 Resistor P AD I / O pad PADB I / O pads T1-6 Transistors T1a, T2a Transistors Iv1-Iv20 Inverters Iv1a, Iv2a Inverters Iv3a-Iv5a Inverters NAND NAND circuit NAND1 NAND circuit NANDa NAND circuit NAND2-NAND7 NAND logic Product circuit NOR Negative OR circuit NOR1 Negative OR circuit NORa Negative OR circuit NOR3, NOR4 Negative OR circuit

Claims (7)

A first power supply region to which a first power supply voltage is supplied;
A second power supply region to which a second power supply voltage having a voltage level higher than the first power supply voltage is supplied;
A third power supply region to which a third power supply voltage having a voltage level higher than the second power supply voltage is supplied;
The MOS transistor formed in the second power supply region is
The gate oxide film is formed with the same film thickness as the gate oxide film of the MOS transistor formed in the third power supply region,
An arbitrary MOS transistor formed in the second power supply region is
A semiconductor integrated circuit device, wherein a gate length is shorter than a MOS transistor formed in the third power supply region. The semiconductor integrated circuit device according to claim 1.
The functional module formed in the second power source region is
A semiconductor integrated circuit device which is an input / output buffer unit. The semiconductor integrated circuit device according to claim 2.
The input / output buffer unit is:
A semiconductor integrated circuit device, wherein an externally connected volatile semiconductor memory is connected. The semiconductor integrated circuit device according to claim 2 or 3,
The input / output buffer unit is:
An input buffer for temporarily storing an externally input signal and transferring the signal to the first power supply region;
An output buffer that temporarily stores a signal output from a power supply region to which the first power supply voltage is supplied and transfers the signal to an I / O pad;
The output buffer is
A driver that amplifies and outputs a signal output from a power supply region to which the first power supply voltage is supplied;
A prebuffer for driving the driver;
A driver control unit that performs drive control of the driver,
Among the output buffers, the MOS transistor formed with a gate length shorter than that of the MOS transistor formed in the third power supply region is a MOS transistor constituting the pre-buffer and the driver control unit. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 2 or 3,
The input / output buffer unit is:
An input buffer for temporarily storing an externally input signal and transferring the signal to the first power supply region;
An output buffer that temporarily stores a signal output from a power supply region to which the first power supply voltage is supplied and transfers the signal to an I / O pad;
The output buffer is
A driver that amplifies and outputs a signal output from a power supply region to which the first power supply voltage is supplied;
A prebuffer for driving the driver;
A driver control unit that performs drive control of the driver,
2. A semiconductor integrated circuit device according to claim 1, wherein gate lengths of all MOS transistors constituting the output buffer and the input buffer are shorter than MOS transistors formed in the third power supply region. The semiconductor integrated circuit device according to claim 2 or 3,
The input / output buffer unit is:
An input buffer for temporarily storing an externally input signal and transferring the signal to the first power supply region;
An output buffer for temporarily storing a signal output from the first power supply region and transferring the signal to an I / O pad;
A level shifter for level-converting a signal inputted / outputted from the first power supply region,
The output buffer is
A driver that amplifies and outputs a signal output from the first power supply region;
A prebuffer for driving the driver;
A driver control unit that performs drive control of the driver,
The MOS transistor formed with a gate length shorter than that of the MOS transistor formed in the third power supply region is
A semiconductor integrated circuit device, which is a MOS transistor used in a partial circuit that operates with the second power supply voltage of the prebuffer, the driver controller, and the level shifter. The semiconductor integrated circuit device according to claim 2 or 3,
The input / output buffer unit is:
An input buffer for temporarily storing an externally input signal and transferring the signal to the first power supply region;
An output buffer for temporarily storing a signal output from the first power supply region and transferring the signal to an I / O pad;
A level shifter for level-converting a signal inputted / outputted from the first power supply region,
The output buffer is
A driver that amplifies and outputs a signal output from the first power supply region;
A prebuffer for driving the driver;
A driver control unit that performs drive control of the driver,
The gate lengths of all the MOS transistors constituting a partial circuit operating with the second power supply voltage of the output buffer, the input buffer, and the level shifter are larger than those of the MOS transistors formed in the third power supply region. A semiconductor integrated circuit device characterized by being formed short.

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