JP2008017400A - Pll synthesizer circuit for am/fm receiver and switching method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL synthesizer circuit which improves S/N characteristics by controlling a crossover frequency in AM reception and FM reception. <P>SOLUTION: The present invention relates to the PLL synthesizer circuit for an AM/FM receiver comprising: a phase comparator circuit which generates a phase difference signal in accordance with a phase difference between a reference signal and a frequency-divided signal frequency-dividing an output signal of the PLL synthesizer circuit; a charge pump circuit which performs current control based on the phase difference signal and generates a charge pump signal while switching the current control in use for AM and in use for FM; a register circuit for switching the current control of the charge pump circuit in use for AM and in use for FM; a VCO circuit which inputs the charge pump signal, smoothes the charge pump signal, oscillates at a frequency corresponding to a control voltage signal as a control voltage and outputs a local oscillation signal; and a frequency divider circuit which frequency-divides the local oscillation signal and outputs a result as the frequency-divided signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PLL synthesizer (phase locked loop synthesizer) circuit, and more particularly to a technique of a PLL synthesizer circuit used in an AM (Amplitude Modulation) / FM (Frequency Modulation) receiver.

  In recent years, many PLL synthesizer circuits are used in AM / FM receivers. The PLL synthesizer circuit is a circuit that has one VCO and detects the phase difference and controls the VCO by feedback so that the frequency and phase of the oscillator match the frequency and phase of the input signal from the outside.

  FIG. 12 is a diagram showing a PLL synthesizer circuit. The PLL synthesizer circuit includes an oscillation circuit 111, a frequency divider circuit 112, a phase comparison circuit 113, a charge pump circuit 114 (Charge Pump), a loop filter circuit 115 (loop filter: low-pass filter, etc.), and a VCO circuit 116 (Voltage-Controlled Oscillator: Voltage-controlled oscillation circuit), a programmable frequency divider circuit 117, and a frequency divider circuit 118.

The oscillation circuit 111 is an oscillator that generates a reference frequency (f_REF).
The frequency dividing circuit 112 divides the reference frequency by the frequency dividing ratio A and inputs it to the phase comparison circuit 113.
The phase comparison circuit 113 performs phase comparison between a reference signal obtained by dividing the reference signal by 1 / A and a divided signal that is an output of a programmable frequency dividing circuit 117 described later, and outputs a positive / negative phase difference signal.

  The charge pump circuit 114 outputs a charge pump signal based on the phase difference signal. Thereafter, the high frequency component of the charge pump signal is removed by the loop filter circuit 115 and an oscillation control signal obtained by smoothing the charge pump signal P is output.

The VCO circuit 116 generates an oscillation signal (FM local oscillation signal) having the oscillation frequency fo in response to the supply of the oscillation control signal.
The programmable frequency dividing circuit 117 divides the oscillation signal by the frequency division ratio B set by the frequency division ratio setting data to generate a frequency division signal having the oscillation frequency fo / B. Here, the programmable frequency dividing circuit 117 has an input interface for generating frequency division ratio setting data in response to the supply of frequency setting data from the outside by a controller.

The frequency dividing circuit 118 divides the oscillation signal by the frequency dividing ratio C to generate an AM local oscillation signal.
Next, the PLL synthesizer circuit is a circuit that sets a desired frequency fo with frequency setting data and controls the oscillation signal of the VCO circuit 116 so that the phases of the reference signal and the divided signal coincide. The phase comparison circuit 113 compares the phases of the reference signal and the frequency-divided signal. When the phase of the frequency-divided signal is delayed from the reference signal, a positive phase difference signal is displayed. When the phase is advanced, the phase is negative. A phase difference signal is generated and supplied to the charge pump circuit 114.

  The charge pump circuit 114 generates a positive DC signal (charge pump signal) when a positive phase difference signal is supplied, and generates a negative DC signal (charge pump signal) when it is a negative phase signal. To do. The charge pump signal generated in this way is supplied to the loop filter circuit 115. The loop filter circuit 115 smoothes the charge pump signal, outputs an oscillation control signal, and supplies it to the VCO circuit 116. The VCO circuit 116 generates an oscillation signal having an oscillation frequency fo corresponding to the voltage level of the oscillation control signal, outputs an FM local oscillation signal, and supplies it to the programmable frequency divider 117. When the voltage of the oscillation control signal is high, the frequency is high, and when the voltage is low, the frequency is low.

  In the programmable frequency dividing circuit 117, the frequency dividing ratio B is set by frequency dividing ratio data from an input interface or the like, and generates a frequency divided signal having the same frequency fo / B as the reference frequency in response to the supply of the oscillation signal. In this way, control is performed so that the phase difference between the reference frequency and the frequency fo / B becomes zero. After the frequency is locked, the phase difference signal is not output, and for example, the output of the charge pump circuit 114 is in a high impedance state.

An important factor that determines the S / N characteristic of such an AM / FM receiver is the phase noise characteristic of the PLL synthesizer circuit.
According to Patent Document 1, a control current flowing out or flowing in from a charge pump circuit based on an up clock or a down clock supplied from a phase frequency comparator is smoothed with an LPF to obtain a control voltage. An internal clock having an oscillation frequency corresponding to the control voltage of the oscillation frequency band based on the oscillation frequency band setting data is generated by the VCO circuit. As the frequency dividing circuit, a PLL circuit that divides an internal clock by a frequency dividing ratio N based on the multiplication rate setting data and outputs it as a frequency divided clock has been proposed. Further, the value of the control current is changed based on the oscillation frequency band setting data and the multiplication rate setting data.

  According to Patent Document 2, the PLL synthesizer circuit is provided with a current amount control circuit that controls the amount of charge pump current based on a band control signal for switching the oscillation frequency band of the voltage controlled oscillator. Here, the amount of the charge pump current is controlled to be small when the oscillation frequency band of the voltage controlled oscillator is high and large when it is low. Thereby, the change in the gain of the voltage controlled oscillator and the change in the charge pump current are canceled out, and the loop bandwidth can be kept constant. As a result, a PLL synthesizer circuit capable of switching an oscillation frequency band that can reduce variations in phase noise characteristics and lock-up time has been proposed.

According to Patent Literature 3, fluctuations in lock time and noise characteristics between each frequency in the high frequency band and the low frequency band are suppressed. A PLL synthesizer circuit with a wide frequency range that controls the charge pump control current of the charge pump current control circuit according to the control data generated from the division ratio setting data and variably controls the current value of the charge pump signal generated by the charge pump circuit. Has been proposed.
Japanese Patent Laid-Open No. 2001-160752 JP 2004-274673 A JP 09-093125 A

  However, the S / N characteristic of the AM / FM receiver is greatly influenced by the phase noise characteristic of the local oscillation signal. Further, since the ideal characteristics of phase noise of AM and FM are different, there is a problem that if the loop filter circuit is made common to AM and FM, the optimum phase noise characteristic is deviated and the best S / N characteristic is not obtained.

  For example, the graph shown in FIG. 13 is a diagram showing phase noise in the VCO circuit 116 alone (open loop). The vertical axis shows phase noise, and the horizontal axis shows the frequency of the detuning point from the center frequency (carrier) (the axis of the detuning frequency is Log display). The detuning point indicates how far away from the center frequency.

Patent Documents 1 to 3 do not propose changing the phase noise characteristic (crossing frequency) between AM and FM in this way.
Further, if the constant of the loop filter circuit is fixed and the control current of the charge pump circuit is fixed, the crossing frequency is fixed and the ideal characteristics of FM and AM cannot be compatible.

Further, there is a problem that the number of parts increases when the constant of the loop filter circuit is switched by AM / FM in order to change the crossing frequency.
The present invention has been made in view of the above circumstances, and provides a PLL synthesizer circuit that improves the S / N characteristics of an AM / FM receiver by controlling the crossover frequency during AM reception and FM reception. The purpose is to do.

  A PLL synthesizer circuit for an AM / FM receiver, which is one aspect of the present invention, an oscillation circuit that generates a reference signal, and a level between the reference signal and a divided signal obtained by dividing the output signal of the PLL synthesizer circuit A phase comparison circuit that generates a phase difference signal (for example, an up clock or a down clock) according to the phase difference, current control based on the phase difference signal, and a case of using in AM and a case of using in FM A charge pump circuit that switches a current control to generate a charge pump signal, a register circuit that holds and sets a code for switching the current control of the charge pump circuit when used in AM and FM A loop filter circuit that receives and smoothes the charge pump signal and outputs a control voltage signal as a control voltage; and A VCO circuit that oscillates at a frequency according to a control voltage signal and outputs a local oscillation signal, and a frequency divider circuit that divides the local oscillation signal based on a set division ratio and outputs the divided signal as the divided signal It is the structure which comprises.

Preferably, the register circuit includes a plurality of registers for holding and setting the corresponding code, and the code may be set from the outside.
The current control is performed based on the phase difference signal according to the phase difference between the reference signal generated by the oscillation circuit according to the present invention and the frequency-divided signal obtained by dividing the output signal of the PLL synthesizer circuit, and is used in the AM. The current control is switched between the case where the current control is used and the case where the current is used in the FM and the charge pump signal is output. The case where the current is used in the AM and the case where the current is used in the FM, the current control is performed by a code corresponding to the charge pump signal. It is characterized by switching.

  With the above configuration, the output current of the charge pump is optimally controlled to change the phase noise characteristics of the local oscillation signal during FM reception and AM reception, and improve the S / N characteristics of the AM and FM reception receivers. Can be made.

  According to the present invention, the setting value of the register is changed between AM and FM and the control current of the charge pump is set by AM and FM, respectively, thereby changing the crossing frequency between AM and FM, and at the time of FM reception. The phase noise characteristic of the local oscillation signal at the time of AM reception is changed. Therefore, the S / N characteristic of the receiver can be optimized by AM and FM without changing the component constant of the loop filter circuit between AM reception and FM reception.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Example 1)
FIG. 1 is a diagram showing a PLL synthesizer circuit. The PLL synthesizer circuit includes an oscillation circuit 1, a frequency divider circuit 2, a phase comparison circuit 3, a charge pump circuit 4, a register circuit 5, a loop filter circuit 6, a VCO circuit 7, a programmable frequency divider circuit 8 (frequency divider circuit), and a frequency divider. The circuit 9 (for generating an AM local oscillation signal) is configured.

  The oscillation circuit 1 is a crystal oscillator that generates a reference signal (reference frequency: f_REF). The frequency dividing circuit 2 divides the reference frequency by the frequency dividing ratio A and inputs it to the phase comparison circuit 3. The phase comparison circuit 3 compares the phase of the reference signal obtained by dividing the reference signal by the frequency division ratio A and the divided signal that is the output of the programmable frequency dividing circuit 8 described later, and outputs a positive / negative phase difference signal. For example, an up clock or a down clock corresponding to a phase frequency difference between a reference signal and a divided signal obtained by dividing the output signal of the PLL synthesizer circuit is output as a phase difference signal.

  The charge pump circuit 4 outputs a charge pump signal based on the phase difference signal. Thereafter, the high frequency component of the charge pump signal is removed by the loop filter circuit 6 and a control voltage signal obtained by smoothing the charge pump signal is output.

The register circuit 5 has a plurality of registers for controlling the output signal of the charge pump circuit 4. Codes can be set to the plurality of registers from the outside.
The VCO circuit 7 generates an oscillation signal having an oscillation frequency fo corresponding to the voltage level of the oscillation control signal, outputs an FM local oscillation signal, and supplies it to the programmable frequency divider circuit 8. When the voltage of the oscillation control signal is high, the frequency is high, and when the voltage is low, the frequency is low.

The programmable frequency dividing circuit 8 divides the oscillation signal by the frequency division ratio B set by the frequency division ratio setting data to generate a frequency division signal having the oscillation frequency fo / B. Here, the programmable frequency dividing circuit 8 includes an input interface for generating frequency division ratio setting data in response to the supply of frequency setting data from the outside by a controller. For example, the frequency division ratio B is set from the input interface according to the frequency division ratio data, and the frequency division signal having the same frequency fo / B as the reference frequency is generated in response to the supply of the oscillation signal. Then, the reference frequency and the frequency fo / B are controlled so that the phase difference becomes zero. The frequency dividing circuit 9 divides the oscillation signal by the frequency division ratio C to generate an AM local oscillation signal.
(Explanation of charge pump circuit)
FIG. 2 is a diagram showing a reference current generation circuit of the charge pump circuit 4. The charge pump circuit 4 generates a positive DC signal (charge pump signal) when the phase difference signal is supplied from the positive phase comparison circuit 3, and a negative DC signal (charge) when the phase signal is negative. Pump signal). For example, an output signal of the phase comparison circuit 3 is input, and a charge pump reference current generated by performing current control based on a register value set in the register circuit 5 is supplied to the charge pump circuit 4.

  The register value set in the register circuit is 4 bits, and the phase difference signal is received from the phase comparison circuit 3 (PD), and the current shown in the figure by the 4-bit register values (CI0 to CI3) shown in FIG. I1 to I4 are controlled.

  The circuit shown in FIG. 2 includes a transistor 21, a current control circuit including transistors 22, 23 and 24, and inverters 25 and 26, a current control circuit including transistors 27, 28 and 29, and inverters 210 and 211. A current control circuit including transistors 212, 213, and 214 and inverters 215 and 216, a current control circuit including transistors 217, 218, and 219 and inverters 220 and 221 and a current source 222 are included.

  In this example, the transistors 21, 22, 24, 27, 29, 212, 214, 217, and 219 are PMOS (p-channel metal-oxide semiconductor). The transistors 23, 28, 213, and 218 are NMOS (n-channel metal-oxide semiconductor).

  The source of the transistor 21 is connected to the output of the current source 222, and the input of the current source 222 and the sources of the transistors 22, 27, 212, and 217 of each current control circuit are connected to the power source (VDD). The gate and drain of the transistor 21 are connected and connected to the gates of the transistors 22, 27, 212, and 217. These transistors constitute a current mirror. Here, the sizes of the transistors constituting the current mirror are M = 2 for the transistor 21, M = 2 for the transistor 22, M = 4 for the transistor 27, M = 8 for the transistor 212, and M = 16 for the transistor 217.

  Next, the drain of the transistor 22 is connected to the drain of the transistor 23 and the source of the transistor 24. The source of the transistor 23 and the drain of the transistor 24 are connected. The gate of transistor 23 is connected to the output of inverter 25, and the gate of transistor 24 is connected to the output of inverter 26.

  Similarly, the drain of the transistor 27 is connected to the drain of the transistor 28 and the source of the transistor 29. The source of the transistor 28 and the drain of the transistor 29 are connected. The gate of transistor 28 is connected to the output of inverter 210, and the gate of transistor 29 is connected to the output of inverter 211.

  The drain of the transistor 212 is connected to the drain of the transistor 213 and the source of the transistor 214. The source of the transistor 213 and the drain of the transistor 214 are connected. The gate of transistor 213 is connected to the output of inverter 2215, and the gate of transistor 214 is connected to the output of inverter 216.

  The drain of the transistor 217 is connected to the drain of the transistor 218 and the source of the transistor 219. The source of the transistor 218 and the drain of the transistor 219 are connected. The gate of transistor 218 is connected to the output of inverter 220, and the gate of transistor 219 is connected to the output of inverter 221.

  The register value held in the register circuit 5 is input from the inputs of the inverters 26, 211, 216 and 221. Here, in this example, an inverter is used, but it is not limited as long as it has the same function.

  Next, a wiring connecting the source of the transistor 23 and the drain of the transistor 24 is connected to the source of the transistor 28 and the drain of the transistor 29, the source of the transistor 213 and the drain of the transistor 214, and the source of the transistor 218 and the drain of the transistor 219. And connected to the charge pump circuit 4.

  By controlling the reference current of the charge pump signal of the charge pump circuit 4 connected in this way, the phase noise characteristics are switched between AM and FM as shown in FIGS. 3A and 3B, the vertical axis indicates phase noise, and the horizontal axis indicates the frequency of the detuning point from the center frequency (carrier) (the axis of the detuning frequency is Log display).

  In the graph shown in FIG. 3A, when the crossing frequency is low, the phase noise in the region where the detuning frequency is high becomes small and the FM has ideal characteristics. In the graph shown in FIG. 3B, when the crossing frequency is high, the phase noise in the region where the detuning frequency is low becomes small, and the AM has ideal characteristics.

  Here, the phase noise of the VCO circuit 7 is not considered because the optimization of the phase noise is considered as a PLL synthesizer circuit system. In the PLL synthesizer circuit system, if the crossing frequency changes, the phase noise of the local oscillation signal changes from the phase noise state of the VCO circuit 7 alone as shown in FIGS. 3 (a) and 3 (b). The crossing frequency is a frequency of 0 dB gain in an open loop.

  FIG. 4 is a diagram showing the configuration of the loop filter circuit 6. It is comprised by the capacitive element and the resistive element. The phase noise characteristics when the constants shown in FIG. 4 are set to clpf1 = 3.3 nF, Rlpf1 = 33 kΩ, and clpf2 = 33 nF are shown in FIGS.

  5 to 11 are diagrams showing that the register value is changed to change the phase noise characteristic. The vertical axis shows phase noise, and the horizontal axis shows the frequency of the detuning point from the center frequency (carrier) (the axis of the detuning frequency is Log display). The measurement point is the output of the VCO circuit 7. The reference frequency (F_REF) of the oscillation circuit 1 of the PLL synthesizer circuit shown in FIG. 1 is set to 10 kHz, and the frequency dividing ratio of the frequency dividing circuit 2 is 15000 (NO in the graphs shown in FIGS. 5 to 11 is the above frequency dividing ratio). ). The center frequency of the VCO circuit 7 is 150 MHz.

  Further, in FIG. 2, when the output current value of the current source 222 is about 12 μA (11.6 μA), if only the register value CI0 is 1 (high), I1 = about 12 μA (11.6 μA), and only the register value CI1 If 1 (high), I2 = about 24 μA, if only register value CI2 is 1 (high), I3 = about 48 μA, and if only register value CI3 is 1 (high), I4 = about 96 μA. If all the register values are set to 1 (high), the maximum output is about 180 μA.

  FIG. 5 shows a case where the register values of the register circuit 5 that performs charge pump current control are set to statuses CI3 = 0, CI2 = 0, CI1 = 0, and CI0 = 1. Since only CI0 is 1 (high), only current I1 is output. That is, the gates of the transistors 23 and 24 are turned on, and current flows through the transistors 23 and 24. In this example, since I1 = about 12.0 (μA), the current value of the charge pump signal is about 12.0 (μA). The phase noise characteristic at that time is good in the S / N characteristic of FM, and the S / N characteristic of AM is bad.

  FIG. 6 shows a case where the register values of the register circuit 5 are set to statuses CI3 = 0, CI2 = 0, CI1 = 1, and CI0 = 0. The charge pump current is about 24.0 (μA).

  FIG. 7 shows a case where the register values of the register circuit 5 are set to statuses CI3 = 0, CI2 = 0, CI1 = 1, and CI0 = 1. Charge pump current = about 36.0 (μA).

  FIG. 8 shows a case where the register values of the register circuit 5 are set to statuses CI3 = 0, CI2 = 1, CI1 = 0, and CI0 = 0. The charge pump current is about 48.0 (μA).

  FIG. 9 shows the case where the register values of the register circuit 5 are set to statuses CI3 = 0, CI2 = 1, CI1 = 0, and CI0 = 1. Charge pump current = approximately 60.0 (μA).

  FIG. 10 shows a case where the register values of the register circuit 5 are set to statuses CI3 = 0, CI2 = 1, CI1 = 1, and CI0 = 0. The charge pump current is about 72.0 (μA).

  FIG. 11 shows a case where the register values of the register circuit 5 are set to statuses CI3 = 0, CI2 = 1, CI1 = 1, and CI0 = 1. Charge pump current = approximately 84.0 (μA). The phase noise characteristics at that time are good in S / N characteristics of AM and bad in S / N characteristics of FM.

  As shown in FIGS. 5 to 11, for example, if the setting is such that there is no rise in the phase noise of approximately 1 kHz, the S / N characteristic at FM is good, and the setting is such that the phase noise of approximately 100 Hz to 1 kHz is low. Then, it can be assumed that the S / N characteristic at the AM is a good setting. That is, the relationship between the phase noise and the S / N characteristic is an integral value at each frequency of the phase noise for AM, and an integral at each frequency of a value obtained by multiplying the phase noise by a weighting function that increases as the frequency increases for FM. Value.

  With the above configuration, the crossing frequency is adjusted by making the control current of the charge pump circuit 4 variable based on the code of the register circuit 5, and the phase noise characteristic that optimizes the S / N characteristic of the AM / FM receiver is controlled. be able to.

  The design of a normal PLL synthesizer circuit is based on the lock-up time, but the S / N characteristic may not be good because the phase noise characteristic (crossing frequency) is not considered in AM and FM.

  Even if the loop filter constant is fixed, the charge pump power supply current can be controlled to switch the crossing frequency according to AM or FM. Thereby, parts can be shared by AM and FM, and the number of parts can be reduced.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

It is a figure which shows the PLL synthesizer circuit of this invention. It is the figure which showed the reference current generation circuit of the charge pump circuit at the transistor level. (A) is a phase noise characteristic suitable for FM reception. (B) is a phase noise characteristic suitable for AM reception. It is a figure which shows the structure of a loop filter circuit. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows a register value and a phase noise characteristic. It is a figure which shows the conventional PLL synthesizer circuit. It is a figure which shows the phase noise characteristic in a VCO circuit single-piece | unit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Oscillator circuit, 2 ... Frequency divider circuit, 3 ... Phase comparison circuit, 4 ... Charge pump circuit,
5 ... register circuit, 6 ... loop filter circuit, 7 ... VCO circuit,
8: Programmable frequency divider, 9 ... Frequency divider,
21, 22, 24, 27, 29, 212, 214, 217, 219 ... PMOS transistors,
23, 28, 213, 218 ... NMOS transistors,
222 ... Current source 111 ... Oscillator circuit 112 ... Divider circuit 113 ... Phase comparator circuit
114 ... charge pump circuit, 115 ... loop filter circuit, 116 ... VCO circuit,
117: Programmable frequency dividing circuit, 118: Frequency dividing circuit,

Claims (3)

A PLL synthesizer circuit for an AM / FM receiver,
An oscillation circuit for generating a reference signal;
A phase comparison circuit that generates a phase difference signal corresponding to a phase difference between the reference signal and a frequency-divided signal obtained by dividing the output signal of the PLL synthesizer circuit;
A charge pump circuit that performs current control based on the phase difference signal, and generates a charge pump signal by switching the current control when used in AM and FM.
A register circuit for holding and setting a code for switching the current control of the charge pump circuit when used in an AM and when used in an FM;
A loop filter circuit that receives and smoothes the charge pump signal and outputs a control voltage signal as a control voltage;
A VCO circuit that oscillates at a frequency according to the control voltage signal and outputs a local oscillation signal;
A frequency dividing circuit that divides the local oscillation signal based on a set frequency dividing ratio and outputs the divided signal as the frequency divided signal;
A PLL synthesizer circuit for an AM / FM receiver.   2. The PLL synthesizer circuit for an AM / FM receiver according to claim 1, wherein the register circuit includes a plurality of registers for holding and setting the corresponding code, and the code is set from the outside. The current control is performed based on the phase difference signal corresponding to the phase difference between the reference signal generated by the oscillation circuit and the frequency division signal obtained by dividing the output signal of the PLL synthesizer circuit. A process of switching the current control and outputting a charge pump signal when used,
A method of switching a PLL synthesizer circuit for an AM / FM receiver, wherein the current control is switched by a code corresponding to the charge pump signal when used in an AM and when used in an FM.