JP2008010851A - Semiconductor device and power supply unit using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for reducing parasitic inductance of the main circuit of a power supply unit. <P>SOLUTION: A semiconductor chip 5a on which a high-side power MOSFET is formed, a semiconductor chip 5b on which a low-side power MOSFET is formed, and a semiconductor chip 5c on which a driver circuit is formed are contained in a single sealing body 6 to constitute a semiconductor device. In the semiconductor device, the power MOSFETs of the semiconductor chips 5a and 5b are formed of n-channel vertical MOSFETs, and a source electrode of the semiconductor chip 5a and a drain electrode of the semiconductor chip 5b are electrically connected via the same die pad 8b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technology of a semiconductor device, and more particularly to a technology effective when applied to a semiconductor device having a power supply circuit and a power supply device using the same.

  For example, a DC-DC converter widely used as an example of a power supply device has a configuration in which a high-side power MOS FET (Metal Oxide Field Effect Transistor) and a low-side power MOS FET are connected in series. have. The power MOS FET for the high side has a switching function for controlling the DC-DC converter, and the power MOS FET for the low side has a switching function for synchronous rectification. The power supply voltage is converted by alternately turning on / off the FET while synchronizing.

  Such a DC-DC converter is described in, for example, Patent Document 1, a high-side power MOS • FET, a low-side power MOS • FET, and a driver circuit that drives these power MOS • FETs, The structure which accommodates an input capacitor in the same package is disclosed.

Further, for example, in Patent Document 2, a high-side power MOS • FET constituting a DC-DC converter is composed of a horizontal power MOS • FET, and a low-side power MOS • FET is composed of a vertical power MOS • FET. A package configuration in which these power MOS FETs are mounted on a common frame is disclosed.
Special table 2003-528449 gazette JP 2002-217416 A

  By the way, non-insulated DC-DC converters used in power supply devices such as desktop personal computers, servers, and game machines have large currents for driving CPUs (Central Processing Units), choke coils, and input / output capacitors. With the demand for downsizing of passive components such as the above, there is a tendency to increase current and frequency.

  However, under high current and high frequency conditions, there is a problem that loss increases due to main circuit inductance parasitic on the main circuit around the input capacitor of the non-insulated DC-DC converter. In particular, if the main circuit inductance parasitic on the main circuit around the input capacitor increases with the increase in current and frequency, the jumping voltage at the time of turn-off of the power MOS FET for the high side of the DC-DC converter increases. As a result, there is a problem that switching loss increases and causes a large loss.

  In order to reduce the main circuit inductance, a semiconductor chip in which a high-side power MOS FET is formed and a semiconductor chip in which a low-side power MOS FET is formed are accommodated in the same package. There is. Also, a semiconductor chip on which a high-side power MOS FET is formed, a semiconductor chip on which a low-side power MOS FET is formed, and a semiconductor chip on which a driver circuit is formed are accommodated in the same package. There is also a configuration. In either case, each semiconductor chip is mounted on a separate die pad, and the source of the high-side power MOS FET is a semiconductor chip on which the low-side power MOS FET is formed through a bonding wire. It is electrically connected to the die pad. However, in these configurations, since the input capacitor is externally attached, the parasitic inductance cannot be sufficiently reduced. In addition, since the source of the high-side power MOS • FET and the die pad and the source of the low-side power MOS • FET and the reference potential are electrically connected by a bonding wire, there is a limit in reducing parasitic inductance.

  Further, in Patent Document 2, a semiconductor chip in which a high-side power MOS FET is formed, a semiconductor chip in which a low-side power MOS FET is formed, a semiconductor chip in which a driver circuit is formed, The structure which accommodates an input capacitor in the same package is disclosed. In this case, the source of the high-side power MOS • FET is electrically connected to the wiring of the wiring board through the bonding wire, and the wiring is electrically connected to the drain of the low-side power MOS • FET. The source of the low-side power MOS • FET is electrically connected to the output wiring of the wiring board through a bonding wire. However, even in such a configuration, since the connection is made with a bonding wire, the parasitic inductance cannot be sufficiently reduced, and since there is a certain distance between the input capacitor and each power MOS, the parasitic inductance is also reduced. There is a limit.

  Accordingly, an object of the present invention is to provide a technique capable of reducing the parasitic inductance of the main circuit of the power supply device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, the field effect transistor of the first semiconductor chip is formed of an n-channel vertical field effect transistor, and the field effect transistor of the second semiconductor chip is formed of an n-channel vertical field effect transistor. The surface of the first semiconductor chip on which the source electrode is disposed and the surface of the second semiconductor chip on which the drain electrode is disposed are mounted on the same chip mounting portion and electrically connected to each other. The drain electrode has a first lead plate connected to an external terminal for supplying input power, and the source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying a reference potential.

  In the present invention, the field effect transistor of the first semiconductor chip is formed of an n-channel vertical field effect transistor, and the field effect transistor of the second semiconductor chip is formed of an n-channel vertical field effect transistor. The surface of the first semiconductor chip on which the source electrode is disposed and the surface of the second semiconductor chip on which the drain electrode is disposed are mounted on the same chip mounting portion and electrically connected to each other. The drain electrode has a first lead plate connected to an external terminal for supplying input power, and the source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying a reference potential, A capacitor electrically connected between the first lead plate and the second lead plate, wherein the capacitor has one of a pair of electrodes bonded to the first lead plate, In which the other is bonded to the second lead plate.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, according to the present invention, the field effect transistor of the first semiconductor chip is formed of an n-channel vertical field effect transistor, and the field effect transistor of the second semiconductor chip is formed of an n-channel vertical field effect transistor. The surface on which the source electrode of the first semiconductor chip is disposed and the surface on which the drain electrode of the second semiconductor chip is disposed are mounted on the same chip mounting portion and are electrically connected to each other. The drain electrode of the chip has a first lead plate connected to an external terminal for supplying input power, and the source electrode of the second semiconductor chip has a second lead plate connected to an external terminal for supplying a reference potential. Thus, the inductance in the wiring path between the first and second semiconductor chips can be reduced, so that the parasitic inductance of the main circuit of the power supply device can be reduced. Kill.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. The other part or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The semiconductor device according to the first embodiment of the present invention is a non-insulated DC-DC converter used for a power supply device of an electronic device such as a desktop personal computer, a notebook personal computer, a server, or a game machine. .

  FIG. 1 shows an example of a circuit diagram of a non-insulated DC-DC converter 1 used in the power supply device of the first embodiment. The non-insulated DC-DC converter 1 includes a control circuit 2, a driver circuit 3, power MOS FETs (hereinafter simply referred to as power MOSs) QH1 and QL1, an input capacitor Cin, an output capacitor Cout, a coil (choke coil) L, etc. It has such an element. The symbol D indicates a drain, and S indicates a source. Symbols L1 to L6 indicate parasitic inductances parasitic on the main circuit of the non-insulated DC-DC converter.

  The control circuit 2 is a circuit that supplies a signal for controlling the voltage switch-on width (ON time) of the power MOSs QH1 and QL1, such as a pulse width modulation (PWM) circuit. The output of the control circuit 2 (control signal terminal) is electrically connected to the input of the driver circuit 3. The output of the driver circuit 3 is electrically connected to the gate terminal GH of the power MOS QH1 and the gate terminal GL of the power MOS QL1. The driver circuit 3 is a circuit that controls the operation of the power MOSs QH1 and QL1 by controlling the potentials of the gate terminals GH and GL of the power MOSs QH1 and QL1 by the control signal supplied from the control circuit 2, respectively. VDIN indicates an input power source of the driver circuit 3.

  The power MOSs QH1 and QL1 are connected in series between a terminal ET1 for supplying a high potential (positive potential) VDD of the input power source VIN and a terminal ET2 for supplying a reference potential (negative potential) GND. That is, the power MOS QH1 which is a rectifying MOSFET is provided such that its source / drain path is connected in series between the terminal ET1 for supplying the high potential VDD of the input power supply VIN and the output node (output terminal) Lx. The power MOSFET QL1, which is a commutation MOSFET, is provided such that its source / drain path is connected in series between the output node Lx and a reference potential GND supply terminal ET2. Dp1 represents a parasitic diode (internal diode) of the power MOS QH1, and Dp2 represents a parasitic diode (internal diode) of the power MOS QL1.

  The power MOS QH1 is a power transistor for a high side switch (high potential side: hereinafter simply referred to as a high side), and a coil L that supplies power to the output of the non-insulated DC-DC converter 1 (input of the load circuit 4). It has a switch function for storing energy. The power MOS QH1 is formed of an n-channel vertical field effect transistor. A vertical field effect transistor is an element in which a channel is formed in the thickness direction of a semiconductor chip. Compared with a horizontal field effect transistor, the channel width per unit area can be increased and the on-resistance can be reduced. Therefore, it is possible to reduce the size of the device and to reduce the packaging.

  On the other hand, the power MOS QL1 is a power transistor for a low-side switch (low potential side: hereinafter simply referred to as low-side), and is a rectifying transistor for the non-insulated DC-DC converter 1, and has a frequency from the control circuit 2. It has a function of performing rectification by lowering the resistance of the transistor synchronously. The power MOS QL1 is formed of an n-channel vertical power MOS, similar to the power MOS QH1. The reason why the vertical type is used is that, as shown in the timing chart of the non-insulated DC-DC converter 1 in FIG. 2, the low-side power MOS QL1 has its on time (time during which voltage is applied). However, since the on-resistance is longer than the on-time of the high-side power MOS QH1 and the on-resistance is larger than the switching loss, the vertical electric field can increase the channel width per unit area as compared with the horizontal field-effect transistor. This is because it is advantageous to use effect transistors. That is, since the on-resistance can be reduced by forming the low-side power MOS QL1 with a vertical field effect transistor, the voltage conversion efficiency can be improved even if the current flowing through the non-insulated DC-DC converter 1 increases. Because you can. In FIG. 2, Ton indicates a pulse width when the high-side power MOS QH1 is turned on, and T indicates a pulse period.

  The input capacitor Cin is electrically connected in parallel with the input power source VIN shown in FIG. The input capacitor Cin is a power supply circuit that temporarily stores energy (charge) supplied from the input power supply VIN and supplies the stored energy to the main circuit of the non-insulated DC-DC converter 1. This is because the input power source VIN is not only a power source for the non-isolated DC-DC converter 1 but also a power source for other devices, and is therefore located far from the non-isolated DC-DC converter 1. When power is directly supplied from the input power source VIN to the non-insulated DC-DC converter 1, the power supply efficiency is lowered. Therefore, the power source is disposed at a position relatively close to the main circuit of the non-insulated DC-DC converter 1. The power is supplied to the input capacitor Cin, and the power is supplied to the main circuit of the non-insulated DC-DC converter 1 from there. The input power supply potential VDD of the input power supply VIN is, for example, about 5 to 12V. The reference potential GND is lower than the input power supply potential, for example, and is 0 (zero) V at the ground potential, for example. The operating frequency of the non-insulated DC-DC converter 1 (cycle when the power MOSQH1 and QL1 are turned on and off) is, for example, 1 MHz.

  The wiring connecting the source of the power MOS QH1 and the drain of the power MOS QL1 of the non-insulated DC-DC converter 1 is provided with the output node Lx for supplying the output power supply potential to the outside. The output node Lx is electrically connected to the coil L via the output wiring, and is further electrically connected to the load circuit 4 via the output wiring. A Schottky Barrier Diode (hereinafter abbreviated as SBD) is provided between an output wiring connecting the output node Lx and the coil L and a terminal for supplying a reference potential GND so as to be in parallel with the power MOS QL1. May be electrically connected. SBD is a diode whose forward voltage Vf is lower than that of the parasitic diode Dp2 of the power MOS QL1. The SBD has an anode electrically connected to the reference potential GND supply terminal ET2, and a cathode electrically connected to an output wiring connecting the output node Lx and the drain of the power MOS QL1. By connecting the SBD in this way, the dead time voltage drop when the power MOS QL1 is turned off can be reduced, so that the diode conduction loss can be reduced and the reverse recovery time (trr) can be increased. This can reduce diode recovery loss.

  The output capacitor Cout is electrically connected between an output wiring connecting the coil L and the load circuit 4 and a reference potential GND supply terminal. Examples of the load circuit 4 include a CPU (Central Processing Unit) or an MPU (Micro Processing Unit) of the electronic device. Iout indicates an output current, and Vout indicates an output voltage.

  In such a circuit, power supply voltage conversion is performed by alternately turning on / off the power MOSs QH1 and QL1 while synchronizing them. That is, when the high-side power MOS QH1 is on, the current I1 flows from the terminal ET1 electrically connected to the drain D of the power MOS QH1 to the output node Lx through the power MOS QH1, and when the high-side power MOS QH1 is off. The current I2 flows due to the counter electromotive voltage of the coil L. The voltage drop can be reduced by turning on the low-side power MOS QL1 when the current I2 is flowing. The current I1 is a large current of about 20 A, for example.

  By the way, in such a non-insulated DC-DC converter 1, the parasitic inductance (L1 + L2 + L3 + L4 + L5 + L6) parasitic on the main circuit around the input capacitor Cin increases as the current increases and the frequency increases. As a result of an increase in the jumping voltage at the time of turn-off of the high-side power MOS QH1 of the DC-DC converter 1, there is a problem that a switching loss increases and a large loss is caused.

  Here, according to the study of the present inventor, there is a configuration shown in FIGS. 3 to 7 as an example of the package structure of the semiconductor device for reducing the parasitic inductance. 3 is a plan view of the inside of the package, and FIG. 4 is a sectional view taken along line Y1-Y1 of FIG. 3 and 4, the semiconductor chip 5a on which the high-side power MOS QH1 is formed and the semiconductor chip 5b on which the low-side power MOS QL1 is formed are accommodated in the same sealing body 6. Semiconductor chips 5a and 5b are mounted on separate die pads 7a1 and 7a2, respectively. The source of the high-side power MOS QH1 is electrically connected to a die pad 7a2 on which the low-side power MOS QL1 is mounted through a bonding wire (hereinafter simply referred to as a wire) W.

  FIG. 5 is a plan view of the inside of the package, and FIG. 6 is a cross-sectional view taken along line Y2-Y2 of FIG. 5 and 6, in addition to the semiconductor chips 5a and 5b, the semiconductor chip 5c on which the driver circuit 3 is formed is also accommodated in the same sealing body 6. The semiconductor chip 5c is mounted on a die pad 7a3 different from the die pads 7a1 and 7a2. Also in this example, the semiconductor chips 5a and 5b are mounted on separate die pads 7a1 and 7a2, and the source of the high-side power MOS QH1 is electrically connected to the die pad 7a2 mounted with the low-side power MOS QL1 through the wire W. It is connected to the.

  Further, FIG. 7 shows a package structure disclosed in Patent Document 2. In addition to the semiconductor chips 5a, 5b, and 5c, an input capacitor Cin is also accommodated in the same sealing body 6. In this case, the source of the high-side power MOS QH1 is electrically connected to the wiring of the wiring board 50 through the wire W, and the wiring is electrically connected to the drain of the low-side power MOS QL1. The source of the low-side power MOS QL 1 is electrically connected to the output wiring of the wiring board 50 through the wire W.

  However, in the configurations as shown in FIGS. 3 and 4 and FIGS. 5 and 6, since the input capacitor Cin is externally attached, the parasitic inductances L1 and L6 cannot be reduced. In addition, the source of the high-side power MOS QH1 and the die pad 7a2 are electrically connected by the wire W, and the source of the low-side power MOS QL1 and the reference potential GND are electrically connected by the wire W. There is a limit to the reduction of the parasitic inductances L3 and L5.

  Further, in the configuration in which the semiconductor chips 5a, 5b, 5c and the input capacitor Cin are accommodated in the same sealing body 6 as shown in FIG. 7, the parasitic inductances L3 and L5 cannot be reduced because the wires W are connected. Since there is a certain distance between the input capacitor Cin and each of the power MOSs QH1 and QL1, there is a limit in reducing the parasitic inductances L1 and L6.

  Therefore, in the first embodiment, in order to reduce the parasitic inductances L3 and L4 among the parasitic inductances L1 to L6, the high-side power MOSQH1 and the low-side power MOSQL1 are combined with a common die pad (tab, Mount on the chip mounting part). Therefore, in the first embodiment, the high-side power MOS QH1 of the non-insulated DC-DC converter 1 is formed of an n-channel vertical power MOS and its source electrode is connected to the die pad. Take flip chip structure.

  8 and 9 show an example of the package structure of the semiconductor device according to the first embodiment. 8 is a plan view of the inside of the package, and FIG. 9 is a sectional view taken along line Y3-Y3 of FIG. In FIG. 8, the inside of the package is shown in a watermark to make the drawing easier to see.

  The package according to the first embodiment is provided with a conductive die pad (first chip mounting portion) 8b having a first main surface and a second main surface opposite to the first main surface, and an input power supply arranged around the die pad 8b. External terminal Vin, reference potential supply external terminal Gnd, output external terminal Lx formed integrally with die pad 8b, and semiconductor chip (first semiconductor chip) mounted on the first main surface of die pad 8b ) 5a, a semiconductor chip (second semiconductor chip) 5b mounted on the first main surface of the die pad 8b, and a lead plate (first plate-like conductivity) for electrically connecting the electrode of the semiconductor chip 5b to the external terminal Gnd Member) 8c, a lead plate (second plate-like conductive member) 8a for electrically connecting the electrode of the semiconductor chip 5a to the external terminal Vin, and a die pad having a first main surface and a second main surface opposite to the first main surface. (No. Chip mounting portion) 8d, semiconductor chip (third semiconductor chip) 5c mounted on the first main surface of die pad 8d, and wires W for electrically connecting source electrode pads and gate electrode pads of semiconductor chips 5c and 5a. A wire W that electrically connects the source electrodes and gate electrodes of the semiconductor chips 5c and 5b, semiconductor chips 5a to 5c, lead plates 8c and 8a, and a sealing body 6 that seals the wires. On the chips 5a and 5b, n-channel vertical field effect transistors are formed, and the source electrode of the semiconductor chip 5a and the drain electrode of the semiconductor chip 5b are electrically connected to the die pad 8b.

  That is, two separate semiconductor chips 5a and 5b are accommodated in the package in a state where they are mounted on a common die pad 8b. On the semiconductor chip 5a, a high-side n-channel vertical power MOS of the non-insulated DC-DC converter 1 is formed. In addition, a low-side n-channel vertical power MOS for the non-insulated DC-DC converter 1 is formed on the semiconductor chip 5b. A semiconductor chip 5c of a driving IC (Integrated Circuits) for driving the gates of the semiconductor chip 5a and the semiconductor chip 5b is mounted on a die pad 8d, and a die pad 8b corresponding to the source electrode of the semiconductor chip 5a and a gate electrode. A corresponding gate electrode pad 9b is connected via a wire W. The semiconductor chip 5c is connected to the source electrode 9c, the gate electrode pad 9a, and the wire W of the semiconductor chip 5b.

  The drain electrode of the semiconductor chip 5a is connected to an external terminal Vin for supplying input power via a lead plate 8a, and the source electrode 9c of the semiconductor chip 5b is connected to an external terminal for supplying a reference potential via a lead plate 8c. Connected to Gnd, the common die pad 8b is connected to an external terminal Lx for output.

  As described above, in the first embodiment, since the semiconductor chip 5a of the high-side power MOS QH1 and the semiconductor chip 5b of the low-side power MOS QL1 are mounted on the common die pad 8b, the parasitic inductances L3 and L4 are reduced. Is done. Since the lead plates 8a and 8c are used to connect the drain electrode of the semiconductor chip 5a of the high-side power MOSQH1 and the external terminal Vin, and to connect the source electrode of the semiconductor chip 5b of the low-side power MOSQL1 and the external terminal Gnd. Parasitic inductances L2 and L5 are reduced. As a result, the parasitic inductance of the main circuit of the non-insulated DC-DC converter can be reduced.

  Next, the low-side MOS of FIG. 8 and its peripheral structure will be described with reference to FIG. FIG. 15A shows a lead frame pattern, showing a gate bonding pad (high side) 9b and a source lead plate 8b. 15A and 12B in FIG. 15B show the structure of the upper layer than the lead frame in FIG. 15A, and show the gate pad 12a and the source pad 12b. FIG. 15C shows the structure of the layer above the gate pad 12a and source pad 12b in FIG. 15B, and shows a semiconductor chip (low-side power MOS) 5a. FIG. 15D shows the configuration of the upper layer of the semiconductor chip 5a in FIG. 15C, and shows a lead plate (power supply voltage) 8a.

(Embodiment 2)
As described above, the inductance L2, L3, L4, and L5 of the wiring shown in FIG. 1 can be reduced by adopting the structure of the first embodiment. However, in the first embodiment, the parasitic inductance L1 caused by the drain terminal of the high-side power MOSQH1 from the plus terminal of the input capacitor Cin, and the parasitic inductance caused by the source terminal of the low-side power MOSQL1 from the minus terminal of the input capacitor Cin. The inductance L6 cannot be reduced. The second embodiment has been made in view of this, and L1 and L6 can be reduced.

  10 and 11 show an example of the package structure of the semiconductor device according to the second embodiment. 10 is a plan view of the inside of the package, and FIG. 11 is a sectional view taken along line Y4-Y4 of FIG. In FIG. 10, the inside of the package is shown in a watermark to make the drawing easier to see.

  The difference between the second embodiment and the first embodiment is that the input capacitor 11 is mounted on the surface of the package. A positive electrode 11a of the input capacitor 11 is connected to a lead plate 8a electrically connected to an external terminal Vin for supplying input power via a conductive member 11c, and a negative electrode 11b of the input capacitor 11 is a conductive member. The lead plate 8c is electrically connected to the external terminal Gnd for supplying a reference potential via 11d.

  Next, the effect of this embodiment will be described with reference to FIGS. In FIG. 13, the horizontal axis represents the wiring inductance of the main circuit, and the vertical axis represents the switching loss of the high-side power MOS. The wiring inductance of the main circuit corresponds to the total value of L1 to L6 in FIG. As the main circuit inductance decreases, the switching loss decreases, but the loss increases when the main circuit inductance falls below 1 nH. The conventional example is a measurement result using the package of FIG. 5, and it can be seen that the switching loss is reduced because the present embodiment (the present invention) has a smaller inductance than the conventional example. If the switching loss is small, a cooling part such as a heat sink is unnecessary, and the power supply is miniaturized. In addition, under the condition that the loss is constant, the present embodiment can improve the switching frequency, so that the output filter composed of the inductor and the capacitor can be downsized.

  In FIG. 14, the horizontal axis represents the wiring inductance of the main circuit, and the vertical axis represents the jumping voltage between the source and drain of the high-side power MOS during switching. The smaller the main circuit inductance, the smaller the jumping voltage. The conventional example is a measurement result using the package of FIG. 5, and this embodiment (the present invention) has a smaller inductance than the conventional example, so that the jumping voltage is reduced. When the jump voltage is low, conduction noise and radiation noise are reduced, and malfunction of other semiconductor devices and electronic devices can be suppressed.

(Embodiment 3)
As described above, by adopting the structure of the second embodiment, the wiring inductances L1 to L6 shown in FIG. 1 can be reduced. However, the second embodiment has a problem in that the surface has a high thermal resistance because the capacitor is mounted on the surface of the package. The third embodiment has been made in view of this, and can reduce the thermal resistance on the surface side.

  FIG. 12 is a diagram for explaining the semiconductor device of the third embodiment. The difference from FIG. 11 is that the lead plates 8a and 8c are exposed on the package surface. The positive electrode 11a of the input capacitor 11 is connected to a lead plate 8a that is electrically connected to the external terminal Vin for supplying input power, and the negative electrode 11b of the input capacitor 11 is electrically connected to the external terminal Gnd for supplying reference potential. Connected to the lead plate 8c.

  In the above description, the case where the invention made mainly by the present inventor is applied to the power supply device of the CPU or DSP which is the field of use as the background has been described. However, the present invention is not limited to this and can be applied in various ways. For example, the present invention can be applied to a power supply device of another circuit.

  The present invention relates to a technology of a semiconductor device, and is particularly effective when applied to a semiconductor device having a power supply circuit and a power supply device such as a non-insulated DC-DC converter using the power supply circuit, for example, a desktop personal computer, It can be used for a power supply device of an electronic device such as a notebook personal computer, a server, or a game machine.

It is a circuit diagram of the non-insulated DC-DC converter used for the power supply device of Embodiment 1 of this invention. 2 is a timing chart of the non-insulated DC-DC converter of FIG. 1. It is a top view inside the package of the semiconductor device which this inventor examined as a comparison technique with respect to this invention. It is sectional drawing of the Y1-Y1 line | wire of FIG. It is a top view inside the package of another semiconductor device which this inventor examined as a comparison technique with respect to this invention. It is sectional drawing of the Y2-Y2 line | wire of FIG. It is a top view inside the package of another semiconductor device (patent document 2) which this inventor examined as a comparison technique with respect to the present invention. It is a top view inside the package of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing of the Y3-Y3 line | wire of FIG. It is a top view inside the package of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing of the Y4-Y4 line | wire of FIG. It is sectional drawing of the semiconductor device of Embodiment 3 of this invention. It is a graph of the relationship between the main circuit inductance and switching loss explaining the effect of embodiment of this invention. It is a graph of the relationship between the main circuit inductance and the jump voltage explaining the effect of the embodiment of the present invention. (A)-(d) is a figure for demonstrating the low side MOS of FIG. 8, and its peripheral structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Non-insulated DC-DC converter, 2 ... Control circuit, 3 ... Driver circuit, 4 ... Load circuit, 5a, 5b, 5c ... Semiconductor chip, 6 ... Sealing body, 7a1, 7a2, 7a3 ... Die pad, 8a ... Lead plate, 8b ... die pad, 8c ... lead plate, 8d ... die pad, 9a, 9b ... gate electrode pad, 9c ... source electrode, 11 ... input capacitor, 11a ... positive electrode, 11b ... negative electrode, 11c, 11d ... conductive 12a ... gate pad, 12b ... source pad, QH1, QL1 ... power MOS-FET, Cin ... input capacitor, Cout ... output capacitor, L ... coil, L1-L6 ... parasitic inductance, GH, GL ... gate terminal, VIN ... input power supply, ET1, ET2 ... terminal, Lx ... output node, Dp1, Dp2 ... parasitic diode, W ... bo Funding wire.

Claims (6)

A conductive first chip mounting portion having a first main surface and a second main surface opposite to the first main surface;
An external terminal for supplying an input power disposed around the first chip mounting portion;
An external terminal for supplying a reference potential disposed around the first chip mounting portion;
An external terminal for output formed integrally with the first chip mounting portion;
A first semiconductor chip mounted on a first main surface of the first chip mounting portion;
A second semiconductor chip mounted on the first main surface of the first chip mounting portion;
A first plate-like conductive member that electrically connects an electrode of the second semiconductor chip to the external terminal for supplying the reference potential;
A second plate-like conductive member that electrically connects an electrode of the first semiconductor chip to the external terminal for supplying input power;
A second chip mounting portion having a first main surface and a second main surface opposite to the first main surface;
A third semiconductor chip mounted on the first main surface of the second chip mounting portion;
A first bonding wire electrically connecting the source electrode pad and the gate electrode pad of the third semiconductor chip and the first semiconductor chip;
A second bonding wire electrically connecting a source electrode and a gate electrode of the third semiconductor chip and the second semiconductor chip;
Sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first plate-like conductive member, the second plate-like conductive member, the first bonding wire, and the second bonding wire And a sealing body
An n-channel vertical field effect transistor is formed on the first semiconductor chip and the second semiconductor chip,
A semiconductor device, wherein a source electrode of the first semiconductor chip and a drain electrode of the second semiconductor chip are electrically connected to the first chip mounting portion. A conductive first chip mounting portion having a first main surface and a second main surface opposite to the first main surface;
An external terminal for supplying an input power disposed around the first chip mounting portion;
An external terminal for supplying a reference potential disposed around the first chip mounting portion;
An external terminal for output formed integrally with the first chip mounting portion;
A first semiconductor chip mounted on a first main surface of the first chip mounting portion;
A second semiconductor chip mounted on the first main surface of the first chip mounting portion;
A first plate-like conductive member that electrically connects an electrode of the second semiconductor chip to the external terminal for supplying the reference potential;
A second plate-like conductive member that electrically connects an electrode of the first semiconductor chip to the external terminal for supplying input power;
A second chip mounting portion having a first main surface and a second main surface opposite to the first main surface;
A third semiconductor chip mounted on the first main surface of the second chip mounting portion;
A first bonding wire electrically connecting the source electrode pad and the gate electrode pad of the third semiconductor chip and the first semiconductor chip;
A second bonding wire electrically connecting a source electrode and a gate electrode of the third semiconductor chip and the second semiconductor chip;
A sealing body for sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first bonding wire, and the second bonding wire;
An n-channel vertical field effect transistor is formed on the first semiconductor chip and the second semiconductor chip,
The surfaces of the first plate-like conductive member and the second plate-like conductive member are exposed,
A semiconductor device, wherein a source electrode of the first semiconductor chip and a drain electrode of the second semiconductor chip are electrically connected to the first chip mounting portion. The semiconductor device according to claim 1,
One electrode of a capacitor is electrically connected to the first plate-like conductive member via a first connection layer, and the capacitor is connected to the second plate-like conductive member via a second connection layer. The other electrode of the semiconductor device is electrically connected. The semiconductor device according to claim 2,
One electrode of a capacitor is electrically connected to the first plate-like conductive member, and the other electrode of the capacitor is electrically connected to the second plate-like conductive member. A featured semiconductor device. One main terminal of the rectifying MOSFET is connected to the positive potential side of the DC input power supply, the other main terminal of the rectifying MOSFET is connected to one terminal of the choke coil and one main terminal of the commutation MOSFET, The other main terminal of the commutation MOSFET is connected to the negative potential side of the DC input power supply, one terminal of the output capacitor is connected to the other terminal of the choke coil, and the other terminal of the output capacitor is used for the commutation One of the terminals connected to the other main terminal of the MOSFET and supplying power to the semiconductor device serving as a load is connected to the other terminal of the choke coil, and the other terminal supplying power to the semiconductor device serving as the load is Connected to the other main terminal of the commutation MOSFET, and the control circuit connects the gates of the rectification MOSFET and the commutation MOSFET. The power supply apparatus of a synchronous rectification system for moving,
The external terminal for supplying input power of the semiconductor device according to claim 3 is connected to the positive potential side of the DC input power supply, and the external terminal for supplying reference potential of the semiconductor device is connected to the negative potential of the DC input power supply. A power supply device, wherein the output external terminal of the semiconductor device is connected to one terminal of the choke coil. One main terminal of the rectifying MOSFET is connected to the positive potential side of the DC input power supply, the other main terminal of the rectifying MOSFET is connected to one terminal of the choke coil and one main terminal of the commutation MOSFET, The other main terminal of the commutation MOSFET is connected to the negative potential side of the DC input power supply, one terminal of the output capacitor is connected to the other terminal of the choke coil, and the other terminal of the output capacitor is used for the commutation One of the terminals connected to the other main terminal of the MOSFET and supplying power to the semiconductor device serving as a load is connected to the other terminal of the choke coil, and the other terminal supplying power to the semiconductor device serving as the load is Connected to the other main terminal of the commutation MOSFET, and the control circuit connects the gates of the rectification MOSFET and the commutation MOSFET. The power supply apparatus of a synchronous rectification system for moving,
The external terminal for supplying input power of the semiconductor device according to claim 4 is connected to the positive potential side of the DC input power supply, and the external terminal for supplying reference potential of the semiconductor device is connected to the negative potential of the DC input power supply. A power supply device, wherein the output external terminal of the semiconductor device is connected to one terminal of the choke coil.

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