JP2008010655A - Circuit for measuring lots of semiconductor elements - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for measuring lots of semiconductor elements which enables the abundant measurings of each variation parameter in order to establish a high precision model used for a submicron process. <P>SOLUTION: By forming 10 pairs to 20 pairs of semiconductor devices with a predetermined arrangement, one small array 10 is constituted. By performing a lattice-like arrangement of a plurality of this small arrays 10, one unit 20 is constituted. By performing further the lattice-like arrangement of this unit 20, a large array 30 is constituted. Each semiconductor element included in the small array 10 is connected to a switch controlled by a control circuit 40. The control circuit 40 is arranged at any two side of the large array 30. By being arranged a plurality of pads 50 in the outside of the large array 30 and the control circuit 40, the circuit 1 for measuring lots of semiconductor elements is constituted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a mass measurement circuit used for mass measurement of semiconductor elements formed by a submicron process.

  ICs for radio circuits (RFICs) used for mobile phones and the like are required to shorten the design / trial period. Conventionally, wireless circuits have been configured with small-scale ICs and modules. For this reason, a plurality of types of ICs having different design values have been created, and products having the best characteristics have been used as products. However, in recent years, wireless circuits have been integrated on a single chip, so that the conventional method requires several years to complete.

  Therefore, the establishment of an RFIC design environment utilizing a simulator (EDA) has been actively performed mainly by EDA vendors. In order not to repeat the trial production, a high-accuracy model of each semiconductor element in the IC is required. The high-accuracy model referred to here is a model having an equivalent circuit that can express high-frequency characteristics and a coefficient that can express variations in semiconductor elements. In particular, the variation needs to consider both the model and the design method.

  In conventional RFIC circuit design, first, the characteristics when all the semiconductor elements of the circuit vary to the worst values are obtained, and then the circuit constants are changed so that the obtained characteristics satisfy the specifications. This is called corner analysis. However, in an analog circuit such as RFIC, a number of parameters affect its characteristics. For this reason, the probability that the variation of all the semiconductor elements in the circuit becomes the worst value is practically close to zero, and the RFIC completed by the corner analysis becomes overspec. In order to eliminate this over-spec, it has been necessary in the past to carry out a design that reduces the current after prototyping / evaluation, and to perform prototyping again.

  On the other hand, an analysis method has been proposed in which a result close to the actual RFIC variation distribution is obtained. This is called statistical analysis. This statistical analysis is designed using a statistical model called a principal factor that uses variables that are independent of each other. The principal factor expresses variations in gate oxide film thickness, gate width, gate length, and the like.

  In order to create this statistical model, it is important to take into account the variation factors of the semiconductor elements in the IC. The variation factors in the IC include local (random) variation in which characteristics change randomly at an early cycle of an interval between adjacent semiconductor elements, layout-dependent variation that changes in an intermediate cycle from end to end of Die, and wafer variation. There is a global variation that changes with a slow period from end to end. FIG. 4 is a diagram for explaining three variations of the semiconductor elements in the IC.

  FIG. 4A shows local variations. Local variation is variation between semiconductor elements due to a defect in a gate oxide film of a field effect transistor (FET). This local variation occurs without depending on the peripheral layout or the arrangement of semiconductor elements in the wafer. Therefore, even adjacent semiconductor elements have different current values, resistance values, and capacitance values. This local variation causes a mismatch.

  FIG. 4B shows layout dependent variations. The characteristics of the semiconductor elements in the IC change due to the density of surrounding metal and polysilicon. Since the IC wafer has a configuration in which Dies having the same layout are spread, the layout-dependent variation has a characteristic of being repeated for each Die.

  FIG. 4C shows the global variation that gradually changes from one end of the wafer to the other end. Also included are variations between different lots. This global variation is caused by the difference in the thickness of the oxide film and the concentration of polysilicon between the wafer edge and the center or lot. The cause of this variation is that conditions such as the diffusion temperature are slightly different between the edge of the wafer and the center or lot.

  In general, variation is modeled by dividing it into local variation, which is variation between semiconductor elements in a circuit block, and systematic variation (layout dependent variation and global variation) that is the same for all semiconductor elements in a circuit block. .

  Conventionally, a measurement circuit for local variation has been studied. This is because, in the measurement method in which two adjacent semiconductor elements are individually probed, variation in the contact resistance of the probe becomes an error factor. The solution to this problem is that a plurality of semiconductor elements can be measured by a single probe operation. In addition, this configuration can shorten the measurement time and can incorporate a very large number of semiconductor elements.

FIG. 5 is a diagram showing a configuration of a conventional variation evaluation circuit described in Non-Patent Document 1. In FIG. In the conventional variation evaluation circuit of FIG. 5, one type of semiconductor element is concentrated on the same position of one Die. Therefore, the mismatch is found from the distribution of the average of all the semiconductor elements and the difference between the semiconductor elements. In addition, a plurality of Die measurements are performed, and the global variation is also known from the average variation for each Die.
However, the layout dependent variation is not known. This is because, as shown in FIG. 6, one semiconductor element is at the same position in Die, and only the same layout-dependent variation can always be measured.

FIG. 7 is a diagram showing the configuration of a conventional semiconductor device mass measurement circuit described in Patent Document 1. In FIG. The conventional mass measurement circuit of FIG. 7 is composed of blocks called 16 × 16 MAU (Measurement Array Unit). A decoder is installed around the MAU, and one semiconductor element in the MAU is selected. 256 MAUs and decoders are built in one Die. In one MAU, a plurality of types of transistors are arranged one by one and a passive element is arranged one by one. Therefore, in this conventional mass measurement circuit, since one semiconductor element is distributed and arranged over the entire Die, semiconductor elements having different layout dependent variations can be evaluated.
Shimizu et al., “Test circuit for high-precision evaluation of MOSFET matching characteristics”, IEICE Transactions C, Vol. J86-C, no. 7, pp. 726-733, July 2003 Japanese Patent No. 3592316

  However, the conventional mass measurement circuit has only one pair of transistors at each position. For this reason, if the mismatch is sufficiently small compared to the layout-dependent variation, the layout-dependent variation can be measured by performing smoothing ((a) of FIG. 8), but if the local variation is large as in the submicron process, There is a problem that smoothing cannot be performed well and local variations and layout-dependent variations cannot be separated ((b) in FIG. 8).

  Also, in the sub-micron process, when there is a dependency that a certain characteristic of a semiconductor element is large, local variation is large, and when a certain characteristic is small, local variation is small, the above-mentioned conventional mass measurement circuit has a correlation between the two. There is a problem that the relationship cannot be measured.

  Therefore, an object of the present invention is to provide a mass measurement circuit that can accurately measure parameters of each variation and establish a high-accuracy model even when using a submicron process in which local variations become large. .

  The present invention is directed to a mass measurement circuit used for mass measurement of semiconductor elements. In order to achieve the above object, the mass measurement circuit of the present invention includes a small array in which at least one type of a plurality of pairs of semiconductor elements is formed in a predetermined size and arrangement, and a plurality of such small arrays are arranged in a grid pattern. And a large array configured by arranging a plurality of the units in a lattice shape, and a control circuit for selecting any one semiconductor element according to a measurement item of the semiconductor element.

Typical semiconductor devices are either metal oxide field effect transistors, bipolar transistors, resistors, or capacitors.
Preferably, a plurality of dummy semiconductor elements having different densities that are not selected by the control circuit are further formed.

  According to the present invention, even when a sub-micron process in which local variations are large is used, it is possible to perform a large amount of measurement that can accurately measure parameters of each variation and establish a high-accuracy model.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a semiconductor device mass measurement circuit 1 according to a first embodiment of the present invention. The mass measurement circuit 1 according to the first embodiment is characterized in that the following configuration is adopted.

  10 pairs to 20 pairs of semiconductor elements are respectively formed in a predetermined size and arrangement to constitute one small array 10. A plurality of small arrays 10 are arranged in a lattice form to constitute one unit 20. Then, a plurality of units 20 are further arranged in a lattice shape to constitute a large array 30. Each semiconductor element included in the plurality of small arrays 10 is connected to a switch controlled by a control circuit (decoder) 40. The control circuit 40 is disposed on any two sides of the large array 30. A plurality of pads 50 are arranged outside the large array 30 and the control circuit 40 to configure the large quantity measurement circuit 1.

The control circuit 40 selects any one semiconductor element (turns on the semiconductor element switch) in accordance with a signal corresponding to a measurement item (DC characteristic or capacitance value) input from the pad 50. Also, a DC voltage or a clock is supplied from the pad 50, or the analog characteristics of the semiconductor element are measured.
Semiconductor elements formed in the small array 10 include a metal oxide field effect transistor (MOSFET), a bipolar transistor (BJT), a polysilicon resistor, a MOS capacitor, and a metal-insulator-metal capacitor (MIM capacitor). .

If the above configuration is used, as shown in FIG. 2, first, local variations can be reduced by averaging the extraction results of a plurality of semiconductor elements included in the plurality of small arrays 10. Further, by taking an average of the plurality of small arrays 10, the influence of layout dependent variation can be reduced. Furthermore, the influence of global variation can be reduced by taking the average of the units 20.
Therefore, it is possible to measure a large amount of each variation parameter in order to establish a high-accuracy model used for the submicron process.

(Second Embodiment)
FIG. 3 is a diagram showing a configuration of the semiconductor element mass measurement circuit 2 according to the second embodiment of the present invention. The mass measurement circuit 2 according to the second embodiment is characterized in that the following configuration is further adopted in the configuration of the mass measurement circuit 1 according to the first embodiment described above.

As shown in FIG. 3, a dummy semiconductor element 60 that is not selected by the control circuit 40 is formed in a surplus area outside the plurality of pads 50, that is, in a scribe lane around Die. In addition, the dummy semiconductor elements 60 are arranged by changing the density of the semiconductor elements.
The dummy semiconductor element 60 formed in the scribe lane includes a MOSFET, a BJT, a polysilicon resistor, a MOS capacitor, and an MIM capacitor.

By using the above configuration, it is possible to ensure the reproducibility of the layout dependent variation of the measurement result.
In addition to the scribe lane, for example, the dummy semiconductor element 60 may be disposed between the large array 30 and the plurality of pads 50 or inside the unit 20.

  The mass measurement circuit of the present invention is suitable for use in evaluating global variations, local variations, layout-dependent variations, and correlations between these variations in semiconductor elements, and in particular, a submicron process used in high-frequency ICs. Suitable for use in etc.

1 is a diagram showing a configuration of a semiconductor device mass measurement circuit 1 according to a first embodiment of the present invention. The figure explaining the effect of the mass measurement circuit 1 which concerns on 1st Embodiment shown in FIG. The figure which shows the structure of the large quantity measurement circuit 2 of the semiconductor element which concerns on the 2nd Embodiment of this invention. The figure explaining three dispersion | variation which a semiconductor element has The figure which shows the structure of the conventional variation evaluation circuit The figure explaining the problem in the conventional dispersion | variation evaluation circuit shown in FIG. Diagram showing the configuration of a conventional semiconductor device mass measurement circuit The figure explaining the problem in the conventional mass measurement circuit shown in FIG.

Explanation of symbols

1, 2 Mass measurement circuit 10 Small array 20 Unit 30 Large array 40 Control circuit 50 Pad 60 Dummy semiconductor element

Claims (3)

A mass measurement circuit used for mass measurement of semiconductor elements,
A small array in which at least one type of a plurality of pairs of semiconductor elements is formed in a predetermined size and arrangement;
A unit configured by arranging a plurality of the small arrays in a grid, and a large array configured by arranging a plurality of the units in a grid,
A large quantity measurement circuit formed with a control circuit for selecting any one semiconductor element in accordance with a measurement item of the semiconductor element.   The mass measurement circuit according to claim 1, wherein the semiconductor element is any one of a metal oxide field effect transistor, a bipolar transistor, a resistor, and a capacitor. The mass measurement circuit according to claim 1, further comprising a plurality of dummy semiconductor elements having different density, which are not selected by the control circuit.

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