JP2008004185A - Semiconductor memory testing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate a test concerning a memory to be tested by shortening time for testing concerning each bit included in the memory cells of the memory to be tested. <P>SOLUTION: This apparatus is provided with an extraction memory 5 where the addresses of failed cells are stored in each failure relieving unit area SG1 to SG4 based on the testing result of the memory 9 to be tested, a failure extraction means 7 which stores the addresses of the failed cells in the extraction memory 5 in each failure relieving unit area based on the testing result in a testing result storing memory 11; and a failure relieving calculation means 3 which performs failure relieving calculation by the addresses of the failed cells stored in the extraction memory 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory test apparatus for executing a test on a memory under test.

  In general, a semiconductor memory test apparatus performs write access and read access to a memory under test (hereinafter also referred to as “DUT”) such as a so-called DRAM (Dynamic Random Access Memory), a flash memory, etc., and writes it to the memory under test. Pass / fail judgment is performed by testing whether or not the read contents can be read.

  A conventional semiconductor memory test apparatus includes a tester unit, a fail memory (corresponding to “defective memory”), and a buffer memory (see Patent Document 1). The tester unit is a device that executes a test on a memory under test. The fail memory is a storage device that stores the test result of the memory under test by the tester unit. The buffer memory is an auxiliary storage device for transferring the test result stored in the fail memory prior to execution of so-called redundancy processing. Note that the redundancy processing here is processing for performing a failure analysis on a memory under test that has failed as a result of a test and relieving a memory cell in which a failure has occurred. This will be specifically described below.

FIG. 7 is a block diagram showing an example of the electrical configuration of a conventional semiconductor memory test apparatus 101.
The conventional semiconductor memory test apparatus 101 is a test apparatus that performs a test on a memory cell of the memory under test 109 and, when a defective cell exists, repairs a defect by a predetermined unit in the defect repair unit area. is there. The semiconductor memory test apparatus 101 includes a CPU (Central Processing Unit) 103, a defective memory (fail memory) 111, a buffer memory 113, a defect extraction circuit 107, an extraction memory 105, and a test execution unit 108.

  First, the address indicating the memory cell of the memory under test 109 is divided into a plurality of defect relief unit areas according to the defect relief structure of the memory under test 109. Each memory cell of the memory under test 109 belongs to one of these defect repair unit areas. The CPU 103 performs failure analysis on each memory cell of the memory under test 109 for each failure remedy unit region.

  The test execution unit 108 determines whether or not the contents written in the memory under test 109 can be normally read out by performing read access to each memory cell of the memory under test 109 after performing write access to the test pattern. The test result (referred to as “good / bad result data”) is stored in the defective memory 111 (hereinafter referred to as “test processing”).

  The defective memory 111 has the same memory map as the memory under test 109. The defective memory 111 stores whether or not a defect has occurred in each memory cell of the memory under test 109 during the test. The buffer memory 113 also has the same memory map as the defective memory 111. When the test of one memory under test 109 is completed, the pass / fail result data stored in the defective memory 111 is copied to the buffer memory 113. After this copying, in parallel with the extraction processing by the defect extraction circuit and the failure analysis processing by the CPU for the pass / fail result described later, the test execution unit performs the next test of the memory under test, and the test The result can be stored in a defective memory.

  The defect extraction circuit 107 sequentially scans and reads the memory space of the buffer memory 113 over a specific address range designated by the CPU 103, and each time a defect is detected, the accessed address is extracted as the address of the defective cell. The defect extraction circuit 107 stores the extraction results in the extraction memory 105 in order from the lower address side (referred to as “extraction processing”). Specifically, for example, it is as follows.

  For example, when considering a memory cell of the memory under test 109 configured by four defect relief unit areas SG1 to SG4 as shown in FIG. 8, the defect extraction circuit 107 performs an extraction process on the defect relief unit area SG1. Then, defective cells (defective) A and defective cells (defective) B are extracted, and their addresses are stored in the extraction memory 105.

  Here, the CPU 103 performs a failure analysis on the memory under test 109 based on the distribution of defective memory cells for each failure relief unit region. The addresses of the defective memory 111 having a large number of words are sequentially scanned and read. It takes time. Therefore, the CPU 103 instead reads the contents of the extraction memory 105 and performs a failure analysis based on the distribution of defective memory cells extracted in the extraction memory 105 (failure analysis processing).

  For this reason, in the conventional semiconductor memory test apparatus 101, after the above-described test, the CPU 103 performs a combination operation of the above-described extraction process and defect analysis process (hereinafter referred to as “a series of processes”) for each defect relief unit area related to the memory under test 109. (Referred to as “operation”).

JP 2003-34495 A

  FIG. 10 is a diagram illustrating a series of operation examples performed by the conventional semiconductor memory test apparatus 101 as time elapses. In this series of operation examples, it is assumed that the length of the arrow indicated by the solid line and the wavy line indicates the length of the operation time, and the characters indicated above the arrow indicate the operation content. Further, the numbers added after the characters such as “extract” and “analysis” are identifiers for distinguishing each defective repair unit area. In FIG. 10, the time advances from the left to the right.

  In the case of the illustrated example, the execution interval of a series of operations is a defect extraction time (corresponding to “extraction 1” shown in the figure) taken by the defect extraction circuit 107 and a defect analysis time (shown by the CPU 103). In addition to this, the total time obtained by multiplying by the number of defective relief unit areas is added, and separately from this, copying for copying from the defective memory 111 to the buffer memory 113 is included. It further includes time (corresponding to “copy” shown). Since the conventional semiconductor memory test apparatus 101 includes such a copying time for the buffer memory, the testing time for the memory under test 109 is long.

  Accordingly, the present invention provides a semiconductor memory test apparatus capable of speeding up a test relating to a memory under test.

  In order to achieve the above object, a first invention is a test execution means for performing a test of a memory under test, a test result storage memory for storing a test result of the test execution means, and a defective relief unit area of the memory under test. An extraction memory for storing the address of the defective cell for each, and a defect extraction means for storing the address of the defective cell in the extraction memory for each defect relief unit area based on the test result of the test result storage memory; A semiconductor memory test apparatus comprising: a defect remedy calculation means for performing a defect remedy calculation based on an address of the defective cell stored in the extraction memory. In this case, the “defective repair operation” means that a defective cell is analyzed based on the address of the defective cell, and the defective cell is repaired for each defective repair unit area (or its predetermined unit) according to the analysis result. It shows a series of operations necessary to do this.

  According to the first aspect of the invention, the defect extraction means stores the address of the defective cell in the memory under test in the extraction memory for each defective remedy unit area to which the defective cell belongs based on the test result of the test result storage memory. ing.

  That is, the defect extraction means stores the addresses of defective cells extracted for each defect relief unit area in the memory under test separately in the extraction memory. For this reason, since the defect extraction means continuously extracts the addresses of the defective cells from the test result storage memory to the extraction memory for all the defect relief unit areas, after such extraction processing, the defect relief calculation means However, it is possible to analyze a defective cell and perform a defective remedy operation based on the address of the defective cell already extracted in the extraction memory.

  Further, after such extraction processing, the test execution means performs the following operation in parallel while the defect relief calculation means performs the defect relief calculation based on the address of the defective cell extracted in the extraction memory. Tests can be performed on the test memory.

  Therefore, according to the semiconductor memory test apparatus of the present invention, there is no need to mount a buffer memory, and there is no time for copying to the buffer memory, so the test time for the memory under test is shortened and the test for the memory under test is performed. Can be speeded up. In addition, the semiconductor memory test apparatus of the present invention does not need to be equipped with such a buffer memory, so that the circuit scale can be reduced.

  According to a second aspect of the present invention, in the configuration of the first aspect, the extraction memory is composed of two or more extraction unit memories, and the defect remedy calculating means is configured such that the defect extraction means includes the two or more extraction unit memories. While the address of the defective cell is stored in any one of the extraction unit memories, the address of the defective cell stored in the other extraction unit memory among the two or more extraction unit memories is read. Features.

  According to the second invention, in addition to the operation of the first invention, the extraction memory composed of two or more extraction unit memories performs a so-called interleave operation, so that the defect remedy operation means can In parallel with the analysis of the defective cell based on the address of the defective cell in the memory under test extracted in the extraction memory, the defect extraction means stores the address of the defective cell in the next memory under test in the other extracted memory. Can be stored. For this reason, in the semiconductor memory test apparatus, the defect remedy calculation means can speed up the defect remedy calculation for the defective cell, and the test can be speeded up.

  According to a third invention, in the configuration of the first invention or the second invention, the defect extraction means extracts the address of the defective cell for each of the defect remedy unit areas from the test result storage memory, and the extraction The defective remedy calculating means reads the addresses of the defective cells for each of the defective remedy unit areas from the lower address side of the extraction memory.

  According to the semiconductor memory test apparatus of the present invention, it is possible to speed up the test relating to the memory under test.

<First Embodiment>
FIG. 1 is a block diagram showing an example of the electrical configuration of a semiconductor memory test apparatus 1 as a first embodiment of the present invention.
The semiconductor memory test apparatus 1 is a test apparatus that performs a test on a memory cell of the memory under test 9 and relieves a defective portion (defective cell) by a predetermined unit in the defect relieving unit area when a defect occurs. The semiconductor memory test apparatus 1 includes a CPU (Central Processing Unit) 3, a defective memory (fail memory) 11, a defect extraction circuit 7, an extraction memory 5, and a test execution unit 8.

  Whether or not the contents written in the memory under test 9 can be normally read out by performing the read access after performing the write access to each memory cell of the memory under test 9 based on the test pattern. The test result (referred to as “good / bad result data”) is stored in the defective memory 11 (hereinafter referred to as “test processing”).

  The defective memory 11 has the same memory map as the memory under test 9 and stores whether or not a defect occurs for each memory cell of the memory under test 9 during the test. When the test of the memory under test 9 is completed, the pass / fail result data accumulated in the defective memory 11 is extracted and stored in the extraction memory 5 as described later.

  The defect extraction circuit 7 detects the defect by sequentially reading the memory space of the defect memory 11 according to the division information of the defect repair unit area designated by the CPU 3 according to the defect repair structure of the memory under test 9. Each time, the address of the defective memory 11 is set as the address of the defective cell. Further, the defect extraction circuit 7 stores the addresses of defective cells, which are the extraction results, packed in order from the lower address side in the extraction target unit area of the extraction memory 5 corresponding to the defect relief unit area to which the cell belongs. Have

  Further, the CPU 3 reads the contents of the extraction memory 5 (distribution of defective memory cells) for each extraction target unit area in order to perform a failure analysis on the memory under test 9 based on the distribution of defective memory cells for each defective relief unit area. . The CPU 3 performs defect analysis based on the distribution of defective cells extracted in the extraction memory 5 (defective relief calculation processing).

The semiconductor memory test apparatus 1 is configured as described above. Next, an operation example of the semiconductor memory test apparatus 1 will be described.
The semiconductor memory test apparatus 1 determines whether or not the contents written in the memory cell of the memory under test 9 can be normally read out by executing write access and read access for the memory cell of the memory under test 9. test. The semiconductor memory test apparatus 1 is an apparatus that executes test processing, extraction processing, analysis processing, and relief processing related to memory cells of the memory under test 9.

<Test processing>
The test execution unit 8 tests whether or not the contents written in the memory under test 9 can be normally read out by performing read access to each memory cell of the memory under test 9 after performing write access. The test result (good / bad result data) is stored in the defective memory 11.

  The defective memory 11 has the same memory map as that of the memory under test 9 and accumulates whether or not a defect occurs in the memory cell of the memory under test 9 during the test. When the test of the memory under test 9 is completed, the defect result data accumulated in the defect memory 11 is extracted as a defect (failure) and stored in the extraction memory 5 as follows.

<Extraction process>
The defect extraction circuit 7 sequentially scans the memory space of the defect memory 11, and each time a defect is detected, the address of the defect cell is determined based on the division information such as the defect repair unit area SG1 designated by the CPU 3 and the cell. Are sequentially packed and stored in the extraction target unit area of the extraction memory 5 corresponding to the defect relief unit area to which the data belongs. In this way, the defect extraction circuit 7 divides the memory under test 9 into each defect relief unit area and assigns the address of the defective cell to the extraction target unit of the extraction memory 5 corresponding to the defect relief unit area to which each defective cell belongs. It will be stored in the area.

  In the present embodiment, for example, consider a memory cell of the memory under test 9 divided into four defect relief unit regions SG1 to SG4 as shown in FIG. Further, in the present embodiment, as a result of testing each memory cell of the memory under test 9, for example, it is assumed that defective cells A to D exist. Of these defective cells A to D, the defective cells A and B each belong to the defective relief unit region SG1, and the defective cells C and D each belong to the defective relief unit region SG4. Note that no defective cells exist in the defective relief unit regions SG2 and SG3. The defect extraction circuit 7 extracts the defective cell A and the defective cell B in the defect repair unit area SG1, and does not extract a defect in the defect repair unit area SG2 and the defect repair unit area SG3. The defective cell C and the defective cell D are extracted.

  Further, the defect extraction circuit 7 lowers the addresses of the defective cells A and B in the extraction target unit region 5a corresponding to the defect repair unit region SG1, for example, as shown in FIG. 3 for each of the defect repair unit regions SG1 to SG4. The addresses of the defective cells C and D are stored in order from the lower address side, for example, in the extraction target unit area 5d corresponding to the defective relief unit area SG4. In the present embodiment, the content extracted into the extraction memory 5 in this way is referred to as “defective memory cell distribution”.

<Defect analysis processing>
Here, the CPU 3 reads out the contents of the extraction memory 5 (distribution of defective memory cells) in order to perform a failure analysis on the memory under test 9 based on the distribution of defective memory cells for each defective relief unit area. The failure analysis is performed based on the distribution of the defective memory cells extracted.

  FIG. 4 is a diagram illustrating an example of a series of operations performed by the semiconductor memory test apparatus 1 over time. In these series of operation examples, it is assumed that the length of the arrow indicated by the solid line and the wavy line indicates the length of the operation time, and the characters indicated above the arrow indicate the operation content. Further, the numbers added after the characters such as “extract” and “analysis” are identifiers for distinguishing each defective repair unit area. In FIG. 4, the time advances from the left to the right.

  In the case of the illustrated example, the execution interval of a series of operations including the extraction process and the analysis process (hereinafter simply referred to as “a series of operations”) after the above-described test process is set to be copied to a buffer memory as in the past. It does not include the copying time, and the defect extraction time (corresponding to “extraction 1” to “extraction 4” in the figure) required for the defect extraction by the defect extraction circuit 7 and the defect analysis time (corresponding to the “analysis” in FIG. 1 ”to“ Analysis 4 ”). That is, in the semiconductor memory test apparatus 1, the execution interval of a series of operations is the total time of the defect extraction time required for defect extraction by the defect extraction circuit 7 and the failure analysis time required for the failure analysis by the CPU 3.

  According to the first embodiment, the defect extraction circuit 7 assigns the address of the defective cell A of the memory under test 9 to the extraction memory 5 on the basis of the test result of the defect memory 11 for each defect relief unit region SG1 and the like. They are stored in order from the address side.

  Further, the defect extraction circuit 7 assigns addresses such as the defective cell C of the same memory under test 9 in the extraction target unit area 5d of the extraction memory 5 corresponding to the defect relief unit area SG4 to which the defective cell C belongs. Stored from the lower address.

  That is, the defect extraction circuit 7 stores the addresses of the defective cells A and the like extracted for each defect relief unit region SG1 in the memory under test 9 separately in the extraction memory 5. For this reason, since the defect extraction circuit 7 continuously extracts the addresses of defective cells from the defect memory 11 to the extraction memory 5 for all defect relief unit regions SG1 and the like with respect to the memory under test 9, such extraction processing is performed. Later, the CPU 3 (defective remedy calculation means) can perform analysis of defective cells (defective remedy calculation) based on the addresses of defective cells already extracted in the extraction memory 5.

  Further, after such extraction processing, the CPU 3 (defective remedy calculation means) performs the defective remedy calculation based on the address of the defective cell extracted in the extraction memory 5, and in parallel, the test execution unit 8 However, a test can be performed on the next memory under test 9.

  Therefore, according to this embodiment, there is no need to mount a buffer memory, and there is no time for copying to such a buffer memory. Therefore, the test time for the memory under test 9 is shortened, and the test for the memory under test 9 is performed. Can be speeded up. In addition, according to the present embodiment, the pass / fail result data is temporarily stored in the semiconductor memory test apparatus 1 when the pass / fail result data accumulated in the defective memory 11 is copied to the extraction memory 5. Therefore, the circuit scale can be reduced.

<Second Embodiment>
FIG. 5 is a block diagram showing an example of the electrical configuration of the semiconductor memory test apparatus 1a as the second embodiment of the present invention.
The semiconductor memory test apparatus 1a has substantially the same configuration as the semiconductor memory test apparatus 1 as the first embodiment and performs almost the same operation. Therefore, the description of the same configuration and operation is omitted, and The description will focus on the differences. Note that, in the second embodiment, when the same configuration and operation as in the first embodiment are described, the same reference numerals as those in the first embodiment are used.

  In the first embodiment, the semiconductor memory test apparatus 1 includes one extraction memory 5, whereas in the second embodiment, a plurality of semiconductor memory test apparatuses 1a (in the second embodiment, 2) are used instead. Extraction memories 5e and 5f (two or more extraction unit memories). That is, in the second embodiment, a so-called interleave operation is realized by these extraction memories 5e and 5f.

In the semiconductor memory test apparatus 1a having such a configuration, the CPU 3 and the defect extraction circuit 7 operate as follows using these extraction memories 5e and 5f.
That is, while the defect extraction circuit 7 stores the address of the defective cell or the like in one of the two extraction memories 5e and 5f (for example, the extraction memory 5e), the CPU 3 makes two extraction memories in parallel. The address of the defective cell already stored in either the other of 5e and 5f (for example, the extraction memory 5f) is read.

FIG. 6 is a diagram showing the operations performed by the semiconductor memory test apparatus 1a in a simplified manner. The terms shown in FIG. 6 are the same as the terms shown in FIG.
The semiconductor memory test apparatus 1a is equipped with two extraction memories 5e and 5f, so that the CPU 3 and the defect extraction circuit 7 can proceed in parallel using the extraction memories 5e and 5f.

  Specifically, the CPU 3 performs the analysis process (corresponding to “Analysis 1” to “Analysis 4” in the figure) based on the extraction result of the extraction memory 5e in parallel, The extraction process (corresponding to “extraction 1” to “extraction 4” shown in the figure) is executed, and the extraction result can be stored in the extraction memory 5f.

  According to the second embodiment, the same usefulness as that of the first embodiment can be exhibited, and in addition, the two or more extraction memories 5e and 5f perform a so-called interleave operation. The addresses of defective cells for the plurality of memories under test 9 are written one after the other and can be read one after another simultaneously. For this reason, the CPU 3 (defective remedy calculation means) performs a failure analysis on the defective cells in succession for the plurality of memories 9 to be tested regardless of the state of writing to the extraction memories 5e and 5f by the defect extraction circuit 7. A relief operation can be performed. For this reason, the semiconductor memory test apparatus 1a can speed up the defect remedy operation for the defective cell, and can speed up the test.

  The above is the description of one embodiment, but the embodiment of the present invention is not limited to this. Each composition of the above-mentioned embodiment can change not only the above-mentioned form but a combination suitably.

1 is a block diagram showing an example of the electrical configuration of a semiconductor memory test apparatus as a first embodiment of the present invention. It is a figure which shows the specific example of arrangement | positioning of the defect in the memory cell of a memory under test. It is a memory map which shows an example of the quality result data stored in the extraction memory. It is the figure which illustrated in a series of the example of a series of operation | movement which a semiconductor memory test device performs. It is a block diagram which shows the electrical structural example of the semiconductor memory test apparatus as 2nd Embodiment of this invention. It is the figure which illustrated in a series of the example of a series of operation | movement which a semiconductor memory test device performs. It is a block diagram which shows the example of an electrical structure of the conventional semiconductor memory test apparatus. It is a figure which shows the specific example of arrangement | positioning of the defect in the memory cell of a memory under test. It is a memory map which shows an example of the quality result data stored in the extraction memory. It is the figure which illustrated the series of operation examples which the conventional semiconductor memory test device performs according to progress of time.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory test device 1a Semiconductor memory test device 3 CPU (defective relief calculation means)
5 Extraction Memory 5a Extraction Target Unit Area 5b Extraction Target Unit Area 5c Extraction Target Unit Area 5d Extraction Target Unit Area 5e Extraction Memory (Extraction Unit Memory)
5f Extraction memory (extraction unit memory)
7 Defect extraction circuit (defect extraction means)
8 Test execution department (Test execution means)
9 Memory under test 11 Defect memory (Test result storage memory)
SG1 Defect Relief Unit Area SG2 Defect Relief Unit Area SG3 Defect Relief Unit Area SG4 Defect Relief Unit Area

Claims (3)

A test execution means for performing a test of the memory under test;
A test result storage memory for storing a test result of the test execution means;
An extraction memory for storing an address of a defective cell for each defective relief unit area of the memory under test;
Based on the test result of the test result storage memory, defect extraction means for storing the address of the defective cell in the extraction memory for each defect relief unit area;
A semiconductor memory test apparatus comprising: a defect remedy calculation means for performing a defect remedy calculation based on an address of the defective cell stored in the extraction memory. The extraction memory is composed of two or more extraction unit memories,
The defect remedy calculating means stores the addresses of the two or more extraction unit memories while the defect extraction means stores the addresses of the defective cells in any one of the two or more extraction unit memories. 2. The semiconductor memory test apparatus according to claim 1, wherein an address of the defective cell stored in another extraction unit memory is read out. The defect extraction means extracts the address of the defective cell for each defect remedy unit region from the test result storage memory, stores it sequentially from the lower address side of the extraction memory,
3. The semiconductor memory test apparatus according to claim 1, wherein the defect remedy calculating unit reads an address of the defective cell for each defect remedy unit region from a lower address side of the extraction memory.

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